Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.72 98.25 93.97 97.02 91.86 96.37 99.77 92.80


Total test records in report: 1106
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T1007 /workspace/coverage/cover_reg_top/23.edn_intr_test.2242290160 Aug 15 06:37:41 PM PDT 24 Aug 15 06:37:42 PM PDT 24 75468484 ps
T1008 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1874727173 Aug 15 06:37:31 PM PDT 24 Aug 15 06:37:32 PM PDT 24 509686759 ps
T1009 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1603581716 Aug 15 06:37:42 PM PDT 24 Aug 15 06:37:45 PM PDT 24 369255186 ps
T1010 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1906571385 Aug 15 06:37:42 PM PDT 24 Aug 15 06:37:44 PM PDT 24 40977459 ps
T1011 /workspace/coverage/cover_reg_top/49.edn_intr_test.2340020790 Aug 15 06:37:41 PM PDT 24 Aug 15 06:37:42 PM PDT 24 32128001 ps
T1012 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3496946177 Aug 15 06:37:34 PM PDT 24 Aug 15 06:37:36 PM PDT 24 28531714 ps
T1013 /workspace/coverage/cover_reg_top/45.edn_intr_test.1170502901 Aug 15 06:37:49 PM PDT 24 Aug 15 06:37:50 PM PDT 24 13122632 ps
T1014 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.4223234510 Aug 15 06:37:36 PM PDT 24 Aug 15 06:37:37 PM PDT 24 36387546 ps
T1015 /workspace/coverage/cover_reg_top/11.edn_intr_test.3830093184 Aug 15 06:37:39 PM PDT 24 Aug 15 06:37:40 PM PDT 24 14850731 ps
T1016 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3890546628 Aug 15 06:37:41 PM PDT 24 Aug 15 06:37:43 PM PDT 24 51683898 ps
T1017 /workspace/coverage/cover_reg_top/4.edn_intr_test.2101324109 Aug 15 06:37:25 PM PDT 24 Aug 15 06:37:26 PM PDT 24 15484108 ps
T1018 /workspace/coverage/cover_reg_top/47.edn_intr_test.3306666509 Aug 15 06:37:45 PM PDT 24 Aug 15 06:37:46 PM PDT 24 24069051 ps
T1019 /workspace/coverage/cover_reg_top/2.edn_intr_test.1460415446 Aug 15 06:37:39 PM PDT 24 Aug 15 06:37:40 PM PDT 24 65936662 ps
T1020 /workspace/coverage/cover_reg_top/2.edn_csr_rw.2936375615 Aug 15 06:37:31 PM PDT 24 Aug 15 06:37:32 PM PDT 24 18300997 ps
T1021 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.341304686 Aug 15 06:37:52 PM PDT 24 Aug 15 06:37:53 PM PDT 24 378120670 ps
T1022 /workspace/coverage/cover_reg_top/10.edn_tl_errors.1269037168 Aug 15 06:37:38 PM PDT 24 Aug 15 06:37:41 PM PDT 24 63070364 ps
T1023 /workspace/coverage/cover_reg_top/17.edn_tl_errors.2379061687 Aug 15 06:37:54 PM PDT 24 Aug 15 06:37:58 PM PDT 24 110064961 ps
T1024 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2231301745 Aug 15 06:37:42 PM PDT 24 Aug 15 06:37:43 PM PDT 24 350261469 ps
T1025 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3159540745 Aug 15 06:37:24 PM PDT 24 Aug 15 06:37:25 PM PDT 24 15691550 ps
T1026 /workspace/coverage/cover_reg_top/48.edn_intr_test.3702719076 Aug 15 06:37:50 PM PDT 24 Aug 15 06:37:51 PM PDT 24 40154023 ps
T1027 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3116568052 Aug 15 06:37:37 PM PDT 24 Aug 15 06:37:39 PM PDT 24 26814624 ps
T1028 /workspace/coverage/cover_reg_top/46.edn_intr_test.2259450857 Aug 15 06:37:51 PM PDT 24 Aug 15 06:37:52 PM PDT 24 13513057 ps
T280 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.342663805 Aug 15 06:37:49 PM PDT 24 Aug 15 06:37:52 PM PDT 24 143434396 ps
T1029 /workspace/coverage/cover_reg_top/33.edn_intr_test.2120921708 Aug 15 06:37:49 PM PDT 24 Aug 15 06:37:50 PM PDT 24 31093089 ps
T1030 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2466360125 Aug 15 06:37:30 PM PDT 24 Aug 15 06:37:31 PM PDT 24 79228258 ps
T1031 /workspace/coverage/cover_reg_top/4.edn_tl_errors.2606426147 Aug 15 06:37:32 PM PDT 24 Aug 15 06:37:35 PM PDT 24 118883966 ps
T1032 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.770886341 Aug 15 06:37:45 PM PDT 24 Aug 15 06:37:46 PM PDT 24 78574380 ps
T1033 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.153182228 Aug 15 06:37:52 PM PDT 24 Aug 15 06:37:54 PM PDT 24 50037006 ps
T1034 /workspace/coverage/cover_reg_top/34.edn_intr_test.3055892636 Aug 15 06:38:02 PM PDT 24 Aug 15 06:38:03 PM PDT 24 60365990 ps
T1035 /workspace/coverage/cover_reg_top/17.edn_intr_test.606760365 Aug 15 06:37:53 PM PDT 24 Aug 15 06:37:54 PM PDT 24 14104857 ps
T1036 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2097471344 Aug 15 06:37:49 PM PDT 24 Aug 15 06:37:50 PM PDT 24 44186139 ps
T1037 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1266151818 Aug 15 06:37:41 PM PDT 24 Aug 15 06:37:44 PM PDT 24 309872171 ps
T1038 /workspace/coverage/cover_reg_top/13.edn_csr_rw.1936064446 Aug 15 06:37:41 PM PDT 24 Aug 15 06:37:42 PM PDT 24 13606729 ps
T1039 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1744506580 Aug 15 06:37:58 PM PDT 24 Aug 15 06:37:59 PM PDT 24 44045626 ps
T1040 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1278841288 Aug 15 06:37:38 PM PDT 24 Aug 15 06:37:39 PM PDT 24 14223792 ps
T1041 /workspace/coverage/cover_reg_top/18.edn_csr_rw.909805638 Aug 15 06:37:44 PM PDT 24 Aug 15 06:37:45 PM PDT 24 27418990 ps
T1042 /workspace/coverage/cover_reg_top/26.edn_intr_test.3519985606 Aug 15 06:38:07 PM PDT 24 Aug 15 06:38:08 PM PDT 24 27857164 ps
T1043 /workspace/coverage/cover_reg_top/13.edn_intr_test.1350388211 Aug 15 06:37:40 PM PDT 24 Aug 15 06:37:41 PM PDT 24 12855946 ps
T1044 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1833858131 Aug 15 06:37:24 PM PDT 24 Aug 15 06:37:26 PM PDT 24 86202206 ps
T1045 /workspace/coverage/cover_reg_top/19.edn_csr_rw.900932926 Aug 15 06:37:49 PM PDT 24 Aug 15 06:37:50 PM PDT 24 33591165 ps
T1046 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3449044402 Aug 15 06:37:26 PM PDT 24 Aug 15 06:37:28 PM PDT 24 434303773 ps
T1047 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3061617833 Aug 15 06:37:39 PM PDT 24 Aug 15 06:37:40 PM PDT 24 19584953 ps
T1048 /workspace/coverage/cover_reg_top/39.edn_intr_test.1226384919 Aug 15 06:37:43 PM PDT 24 Aug 15 06:37:44 PM PDT 24 11250108 ps
T1049 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1366284394 Aug 15 06:37:45 PM PDT 24 Aug 15 06:37:46 PM PDT 24 28293567 ps
T1050 /workspace/coverage/cover_reg_top/11.edn_tl_errors.3006501665 Aug 15 06:37:41 PM PDT 24 Aug 15 06:37:44 PM PDT 24 98311503 ps
T1051 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3268698226 Aug 15 06:37:41 PM PDT 24 Aug 15 06:37:43 PM PDT 24 645100770 ps
T250 /workspace/coverage/cover_reg_top/5.edn_csr_rw.4024025841 Aug 15 06:37:45 PM PDT 24 Aug 15 06:37:46 PM PDT 24 47103822 ps
T1052 /workspace/coverage/cover_reg_top/27.edn_intr_test.350409985 Aug 15 06:37:41 PM PDT 24 Aug 15 06:37:42 PM PDT 24 13593317 ps
T1053 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.4003511201 Aug 15 06:37:38 PM PDT 24 Aug 15 06:37:39 PM PDT 24 15674850 ps
T1054 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.759605216 Aug 15 06:37:35 PM PDT 24 Aug 15 06:37:38 PM PDT 24 248467705 ps
T1055 /workspace/coverage/cover_reg_top/16.edn_intr_test.1364401839 Aug 15 06:37:54 PM PDT 24 Aug 15 06:37:55 PM PDT 24 43171205 ps
T1056 /workspace/coverage/cover_reg_top/35.edn_intr_test.3169868803 Aug 15 06:37:51 PM PDT 24 Aug 15 06:37:52 PM PDT 24 13807020 ps
T251 /workspace/coverage/cover_reg_top/3.edn_csr_rw.227848553 Aug 15 06:37:46 PM PDT 24 Aug 15 06:37:47 PM PDT 24 16889532 ps
T1057 /workspace/coverage/cover_reg_top/7.edn_tl_errors.753144533 Aug 15 06:37:41 PM PDT 24 Aug 15 06:37:43 PM PDT 24 53070058 ps
T1058 /workspace/coverage/cover_reg_top/14.edn_tl_errors.1200901350 Aug 15 06:37:34 PM PDT 24 Aug 15 06:37:38 PM PDT 24 42665146 ps
T1059 /workspace/coverage/cover_reg_top/7.edn_csr_rw.3660887788 Aug 15 06:37:45 PM PDT 24 Aug 15 06:37:46 PM PDT 24 15339512 ps
T1060 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.215988583 Aug 15 06:37:34 PM PDT 24 Aug 15 06:37:35 PM PDT 24 21529941 ps
T1061 /workspace/coverage/cover_reg_top/15.edn_csr_rw.2743714908 Aug 15 06:37:54 PM PDT 24 Aug 15 06:37:55 PM PDT 24 65845406 ps
T1062 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.572047150 Aug 15 06:37:30 PM PDT 24 Aug 15 06:37:32 PM PDT 24 46280263 ps
T1063 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2430645064 Aug 15 06:38:00 PM PDT 24 Aug 15 06:38:01 PM PDT 24 119841255 ps
T1064 /workspace/coverage/cover_reg_top/15.edn_intr_test.1829258528 Aug 15 06:37:55 PM PDT 24 Aug 15 06:37:56 PM PDT 24 26808423 ps
T1065 /workspace/coverage/cover_reg_top/10.edn_intr_test.3248575157 Aug 15 06:37:35 PM PDT 24 Aug 15 06:37:36 PM PDT 24 120232169 ps
T1066 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.749711630 Aug 15 06:37:32 PM PDT 24 Aug 15 06:37:34 PM PDT 24 178917634 ps
T1067 /workspace/coverage/cover_reg_top/11.edn_csr_rw.1649720372 Aug 15 06:37:38 PM PDT 24 Aug 15 06:37:39 PM PDT 24 16339135 ps
T1068 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.867548514 Aug 15 06:37:40 PM PDT 24 Aug 15 06:37:44 PM PDT 24 96513136 ps
T1069 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3189913348 Aug 15 06:37:29 PM PDT 24 Aug 15 06:37:31 PM PDT 24 54130998 ps
T1070 /workspace/coverage/cover_reg_top/36.edn_intr_test.434178959 Aug 15 06:37:46 PM PDT 24 Aug 15 06:37:47 PM PDT 24 17627439 ps
T1071 /workspace/coverage/cover_reg_top/41.edn_intr_test.1905528628 Aug 15 06:37:42 PM PDT 24 Aug 15 06:37:43 PM PDT 24 14517849 ps
T1072 /workspace/coverage/cover_reg_top/25.edn_intr_test.2713472710 Aug 15 06:37:58 PM PDT 24 Aug 15 06:38:04 PM PDT 24 22846624 ps
T1073 /workspace/coverage/cover_reg_top/12.edn_tl_errors.2952290278 Aug 15 06:37:49 PM PDT 24 Aug 15 06:37:53 PM PDT 24 267452248 ps
T1074 /workspace/coverage/cover_reg_top/17.edn_csr_rw.2846101390 Aug 15 06:38:02 PM PDT 24 Aug 15 06:38:03 PM PDT 24 44491800 ps
T1075 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1825045514 Aug 15 06:37:31 PM PDT 24 Aug 15 06:37:32 PM PDT 24 22401795 ps
T1076 /workspace/coverage/cover_reg_top/7.edn_intr_test.3934496059 Aug 15 06:37:46 PM PDT 24 Aug 15 06:37:49 PM PDT 24 19103246 ps
T252 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.643109166 Aug 15 06:37:28 PM PDT 24 Aug 15 06:37:29 PM PDT 24 15504395 ps
T1077 /workspace/coverage/cover_reg_top/8.edn_csr_rw.3006958649 Aug 15 06:37:36 PM PDT 24 Aug 15 06:37:37 PM PDT 24 20708464 ps
T1078 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1061061923 Aug 15 06:37:50 PM PDT 24 Aug 15 06:37:52 PM PDT 24 66257240 ps
T1079 /workspace/coverage/cover_reg_top/40.edn_intr_test.2181732786 Aug 15 06:37:54 PM PDT 24 Aug 15 06:37:55 PM PDT 24 18067961 ps
T1080 /workspace/coverage/cover_reg_top/29.edn_intr_test.1319575997 Aug 15 06:38:06 PM PDT 24 Aug 15 06:38:07 PM PDT 24 12492152 ps
T1081 /workspace/coverage/cover_reg_top/1.edn_csr_rw.2244262718 Aug 15 06:37:34 PM PDT 24 Aug 15 06:37:35 PM PDT 24 28997152 ps
T1082 /workspace/coverage/cover_reg_top/18.edn_intr_test.1662146003 Aug 15 06:37:56 PM PDT 24 Aug 15 06:37:57 PM PDT 24 26549041 ps
T1083 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1068429895 Aug 15 06:37:46 PM PDT 24 Aug 15 06:37:50 PM PDT 24 103530239 ps
T1084 /workspace/coverage/cover_reg_top/2.edn_tl_errors.3028496406 Aug 15 06:37:31 PM PDT 24 Aug 15 06:37:34 PM PDT 24 278767370 ps
T1085 /workspace/coverage/cover_reg_top/1.edn_intr_test.862103484 Aug 15 06:37:30 PM PDT 24 Aug 15 06:37:31 PM PDT 24 41026129 ps
T1086 /workspace/coverage/cover_reg_top/14.edn_csr_rw.1098974265 Aug 15 06:38:11 PM PDT 24 Aug 15 06:38:12 PM PDT 24 50483801 ps
T1087 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1194667074 Aug 15 06:37:36 PM PDT 24 Aug 15 06:37:38 PM PDT 24 95364476 ps
T1088 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.4007263592 Aug 15 06:37:42 PM PDT 24 Aug 15 06:37:44 PM PDT 24 113091886 ps
T282 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1729703640 Aug 15 06:37:41 PM PDT 24 Aug 15 06:37:44 PM PDT 24 236894816 ps
T1089 /workspace/coverage/cover_reg_top/30.edn_intr_test.80500285 Aug 15 06:37:41 PM PDT 24 Aug 15 06:37:42 PM PDT 24 103638102 ps
T1090 /workspace/coverage/cover_reg_top/5.edn_tl_errors.3502969149 Aug 15 06:37:35 PM PDT 24 Aug 15 06:37:37 PM PDT 24 43126681 ps
T1091 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.654724630 Aug 15 06:37:26 PM PDT 24 Aug 15 06:37:27 PM PDT 24 53831740 ps
T1092 /workspace/coverage/cover_reg_top/12.edn_intr_test.2921835216 Aug 15 06:37:36 PM PDT 24 Aug 15 06:37:37 PM PDT 24 48117515 ps
T1093 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.781144379 Aug 15 06:37:44 PM PDT 24 Aug 15 06:37:47 PM PDT 24 77966200 ps
T1094 /workspace/coverage/cover_reg_top/19.edn_tl_errors.373958542 Aug 15 06:37:49 PM PDT 24 Aug 15 06:37:52 PM PDT 24 161383141 ps
T1095 /workspace/coverage/cover_reg_top/28.edn_intr_test.1493227769 Aug 15 06:37:49 PM PDT 24 Aug 15 06:37:50 PM PDT 24 46021846 ps
T1096 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1489260167 Aug 15 06:37:42 PM PDT 24 Aug 15 06:37:44 PM PDT 24 223410339 ps
T1097 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.463348836 Aug 15 06:37:38 PM PDT 24 Aug 15 06:37:39 PM PDT 24 31739234 ps
T1098 /workspace/coverage/cover_reg_top/42.edn_intr_test.3371728273 Aug 15 06:37:58 PM PDT 24 Aug 15 06:37:59 PM PDT 24 61281413 ps
T1099 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1208026968 Aug 15 06:37:38 PM PDT 24 Aug 15 06:37:39 PM PDT 24 78930903 ps
T1100 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2929117527 Aug 15 06:37:41 PM PDT 24 Aug 15 06:37:43 PM PDT 24 48740580 ps
T1101 /workspace/coverage/cover_reg_top/24.edn_intr_test.272245058 Aug 15 06:38:07 PM PDT 24 Aug 15 06:38:08 PM PDT 24 13282207 ps
T1102 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3400275071 Aug 15 06:37:45 PM PDT 24 Aug 15 06:37:46 PM PDT 24 48953546 ps
T1103 /workspace/coverage/cover_reg_top/21.edn_intr_test.463139474 Aug 15 06:37:56 PM PDT 24 Aug 15 06:37:57 PM PDT 24 38807728 ps
T1104 /workspace/coverage/cover_reg_top/6.edn_intr_test.1049572140 Aug 15 06:37:46 PM PDT 24 Aug 15 06:37:47 PM PDT 24 45034511 ps
T1105 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.634487617 Aug 15 06:37:41 PM PDT 24 Aug 15 06:37:42 PM PDT 24 88132718 ps
T1106 /workspace/coverage/cover_reg_top/1.edn_tl_errors.3637190591 Aug 15 06:37:31 PM PDT 24 Aug 15 06:37:33 PM PDT 24 48978834 ps
T253 /workspace/coverage/cover_reg_top/9.edn_csr_rw.3752181121 Aug 15 06:37:41 PM PDT 24 Aug 15 06:37:42 PM PDT 24 18726130 ps

Test location /workspace/coverage/default/22.edn_genbits.4204208720
Short name T1
Test name
Test status
Simulation time 52802455 ps
CPU time 1.69 seconds
Started Aug 15 06:32:38 PM PDT 24
Finished Aug 15 06:32:40 PM PDT 24
Peak memory 220424 kb
Host smart-8a93d732-62f0-4b47-9ba4-711256dd9838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204208720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.4204208720
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.2826690339
Short name T2
Test name
Test status
Simulation time 5436237726 ps
CPU time 32.47 seconds
Started Aug 15 06:32:52 PM PDT 24
Finished Aug 15 06:33:25 PM PDT 24
Peak memory 217924 kb
Host smart-8093b283-cfcf-4630-9558-669e3002026f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826690339 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.2826690339
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.691428254
Short name T30
Test name
Test status
Simulation time 48596251 ps
CPU time 1.29 seconds
Started Aug 15 06:33:51 PM PDT 24
Finished Aug 15 06:33:52 PM PDT 24
Peak memory 218812 kb
Host smart-2f485bff-2bda-4fde-b5d5-97c7dd6914c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691428254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.691428254
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_sec_cm.695526357
Short name T15
Test name
Test status
Simulation time 4176939284 ps
CPU time 6.12 seconds
Started Aug 15 06:32:05 PM PDT 24
Finished Aug 15 06:32:11 PM PDT 24
Peak memory 243692 kb
Host smart-0c93824a-4fac-47d0-8edb-ec8d601dc33b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695526357 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.695526357
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/186.edn_alert.3879460965
Short name T10
Test name
Test status
Simulation time 29601989 ps
CPU time 1.23 seconds
Started Aug 15 06:34:14 PM PDT 24
Finished Aug 15 06:34:16 PM PDT 24
Peak memory 219764 kb
Host smart-bc6c9545-5b16-45bf-9314-e23e475e439e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879460965 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.3879460965
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.606118586
Short name T45
Test name
Test status
Simulation time 47634229 ps
CPU time 1.73 seconds
Started Aug 15 06:34:04 PM PDT 24
Finished Aug 15 06:34:06 PM PDT 24
Peak memory 217324 kb
Host smart-bb8e3899-6a46-4fdc-a0ef-8ce7bd0e4765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606118586 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.606118586
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_sec_cm.1431971186
Short name T57
Test name
Test status
Simulation time 522813848 ps
CPU time 7.93 seconds
Started Aug 15 06:32:07 PM PDT 24
Finished Aug 15 06:32:15 PM PDT 24
Peak memory 243104 kb
Host smart-9fc24933-d148-44c1-8288-0cbb7fc83ce2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431971186 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.1431971186
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/19.edn_disable.2437282392
Short name T180
Test name
Test status
Simulation time 40668191 ps
CPU time 0.85 seconds
Started Aug 15 06:32:26 PM PDT 24
Finished Aug 15 06:32:27 PM PDT 24
Peak memory 215448 kb
Host smart-07b6fa78-c0d9-47a8-adcb-f9c4da19beb1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437282392 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2437282392
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/13.edn_err.3395179001
Short name T14
Test name
Test status
Simulation time 23550596 ps
CPU time 1.09 seconds
Started Aug 15 06:32:15 PM PDT 24
Finished Aug 15 06:32:16 PM PDT 24
Peak memory 223404 kb
Host smart-fef9f382-e21c-4901-a918-611485bb1d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395179001 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3395179001
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/9.edn_alert.2186116905
Short name T102
Test name
Test status
Simulation time 28089869 ps
CPU time 1.22 seconds
Started Aug 15 06:32:13 PM PDT 24
Finished Aug 15 06:32:14 PM PDT 24
Peak memory 220984 kb
Host smart-d4678581-dd87-4880-912c-a3c96634006d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186116905 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.2186116905
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.3265290210
Short name T8
Test name
Test status
Simulation time 39059432 ps
CPU time 1.23 seconds
Started Aug 15 06:33:27 PM PDT 24
Finished Aug 15 06:33:28 PM PDT 24
Peak memory 220136 kb
Host smart-16a2b35d-c160-4b0b-aebf-a20e913c81ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265290210 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.3265290210
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.2744627105
Short name T3
Test name
Test status
Simulation time 119765072 ps
CPU time 1.11 seconds
Started Aug 15 06:32:42 PM PDT 24
Finished Aug 15 06:32:44 PM PDT 24
Peak memory 216744 kb
Host smart-e8247b85-3202-4b3c-9c7e-114101adf949
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744627105 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.2744627105
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/125.edn_alert.4079158142
Short name T308
Test name
Test status
Simulation time 49783709 ps
CPU time 1.26 seconds
Started Aug 15 06:33:57 PM PDT 24
Finished Aug 15 06:33:58 PM PDT 24
Peak memory 219876 kb
Host smart-389cd1ef-3a1d-4977-b16a-c622f1532198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079158142 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.4079158142
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3196415645
Short name T4
Test name
Test status
Simulation time 7519703783 ps
CPU time 38.3 seconds
Started Aug 15 06:32:38 PM PDT 24
Finished Aug 15 06:33:17 PM PDT 24
Peak memory 221644 kb
Host smart-d3444a7c-d943-4557-b06f-6178c3b4a5fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196415645 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3196415645
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/118.edn_alert.3906995025
Short name T159
Test name
Test status
Simulation time 43545145 ps
CPU time 1.09 seconds
Started Aug 15 06:33:50 PM PDT 24
Finished Aug 15 06:33:52 PM PDT 24
Peak memory 218944 kb
Host smart-5194631d-11e2-4eaf-a0da-27bb97282525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906995025 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.3906995025
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2608978381
Short name T271
Test name
Test status
Simulation time 86663000 ps
CPU time 2.49 seconds
Started Aug 15 06:37:35 PM PDT 24
Finished Aug 15 06:37:38 PM PDT 24
Peak memory 215340 kb
Host smart-24909456-8549-4437-b004-a8ac166789bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608978381 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.2608978381
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/default/166.edn_alert.3464227935
Short name T105
Test name
Test status
Simulation time 162779031 ps
CPU time 1.21 seconds
Started Aug 15 06:33:59 PM PDT 24
Finished Aug 15 06:34:00 PM PDT 24
Peak memory 218720 kb
Host smart-faec6e39-66da-4b6b-8dc8-daffeda6b503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464227935 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.3464227935
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/38.edn_disable.1103560800
Short name T78
Test name
Test status
Simulation time 26274948 ps
CPU time 0.86 seconds
Started Aug 15 06:33:00 PM PDT 24
Finished Aug 15 06:33:01 PM PDT 24
Peak memory 215456 kb
Host smart-688a93a0-8c61-4da2-aa32-58fa3ef557c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103560800 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1103560800
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/140.edn_alert.1926820502
Short name T153
Test name
Test status
Simulation time 69458805 ps
CPU time 1.19 seconds
Started Aug 15 06:33:46 PM PDT 24
Finished Aug 15 06:33:48 PM PDT 24
Peak memory 218728 kb
Host smart-beb747ab-612b-413b-90f3-1682fe977625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926820502 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.1926820502
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/12.edn_disable.1802417150
Short name T194
Test name
Test status
Simulation time 38942919 ps
CPU time 0.88 seconds
Started Aug 15 06:32:13 PM PDT 24
Finished Aug 15 06:32:14 PM PDT 24
Peak memory 215456 kb
Host smart-097070e0-dc5e-4256-90ab-166e0865951c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802417150 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1802417150
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable.3464546804
Short name T212
Test name
Test status
Simulation time 19502904 ps
CPU time 0.92 seconds
Started Aug 15 06:32:55 PM PDT 24
Finished Aug 15 06:32:56 PM PDT 24
Peak memory 215452 kb
Host smart-871519b7-ad30-40de-9813-aa39fefea613
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464546804 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3464546804
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.2745698830
Short name T144
Test name
Test status
Simulation time 47489344 ps
CPU time 1.12 seconds
Started Aug 15 06:32:36 PM PDT 24
Finished Aug 15 06:32:37 PM PDT 24
Peak memory 216964 kb
Host smart-0fb87bd7-54e4-418b-b184-f2c1b3e5c12f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745698830 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.2745698830
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.3144235869
Short name T119
Test name
Test status
Simulation time 71277428 ps
CPU time 1.12 seconds
Started Aug 15 06:33:09 PM PDT 24
Finished Aug 15 06:33:11 PM PDT 24
Peak memory 217032 kb
Host smart-f896a696-a01e-46f6-bcbe-54f8ef09aa31
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144235869 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.3144235869
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.4024025841
Short name T250
Test name
Test status
Simulation time 47103822 ps
CPU time 0.9 seconds
Started Aug 15 06:37:45 PM PDT 24
Finished Aug 15 06:37:46 PM PDT 24
Peak memory 207064 kb
Host smart-ab8870ea-8bfa-462e-a879-5e489ce63f0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024025841 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.4024025841
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/default/42.edn_stress_all.69399228
Short name T306
Test name
Test status
Simulation time 397414727 ps
CPU time 3.22 seconds
Started Aug 15 06:32:58 PM PDT 24
Finished Aug 15 06:33:02 PM PDT 24
Peak memory 215336 kb
Host smart-28341342-6a8a-4092-9c57-94591f4b7468
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69399228 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.69399228
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2777519906
Short name T38
Test name
Test status
Simulation time 2180791289 ps
CPU time 30.61 seconds
Started Aug 15 06:32:29 PM PDT 24
Finished Aug 15 06:33:00 PM PDT 24
Peak memory 218680 kb
Host smart-f609664d-5871-4d18-a6b7-58ab2b26b579
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777519906 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2777519906
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.2187371049
Short name T183
Test name
Test status
Simulation time 24037045 ps
CPU time 1.24 seconds
Started Aug 15 06:34:01 PM PDT 24
Finished Aug 15 06:34:03 PM PDT 24
Peak memory 219800 kb
Host smart-591a63a6-0bbe-40c0-8fbe-7e10f752de1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187371049 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.2187371049
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/107.edn_alert.2605792845
Short name T128
Test name
Test status
Simulation time 40981243 ps
CPU time 1.19 seconds
Started Aug 15 06:33:38 PM PDT 24
Finished Aug 15 06:33:39 PM PDT 24
Peak memory 218760 kb
Host smart-e616a7d2-34a8-4820-a759-1ce1b81fa08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605792845 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.2605792845
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/116.edn_alert.881052205
Short name T140
Test name
Test status
Simulation time 27351465 ps
CPU time 1.18 seconds
Started Aug 15 06:33:43 PM PDT 24
Finished Aug 15 06:33:45 PM PDT 24
Peak memory 220868 kb
Host smart-c538f989-d68a-4deb-8c04-05de01c8de30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881052205 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.881052205
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/26.edn_intr.2652140352
Short name T87
Test name
Test status
Simulation time 38413017 ps
CPU time 0.88 seconds
Started Aug 15 06:32:45 PM PDT 24
Finished Aug 15 06:32:46 PM PDT 24
Peak memory 215760 kb
Host smart-760e4b2b-7fe4-4d17-a0d8-2a75ba263ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652140352 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2652140352
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/44.edn_err.2001343137
Short name T52
Test name
Test status
Simulation time 24979628 ps
CPU time 1.05 seconds
Started Aug 15 06:33:10 PM PDT 24
Finished Aug 15 06:33:11 PM PDT 24
Peak memory 224124 kb
Host smart-f66cab9a-5a43-4037-95f9-a0644bdf97d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001343137 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.2001343137
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/30.edn_alert.3573801821
Short name T352
Test name
Test status
Simulation time 48513046 ps
CPU time 1.22 seconds
Started Aug 15 06:32:53 PM PDT 24
Finished Aug 15 06:32:54 PM PDT 24
Peak memory 220892 kb
Host smart-52f5bf72-fc61-4061-93fb-de838a0f9483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573801821 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.3573801821
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.3724676466
Short name T276
Test name
Test status
Simulation time 32392888 ps
CPU time 1.28 seconds
Started Aug 15 06:33:42 PM PDT 24
Finished Aug 15 06:33:43 PM PDT 24
Peak memory 218716 kb
Host smart-7a498a2f-f6b9-401d-aa21-e88e363323f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724676466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.3724676466
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_disable.3024992855
Short name T207
Test name
Test status
Simulation time 18938369 ps
CPU time 0.87 seconds
Started Aug 15 06:31:59 PM PDT 24
Finished Aug 15 06:32:00 PM PDT 24
Peak memory 215420 kb
Host smart-496443c6-7df7-4991-8310-0d52459882a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024992855 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3024992855
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/196.edn_alert.982829710
Short name T811
Test name
Test status
Simulation time 46207157 ps
CPU time 1.14 seconds
Started Aug 15 06:34:14 PM PDT 24
Finished Aug 15 06:34:16 PM PDT 24
Peak memory 215740 kb
Host smart-7d4d45e8-edfb-4637-9e86-197884a15ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982829710 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.982829710
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2964110679
Short name T68
Test name
Test status
Simulation time 254462864 ps
CPU time 1.03 seconds
Started Aug 15 06:33:09 PM PDT 24
Finished Aug 15 06:33:10 PM PDT 24
Peak memory 216888 kb
Host smart-dcd8e4ab-e4ce-473a-80ac-43838d2c3be6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964110679 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2964110679
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3634219184
Short name T40
Test name
Test status
Simulation time 315797396 ps
CPU time 1.19 seconds
Started Aug 15 06:32:16 PM PDT 24
Finished Aug 15 06:32:17 PM PDT 24
Peak memory 216852 kb
Host smart-e809ad59-deff-4cd2-a9e4-6e224aa1295b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634219184 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3634219184
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_alert.1470399585
Short name T928
Test name
Test status
Simulation time 34691179 ps
CPU time 1.19 seconds
Started Aug 15 06:32:11 PM PDT 24
Finished Aug 15 06:32:12 PM PDT 24
Peak memory 219896 kb
Host smart-e857be7e-5d44-4533-a361-32c9b6489961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470399585 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.1470399585
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_disable.1957617742
Short name T202
Test name
Test status
Simulation time 19316757 ps
CPU time 0.87 seconds
Started Aug 15 06:32:13 PM PDT 24
Finished Aug 15 06:32:14 PM PDT 24
Peak memory 215448 kb
Host smart-e50f1b34-5f6c-4616-a131-e894d0462663
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957617742 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.1957617742
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/110.edn_alert.3512774077
Short name T721
Test name
Test status
Simulation time 33213776 ps
CPU time 1.29 seconds
Started Aug 15 06:33:45 PM PDT 24
Finished Aug 15 06:33:46 PM PDT 24
Peak memory 220620 kb
Host smart-0d2608c0-390e-43e1-b3a6-1a3675e9819b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512774077 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.3512774077
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/114.edn_alert.3589830078
Short name T96
Test name
Test status
Simulation time 25592837 ps
CPU time 1.22 seconds
Started Aug 15 06:33:41 PM PDT 24
Finished Aug 15 06:33:42 PM PDT 24
Peak memory 219860 kb
Host smart-1b0e5c68-4c31-4b4a-85f5-459c19084264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589830078 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.3589830078
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/129.edn_alert.851719301
Short name T521
Test name
Test status
Simulation time 66696137 ps
CPU time 1.04 seconds
Started Aug 15 06:33:58 PM PDT 24
Finished Aug 15 06:33:59 PM PDT 24
Peak memory 219612 kb
Host smart-af0c015e-1a18-4ccd-83dc-4153e59d11a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851719301 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.851719301
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/144.edn_alert.500138359
Short name T145
Test name
Test status
Simulation time 23666294 ps
CPU time 1.2 seconds
Started Aug 15 06:34:00 PM PDT 24
Finished Aug 15 06:34:01 PM PDT 24
Peak memory 218796 kb
Host smart-3bbad143-c6ab-4e81-aa05-c1010fc9266c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500138359 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.500138359
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/26.edn_err.1577515624
Short name T192
Test name
Test status
Simulation time 31173588 ps
CPU time 0.97 seconds
Started Aug 15 06:32:43 PM PDT 24
Finished Aug 15 06:32:44 PM PDT 24
Peak memory 219484 kb
Host smart-7c56f386-1def-4c8e-9dd2-62d0c197241c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577515624 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1577515624
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/30.edn_err.2095962100
Short name T182
Test name
Test status
Simulation time 19385322 ps
CPU time 1.03 seconds
Started Aug 15 06:32:50 PM PDT 24
Finished Aug 15 06:32:52 PM PDT 24
Peak memory 215356 kb
Host smart-50dedf66-3957-4e58-a75d-7b2029c4a2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095962100 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.2095962100
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/36.edn_disable.2334576359
Short name T196
Test name
Test status
Simulation time 42531237 ps
CPU time 0.88 seconds
Started Aug 15 06:32:54 PM PDT 24
Finished Aug 15 06:32:55 PM PDT 24
Peak memory 215412 kb
Host smart-f52b0637-1183-4489-9580-aed05ad4a275
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334576359 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2334576359
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/267.edn_genbits.1549162289
Short name T287
Test name
Test status
Simulation time 38844720 ps
CPU time 1.66 seconds
Started Aug 15 06:34:12 PM PDT 24
Finished Aug 15 06:34:14 PM PDT 24
Peak memory 218796 kb
Host smart-35050c7d-aa9f-47e5-afe5-8650af0eea4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549162289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1549162289
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.1036359151
Short name T72
Test name
Test status
Simulation time 50389249 ps
CPU time 1.02 seconds
Started Aug 15 06:33:57 PM PDT 24
Finished Aug 15 06:33:59 PM PDT 24
Peak memory 217380 kb
Host smart-54af8d56-5842-471d-b82f-561b81f5c897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036359151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1036359151
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.2527957551
Short name T73
Test name
Test status
Simulation time 37885104 ps
CPU time 1.35 seconds
Started Aug 15 06:34:07 PM PDT 24
Finished Aug 15 06:34:09 PM PDT 24
Peak memory 218472 kb
Host smart-e23da6d0-05d9-4ffe-9094-6a260b67dd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527957551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.2527957551
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert_test.3944026131
Short name T64
Test name
Test status
Simulation time 30579300 ps
CPU time 0.99 seconds
Started Aug 15 06:32:14 PM PDT 24
Finished Aug 15 06:32:15 PM PDT 24
Peak memory 205612 kb
Host smart-01451472-8434-4817-93bc-2d939b201e33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944026131 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3944026131
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_stress_all.2916247460
Short name T286
Test name
Test status
Simulation time 149684338 ps
CPU time 1.44 seconds
Started Aug 15 06:32:20 PM PDT 24
Finished Aug 15 06:32:21 PM PDT 24
Peak memory 217180 kb
Host smart-bbf9a11d-7d02-441c-9eac-d8fe08c361fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916247460 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2916247460
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_intr.3014575210
Short name T89
Test name
Test status
Simulation time 34478138 ps
CPU time 0.89 seconds
Started Aug 15 06:31:58 PM PDT 24
Finished Aug 15 06:31:59 PM PDT 24
Peak memory 215740 kb
Host smart-5b955791-8c15-43ec-ab6d-90873078da50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014575210 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.3014575210
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/119.edn_genbits.2156775933
Short name T556
Test name
Test status
Simulation time 139615994 ps
CPU time 1.24 seconds
Started Aug 15 06:33:41 PM PDT 24
Finished Aug 15 06:33:42 PM PDT 24
Peak memory 217648 kb
Host smart-d34e1a48-105c-4fae-b651-e10b0032b7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156775933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.2156775933
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.668631537
Short name T787
Test name
Test status
Simulation time 285795612 ps
CPU time 1.57 seconds
Started Aug 15 06:33:53 PM PDT 24
Finished Aug 15 06:33:55 PM PDT 24
Peak memory 217512 kb
Host smart-989cd06b-703d-48c9-9347-481776c1291e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668631537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.668631537
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.1964198985
Short name T261
Test name
Test status
Simulation time 16945882 ps
CPU time 0.96 seconds
Started Aug 15 06:37:38 PM PDT 24
Finished Aug 15 06:37:39 PM PDT 24
Peak memory 207016 kb
Host smart-2b54faeb-bab5-4237-93d6-f5d4e1c57080
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964198985 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1964198985
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1683875338
Short name T281
Test name
Test status
Simulation time 163484836 ps
CPU time 2.28 seconds
Started Aug 15 06:37:47 PM PDT 24
Finished Aug 15 06:37:50 PM PDT 24
Peak memory 207300 kb
Host smart-db30b644-0e65-446d-bd25-dbb58ef9eb0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683875338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1683875338
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/default/10.edn_stress_all.2156110603
Short name T540
Test name
Test status
Simulation time 92630307 ps
CPU time 1.21 seconds
Started Aug 15 06:32:13 PM PDT 24
Finished Aug 15 06:32:14 PM PDT 24
Peak memory 217480 kb
Host smart-ad13b3d1-7d63-4222-8f82-af95b4a589ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156110603 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.2156110603
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/104.edn_genbits.999315254
Short name T751
Test name
Test status
Simulation time 43176993 ps
CPU time 1.59 seconds
Started Aug 15 06:33:36 PM PDT 24
Finished Aug 15 06:33:38 PM PDT 24
Peak memory 217740 kb
Host smart-a0d0b35e-e2ea-401e-a16c-dd7b1c70ad64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999315254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.999315254
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.762310708
Short name T295
Test name
Test status
Simulation time 92064260 ps
CPU time 1.61 seconds
Started Aug 15 06:33:41 PM PDT 24
Finished Aug 15 06:33:43 PM PDT 24
Peak memory 218772 kb
Host smart-887898cb-f8a8-4904-80dd-0b9a992117aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762310708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.762310708
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.568108050
Short name T263
Test name
Test status
Simulation time 188146784 ps
CPU time 2.52 seconds
Started Aug 15 06:33:40 PM PDT 24
Finished Aug 15 06:33:42 PM PDT 24
Peak memory 220644 kb
Host smart-99d37bbf-4e94-4062-9f6a-acfb9d2a3fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568108050 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.568108050
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/140.edn_genbits.478338820
Short name T284
Test name
Test status
Simulation time 66896242 ps
CPU time 1.68 seconds
Started Aug 15 06:33:57 PM PDT 24
Finished Aug 15 06:33:59 PM PDT 24
Peak memory 218948 kb
Host smart-347e8b8c-d05b-4b8a-9349-05e1f9421921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478338820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.478338820
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.2675995559
Short name T906
Test name
Test status
Simulation time 43538461 ps
CPU time 1.63 seconds
Started Aug 15 06:33:59 PM PDT 24
Finished Aug 15 06:34:00 PM PDT 24
Peak memory 218824 kb
Host smart-271ad747-3194-4283-a95a-6dfa1ec7c592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675995559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2675995559
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.2709300773
Short name T299
Test name
Test status
Simulation time 73559176 ps
CPU time 1.8 seconds
Started Aug 15 06:34:08 PM PDT 24
Finished Aug 15 06:34:10 PM PDT 24
Peak memory 220504 kb
Host smart-227ad094-5564-4573-ace7-46e52f036bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709300773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.2709300773
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_genbits.2882003602
Short name T12
Test name
Test status
Simulation time 37380904 ps
CPU time 1.17 seconds
Started Aug 15 06:32:58 PM PDT 24
Finished Aug 15 06:32:59 PM PDT 24
Peak memory 220452 kb
Host smart-501afac0-651e-44d1-aecc-56674dcab42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882003602 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.2882003602
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_genbits.2130329554
Short name T289
Test name
Test status
Simulation time 45980092 ps
CPU time 1.3 seconds
Started Aug 15 06:33:38 PM PDT 24
Finished Aug 15 06:33:40 PM PDT 24
Peak memory 217728 kb
Host smart-ee3df18f-e91b-4d0a-942e-988683c16572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130329554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2130329554
Directory /workspace/99.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.187091119
Short name T34
Test name
Test status
Simulation time 41560099 ps
CPU time 0.85 seconds
Started Aug 15 06:32:26 PM PDT 24
Finished Aug 15 06:32:27 PM PDT 24
Peak memory 215752 kb
Host smart-9a544c1d-072f-4f5d-b6d9-78ed579042a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187091119 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.187091119
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/12.edn_intr.272458773
Short name T110
Test name
Test status
Simulation time 20888930 ps
CPU time 1.09 seconds
Started Aug 15 06:32:13 PM PDT 24
Finished Aug 15 06:32:14 PM PDT 24
Peak memory 214596 kb
Host smart-7050cb75-f589-4ac4-8062-b6dc732827b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272458773 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.272458773
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/101.edn_alert.2322474812
Short name T955
Test name
Test status
Simulation time 31573515 ps
CPU time 1.25 seconds
Started Aug 15 06:33:36 PM PDT 24
Finished Aug 15 06:33:38 PM PDT 24
Peak memory 219880 kb
Host smart-c85a7438-f791-48ac-852c-32d56b73547a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322474812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.2322474812
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/133.edn_alert.2724958201
Short name T113
Test name
Test status
Simulation time 48084745 ps
CPU time 1.37 seconds
Started Aug 15 06:33:49 PM PDT 24
Finished Aug 15 06:33:50 PM PDT 24
Peak memory 215764 kb
Host smart-d8c74b66-1306-4bf1-95b7-880f4efd7d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724958201 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.2724958201
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.643109166
Short name T252
Test name
Test status
Simulation time 15504395 ps
CPU time 1.07 seconds
Started Aug 15 06:37:28 PM PDT 24
Finished Aug 15 06:37:29 PM PDT 24
Peak memory 207060 kb
Host smart-b23ecd10-cb33-4ae5-b73b-d960889c9a18
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643109166 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.643109166
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3477425336
Short name T967
Test name
Test status
Simulation time 533208930 ps
CPU time 3.69 seconds
Started Aug 15 06:37:32 PM PDT 24
Finished Aug 15 06:37:36 PM PDT 24
Peak memory 207008 kb
Host smart-c3f60ba8-ca65-4ffe-849e-380f83393562
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477425336 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3477425336
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.654724630
Short name T1091
Test name
Test status
Simulation time 53831740 ps
CPU time 0.92 seconds
Started Aug 15 06:37:26 PM PDT 24
Finished Aug 15 06:37:27 PM PDT 24
Peak memory 207016 kb
Host smart-85dfddef-29ae-41cf-8a02-3fcbef9a02f1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654724630 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.654724630
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2686339372
Short name T983
Test name
Test status
Simulation time 24874532 ps
CPU time 1.26 seconds
Started Aug 15 06:37:35 PM PDT 24
Finished Aug 15 06:37:37 PM PDT 24
Peak memory 223568 kb
Host smart-9dfadd02-4f65-473f-a2de-9efafabaa699
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686339372 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2686339372
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.820878325
Short name T987
Test name
Test status
Simulation time 31562975 ps
CPU time 0.78 seconds
Started Aug 15 06:37:35 PM PDT 24
Finished Aug 15 06:37:36 PM PDT 24
Peak memory 206760 kb
Host smart-17c2860a-f245-4cea-bf32-b117fcd9ce9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820878325 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.820878325
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1874727173
Short name T1008
Test name
Test status
Simulation time 509686759 ps
CPU time 1.33 seconds
Started Aug 15 06:37:31 PM PDT 24
Finished Aug 15 06:37:32 PM PDT 24
Peak memory 207196 kb
Host smart-ba3a3d09-f98f-449f-b157-89646d7e1079
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874727173 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.1874727173
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.1833653764
Short name T976
Test name
Test status
Simulation time 103752096 ps
CPU time 2.2 seconds
Started Aug 15 06:37:32 PM PDT 24
Finished Aug 15 06:37:35 PM PDT 24
Peak memory 215388 kb
Host smart-9ed277d3-456b-4c4a-b909-46f01b7b6719
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833653764 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1833653764
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3449044402
Short name T1046
Test name
Test status
Simulation time 434303773 ps
CPU time 1.66 seconds
Started Aug 15 06:37:26 PM PDT 24
Finished Aug 15 06:37:28 PM PDT 24
Peak memory 207060 kb
Host smart-03f1d964-2c82-4f90-86db-04c92ae04d4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449044402 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3449044402
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.215988583
Short name T1060
Test name
Test status
Simulation time 21529941 ps
CPU time 1.18 seconds
Started Aug 15 06:37:34 PM PDT 24
Finished Aug 15 06:37:35 PM PDT 24
Peak memory 207060 kb
Host smart-78126042-262b-4e0c-8749-98d50979a730
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215988583 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.215988583
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2695177481
Short name T254
Test name
Test status
Simulation time 229175254 ps
CPU time 3.35 seconds
Started Aug 15 06:37:25 PM PDT 24
Finished Aug 15 06:37:28 PM PDT 24
Peak memory 207108 kb
Host smart-f070970c-b2eb-4cb9-af1c-81741fb93512
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695177481 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2695177481
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3159540745
Short name T1025
Test name
Test status
Simulation time 15691550 ps
CPU time 0.92 seconds
Started Aug 15 06:37:24 PM PDT 24
Finished Aug 15 06:37:25 PM PDT 24
Peak memory 207056 kb
Host smart-1758f68e-bac2-4d41-9b6f-f5a7a09850ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159540745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3159540745
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2466360125
Short name T1030
Test name
Test status
Simulation time 79228258 ps
CPU time 1.18 seconds
Started Aug 15 06:37:30 PM PDT 24
Finished Aug 15 06:37:31 PM PDT 24
Peak memory 215336 kb
Host smart-2b42cae4-7fb4-43f2-913a-46dfb0f82148
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466360125 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2466360125
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.2244262718
Short name T1081
Test name
Test status
Simulation time 28997152 ps
CPU time 0.79 seconds
Started Aug 15 06:37:34 PM PDT 24
Finished Aug 15 06:37:35 PM PDT 24
Peak memory 206820 kb
Host smart-8242dd2f-56d0-4528-a594-fb884782eaed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244262718 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2244262718
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.862103484
Short name T1085
Test name
Test status
Simulation time 41026129 ps
CPU time 0.92 seconds
Started Aug 15 06:37:30 PM PDT 24
Finished Aug 15 06:37:31 PM PDT 24
Peak memory 206972 kb
Host smart-aad4202c-2ca3-4ee1-b3f0-f5a768756adc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862103484 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.862103484
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.4223234510
Short name T1014
Test name
Test status
Simulation time 36387546 ps
CPU time 1.04 seconds
Started Aug 15 06:37:36 PM PDT 24
Finished Aug 15 06:37:37 PM PDT 24
Peak memory 207172 kb
Host smart-0950b33b-aea9-4673-82af-572953e72a11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223234510 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.4223234510
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.3637190591
Short name T1106
Test name
Test status
Simulation time 48978834 ps
CPU time 1.75 seconds
Started Aug 15 06:37:31 PM PDT 24
Finished Aug 15 06:37:33 PM PDT 24
Peak memory 215348 kb
Host smart-85ba923a-fd54-4155-b7e7-5c9781139e7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637190591 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3637190591
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.759605216
Short name T1054
Test name
Test status
Simulation time 248467705 ps
CPU time 2.01 seconds
Started Aug 15 06:37:35 PM PDT 24
Finished Aug 15 06:37:38 PM PDT 24
Peak memory 207056 kb
Host smart-6374359e-dfa2-44f9-9550-3abe0c2a4578
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759605216 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.759605216
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.4040620178
Short name T968
Test name
Test status
Simulation time 38729580 ps
CPU time 1.34 seconds
Started Aug 15 06:37:50 PM PDT 24
Finished Aug 15 06:37:51 PM PDT 24
Peak memory 215328 kb
Host smart-c81462a4-2320-45f5-8069-a8f0d5347d64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040620178 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.4040620178
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.3569997075
Short name T255
Test name
Test status
Simulation time 16599306 ps
CPU time 0.93 seconds
Started Aug 15 06:37:51 PM PDT 24
Finished Aug 15 06:37:52 PM PDT 24
Peak memory 207048 kb
Host smart-4a3db052-95db-42dc-91d8-0926496ff8a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569997075 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3569997075
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.3248575157
Short name T1065
Test name
Test status
Simulation time 120232169 ps
CPU time 0.88 seconds
Started Aug 15 06:37:35 PM PDT 24
Finished Aug 15 06:37:36 PM PDT 24
Peak memory 206948 kb
Host smart-5596bd93-d3f7-43b5-8132-03a965f3e7cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248575157 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.3248575157
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3065641958
Short name T235
Test name
Test status
Simulation time 21908307 ps
CPU time 1.07 seconds
Started Aug 15 06:37:38 PM PDT 24
Finished Aug 15 06:37:39 PM PDT 24
Peak memory 207160 kb
Host smart-6fc18cf0-c4d5-4334-8993-9122526ffdec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065641958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.3065641958
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1269037168
Short name T1022
Test name
Test status
Simulation time 63070364 ps
CPU time 2.78 seconds
Started Aug 15 06:37:38 PM PDT 24
Finished Aug 15 06:37:41 PM PDT 24
Peak memory 215304 kb
Host smart-46c962f8-8cfe-4df0-a5ee-f83ff3328fd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269037168 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1269037168
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.781144379
Short name T1093
Test name
Test status
Simulation time 77966200 ps
CPU time 2.39 seconds
Started Aug 15 06:37:44 PM PDT 24
Finished Aug 15 06:37:47 PM PDT 24
Peak memory 207160 kb
Host smart-6014562e-f4fa-47f7-91d0-fce1def0e39f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781144379 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.781144379
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.4007263592
Short name T1088
Test name
Test status
Simulation time 113091886 ps
CPU time 1.44 seconds
Started Aug 15 06:37:42 PM PDT 24
Finished Aug 15 06:37:44 PM PDT 24
Peak memory 215436 kb
Host smart-b3554b5a-0acc-4a52-86e2-b4f4b618e442
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007263592 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.4007263592
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.1649720372
Short name T1067
Test name
Test status
Simulation time 16339135 ps
CPU time 0.91 seconds
Started Aug 15 06:37:38 PM PDT 24
Finished Aug 15 06:37:39 PM PDT 24
Peak memory 207028 kb
Host smart-6cf469c0-42a2-40b7-9832-77f27e935672
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649720372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1649720372
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.3830093184
Short name T1015
Test name
Test status
Simulation time 14850731 ps
CPU time 0.91 seconds
Started Aug 15 06:37:39 PM PDT 24
Finished Aug 15 06:37:40 PM PDT 24
Peak memory 207160 kb
Host smart-240d18f8-137b-45aa-9dfc-40dfceca0ead
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830093184 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.3830093184
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2097471344
Short name T1036
Test name
Test status
Simulation time 44186139 ps
CPU time 0.98 seconds
Started Aug 15 06:37:49 PM PDT 24
Finished Aug 15 06:37:50 PM PDT 24
Peak memory 207128 kb
Host smart-8b9543f4-6d88-4adc-89e8-165346ed2042
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097471344 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2097471344
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.3006501665
Short name T1050
Test name
Test status
Simulation time 98311503 ps
CPU time 2.61 seconds
Started Aug 15 06:37:41 PM PDT 24
Finished Aug 15 06:37:44 PM PDT 24
Peak memory 215368 kb
Host smart-674ec8ce-29aa-4509-b4bf-ec9d54b4aa9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006501665 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3006501665
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3835650359
Short name T996
Test name
Test status
Simulation time 87767196 ps
CPU time 1.66 seconds
Started Aug 15 06:37:44 PM PDT 24
Finished Aug 15 06:37:46 PM PDT 24
Peak memory 207128 kb
Host smart-6d39a0f1-0abb-4fe9-994c-395653779036
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835650359 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.3835650359
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.702690634
Short name T978
Test name
Test status
Simulation time 37548395 ps
CPU time 1.33 seconds
Started Aug 15 06:37:46 PM PDT 24
Finished Aug 15 06:37:48 PM PDT 24
Peak memory 218136 kb
Host smart-a0c99ab5-b73b-4b4f-9a98-969bf20c7caf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702690634 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.702690634
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2455199940
Short name T1005
Test name
Test status
Simulation time 10740516 ps
CPU time 0.96 seconds
Started Aug 15 06:37:44 PM PDT 24
Finished Aug 15 06:37:45 PM PDT 24
Peak memory 207040 kb
Host smart-4193b52e-1f7e-411b-9899-13565942502b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455199940 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2455199940
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2921835216
Short name T1092
Test name
Test status
Simulation time 48117515 ps
CPU time 0.87 seconds
Started Aug 15 06:37:36 PM PDT 24
Finished Aug 15 06:37:37 PM PDT 24
Peak memory 206980 kb
Host smart-906a6e02-085f-4d9d-9b81-9981499c6306
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921835216 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2921835216
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3777276942
Short name T256
Test name
Test status
Simulation time 43889847 ps
CPU time 0.95 seconds
Started Aug 15 06:37:45 PM PDT 24
Finished Aug 15 06:37:46 PM PDT 24
Peak memory 207112 kb
Host smart-de44b4ac-9599-4fe8-90d2-16c37a5c29ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777276942 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.3777276942
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.2952290278
Short name T1073
Test name
Test status
Simulation time 267452248 ps
CPU time 2.87 seconds
Started Aug 15 06:37:49 PM PDT 24
Finished Aug 15 06:37:53 PM PDT 24
Peak memory 215248 kb
Host smart-7604e1c5-5919-4019-bbab-64a1e9812ae5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952290278 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.2952290278
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1389516798
Short name T273
Test name
Test status
Simulation time 203610134 ps
CPU time 4.13 seconds
Started Aug 15 06:37:41 PM PDT 24
Finished Aug 15 06:37:46 PM PDT 24
Peak memory 207112 kb
Host smart-50abb572-bf37-4c91-8f9d-d5728e85a535
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389516798 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.1389516798
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.463348836
Short name T1097
Test name
Test status
Simulation time 31739234 ps
CPU time 1.43 seconds
Started Aug 15 06:37:38 PM PDT 24
Finished Aug 15 06:37:39 PM PDT 24
Peak memory 218016 kb
Host smart-3502cf75-e3a9-40c7-90f9-ed8545dd1c24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463348836 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.463348836
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.1936064446
Short name T1038
Test name
Test status
Simulation time 13606729 ps
CPU time 0.85 seconds
Started Aug 15 06:37:41 PM PDT 24
Finished Aug 15 06:37:42 PM PDT 24
Peak memory 207048 kb
Host smart-b7d8fd24-e61c-468a-9f4d-e2c41b866c3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936064446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1936064446
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.1350388211
Short name T1043
Test name
Test status
Simulation time 12855946 ps
CPU time 0.85 seconds
Started Aug 15 06:37:40 PM PDT 24
Finished Aug 15 06:37:41 PM PDT 24
Peak memory 206920 kb
Host smart-0e4ffb8b-7933-44fd-a9d6-911812ecabc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350388211 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1350388211
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2929117527
Short name T1100
Test name
Test status
Simulation time 48740580 ps
CPU time 1.27 seconds
Started Aug 15 06:37:41 PM PDT 24
Finished Aug 15 06:37:43 PM PDT 24
Peak memory 207200 kb
Host smart-a3f251f2-e705-4bf1-aac3-3e90b7bd2e17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929117527 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2929117527
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.1113958539
Short name T980
Test name
Test status
Simulation time 42912323 ps
CPU time 1.7 seconds
Started Aug 15 06:37:40 PM PDT 24
Finished Aug 15 06:37:42 PM PDT 24
Peak memory 215328 kb
Host smart-6c8ca345-53d4-4a31-b589-743a73093fdd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113958539 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1113958539
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2209504729
Short name T995
Test name
Test status
Simulation time 91086236 ps
CPU time 1.54 seconds
Started Aug 15 06:37:47 PM PDT 24
Finished Aug 15 06:37:49 PM PDT 24
Peak memory 215312 kb
Host smart-bd36a90e-e871-42cb-9c3d-7b6c10df01fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209504729 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2209504729
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2294475096
Short name T989
Test name
Test status
Simulation time 29609609 ps
CPU time 1 seconds
Started Aug 15 06:37:50 PM PDT 24
Finished Aug 15 06:37:52 PM PDT 24
Peak memory 207172 kb
Host smart-0173d997-8ac6-4042-83ff-6a49aa98cb59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294475096 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2294475096
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1098974265
Short name T1086
Test name
Test status
Simulation time 50483801 ps
CPU time 0.91 seconds
Started Aug 15 06:38:11 PM PDT 24
Finished Aug 15 06:38:12 PM PDT 24
Peak memory 206960 kb
Host smart-2d9bc11d-2526-438a-9a5a-d31c11816237
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098974265 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1098974265
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.1719779004
Short name T965
Test name
Test status
Simulation time 49966445 ps
CPU time 0.87 seconds
Started Aug 15 06:37:41 PM PDT 24
Finished Aug 15 06:37:42 PM PDT 24
Peak memory 206908 kb
Host smart-40e3d1a1-a5ba-4e57-a82a-8a4e87498032
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719779004 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.1719779004
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3672350036
Short name T1002
Test name
Test status
Simulation time 24970250 ps
CPU time 1.02 seconds
Started Aug 15 06:37:53 PM PDT 24
Finished Aug 15 06:37:54 PM PDT 24
Peak memory 207036 kb
Host smart-d46eadb5-3f5f-4da4-8054-d0342b89c746
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672350036 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.3672350036
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.1200901350
Short name T1058
Test name
Test status
Simulation time 42665146 ps
CPU time 2.91 seconds
Started Aug 15 06:37:34 PM PDT 24
Finished Aug 15 06:37:38 PM PDT 24
Peak memory 215280 kb
Host smart-4ff547af-afad-482d-9668-6475d6fd897d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200901350 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1200901350
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1489260167
Short name T1096
Test name
Test status
Simulation time 223410339 ps
CPU time 1.19 seconds
Started Aug 15 06:37:42 PM PDT 24
Finished Aug 15 06:37:44 PM PDT 24
Peak memory 215332 kb
Host smart-4ea0a2f2-1a59-4014-a84c-f4e8936ca2af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489260167 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1489260167
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2743714908
Short name T1061
Test name
Test status
Simulation time 65845406 ps
CPU time 0.86 seconds
Started Aug 15 06:37:54 PM PDT 24
Finished Aug 15 06:37:55 PM PDT 24
Peak memory 206844 kb
Host smart-851ef672-1437-4f93-875b-2348e345a32c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743714908 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2743714908
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.1829258528
Short name T1064
Test name
Test status
Simulation time 26808423 ps
CPU time 0.92 seconds
Started Aug 15 06:37:55 PM PDT 24
Finished Aug 15 06:37:56 PM PDT 24
Peak memory 206960 kb
Host smart-37f5ff18-221a-48dd-8132-0589b6363ba1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829258528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1829258528
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3400275071
Short name T1102
Test name
Test status
Simulation time 48953546 ps
CPU time 0.93 seconds
Started Aug 15 06:37:45 PM PDT 24
Finished Aug 15 06:37:46 PM PDT 24
Peak memory 207072 kb
Host smart-cee01eff-73c3-44e6-8fd7-82e060bf578e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400275071 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.3400275071
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.645283239
Short name T1001
Test name
Test status
Simulation time 57221858 ps
CPU time 2.17 seconds
Started Aug 15 06:37:41 PM PDT 24
Finished Aug 15 06:37:44 PM PDT 24
Peak memory 215356 kb
Host smart-ada06086-59b8-4dea-84bb-ded374c784eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645283239 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.645283239
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3727706682
Short name T966
Test name
Test status
Simulation time 100820483 ps
CPU time 0.98 seconds
Started Aug 15 06:38:11 PM PDT 24
Finished Aug 15 06:38:12 PM PDT 24
Peak memory 207144 kb
Host smart-4ef7f881-cda1-44d6-aeb0-3f31a11a87ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727706682 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3727706682
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.2272132329
Short name T248
Test name
Test status
Simulation time 41914010 ps
CPU time 0.85 seconds
Started Aug 15 06:37:39 PM PDT 24
Finished Aug 15 06:37:40 PM PDT 24
Peak memory 207028 kb
Host smart-35a18e8b-f722-443e-bbb2-c70e7e672f44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272132329 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.2272132329
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.1364401839
Short name T1055
Test name
Test status
Simulation time 43171205 ps
CPU time 0.83 seconds
Started Aug 15 06:37:54 PM PDT 24
Finished Aug 15 06:37:55 PM PDT 24
Peak memory 206756 kb
Host smart-08412de7-5650-466a-b38b-88260da28745
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364401839 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.1364401839
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.332187066
Short name T260
Test name
Test status
Simulation time 134915155 ps
CPU time 1.37 seconds
Started Aug 15 06:37:42 PM PDT 24
Finished Aug 15 06:37:44 PM PDT 24
Peak memory 207124 kb
Host smart-e9572ca8-b79f-405a-86b5-f0aa92181c76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332187066 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_ou
tstanding.332187066
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.2673883850
Short name T973
Test name
Test status
Simulation time 158049127 ps
CPU time 2.86 seconds
Started Aug 15 06:37:56 PM PDT 24
Finished Aug 15 06:37:59 PM PDT 24
Peak memory 215320 kb
Host smart-cccb1aa2-5f64-4d0a-890a-8cd8cf39211f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673883850 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.2673883850
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.20604698
Short name T985
Test name
Test status
Simulation time 42407361 ps
CPU time 1.57 seconds
Started Aug 15 06:37:52 PM PDT 24
Finished Aug 15 06:37:54 PM PDT 24
Peak memory 207184 kb
Host smart-536e8dcb-7c5a-4fba-b0ce-0af27b3c6463
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20604698 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.20604698
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1366284394
Short name T1049
Test name
Test status
Simulation time 28293567 ps
CPU time 1.22 seconds
Started Aug 15 06:37:45 PM PDT 24
Finished Aug 15 06:37:46 PM PDT 24
Peak memory 215300 kb
Host smart-48af5eb7-af9e-4421-b4f0-ec988231bad2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366284394 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.1366284394
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.2846101390
Short name T1074
Test name
Test status
Simulation time 44491800 ps
CPU time 0.92 seconds
Started Aug 15 06:38:02 PM PDT 24
Finished Aug 15 06:38:03 PM PDT 24
Peak memory 206960 kb
Host smart-1bab7779-f21c-466b-b150-5f8150d60e1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846101390 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2846101390
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.606760365
Short name T1035
Test name
Test status
Simulation time 14104857 ps
CPU time 0.9 seconds
Started Aug 15 06:37:53 PM PDT 24
Finished Aug 15 06:37:54 PM PDT 24
Peak memory 206972 kb
Host smart-1c5675d8-4516-4785-ac42-1fc47c285cf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606760365 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.606760365
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2430645064
Short name T1063
Test name
Test status
Simulation time 119841255 ps
CPU time 1.05 seconds
Started Aug 15 06:38:00 PM PDT 24
Finished Aug 15 06:38:01 PM PDT 24
Peak memory 207120 kb
Host smart-7eb45c42-6201-485e-9221-63c49eb3b263
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430645064 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.2430645064
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.2379061687
Short name T1023
Test name
Test status
Simulation time 110064961 ps
CPU time 4.02 seconds
Started Aug 15 06:37:54 PM PDT 24
Finished Aug 15 06:37:58 PM PDT 24
Peak memory 215296 kb
Host smart-dab30bf2-27de-4eb2-bc8d-c3b37d54bb10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379061687 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2379061687
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1603581716
Short name T1009
Test name
Test status
Simulation time 369255186 ps
CPU time 2.54 seconds
Started Aug 15 06:37:42 PM PDT 24
Finished Aug 15 06:37:45 PM PDT 24
Peak memory 207232 kb
Host smart-e2edf88a-1034-4500-9520-e5f4c8001714
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603581716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.1603581716
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1068429895
Short name T1083
Test name
Test status
Simulation time 103530239 ps
CPU time 1.91 seconds
Started Aug 15 06:37:46 PM PDT 24
Finished Aug 15 06:37:50 PM PDT 24
Peak memory 215456 kb
Host smart-7d272c42-4f1e-4205-92cc-77b4b1487a3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068429895 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1068429895
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.909805638
Short name T1041
Test name
Test status
Simulation time 27418990 ps
CPU time 0.94 seconds
Started Aug 15 06:37:44 PM PDT 24
Finished Aug 15 06:37:45 PM PDT 24
Peak memory 206980 kb
Host smart-709174da-4215-4dfa-b8bb-6d7494b5846c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909805638 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.909805638
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.1662146003
Short name T1082
Test name
Test status
Simulation time 26549041 ps
CPU time 0.9 seconds
Started Aug 15 06:37:56 PM PDT 24
Finished Aug 15 06:37:57 PM PDT 24
Peak memory 206972 kb
Host smart-ad48ff36-d76d-416b-87ee-629678764e9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662146003 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.1662146003
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1744506580
Short name T1039
Test name
Test status
Simulation time 44045626 ps
CPU time 0.94 seconds
Started Aug 15 06:37:58 PM PDT 24
Finished Aug 15 06:37:59 PM PDT 24
Peak memory 207188 kb
Host smart-3c2d3a1a-3fa0-4553-bc7e-d03464abea89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744506580 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.1744506580
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.898365649
Short name T969
Test name
Test status
Simulation time 29698104 ps
CPU time 2.02 seconds
Started Aug 15 06:37:45 PM PDT 24
Finished Aug 15 06:37:47 PM PDT 24
Peak memory 215308 kb
Host smart-91b8c44c-6393-4035-9bd9-36bcde8c1f60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898365649 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.898365649
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1061061923
Short name T1078
Test name
Test status
Simulation time 66257240 ps
CPU time 1.65 seconds
Started Aug 15 06:37:50 PM PDT 24
Finished Aug 15 06:37:52 PM PDT 24
Peak memory 207128 kb
Host smart-4b78c7fa-cd78-4409-b981-404a10052447
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061061923 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1061061923
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1433096038
Short name T982
Test name
Test status
Simulation time 40996463 ps
CPU time 0.95 seconds
Started Aug 15 06:37:44 PM PDT 24
Finished Aug 15 06:37:45 PM PDT 24
Peak memory 207104 kb
Host smart-cff25650-f67c-4ed5-b344-d2860ecb7f6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433096038 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1433096038
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.900932926
Short name T1045
Test name
Test status
Simulation time 33591165 ps
CPU time 0.8 seconds
Started Aug 15 06:37:49 PM PDT 24
Finished Aug 15 06:37:50 PM PDT 24
Peak memory 206824 kb
Host smart-e22419a5-4d3b-494d-b79e-aa6233541742
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900932926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.900932926
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2321717243
Short name T991
Test name
Test status
Simulation time 81248096 ps
CPU time 0.96 seconds
Started Aug 15 06:38:02 PM PDT 24
Finished Aug 15 06:38:03 PM PDT 24
Peak memory 206920 kb
Host smart-cbd0ef4b-f3a6-4126-a034-e396546ae8cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321717243 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2321717243
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.153182228
Short name T1033
Test name
Test status
Simulation time 50037006 ps
CPU time 1.25 seconds
Started Aug 15 06:37:52 PM PDT 24
Finished Aug 15 06:37:54 PM PDT 24
Peak memory 207300 kb
Host smart-db1511e3-349a-412e-8a07-6d77c903cf20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153182228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_ou
tstanding.153182228
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.373958542
Short name T1094
Test name
Test status
Simulation time 161383141 ps
CPU time 2.98 seconds
Started Aug 15 06:37:49 PM PDT 24
Finished Aug 15 06:37:52 PM PDT 24
Peak memory 215360 kb
Host smart-5c632480-00db-44be-99a2-21b4a16edbad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373958542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.373958542
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.342663805
Short name T280
Test name
Test status
Simulation time 143434396 ps
CPU time 3.25 seconds
Started Aug 15 06:37:49 PM PDT 24
Finished Aug 15 06:37:52 PM PDT 24
Peak memory 207404 kb
Host smart-194b62b7-8add-4871-8c11-2c2c1b65ec17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342663805 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.342663805
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.4003511201
Short name T1053
Test name
Test status
Simulation time 15674850 ps
CPU time 1.05 seconds
Started Aug 15 06:37:38 PM PDT 24
Finished Aug 15 06:37:39 PM PDT 24
Peak memory 207016 kb
Host smart-0b163abe-8767-489e-bdce-63e0b4dcf799
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003511201 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.4003511201
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.867548514
Short name T1068
Test name
Test status
Simulation time 96513136 ps
CPU time 3 seconds
Started Aug 15 06:37:40 PM PDT 24
Finished Aug 15 06:37:44 PM PDT 24
Peak memory 207076 kb
Host smart-253e4b2d-ae4b-4d5f-a191-beb8df6b206b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867548514 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.867548514
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1321008472
Short name T249
Test name
Test status
Simulation time 135124509 ps
CPU time 0.84 seconds
Started Aug 15 06:37:36 PM PDT 24
Finished Aug 15 06:37:37 PM PDT 24
Peak memory 206848 kb
Host smart-9098ca89-5845-4f55-9bcf-63b2effd4d70
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321008472 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1321008472
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.572047150
Short name T1062
Test name
Test status
Simulation time 46280263 ps
CPU time 1.29 seconds
Started Aug 15 06:37:30 PM PDT 24
Finished Aug 15 06:37:32 PM PDT 24
Peak memory 215436 kb
Host smart-edf31833-ae28-4a76-b034-1bd9a6353dc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572047150 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.572047150
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2936375615
Short name T1020
Test name
Test status
Simulation time 18300997 ps
CPU time 0.85 seconds
Started Aug 15 06:37:31 PM PDT 24
Finished Aug 15 06:37:32 PM PDT 24
Peak memory 206852 kb
Host smart-b3870f2f-0e93-4651-bff1-031f1c7ff969
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936375615 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2936375615
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1460415446
Short name T1019
Test name
Test status
Simulation time 65936662 ps
CPU time 0.81 seconds
Started Aug 15 06:37:39 PM PDT 24
Finished Aug 15 06:37:40 PM PDT 24
Peak memory 206816 kb
Host smart-7044de75-fdf9-4b40-b874-4e3efddd546d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460415446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1460415446
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3189913348
Short name T1069
Test name
Test status
Simulation time 54130998 ps
CPU time 1.6 seconds
Started Aug 15 06:37:29 PM PDT 24
Finished Aug 15 06:37:31 PM PDT 24
Peak memory 207192 kb
Host smart-f0ce7e17-2576-44a9-8ba9-c02b7ffea475
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189913348 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.3189913348
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.3028496406
Short name T1084
Test name
Test status
Simulation time 278767370 ps
CPU time 3.08 seconds
Started Aug 15 06:37:31 PM PDT 24
Finished Aug 15 06:37:34 PM PDT 24
Peak memory 215284 kb
Host smart-15b85647-4e60-4631-95a0-67c6184192a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028496406 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.3028496406
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3815557824
Short name T988
Test name
Test status
Simulation time 458318264 ps
CPU time 1.93 seconds
Started Aug 15 06:37:23 PM PDT 24
Finished Aug 15 06:37:25 PM PDT 24
Peak memory 207152 kb
Host smart-6f278b83-81c0-4964-8d4d-f6017698aaee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815557824 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3815557824
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.3455603897
Short name T999
Test name
Test status
Simulation time 16820548 ps
CPU time 0.9 seconds
Started Aug 15 06:38:00 PM PDT 24
Finished Aug 15 06:38:01 PM PDT 24
Peak memory 206920 kb
Host smart-4efa492a-5658-462a-bdc2-31799c4cb275
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455603897 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3455603897
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.463139474
Short name T1103
Test name
Test status
Simulation time 38807728 ps
CPU time 0.83 seconds
Started Aug 15 06:37:56 PM PDT 24
Finished Aug 15 06:37:57 PM PDT 24
Peak memory 206744 kb
Host smart-094eb2cd-ad79-4730-ad18-3944c0112a98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463139474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.463139474
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1802388802
Short name T972
Test name
Test status
Simulation time 42706071 ps
CPU time 0.84 seconds
Started Aug 15 06:37:48 PM PDT 24
Finished Aug 15 06:37:49 PM PDT 24
Peak memory 207156 kb
Host smart-1b744835-d5dc-4d74-836d-296efe0c5e62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802388802 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1802388802
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.2242290160
Short name T1007
Test name
Test status
Simulation time 75468484 ps
CPU time 0.85 seconds
Started Aug 15 06:37:41 PM PDT 24
Finished Aug 15 06:37:42 PM PDT 24
Peak memory 206844 kb
Host smart-e0a3849e-2957-4973-b4c8-5bd1509b3f72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242290160 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2242290160
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.272245058
Short name T1101
Test name
Test status
Simulation time 13282207 ps
CPU time 0.85 seconds
Started Aug 15 06:38:07 PM PDT 24
Finished Aug 15 06:38:08 PM PDT 24
Peak memory 206892 kb
Host smart-0ca161b3-2be5-43b4-a9ff-176e6feadffc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272245058 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.272245058
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.2713472710
Short name T1072
Test name
Test status
Simulation time 22846624 ps
CPU time 0.88 seconds
Started Aug 15 06:37:58 PM PDT 24
Finished Aug 15 06:38:04 PM PDT 24
Peak memory 206932 kb
Host smart-4babdf0e-439b-4381-b47b-cd980aeba037
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713472710 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2713472710
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.3519985606
Short name T1042
Test name
Test status
Simulation time 27857164 ps
CPU time 0.91 seconds
Started Aug 15 06:38:07 PM PDT 24
Finished Aug 15 06:38:08 PM PDT 24
Peak memory 206884 kb
Host smart-10d99892-4301-4558-8081-e948667a311a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519985606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3519985606
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.350409985
Short name T1052
Test name
Test status
Simulation time 13593317 ps
CPU time 0.86 seconds
Started Aug 15 06:37:41 PM PDT 24
Finished Aug 15 06:37:42 PM PDT 24
Peak memory 206956 kb
Host smart-a9827a2a-0bfd-4658-9db9-d6774ddf5759
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350409985 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.350409985
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.1493227769
Short name T1095
Test name
Test status
Simulation time 46021846 ps
CPU time 0.86 seconds
Started Aug 15 06:37:49 PM PDT 24
Finished Aug 15 06:37:50 PM PDT 24
Peak memory 206964 kb
Host smart-ea269d56-03b9-405d-bd50-61e9740faad3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493227769 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.1493227769
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.1319575997
Short name T1080
Test name
Test status
Simulation time 12492152 ps
CPU time 0.85 seconds
Started Aug 15 06:38:06 PM PDT 24
Finished Aug 15 06:38:07 PM PDT 24
Peak memory 206896 kb
Host smart-25e34a19-a39c-4394-b3ec-a5505979ff8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319575997 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1319575997
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1825045514
Short name T1075
Test name
Test status
Simulation time 22401795 ps
CPU time 1.16 seconds
Started Aug 15 06:37:31 PM PDT 24
Finished Aug 15 06:37:32 PM PDT 24
Peak memory 207012 kb
Host smart-e8e676ab-9d1b-44ba-b37a-caa9ad3fc219
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825045514 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1825045514
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3384866410
Short name T1004
Test name
Test status
Simulation time 173856657 ps
CPU time 5.01 seconds
Started Aug 15 06:37:34 PM PDT 24
Finished Aug 15 06:37:40 PM PDT 24
Peak memory 207044 kb
Host smart-602e0738-e29b-43d3-9a6e-3f4d006f0d3f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384866410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3384866410
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3496946177
Short name T1012
Test name
Test status
Simulation time 28531714 ps
CPU time 0.95 seconds
Started Aug 15 06:37:34 PM PDT 24
Finished Aug 15 06:37:36 PM PDT 24
Peak memory 206996 kb
Host smart-82af97ea-bd92-4130-b45e-20c0c0ef1f68
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496946177 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.3496946177
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1833858131
Short name T1044
Test name
Test status
Simulation time 86202206 ps
CPU time 1.49 seconds
Started Aug 15 06:37:24 PM PDT 24
Finished Aug 15 06:37:26 PM PDT 24
Peak memory 215380 kb
Host smart-0e78eb50-56f0-4c26-a120-4bd9de57a3bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833858131 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.1833858131
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.227848553
Short name T251
Test name
Test status
Simulation time 16889532 ps
CPU time 0.87 seconds
Started Aug 15 06:37:46 PM PDT 24
Finished Aug 15 06:37:47 PM PDT 24
Peak memory 207032 kb
Host smart-2a3b161d-b36d-4b1e-9d26-736c7ff78379
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227848553 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.227848553
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.2252766847
Short name T981
Test name
Test status
Simulation time 15596548 ps
CPU time 0.9 seconds
Started Aug 15 06:37:32 PM PDT 24
Finished Aug 15 06:37:33 PM PDT 24
Peak memory 206944 kb
Host smart-b19ba7bc-35a3-42dc-bbcc-733c9f78a637
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252766847 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.2252766847
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3984158364
Short name T262
Test name
Test status
Simulation time 17668833 ps
CPU time 1.16 seconds
Started Aug 15 06:37:30 PM PDT 24
Finished Aug 15 06:37:31 PM PDT 24
Peak memory 207096 kb
Host smart-44967b81-2910-4680-8b36-6a4e6df2a44f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984158364 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.3984158364
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.2249109962
Short name T984
Test name
Test status
Simulation time 100730503 ps
CPU time 3.7 seconds
Started Aug 15 06:37:37 PM PDT 24
Finished Aug 15 06:37:41 PM PDT 24
Peak memory 223452 kb
Host smart-8f45b7d6-1b19-4eac-81d3-342babe42d0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249109962 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2249109962
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.693867593
Short name T272
Test name
Test status
Simulation time 336023777 ps
CPU time 2.17 seconds
Started Aug 15 06:37:35 PM PDT 24
Finished Aug 15 06:37:38 PM PDT 24
Peak memory 215332 kb
Host smart-9f865edf-460c-4a4f-95d2-b19ffb6649d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693867593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.693867593
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.80500285
Short name T1089
Test name
Test status
Simulation time 103638102 ps
CPU time 0.85 seconds
Started Aug 15 06:37:41 PM PDT 24
Finished Aug 15 06:37:42 PM PDT 24
Peak memory 207024 kb
Host smart-c1ca1b21-07b1-4ac1-bae7-4a9e6f027c60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80500285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.80500285
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.749242298
Short name T974
Test name
Test status
Simulation time 12301554 ps
CPU time 0.9 seconds
Started Aug 15 06:37:43 PM PDT 24
Finished Aug 15 06:37:44 PM PDT 24
Peak memory 206916 kb
Host smart-c9705c42-ba74-4572-80b5-e4a7335a30f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749242298 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.749242298
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.3344565201
Short name T992
Test name
Test status
Simulation time 14396165 ps
CPU time 0.87 seconds
Started Aug 15 06:37:49 PM PDT 24
Finished Aug 15 06:37:50 PM PDT 24
Peak memory 206928 kb
Host smart-d3191627-0bd9-481c-9d1d-41dc58d41c40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344565201 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3344565201
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.2120921708
Short name T1029
Test name
Test status
Simulation time 31093089 ps
CPU time 0.75 seconds
Started Aug 15 06:37:49 PM PDT 24
Finished Aug 15 06:37:50 PM PDT 24
Peak memory 206788 kb
Host smart-97084fe2-32d6-436d-a6ad-dad2f9708c2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120921708 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2120921708
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3055892636
Short name T1034
Test name
Test status
Simulation time 60365990 ps
CPU time 0.87 seconds
Started Aug 15 06:38:02 PM PDT 24
Finished Aug 15 06:38:03 PM PDT 24
Peak memory 206752 kb
Host smart-f3d947c8-7cde-4c9b-8448-1c756e9c5c31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055892636 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3055892636
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.3169868803
Short name T1056
Test name
Test status
Simulation time 13807020 ps
CPU time 0.87 seconds
Started Aug 15 06:37:51 PM PDT 24
Finished Aug 15 06:37:52 PM PDT 24
Peak memory 206976 kb
Host smart-95ffeba6-44ce-4990-93c3-5e6e8de25c0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169868803 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3169868803
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.434178959
Short name T1070
Test name
Test status
Simulation time 17627439 ps
CPU time 0.84 seconds
Started Aug 15 06:37:46 PM PDT 24
Finished Aug 15 06:37:47 PM PDT 24
Peak memory 206980 kb
Host smart-62fe4afa-03d3-40d9-a455-9f80b27c4a17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434178959 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.434178959
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.3646608661
Short name T975
Test name
Test status
Simulation time 21359577 ps
CPU time 0.9 seconds
Started Aug 15 06:37:59 PM PDT 24
Finished Aug 15 06:38:00 PM PDT 24
Peak memory 206948 kb
Host smart-705db465-e084-4fe8-a40c-8385a7eb271d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646608661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.3646608661
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.3348718251
Short name T998
Test name
Test status
Simulation time 42422787 ps
CPU time 0.88 seconds
Started Aug 15 06:37:53 PM PDT 24
Finished Aug 15 06:37:54 PM PDT 24
Peak memory 206976 kb
Host smart-653ee381-4ae0-44a1-b442-fa38c3aff62a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348718251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3348718251
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.1226384919
Short name T1048
Test name
Test status
Simulation time 11250108 ps
CPU time 0.81 seconds
Started Aug 15 06:37:43 PM PDT 24
Finished Aug 15 06:37:44 PM PDT 24
Peak memory 206948 kb
Host smart-658748b9-a242-40a8-9c06-31afab2aa835
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226384919 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.1226384919
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.634487617
Short name T1105
Test name
Test status
Simulation time 88132718 ps
CPU time 1.19 seconds
Started Aug 15 06:37:41 PM PDT 24
Finished Aug 15 06:37:42 PM PDT 24
Peak memory 207104 kb
Host smart-1eaa2931-8d29-4140-ad92-05a69247539e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634487617 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.634487617
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1220026334
Short name T986
Test name
Test status
Simulation time 1102152909 ps
CPU time 4.92 seconds
Started Aug 15 06:37:45 PM PDT 24
Finished Aug 15 06:37:50 PM PDT 24
Peak memory 207056 kb
Host smart-8ba115a9-0db7-4d26-8be5-8e9ca4d6b515
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220026334 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.1220026334
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1278841288
Short name T1040
Test name
Test status
Simulation time 14223792 ps
CPU time 0.86 seconds
Started Aug 15 06:37:38 PM PDT 24
Finished Aug 15 06:37:39 PM PDT 24
Peak memory 206848 kb
Host smart-ca9e997f-1174-430b-a06f-3194fd69c475
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278841288 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.1278841288
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.4246549702
Short name T1000
Test name
Test status
Simulation time 26344884 ps
CPU time 1.24 seconds
Started Aug 15 06:37:48 PM PDT 24
Finished Aug 15 06:37:49 PM PDT 24
Peak memory 218372 kb
Host smart-ad30d599-a1ed-4596-8bb9-04435e92b4fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246549702 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.4246549702
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.552499326
Short name T994
Test name
Test status
Simulation time 18932803 ps
CPU time 0.99 seconds
Started Aug 15 06:37:31 PM PDT 24
Finished Aug 15 06:37:32 PM PDT 24
Peak memory 207012 kb
Host smart-6167eefa-4e05-48ec-878a-ef759bef07eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552499326 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.552499326
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.2101324109
Short name T1017
Test name
Test status
Simulation time 15484108 ps
CPU time 0.91 seconds
Started Aug 15 06:37:25 PM PDT 24
Finished Aug 15 06:37:26 PM PDT 24
Peak memory 206956 kb
Host smart-43c74189-0c72-45c3-871a-a2967d842fd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101324109 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2101324109
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2539131316
Short name T259
Test name
Test status
Simulation time 32372126 ps
CPU time 0.97 seconds
Started Aug 15 06:37:45 PM PDT 24
Finished Aug 15 06:37:46 PM PDT 24
Peak memory 207120 kb
Host smart-e8a98f74-53b7-458a-a55e-373993384941
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539131316 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.2539131316
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.2606426147
Short name T1031
Test name
Test status
Simulation time 118883966 ps
CPU time 2.44 seconds
Started Aug 15 06:37:32 PM PDT 24
Finished Aug 15 06:37:35 PM PDT 24
Peak memory 215280 kb
Host smart-934cce56-6070-4bec-a92f-dc4bcbbd9828
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606426147 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2606426147
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.118229788
Short name T279
Test name
Test status
Simulation time 372053720 ps
CPU time 1.68 seconds
Started Aug 15 06:37:32 PM PDT 24
Finished Aug 15 06:37:34 PM PDT 24
Peak memory 207208 kb
Host smart-25098f05-8748-4d7a-b6a3-91c77d64c4f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118229788 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.118229788
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.2181732786
Short name T1079
Test name
Test status
Simulation time 18067961 ps
CPU time 0.87 seconds
Started Aug 15 06:37:54 PM PDT 24
Finished Aug 15 06:37:55 PM PDT 24
Peak memory 206980 kb
Host smart-bf7159f9-0c5f-46e4-a1a5-9a02f1d891ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181732786 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.2181732786
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1905528628
Short name T1071
Test name
Test status
Simulation time 14517849 ps
CPU time 0.85 seconds
Started Aug 15 06:37:42 PM PDT 24
Finished Aug 15 06:37:43 PM PDT 24
Peak memory 206920 kb
Host smart-09100f4f-e90b-4dde-9786-096377d83aef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905528628 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1905528628
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3371728273
Short name T1098
Test name
Test status
Simulation time 61281413 ps
CPU time 0.82 seconds
Started Aug 15 06:37:58 PM PDT 24
Finished Aug 15 06:37:59 PM PDT 24
Peak memory 206956 kb
Host smart-1ea9221f-f9cc-4504-91af-af1fc633c5a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371728273 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3371728273
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.1763275170
Short name T1006
Test name
Test status
Simulation time 68000477 ps
CPU time 0.93 seconds
Started Aug 15 06:37:56 PM PDT 24
Finished Aug 15 06:37:57 PM PDT 24
Peak memory 206932 kb
Host smart-3e8a3c56-8412-4344-a3b0-e59b5f567bd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763275170 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.1763275170
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.1381396459
Short name T993
Test name
Test status
Simulation time 15669184 ps
CPU time 0.93 seconds
Started Aug 15 06:37:50 PM PDT 24
Finished Aug 15 06:37:51 PM PDT 24
Peak memory 206988 kb
Host smart-904b813d-9e21-48e7-a778-84c967ef9bd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381396459 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.1381396459
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1170502901
Short name T1013
Test name
Test status
Simulation time 13122632 ps
CPU time 0.89 seconds
Started Aug 15 06:37:49 PM PDT 24
Finished Aug 15 06:37:50 PM PDT 24
Peak memory 206940 kb
Host smart-60b76071-69e6-4212-b114-5965ca26a033
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170502901 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1170502901
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.2259450857
Short name T1028
Test name
Test status
Simulation time 13513057 ps
CPU time 0.87 seconds
Started Aug 15 06:37:51 PM PDT 24
Finished Aug 15 06:37:52 PM PDT 24
Peak memory 206976 kb
Host smart-269ace94-6d9b-4d97-83fb-112187a9b526
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259450857 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.2259450857
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.3306666509
Short name T1018
Test name
Test status
Simulation time 24069051 ps
CPU time 0.9 seconds
Started Aug 15 06:37:45 PM PDT 24
Finished Aug 15 06:37:46 PM PDT 24
Peak memory 206904 kb
Host smart-6f09a1e0-0de9-4e09-9bdc-63238319a19d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306666509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.3306666509
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.3702719076
Short name T1026
Test name
Test status
Simulation time 40154023 ps
CPU time 0.81 seconds
Started Aug 15 06:37:50 PM PDT 24
Finished Aug 15 06:37:51 PM PDT 24
Peak memory 206800 kb
Host smart-d154f017-a96c-4019-8193-bda244c02752
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702719076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3702719076
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.2340020790
Short name T1011
Test name
Test status
Simulation time 32128001 ps
CPU time 0.84 seconds
Started Aug 15 06:37:41 PM PDT 24
Finished Aug 15 06:37:42 PM PDT 24
Peak memory 206920 kb
Host smart-66d99108-850a-4d12-b170-83c4fc49d37f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340020790 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2340020790
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2231301745
Short name T1024
Test name
Test status
Simulation time 350261469 ps
CPU time 1.54 seconds
Started Aug 15 06:37:42 PM PDT 24
Finished Aug 15 06:37:43 PM PDT 24
Peak memory 215400 kb
Host smart-00ae69d0-db1a-4709-ac97-1bdcaed054cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231301745 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2231301745
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.2220925954
Short name T1003
Test name
Test status
Simulation time 11967406 ps
CPU time 0.9 seconds
Started Aug 15 06:37:40 PM PDT 24
Finished Aug 15 06:37:41 PM PDT 24
Peak memory 206980 kb
Host smart-ee9695be-565c-4403-b1d0-1387b1f1bbc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220925954 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2220925954
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3921737221
Short name T257
Test name
Test status
Simulation time 69003125 ps
CPU time 1.38 seconds
Started Aug 15 06:37:38 PM PDT 24
Finished Aug 15 06:37:39 PM PDT 24
Peak memory 207204 kb
Host smart-cc024f06-db40-450f-952f-6ba255e59a9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921737221 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.3921737221
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.3502969149
Short name T1090
Test name
Test status
Simulation time 43126681 ps
CPU time 2.78 seconds
Started Aug 15 06:37:35 PM PDT 24
Finished Aug 15 06:37:37 PM PDT 24
Peak memory 215304 kb
Host smart-31fb3cac-e015-49f8-9d8f-c334e54076ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502969149 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.3502969149
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1266151818
Short name T1037
Test name
Test status
Simulation time 309872171 ps
CPU time 2.59 seconds
Started Aug 15 06:37:41 PM PDT 24
Finished Aug 15 06:37:44 PM PDT 24
Peak memory 215300 kb
Host smart-b7f02cb2-a69a-49fb-8587-fd0a32727508
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266151818 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1266151818
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.355109707
Short name T979
Test name
Test status
Simulation time 47920505 ps
CPU time 1.35 seconds
Started Aug 15 06:37:40 PM PDT 24
Finished Aug 15 06:37:41 PM PDT 24
Peak memory 215372 kb
Host smart-8f1e23c5-ca02-49fa-aae5-24684b1e3c54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355109707 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.355109707
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.23763845
Short name T258
Test name
Test status
Simulation time 13879893 ps
CPU time 0.93 seconds
Started Aug 15 06:37:41 PM PDT 24
Finished Aug 15 06:37:42 PM PDT 24
Peak memory 207048 kb
Host smart-83c96a7b-3a8e-4e38-9eaf-e1538de18cc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23763845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.23763845
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.1049572140
Short name T1104
Test name
Test status
Simulation time 45034511 ps
CPU time 0.82 seconds
Started Aug 15 06:37:46 PM PDT 24
Finished Aug 15 06:37:47 PM PDT 24
Peak memory 206980 kb
Host smart-ea0ecb3e-762d-44e3-a6cc-13baab9d1b5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049572140 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.1049572140
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1906571385
Short name T1010
Test name
Test status
Simulation time 40977459 ps
CPU time 1.58 seconds
Started Aug 15 06:37:42 PM PDT 24
Finished Aug 15 06:37:44 PM PDT 24
Peak memory 207168 kb
Host smart-a0ebd3ee-3e9b-4814-93ea-967c469fe7b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906571385 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.1906571385
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.2901974300
Short name T977
Test name
Test status
Simulation time 41502725 ps
CPU time 2.61 seconds
Started Aug 15 06:37:39 PM PDT 24
Finished Aug 15 06:37:42 PM PDT 24
Peak memory 215348 kb
Host smart-894d90e0-0a77-463e-9c08-2f15b32e07ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901974300 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2901974300
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1194667074
Short name T1087
Test name
Test status
Simulation time 95364476 ps
CPU time 2.09 seconds
Started Aug 15 06:37:36 PM PDT 24
Finished Aug 15 06:37:38 PM PDT 24
Peak memory 207252 kb
Host smart-0fc77bb3-a67b-4e32-90c3-cc023ba766ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194667074 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.1194667074
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.341304686
Short name T1021
Test name
Test status
Simulation time 378120670 ps
CPU time 1.37 seconds
Started Aug 15 06:37:52 PM PDT 24
Finished Aug 15 06:37:53 PM PDT 24
Peak memory 215456 kb
Host smart-4c2e6c62-3d3b-46ea-a2ac-6812c9616415
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341304686 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.341304686
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.3660887788
Short name T1059
Test name
Test status
Simulation time 15339512 ps
CPU time 0.93 seconds
Started Aug 15 06:37:45 PM PDT 24
Finished Aug 15 06:37:46 PM PDT 24
Peak memory 207028 kb
Host smart-14cf492a-923c-42e0-8942-d8f4a34a9303
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660887788 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.3660887788
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.3934496059
Short name T1076
Test name
Test status
Simulation time 19103246 ps
CPU time 0.82 seconds
Started Aug 15 06:37:46 PM PDT 24
Finished Aug 15 06:37:49 PM PDT 24
Peak memory 206808 kb
Host smart-ebe8c1d1-e6eb-4f2d-9cc0-e0ae378c1b56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934496059 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.3934496059
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3890546628
Short name T1016
Test name
Test status
Simulation time 51683898 ps
CPU time 1.08 seconds
Started Aug 15 06:37:41 PM PDT 24
Finished Aug 15 06:37:43 PM PDT 24
Peak memory 207164 kb
Host smart-93ddbb59-48b2-4408-881b-65e8aa0e1d66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890546628 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.3890546628
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.753144533
Short name T1057
Test name
Test status
Simulation time 53070058 ps
CPU time 2.07 seconds
Started Aug 15 06:37:41 PM PDT 24
Finished Aug 15 06:37:43 PM PDT 24
Peak memory 215240 kb
Host smart-242de1b0-cf3f-4883-83f9-d488f80c7a20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753144533 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.753144533
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.749711630
Short name T1066
Test name
Test status
Simulation time 178917634 ps
CPU time 1.61 seconds
Started Aug 15 06:37:32 PM PDT 24
Finished Aug 15 06:37:34 PM PDT 24
Peak memory 207108 kb
Host smart-b4d4e51a-7b37-457f-9a01-069adf762b4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749711630 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.749711630
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.770886341
Short name T1032
Test name
Test status
Simulation time 78574380 ps
CPU time 1.12 seconds
Started Aug 15 06:37:45 PM PDT 24
Finished Aug 15 06:37:46 PM PDT 24
Peak memory 215384 kb
Host smart-6592e1c0-960a-47a0-aa64-cd8ec253dc90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770886341 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.770886341
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.3006958649
Short name T1077
Test name
Test status
Simulation time 20708464 ps
CPU time 0.85 seconds
Started Aug 15 06:37:36 PM PDT 24
Finished Aug 15 06:37:37 PM PDT 24
Peak memory 207016 kb
Host smart-5ccd472b-e170-402c-8c81-aed7ee1ece1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006958649 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.3006958649
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1422477197
Short name T971
Test name
Test status
Simulation time 22661629 ps
CPU time 0.85 seconds
Started Aug 15 06:37:40 PM PDT 24
Finished Aug 15 06:37:41 PM PDT 24
Peak memory 206984 kb
Host smart-65ae54b5-cace-4156-9b76-b6109d9373e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422477197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1422477197
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3061617833
Short name T1047
Test name
Test status
Simulation time 19584953 ps
CPU time 1.16 seconds
Started Aug 15 06:37:39 PM PDT 24
Finished Aug 15 06:37:40 PM PDT 24
Peak memory 207116 kb
Host smart-4a6f4f58-d67c-48af-9090-8d544b0bdc36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061617833 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.3061617833
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.1312333778
Short name T990
Test name
Test status
Simulation time 99521340 ps
CPU time 3.49 seconds
Started Aug 15 06:37:43 PM PDT 24
Finished Aug 15 06:37:46 PM PDT 24
Peak memory 215368 kb
Host smart-9ba46d89-842f-4e17-bf9b-9ab1bfbe6453
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312333778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1312333778
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1729703640
Short name T282
Test name
Test status
Simulation time 236894816 ps
CPU time 2.16 seconds
Started Aug 15 06:37:41 PM PDT 24
Finished Aug 15 06:37:44 PM PDT 24
Peak memory 207116 kb
Host smart-0b74cc50-a699-4035-b9e3-89928a677cd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729703640 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1729703640
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3116568052
Short name T1027
Test name
Test status
Simulation time 26814624 ps
CPU time 1.64 seconds
Started Aug 15 06:37:37 PM PDT 24
Finished Aug 15 06:37:39 PM PDT 24
Peak memory 215408 kb
Host smart-1dc7aa9d-ef01-4b50-984c-9c890c21c36c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116568052 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.3116568052
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3752181121
Short name T253
Test name
Test status
Simulation time 18726130 ps
CPU time 0.83 seconds
Started Aug 15 06:37:41 PM PDT 24
Finished Aug 15 06:37:42 PM PDT 24
Peak memory 207036 kb
Host smart-a6113198-f9d1-46b5-9c84-e8ccf3968586
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752181121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3752181121
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.1055778615
Short name T997
Test name
Test status
Simulation time 15448388 ps
CPU time 0.77 seconds
Started Aug 15 06:37:35 PM PDT 24
Finished Aug 15 06:37:36 PM PDT 24
Peak memory 206780 kb
Host smart-82393741-7fc6-47e2-8c46-e4ed1a2898a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055778615 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1055778615
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1208026968
Short name T1099
Test name
Test status
Simulation time 78930903 ps
CPU time 1.1 seconds
Started Aug 15 06:37:38 PM PDT 24
Finished Aug 15 06:37:39 PM PDT 24
Peak memory 207176 kb
Host smart-e8d4d0d4-e43d-4ee1-9d7d-ee8cde6a746d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208026968 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1208026968
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.1669132022
Short name T970
Test name
Test status
Simulation time 321298260 ps
CPU time 3.18 seconds
Started Aug 15 06:37:44 PM PDT 24
Finished Aug 15 06:37:48 PM PDT 24
Peak memory 215388 kb
Host smart-af0b45ab-db5c-49e1-9545-fe45f34ff8b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669132022 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1669132022
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3268698226
Short name T1051
Test name
Test status
Simulation time 645100770 ps
CPU time 2.32 seconds
Started Aug 15 06:37:41 PM PDT 24
Finished Aug 15 06:37:43 PM PDT 24
Peak memory 207136 kb
Host smart-50ef432d-5c94-41e6-9e6e-332fe8169b25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268698226 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3268698226
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.3609312123
Short name T941
Test name
Test status
Simulation time 79441786 ps
CPU time 1.23 seconds
Started Aug 15 06:32:00 PM PDT 24
Finished Aug 15 06:32:01 PM PDT 24
Peak memory 220720 kb
Host smart-25843024-df84-4aca-a3ea-8908442e079b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609312123 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3609312123
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.2385927698
Short name T741
Test name
Test status
Simulation time 13813823 ps
CPU time 0.92 seconds
Started Aug 15 06:31:56 PM PDT 24
Finished Aug 15 06:31:58 PM PDT 24
Peak memory 206884 kb
Host smart-8b8615de-18ea-4117-a6f0-8b69a5af41f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385927698 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2385927698
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.3668081204
Short name T328
Test name
Test status
Simulation time 15950880 ps
CPU time 0.91 seconds
Started Aug 15 06:32:00 PM PDT 24
Finished Aug 15 06:32:01 PM PDT 24
Peak memory 215216 kb
Host smart-b46fbb1f-182b-48e7-8e59-6fcbb6b4bf81
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668081204 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3668081204
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.3447795306
Short name T835
Test name
Test status
Simulation time 61149937 ps
CPU time 1.15 seconds
Started Aug 15 06:31:57 PM PDT 24
Finished Aug 15 06:31:59 PM PDT 24
Peak memory 216884 kb
Host smart-c0431629-3e39-4fa9-86c6-27309624b940
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447795306 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.3447795306
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.1242501838
Short name T138
Test name
Test status
Simulation time 87004041 ps
CPU time 1.28 seconds
Started Aug 15 06:31:57 PM PDT 24
Finished Aug 15 06:31:58 PM PDT 24
Peak memory 225908 kb
Host smart-256a027c-d443-4441-b98e-c2a288b9d962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242501838 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1242501838
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.973673061
Short name T641
Test name
Test status
Simulation time 40910748 ps
CPU time 1.69 seconds
Started Aug 15 06:31:58 PM PDT 24
Finished Aug 15 06:32:00 PM PDT 24
Peak memory 218636 kb
Host smart-66864ff3-a94c-4d37-aa00-bf69fa574371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973673061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.973673061
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_regwen.3658012352
Short name T919
Test name
Test status
Simulation time 16916775 ps
CPU time 1.02 seconds
Started Aug 15 06:32:00 PM PDT 24
Finished Aug 15 06:32:01 PM PDT 24
Peak memory 207180 kb
Host smart-ddcb8902-0b9a-4fc0-9f4a-39ffe2aaf68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658012352 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.3658012352
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.1903224941
Short name T58
Test name
Test status
Simulation time 738962973 ps
CPU time 11.76 seconds
Started Aug 15 06:32:01 PM PDT 24
Finished Aug 15 06:32:13 PM PDT 24
Peak memory 240300 kb
Host smart-6b1523b5-7940-45f8-834e-0a883482b93a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903224941 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1903224941
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.2325429234
Short name T348
Test name
Test status
Simulation time 89188507 ps
CPU time 0.93 seconds
Started Aug 15 06:32:00 PM PDT 24
Finished Aug 15 06:32:01 PM PDT 24
Peak memory 215376 kb
Host smart-c4852a98-aaf5-42a8-b5ff-3ca4d79f96c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325429234 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2325429234
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.2283719803
Short name T842
Test name
Test status
Simulation time 450711252 ps
CPU time 2.1 seconds
Started Aug 15 06:31:57 PM PDT 24
Finished Aug 15 06:31:59 PM PDT 24
Peak memory 220028 kb
Host smart-0cd36089-0b9d-46f7-ad5b-e838558cded7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283719803 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2283719803
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_alert.1443867221
Short name T476
Test name
Test status
Simulation time 99625468 ps
CPU time 1.14 seconds
Started Aug 15 06:31:59 PM PDT 24
Finished Aug 15 06:32:00 PM PDT 24
Peak memory 220376 kb
Host smart-e2d08967-b706-479b-8a74-66b9a0dc5fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443867221 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1443867221
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.1763580271
Short name T850
Test name
Test status
Simulation time 19572777 ps
CPU time 0.79 seconds
Started Aug 15 06:31:56 PM PDT 24
Finished Aug 15 06:31:57 PM PDT 24
Peak memory 206852 kb
Host smart-c80a10b2-edda-4b60-bb18-6b5e256f6652
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763580271 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1763580271
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1047641252
Short name T22
Test name
Test status
Simulation time 20252745 ps
CPU time 1 seconds
Started Aug 15 06:31:57 PM PDT 24
Finished Aug 15 06:31:58 PM PDT 24
Peak memory 216936 kb
Host smart-0c3c5988-9e2f-4376-aaab-942e0cbaee1d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047641252 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1047641252
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.1952719011
Short name T99
Test name
Test status
Simulation time 27392961 ps
CPU time 0.86 seconds
Started Aug 15 06:32:00 PM PDT 24
Finished Aug 15 06:32:01 PM PDT 24
Peak memory 218280 kb
Host smart-b4bd7bfc-1385-4cb2-9d79-79e59d426bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952719011 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.1952719011
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.3974732555
Short name T818
Test name
Test status
Simulation time 54184762 ps
CPU time 2.05 seconds
Started Aug 15 06:31:58 PM PDT 24
Finished Aug 15 06:32:00 PM PDT 24
Peak memory 218608 kb
Host smart-dfe9c566-9d7f-47cb-9e62-a7ab7dcbe848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974732555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.3974732555
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.4202662950
Short name T560
Test name
Test status
Simulation time 33104429 ps
CPU time 0.88 seconds
Started Aug 15 06:31:57 PM PDT 24
Finished Aug 15 06:31:58 PM PDT 24
Peak memory 215544 kb
Host smart-6a10adcd-4593-466f-974e-02085595ba90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202662950 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.4202662950
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.1668823195
Short name T710
Test name
Test status
Simulation time 17067788 ps
CPU time 0.96 seconds
Started Aug 15 06:31:57 PM PDT 24
Finished Aug 15 06:31:58 PM PDT 24
Peak memory 207136 kb
Host smart-d334c696-5564-43f2-bfa0-bc37e9e900f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668823195 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.1668823195
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.1822039781
Short name T16
Test name
Test status
Simulation time 1793327987 ps
CPU time 9.44 seconds
Started Aug 15 06:31:57 PM PDT 24
Finished Aug 15 06:32:07 PM PDT 24
Peak memory 237136 kb
Host smart-14c778b3-db4c-4610-8e01-1b1f7c8bdab1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822039781 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1822039781
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.4258439344
Short name T79
Test name
Test status
Simulation time 16284001 ps
CPU time 1.02 seconds
Started Aug 15 06:31:57 PM PDT 24
Finished Aug 15 06:31:58 PM PDT 24
Peak memory 215348 kb
Host smart-3cc48f18-d645-467b-966b-8a6caa0adff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258439344 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.4258439344
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.2085474167
Short name T964
Test name
Test status
Simulation time 259541143 ps
CPU time 3.19 seconds
Started Aug 15 06:31:59 PM PDT 24
Finished Aug 15 06:32:02 PM PDT 24
Peak memory 217468 kb
Host smart-b70538c9-83a2-4351-9042-cf44de03396a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085474167 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2085474167
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1199456825
Short name T226
Test name
Test status
Simulation time 2308440008 ps
CPU time 64.29 seconds
Started Aug 15 06:31:59 PM PDT 24
Finished Aug 15 06:33:03 PM PDT 24
Peak memory 218248 kb
Host smart-9ab60fc4-a736-4910-9c47-30a09c08166e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199456825 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1199456825
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.2494819206
Short name T705
Test name
Test status
Simulation time 30003050 ps
CPU time 1.31 seconds
Started Aug 15 06:32:14 PM PDT 24
Finished Aug 15 06:32:15 PM PDT 24
Peak memory 220748 kb
Host smart-3eee95bd-072c-405d-9da6-34777af2e2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494819206 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.2494819206
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.2570294687
Short name T405
Test name
Test status
Simulation time 19536466 ps
CPU time 1.02 seconds
Started Aug 15 06:32:19 PM PDT 24
Finished Aug 15 06:32:21 PM PDT 24
Peak memory 206808 kb
Host smart-26783bc1-96a8-4286-a753-6fafbf03fa36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570294687 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2570294687
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.3751562416
Short name T462
Test name
Test status
Simulation time 34598989 ps
CPU time 0.87 seconds
Started Aug 15 06:32:13 PM PDT 24
Finished Aug 15 06:32:14 PM PDT 24
Peak memory 215184 kb
Host smart-a14ede54-c845-4018-9113-78bf62c4496e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751562416 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3751562416
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.1164757070
Short name T148
Test name
Test status
Simulation time 56716683 ps
CPU time 1 seconds
Started Aug 15 06:32:16 PM PDT 24
Finished Aug 15 06:32:17 PM PDT 24
Peak memory 219604 kb
Host smart-28cdd7f3-2c7c-4447-a6e0-6e4784874014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164757070 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1164757070
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.180593614
Short name T830
Test name
Test status
Simulation time 56360788 ps
CPU time 0.98 seconds
Started Aug 15 06:32:17 PM PDT 24
Finished Aug 15 06:32:18 PM PDT 24
Peak memory 217200 kb
Host smart-1acbc618-887e-404c-a9f5-aca5becde2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180593614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.180593614
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.1471479857
Short name T55
Test name
Test status
Simulation time 29941610 ps
CPU time 0.96 seconds
Started Aug 15 06:32:13 PM PDT 24
Finished Aug 15 06:32:14 PM PDT 24
Peak memory 224020 kb
Host smart-50eae030-6e92-4948-adb3-9e9fc3840a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471479857 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1471479857
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.2459557015
Short name T335
Test name
Test status
Simulation time 16279930 ps
CPU time 1.02 seconds
Started Aug 15 06:32:14 PM PDT 24
Finished Aug 15 06:32:15 PM PDT 24
Peak memory 215376 kb
Host smart-83113bdb-5edf-425a-b2bf-fd741a685626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459557015 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.2459557015
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/100.edn_alert.2966368188
Short name T241
Test name
Test status
Simulation time 92779463 ps
CPU time 1.26 seconds
Started Aug 15 06:33:58 PM PDT 24
Finished Aug 15 06:33:59 PM PDT 24
Peak memory 219940 kb
Host smart-eb5723a3-f50c-4a5c-bc31-66e2889e013b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966368188 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.2966368188
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.93983689
Short name T558
Test name
Test status
Simulation time 96918544 ps
CPU time 1.24 seconds
Started Aug 15 06:33:53 PM PDT 24
Finished Aug 15 06:33:55 PM PDT 24
Peak memory 217564 kb
Host smart-2b0b58d4-dffc-49bd-9320-f4bf24a59a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93983689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.93983689
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.563235456
Short name T635
Test name
Test status
Simulation time 50762245 ps
CPU time 1.24 seconds
Started Aug 15 06:33:54 PM PDT 24
Finished Aug 15 06:33:55 PM PDT 24
Peak memory 218640 kb
Host smart-999bb42f-5a12-4cef-bf6b-3db5be4c9ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563235456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.563235456
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.3455037707
Short name T912
Test name
Test status
Simulation time 39683062 ps
CPU time 1.14 seconds
Started Aug 15 06:33:51 PM PDT 24
Finished Aug 15 06:33:53 PM PDT 24
Peak memory 218712 kb
Host smart-e957ae8a-0220-4fcc-9d46-e61320e9f82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455037707 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.3455037707
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.785333238
Short name T600
Test name
Test status
Simulation time 43204294 ps
CPU time 1.09 seconds
Started Aug 15 06:33:48 PM PDT 24
Finished Aug 15 06:33:49 PM PDT 24
Peak memory 217320 kb
Host smart-bb04eb4f-ef27-424f-80e6-3556029ec0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785333238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.785333238
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.1977612035
Short name T795
Test name
Test status
Simulation time 66170222 ps
CPU time 1.15 seconds
Started Aug 15 06:33:47 PM PDT 24
Finished Aug 15 06:33:48 PM PDT 24
Peak memory 218572 kb
Host smart-5f8ea297-adef-4aa5-af3e-951faa390c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977612035 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.1977612035
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.1497232990
Short name T518
Test name
Test status
Simulation time 36999925 ps
CPU time 1.6 seconds
Started Aug 15 06:33:43 PM PDT 24
Finished Aug 15 06:33:45 PM PDT 24
Peak memory 218428 kb
Host smart-517c0a4d-c445-42fd-ba9b-7f708f53a373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497232990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.1497232990
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.2267495170
Short name T71
Test name
Test status
Simulation time 25470063 ps
CPU time 1.22 seconds
Started Aug 15 06:33:37 PM PDT 24
Finished Aug 15 06:33:39 PM PDT 24
Peak memory 218768 kb
Host smart-78e0e137-524a-4a7a-ad2c-74fb6ddf6fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267495170 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.2267495170
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/105.edn_alert.3132784043
Short name T160
Test name
Test status
Simulation time 249018188 ps
CPU time 1.41 seconds
Started Aug 15 06:33:43 PM PDT 24
Finished Aug 15 06:33:45 PM PDT 24
Peak memory 220516 kb
Host smart-3e1011c5-ce31-4e45-8e0e-7bb760429b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132784043 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.3132784043
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.836520760
Short name T386
Test name
Test status
Simulation time 54579754 ps
CPU time 1.25 seconds
Started Aug 15 06:33:45 PM PDT 24
Finished Aug 15 06:33:46 PM PDT 24
Peak memory 218484 kb
Host smart-e18fe37e-e96c-4b4c-833d-8a1b2097648c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836520760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.836520760
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.731462603
Short name T591
Test name
Test status
Simulation time 46988297 ps
CPU time 1.2 seconds
Started Aug 15 06:33:50 PM PDT 24
Finished Aug 15 06:33:52 PM PDT 24
Peak memory 215740 kb
Host smart-53ee0d0b-bae7-421a-805e-733d55141d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731462603 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.731462603
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.1529943046
Short name T875
Test name
Test status
Simulation time 74739450 ps
CPU time 1.68 seconds
Started Aug 15 06:33:52 PM PDT 24
Finished Aug 15 06:33:54 PM PDT 24
Peak memory 218752 kb
Host smart-cc867961-bf5f-4679-8633-ec47609a3683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529943046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1529943046
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.3784829629
Short name T373
Test name
Test status
Simulation time 178492659 ps
CPU time 1.58 seconds
Started Aug 15 06:33:48 PM PDT 24
Finished Aug 15 06:33:50 PM PDT 24
Peak memory 218748 kb
Host smart-3218c4ac-7be5-4556-8101-08594cac6233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784829629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3784829629
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.2743935775
Short name T736
Test name
Test status
Simulation time 44204964 ps
CPU time 1.15 seconds
Started Aug 15 06:33:41 PM PDT 24
Finished Aug 15 06:33:42 PM PDT 24
Peak memory 218844 kb
Host smart-9b3c5852-7ae9-4695-9553-bce1ecdb68c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743935775 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.2743935775
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.3850631565
Short name T692
Test name
Test status
Simulation time 32825794 ps
CPU time 1.01 seconds
Started Aug 15 06:33:40 PM PDT 24
Finished Aug 15 06:33:41 PM PDT 24
Peak memory 217436 kb
Host smart-4ce53ea1-c082-4dc2-8633-e041ebfbcd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850631565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3850631565
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.3230584122
Short name T246
Test name
Test status
Simulation time 30539143 ps
CPU time 1.29 seconds
Started Aug 15 06:33:42 PM PDT 24
Finished Aug 15 06:33:44 PM PDT 24
Peak memory 218616 kb
Host smart-c4c7c6a4-e41a-4c30-8121-b98dbc475b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230584122 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.3230584122
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.2661037605
Short name T903
Test name
Test status
Simulation time 59814298 ps
CPU time 1.37 seconds
Started Aug 15 06:33:40 PM PDT 24
Finished Aug 15 06:33:42 PM PDT 24
Peak memory 218576 kb
Host smart-07566590-1d9e-44c9-9e02-d06e6453ef15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661037605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.2661037605
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.2837488911
Short name T513
Test name
Test status
Simulation time 22004491 ps
CPU time 0.88 seconds
Started Aug 15 06:32:20 PM PDT 24
Finished Aug 15 06:32:21 PM PDT 24
Peak memory 206552 kb
Host smart-02732aad-03cc-4305-b648-f575a21d1335
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837488911 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.2837488911
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.932042151
Short name T268
Test name
Test status
Simulation time 34322342 ps
CPU time 1.24 seconds
Started Aug 15 06:32:13 PM PDT 24
Finished Aug 15 06:32:15 PM PDT 24
Peak memory 216920 kb
Host smart-877c8ad5-312c-45b4-844a-caf9a2de2f54
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932042151 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_di
sable_auto_req_mode.932042151
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.388899082
Short name T779
Test name
Test status
Simulation time 25870151 ps
CPU time 0.97 seconds
Started Aug 15 06:32:14 PM PDT 24
Finished Aug 15 06:32:15 PM PDT 24
Peak memory 218780 kb
Host smart-82ddde3b-1fc7-4415-93b7-fd779cd3721f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388899082 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.388899082
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.2409015746
Short name T412
Test name
Test status
Simulation time 46208926 ps
CPU time 1.51 seconds
Started Aug 15 06:32:10 PM PDT 24
Finished Aug 15 06:32:12 PM PDT 24
Peak memory 218600 kb
Host smart-ce192523-33c3-4cae-aa44-82dd592ae59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409015746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2409015746
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.2622781092
Short name T32
Test name
Test status
Simulation time 20753575 ps
CPU time 1.07 seconds
Started Aug 15 06:32:15 PM PDT 24
Finished Aug 15 06:32:16 PM PDT 24
Peak memory 215860 kb
Host smart-017c884b-f8d7-4a09-9c21-b5e86f71f898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622781092 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.2622781092
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.856324492
Short name T886
Test name
Test status
Simulation time 58208564 ps
CPU time 0.92 seconds
Started Aug 15 06:32:13 PM PDT 24
Finished Aug 15 06:32:14 PM PDT 24
Peak memory 215380 kb
Host smart-5b95473e-9c1d-4016-b35f-9be9b1c4a203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856324492 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.856324492
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.567147164
Short name T347
Test name
Test status
Simulation time 382684015 ps
CPU time 3.61 seconds
Started Aug 15 06:32:17 PM PDT 24
Finished Aug 15 06:32:20 PM PDT 24
Peak memory 215424 kb
Host smart-a6f5a704-fb21-4e82-86d6-2eba8ff3dcdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567147164 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.567147164
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/110.edn_genbits.1529515524
Short name T703
Test name
Test status
Simulation time 42310428 ps
CPU time 1.43 seconds
Started Aug 15 06:33:47 PM PDT 24
Finished Aug 15 06:33:48 PM PDT 24
Peak memory 220248 kb
Host smart-65311908-3b9a-4094-bfeb-a8371db215f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529515524 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.1529515524
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.3822849482
Short name T541
Test name
Test status
Simulation time 27866784 ps
CPU time 1.31 seconds
Started Aug 15 06:33:41 PM PDT 24
Finished Aug 15 06:33:42 PM PDT 24
Peak memory 219796 kb
Host smart-313d96c4-d11d-420d-8b5e-472dff29a121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822849482 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.3822849482
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.2232040750
Short name T564
Test name
Test status
Simulation time 137097852 ps
CPU time 1.02 seconds
Started Aug 15 06:33:41 PM PDT 24
Finished Aug 15 06:33:42 PM PDT 24
Peak memory 217432 kb
Host smart-a57f15ec-7f30-47d5-89c0-3e5b60203c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232040750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.2232040750
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.4034039755
Short name T804
Test name
Test status
Simulation time 340155948 ps
CPU time 1.37 seconds
Started Aug 15 06:33:47 PM PDT 24
Finished Aug 15 06:33:49 PM PDT 24
Peak memory 220520 kb
Host smart-7f1b9046-5a5f-416a-8ee9-d23a3942961e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034039755 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.4034039755
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.2489329638
Short name T802
Test name
Test status
Simulation time 53188115 ps
CPU time 1.51 seconds
Started Aug 15 06:33:41 PM PDT 24
Finished Aug 15 06:33:43 PM PDT 24
Peak memory 218416 kb
Host smart-74899e98-034e-4b62-8dd3-ea865a735244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489329638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2489329638
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.2739503716
Short name T744
Test name
Test status
Simulation time 39584378 ps
CPU time 1.18 seconds
Started Aug 15 06:33:49 PM PDT 24
Finished Aug 15 06:33:51 PM PDT 24
Peak memory 218696 kb
Host smart-82091d16-badf-4491-b1fe-64a29b84251f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739503716 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.2739503716
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/115.edn_alert.3302730790
Short name T103
Test name
Test status
Simulation time 95356001 ps
CPU time 1.09 seconds
Started Aug 15 06:33:49 PM PDT 24
Finished Aug 15 06:33:50 PM PDT 24
Peak memory 219596 kb
Host smart-26425fba-4268-4c0c-b463-e0991ffd8cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302730790 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.3302730790
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.1401942954
Short name T339
Test name
Test status
Simulation time 54158242 ps
CPU time 1.58 seconds
Started Aug 15 06:33:49 PM PDT 24
Finished Aug 15 06:33:51 PM PDT 24
Peak memory 218404 kb
Host smart-01644053-c9fb-49f6-ac62-c89b4190f4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401942954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1401942954
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.2862395965
Short name T766
Test name
Test status
Simulation time 68274978 ps
CPU time 1.29 seconds
Started Aug 15 06:33:42 PM PDT 24
Finished Aug 15 06:33:43 PM PDT 24
Peak memory 217388 kb
Host smart-098da77e-8c8f-4fd6-a804-523eaf07d1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862395965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.2862395965
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.623244119
Short name T526
Test name
Test status
Simulation time 69310337 ps
CPU time 1.23 seconds
Started Aug 15 06:33:50 PM PDT 24
Finished Aug 15 06:33:52 PM PDT 24
Peak memory 215736 kb
Host smart-b2ff43c4-037a-46a9-9c78-167af1e00036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623244119 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.623244119
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.2662403335
Short name T907
Test name
Test status
Simulation time 80038075 ps
CPU time 1.12 seconds
Started Aug 15 06:33:47 PM PDT 24
Finished Aug 15 06:33:49 PM PDT 24
Peak memory 215428 kb
Host smart-0232aa9e-2102-445b-9ce3-603bea0940f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662403335 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.2662403335
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.3314723563
Short name T861
Test name
Test status
Simulation time 29509482 ps
CPU time 1.29 seconds
Started Aug 15 06:33:46 PM PDT 24
Finished Aug 15 06:33:47 PM PDT 24
Peak memory 217256 kb
Host smart-4cead78d-0645-4893-93f4-35127f44005f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314723563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3314723563
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.2354501833
Short name T486
Test name
Test status
Simulation time 22539807 ps
CPU time 1.22 seconds
Started Aug 15 06:33:42 PM PDT 24
Finished Aug 15 06:33:44 PM PDT 24
Peak memory 219972 kb
Host smart-b8101916-3bd2-4a3f-baf1-e1947b20835f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354501833 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.2354501833
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert.2636180991
Short name T659
Test name
Test status
Simulation time 38281792 ps
CPU time 1.14 seconds
Started Aug 15 06:32:15 PM PDT 24
Finished Aug 15 06:32:17 PM PDT 24
Peak memory 219792 kb
Host smart-0ee95855-1e34-4308-854e-c11412420f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636180991 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.2636180991
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.1188805173
Short name T695
Test name
Test status
Simulation time 45421383 ps
CPU time 1.01 seconds
Started Aug 15 06:32:13 PM PDT 24
Finished Aug 15 06:32:14 PM PDT 24
Peak memory 215072 kb
Host smart-85799a01-b9e0-4a8d-bb5f-3da4ec200bb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188805173 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.1188805173
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.4214558633
Short name T718
Test name
Test status
Simulation time 62757734 ps
CPU time 0.99 seconds
Started Aug 15 06:32:16 PM PDT 24
Finished Aug 15 06:32:18 PM PDT 24
Peak memory 218624 kb
Host smart-7a4b4b92-2761-4103-897a-39d7be86528c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214558633 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.4214558633
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.1556767925
Short name T914
Test name
Test status
Simulation time 44598261 ps
CPU time 1.12 seconds
Started Aug 15 06:32:16 PM PDT 24
Finished Aug 15 06:32:17 PM PDT 24
Peak memory 219700 kb
Host smart-b7553055-0f2f-44cf-9b6f-92aec2f38dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556767925 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.1556767925
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.1647127344
Short name T60
Test name
Test status
Simulation time 93558638 ps
CPU time 1.39 seconds
Started Aug 15 06:32:15 PM PDT 24
Finished Aug 15 06:32:17 PM PDT 24
Peak memory 219076 kb
Host smart-e64d868f-f397-4fb2-a2e6-9a9a1018c7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647127344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.1647127344
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_smoke.3130864292
Short name T670
Test name
Test status
Simulation time 47872704 ps
CPU time 0.95 seconds
Started Aug 15 06:32:15 PM PDT 24
Finished Aug 15 06:32:16 PM PDT 24
Peak memory 214612 kb
Host smart-e35fa9c3-48d1-4e44-bf52-e108ffb21e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130864292 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.3130864292
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.3909020966
Short name T859
Test name
Test status
Simulation time 591861142 ps
CPU time 4.28 seconds
Started Aug 15 06:32:16 PM PDT 24
Finished Aug 15 06:32:20 PM PDT 24
Peak memory 215432 kb
Host smart-249c8141-eded-46ed-a40a-f1e26379aba0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909020966 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.3909020966
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/120.edn_alert.1699354933
Short name T956
Test name
Test status
Simulation time 44995483 ps
CPU time 1.17 seconds
Started Aug 15 06:33:53 PM PDT 24
Finished Aug 15 06:33:54 PM PDT 24
Peak memory 219936 kb
Host smart-2844b30f-aaa4-4f5a-9be6-078e5cdce22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699354933 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.1699354933
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.982501183
Short name T610
Test name
Test status
Simulation time 234664093 ps
CPU time 1.29 seconds
Started Aug 15 06:33:36 PM PDT 24
Finished Aug 15 06:33:37 PM PDT 24
Peak memory 218988 kb
Host smart-2c20626f-8f99-4c12-8d59-463d5093a986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982501183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.982501183
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.1677085666
Short name T528
Test name
Test status
Simulation time 127239017 ps
CPU time 1.13 seconds
Started Aug 15 06:33:46 PM PDT 24
Finished Aug 15 06:33:48 PM PDT 24
Peak memory 220916 kb
Host smart-00d5af50-9e39-49e5-951d-feec9233bc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677085666 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.1677085666
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.2114241683
Short name T42
Test name
Test status
Simulation time 67864452 ps
CPU time 1.09 seconds
Started Aug 15 06:33:41 PM PDT 24
Finished Aug 15 06:33:42 PM PDT 24
Peak memory 218804 kb
Host smart-babd5fe5-d01c-4b0c-9d04-15df62ed7d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114241683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.2114241683
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.2819523019
Short name T614
Test name
Test status
Simulation time 226288098 ps
CPU time 1.31 seconds
Started Aug 15 06:33:59 PM PDT 24
Finished Aug 15 06:34:00 PM PDT 24
Peak memory 218632 kb
Host smart-123583ee-f601-4875-83a2-dc19212e9a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819523019 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.2819523019
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.994019827
Short name T301
Test name
Test status
Simulation time 43004851 ps
CPU time 1.63 seconds
Started Aug 15 06:33:58 PM PDT 24
Finished Aug 15 06:34:00 PM PDT 24
Peak memory 218532 kb
Host smart-1f3a3587-1d07-4763-9d55-53084a9b76d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994019827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.994019827
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.1629517781
Short name T152
Test name
Test status
Simulation time 30156628 ps
CPU time 1.28 seconds
Started Aug 15 06:34:04 PM PDT 24
Finished Aug 15 06:34:06 PM PDT 24
Peak memory 218880 kb
Host smart-35570124-61e7-4d64-a6d8-8ff85c747d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629517781 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.1629517781
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.2266115662
Short name T720
Test name
Test status
Simulation time 54007047 ps
CPU time 1.46 seconds
Started Aug 15 06:33:48 PM PDT 24
Finished Aug 15 06:33:50 PM PDT 24
Peak memory 218432 kb
Host smart-d3b5d957-f162-418e-a4cb-fecba5c2b624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266115662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2266115662
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.2387016404
Short name T582
Test name
Test status
Simulation time 58049427 ps
CPU time 1.11 seconds
Started Aug 15 06:33:43 PM PDT 24
Finished Aug 15 06:33:44 PM PDT 24
Peak memory 219236 kb
Host smart-702ca1c9-3a60-4343-8523-c2f13acea691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387016404 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.2387016404
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.2983307737
Short name T376
Test name
Test status
Simulation time 46252519 ps
CPU time 1.21 seconds
Started Aug 15 06:34:00 PM PDT 24
Finished Aug 15 06:34:01 PM PDT 24
Peak memory 218556 kb
Host smart-d2989e4a-fef3-4e12-8f54-42ecdf657f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983307737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.2983307737
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.342422535
Short name T354
Test name
Test status
Simulation time 75784180 ps
CPU time 1.18 seconds
Started Aug 15 06:33:58 PM PDT 24
Finished Aug 15 06:33:59 PM PDT 24
Peak memory 219900 kb
Host smart-a60107ac-25a7-464a-9b23-ad593bbd0391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342422535 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.342422535
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.2755019732
Short name T814
Test name
Test status
Simulation time 48705686 ps
CPU time 1.09 seconds
Started Aug 15 06:33:50 PM PDT 24
Finished Aug 15 06:33:51 PM PDT 24
Peak memory 217460 kb
Host smart-d87e5f27-f0c9-439e-bc4e-cea1e853d8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755019732 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.2755019732
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.2854877795
Short name T572
Test name
Test status
Simulation time 83025661 ps
CPU time 1.17 seconds
Started Aug 15 06:33:48 PM PDT 24
Finished Aug 15 06:33:49 PM PDT 24
Peak memory 219684 kb
Host smart-5f399407-a72a-4cad-b1a0-ed846858b67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854877795 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.2854877795
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.3217477554
Short name T334
Test name
Test status
Simulation time 40270513 ps
CPU time 1.65 seconds
Started Aug 15 06:33:58 PM PDT 24
Finished Aug 15 06:34:00 PM PDT 24
Peak memory 218756 kb
Host smart-78c7588c-18e4-466e-8128-dff4e54c63a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217477554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.3217477554
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.2419220332
Short name T534
Test name
Test status
Simulation time 163177572 ps
CPU time 1.08 seconds
Started Aug 15 06:33:55 PM PDT 24
Finished Aug 15 06:33:56 PM PDT 24
Peak memory 218480 kb
Host smart-2396d40e-3624-40d4-9b8f-d386b20aa52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419220332 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.2419220332
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.2191014885
Short name T897
Test name
Test status
Simulation time 31775818 ps
CPU time 1.22 seconds
Started Aug 15 06:33:52 PM PDT 24
Finished Aug 15 06:33:53 PM PDT 24
Peak memory 218548 kb
Host smart-f1b6fb48-7042-4a4d-91e2-c638f05c1c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191014885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.2191014885
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.3032226924
Short name T438
Test name
Test status
Simulation time 53080974 ps
CPU time 1.3 seconds
Started Aug 15 06:33:42 PM PDT 24
Finished Aug 15 06:33:43 PM PDT 24
Peak memory 218864 kb
Host smart-5f161e7c-efb8-4d40-b327-87a41b58bf46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032226924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3032226924
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.717362442
Short name T466
Test name
Test status
Simulation time 117379411 ps
CPU time 1.1 seconds
Started Aug 15 06:32:11 PM PDT 24
Finished Aug 15 06:32:12 PM PDT 24
Peak memory 218604 kb
Host smart-9d0db4c1-a9cd-4117-9e4f-c90a53cb5a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717362442 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.717362442
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_disable.813925274
Short name T211
Test name
Test status
Simulation time 76267842 ps
CPU time 0.83 seconds
Started Aug 15 06:32:15 PM PDT 24
Finished Aug 15 06:32:16 PM PDT 24
Peak memory 215364 kb
Host smart-c7371724-368a-4097-820b-8c0877acac17
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813925274 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.813925274
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.2529970987
Short name T520
Test name
Test status
Simulation time 30509760 ps
CPU time 1.03 seconds
Started Aug 15 06:32:15 PM PDT 24
Finished Aug 15 06:32:16 PM PDT 24
Peak memory 218584 kb
Host smart-9d7dfe97-ee01-4616-afa0-4d1cf0670ebb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529970987 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.2529970987
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_genbits.1733626356
Short name T598
Test name
Test status
Simulation time 37273399 ps
CPU time 1.03 seconds
Started Aug 15 06:32:17 PM PDT 24
Finished Aug 15 06:32:18 PM PDT 24
Peak memory 217404 kb
Host smart-0b7eba67-7039-4ade-81f3-010b45a75ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733626356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1733626356
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.2026193531
Short name T367
Test name
Test status
Simulation time 25636588 ps
CPU time 0.94 seconds
Started Aug 15 06:32:19 PM PDT 24
Finished Aug 15 06:32:20 PM PDT 24
Peak memory 215456 kb
Host smart-c334870a-556c-45fa-b436-5ca04610525e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026193531 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.2026193531
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.2783125233
Short name T628
Test name
Test status
Simulation time 58010088 ps
CPU time 0.92 seconds
Started Aug 15 06:32:15 PM PDT 24
Finished Aug 15 06:32:16 PM PDT 24
Peak memory 215296 kb
Host smart-5330d90d-6306-4427-bda7-1cedf4328a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783125233 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.2783125233
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.3172115523
Short name T684
Test name
Test status
Simulation time 266371009 ps
CPU time 5.37 seconds
Started Aug 15 06:32:20 PM PDT 24
Finished Aug 15 06:32:26 PM PDT 24
Peak memory 215340 kb
Host smart-75e586ce-f066-4912-892c-ec98dd888813
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172115523 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3172115523
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.3383407243
Short name T227
Test name
Test status
Simulation time 34464043830 ps
CPU time 72.31 seconds
Started Aug 15 06:32:15 PM PDT 24
Finished Aug 15 06:33:27 PM PDT 24
Peak memory 217376 kb
Host smart-1ab47301-0208-49ce-a0ce-bff957c551a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383407243 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.3383407243
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.4053805840
Short name T879
Test name
Test status
Simulation time 65402868 ps
CPU time 1.14 seconds
Started Aug 15 06:33:57 PM PDT 24
Finished Aug 15 06:33:59 PM PDT 24
Peak memory 219304 kb
Host smart-04f74e80-5984-4d45-ace6-f227842604b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053805840 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.4053805840
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/131.edn_alert.1651957342
Short name T651
Test name
Test status
Simulation time 95412757 ps
CPU time 1.23 seconds
Started Aug 15 06:33:53 PM PDT 24
Finished Aug 15 06:33:55 PM PDT 24
Peak memory 215832 kb
Host smart-b9244fe5-fdfe-4c2e-97a6-9ce12825b374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651957342 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.1651957342
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.96370420
Short name T871
Test name
Test status
Simulation time 39490411 ps
CPU time 1.59 seconds
Started Aug 15 06:33:57 PM PDT 24
Finished Aug 15 06:33:59 PM PDT 24
Peak memory 218780 kb
Host smart-0016fd02-2841-4004-8501-dd798e322ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96370420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.96370420
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.644954303
Short name T668
Test name
Test status
Simulation time 104576079 ps
CPU time 1.22 seconds
Started Aug 15 06:33:47 PM PDT 24
Finished Aug 15 06:33:49 PM PDT 24
Peak memory 218448 kb
Host smart-fdd5f10e-6a3b-49ee-9904-70903546ec0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644954303 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.644954303
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.3657835700
Short name T652
Test name
Test status
Simulation time 64513460 ps
CPU time 1.53 seconds
Started Aug 15 06:33:56 PM PDT 24
Finished Aug 15 06:33:58 PM PDT 24
Peak memory 218788 kb
Host smart-8476cbd0-26c2-4d21-8437-176097c5994a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657835700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3657835700
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.3991760697
Short name T619
Test name
Test status
Simulation time 26724938 ps
CPU time 1.16 seconds
Started Aug 15 06:34:04 PM PDT 24
Finished Aug 15 06:34:05 PM PDT 24
Peak memory 219680 kb
Host smart-9c8479c7-45f0-4717-9fbd-d126bc9d738f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991760697 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.3991760697
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.3757288491
Short name T324
Test name
Test status
Simulation time 46793870 ps
CPU time 1.13 seconds
Started Aug 15 06:33:50 PM PDT 24
Finished Aug 15 06:33:52 PM PDT 24
Peak memory 217464 kb
Host smart-fa37dba6-f1fa-48a1-b6f2-76aaab75bd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757288491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3757288491
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.2703499449
Short name T247
Test name
Test status
Simulation time 31110202 ps
CPU time 1.25 seconds
Started Aug 15 06:33:48 PM PDT 24
Finished Aug 15 06:33:49 PM PDT 24
Peak memory 220744 kb
Host smart-e2bc37f1-1e4c-4153-9c6b-01824574ad9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703499449 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.2703499449
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.2547745103
Short name T465
Test name
Test status
Simulation time 60763942 ps
CPU time 1.26 seconds
Started Aug 15 06:33:56 PM PDT 24
Finished Aug 15 06:33:58 PM PDT 24
Peak memory 218352 kb
Host smart-9fbccaf5-eb84-4249-bacd-9a1860c07a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547745103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.2547745103
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.1355415286
Short name T696
Test name
Test status
Simulation time 83382864 ps
CPU time 1.21 seconds
Started Aug 15 06:33:56 PM PDT 24
Finished Aug 15 06:33:57 PM PDT 24
Peak memory 220940 kb
Host smart-6268ec6c-8645-41fb-8cb5-3130b203b4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355415286 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.1355415286
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.1100582083
Short name T676
Test name
Test status
Simulation time 33182718 ps
CPU time 1.41 seconds
Started Aug 15 06:33:48 PM PDT 24
Finished Aug 15 06:33:50 PM PDT 24
Peak memory 217540 kb
Host smart-075985cf-3472-46ec-b1d7-3c4e830c80dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100582083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.1100582083
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.205186528
Short name T403
Test name
Test status
Simulation time 29868756 ps
CPU time 1.36 seconds
Started Aug 15 06:33:59 PM PDT 24
Finished Aug 15 06:34:00 PM PDT 24
Peak memory 219868 kb
Host smart-69f280dd-2820-4da3-8349-68350a05cae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205186528 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.205186528
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.178553972
Short name T494
Test name
Test status
Simulation time 31377677 ps
CPU time 1.34 seconds
Started Aug 15 06:33:49 PM PDT 24
Finished Aug 15 06:33:51 PM PDT 24
Peak memory 217600 kb
Host smart-2dc5f03c-3170-453c-8458-530536944479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178553972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.178553972
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.2916190376
Short name T85
Test name
Test status
Simulation time 27215515 ps
CPU time 1.22 seconds
Started Aug 15 06:33:59 PM PDT 24
Finished Aug 15 06:34:01 PM PDT 24
Peak memory 218588 kb
Host smart-5fabb319-811d-4e2a-944b-a05436639e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916190376 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.2916190376
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.860921683
Short name T944
Test name
Test status
Simulation time 27346234 ps
CPU time 1.27 seconds
Started Aug 15 06:34:04 PM PDT 24
Finished Aug 15 06:34:05 PM PDT 24
Peak memory 220388 kb
Host smart-fbefbe89-8e08-4a77-8227-079b5c381a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860921683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.860921683
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.2588495838
Short name T67
Test name
Test status
Simulation time 184575225 ps
CPU time 1.31 seconds
Started Aug 15 06:33:58 PM PDT 24
Finished Aug 15 06:33:59 PM PDT 24
Peak memory 219776 kb
Host smart-bb9ca41d-a9ab-4ea8-baf7-bf8de02fc191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588495838 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.2588495838
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.3118516351
Short name T663
Test name
Test status
Simulation time 49569301 ps
CPU time 1.24 seconds
Started Aug 15 06:34:00 PM PDT 24
Finished Aug 15 06:34:01 PM PDT 24
Peak memory 217500 kb
Host smart-768645e4-d69d-41a8-8525-f0c23d5b0c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118516351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3118516351
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.1772217750
Short name T574
Test name
Test status
Simulation time 124154142 ps
CPU time 1.22 seconds
Started Aug 15 06:32:18 PM PDT 24
Finished Aug 15 06:32:19 PM PDT 24
Peak memory 218608 kb
Host smart-00e4e977-0b12-40b7-878a-d81ed3f74621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772217750 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.1772217750
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.3933367256
Short name T504
Test name
Test status
Simulation time 33508434 ps
CPU time 1 seconds
Started Aug 15 06:32:24 PM PDT 24
Finished Aug 15 06:32:25 PM PDT 24
Peak memory 215048 kb
Host smart-4f679c87-9af6-493d-bfc4-4c073655c1be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933367256 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3933367256
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.2719874064
Short name T216
Test name
Test status
Simulation time 13149943 ps
CPU time 0.82 seconds
Started Aug 15 06:32:19 PM PDT 24
Finished Aug 15 06:32:21 PM PDT 24
Peak memory 215416 kb
Host smart-863cd9a5-a776-4d72-851c-217162563d25
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719874064 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.2719874064
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.1223406318
Short name T642
Test name
Test status
Simulation time 28235375 ps
CPU time 1.15 seconds
Started Aug 15 06:32:20 PM PDT 24
Finished Aug 15 06:32:22 PM PDT 24
Peak memory 216764 kb
Host smart-2e0f8be2-04a5-43f7-9502-e2ca1e3ce255
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223406318 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.1223406318
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.1237059678
Short name T623
Test name
Test status
Simulation time 28275107 ps
CPU time 0.93 seconds
Started Aug 15 06:32:22 PM PDT 24
Finished Aug 15 06:32:23 PM PDT 24
Peak memory 218240 kb
Host smart-1507e8cc-d854-4da0-b389-caf91b251de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237059678 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.1237059678
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.1181456081
Short name T372
Test name
Test status
Simulation time 75143071 ps
CPU time 1.43 seconds
Started Aug 15 06:32:18 PM PDT 24
Finished Aug 15 06:32:20 PM PDT 24
Peak memory 218900 kb
Host smart-eafe0aaf-ff45-46bb-b53a-ccead68bd403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181456081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1181456081
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.1890803910
Short name T93
Test name
Test status
Simulation time 30201665 ps
CPU time 0.91 seconds
Started Aug 15 06:32:19 PM PDT 24
Finished Aug 15 06:32:20 PM PDT 24
Peak memory 215980 kb
Host smart-b0e2da4b-1889-4299-8843-a08c071999c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890803910 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.1890803910
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.106186974
Short name T780
Test name
Test status
Simulation time 71999824 ps
CPU time 0.93 seconds
Started Aug 15 06:32:19 PM PDT 24
Finished Aug 15 06:32:20 PM PDT 24
Peak memory 215296 kb
Host smart-7ba651ef-8328-4255-897a-4079307d0cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106186974 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.106186974
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.2806045274
Short name T789
Test name
Test status
Simulation time 3109488418 ps
CPU time 84.09 seconds
Started Aug 15 06:32:24 PM PDT 24
Finished Aug 15 06:33:48 PM PDT 24
Peak memory 221252 kb
Host smart-e3745231-ea7d-4308-bbab-7158166de1c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806045274 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.2806045274
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/141.edn_alert.3838525366
Short name T82
Test name
Test status
Simulation time 67389032 ps
CPU time 1.09 seconds
Started Aug 15 06:33:56 PM PDT 24
Finished Aug 15 06:33:57 PM PDT 24
Peak memory 220172 kb
Host smart-8f695840-c00c-4318-8bfe-37c2658a489a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838525366 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.3838525366
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.4108399216
Short name T689
Test name
Test status
Simulation time 29214009 ps
CPU time 1.34 seconds
Started Aug 15 06:33:57 PM PDT 24
Finished Aug 15 06:33:59 PM PDT 24
Peak memory 218580 kb
Host smart-176948fc-7355-42bf-8b1e-e3b4ef336622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108399216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.4108399216
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.2048218913
Short name T139
Test name
Test status
Simulation time 67069986 ps
CPU time 1.06 seconds
Started Aug 15 06:33:46 PM PDT 24
Finished Aug 15 06:33:47 PM PDT 24
Peak memory 220800 kb
Host smart-e9015593-0fb1-4f49-90bf-2851893db886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048218913 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.2048218913
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.1697935697
Short name T646
Test name
Test status
Simulation time 185922765 ps
CPU time 1.01 seconds
Started Aug 15 06:33:57 PM PDT 24
Finished Aug 15 06:33:58 PM PDT 24
Peak memory 217516 kb
Host smart-122c16ec-1e49-468e-8a66-d69d9ef52b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697935697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1697935697
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.4031368041
Short name T765
Test name
Test status
Simulation time 24248030 ps
CPU time 1.15 seconds
Started Aug 15 06:33:59 PM PDT 24
Finished Aug 15 06:34:00 PM PDT 24
Peak memory 219584 kb
Host smart-877df081-4160-454f-9102-da8677d84277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031368041 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.4031368041
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.461809294
Short name T416
Test name
Test status
Simulation time 43898239 ps
CPU time 1.48 seconds
Started Aug 15 06:33:48 PM PDT 24
Finished Aug 15 06:33:50 PM PDT 24
Peak memory 219792 kb
Host smart-5b9a9ef3-2c7f-4e56-a997-4042d44fd21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461809294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.461809294
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.2167549368
Short name T793
Test name
Test status
Simulation time 55064280 ps
CPU time 0.94 seconds
Started Aug 15 06:34:04 PM PDT 24
Finished Aug 15 06:34:05 PM PDT 24
Peak memory 217360 kb
Host smart-51559ca1-50f3-47b9-8a80-6fc69a016429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167549368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.2167549368
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.2707311012
Short name T782
Test name
Test status
Simulation time 25421928 ps
CPU time 1.2 seconds
Started Aug 15 06:33:51 PM PDT 24
Finished Aug 15 06:33:52 PM PDT 24
Peak memory 218632 kb
Host smart-3807558d-cb7b-4c73-b490-ad9f97a1e0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707311012 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.2707311012
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.4146297369
Short name T414
Test name
Test status
Simulation time 31997776 ps
CPU time 1.27 seconds
Started Aug 15 06:33:57 PM PDT 24
Finished Aug 15 06:33:58 PM PDT 24
Peak memory 218504 kb
Host smart-44a81131-48f9-477a-bc33-2a77ed50aaa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146297369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.4146297369
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.1151855862
Short name T776
Test name
Test status
Simulation time 64785018 ps
CPU time 1.1 seconds
Started Aug 15 06:33:56 PM PDT 24
Finished Aug 15 06:33:57 PM PDT 24
Peak memory 215812 kb
Host smart-098db785-c48c-4272-a1d1-be36d5bf1ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151855862 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.1151855862
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.346258466
Short name T421
Test name
Test status
Simulation time 133489247 ps
CPU time 2.02 seconds
Started Aug 15 06:34:04 PM PDT 24
Finished Aug 15 06:34:06 PM PDT 24
Peak memory 217532 kb
Host smart-81e756cd-032b-4368-a8da-44c9e1f2979d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346258466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.346258466
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.4223493293
Short name T217
Test name
Test status
Simulation time 36743543 ps
CPU time 1.08 seconds
Started Aug 15 06:34:03 PM PDT 24
Finished Aug 15 06:34:04 PM PDT 24
Peak memory 219036 kb
Host smart-02cc0d84-6613-40c8-ba6f-1dde5650d809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223493293 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.4223493293
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.4053244353
Short name T419
Test name
Test status
Simulation time 48521651 ps
CPU time 1.51 seconds
Started Aug 15 06:33:49 PM PDT 24
Finished Aug 15 06:33:51 PM PDT 24
Peak memory 219264 kb
Host smart-603be3d6-483a-4c1d-99ed-69121c522d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053244353 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.4053244353
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.4236076590
Short name T888
Test name
Test status
Simulation time 48594135 ps
CPU time 1.13 seconds
Started Aug 15 06:33:56 PM PDT 24
Finished Aug 15 06:33:57 PM PDT 24
Peak memory 218696 kb
Host smart-447c2b02-4367-4c2b-81f0-1729d70493c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236076590 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.4236076590
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.3033413031
Short name T433
Test name
Test status
Simulation time 55499290 ps
CPU time 1.94 seconds
Started Aug 15 06:33:56 PM PDT 24
Finished Aug 15 06:33:58 PM PDT 24
Peak memory 218652 kb
Host smart-1ab7458d-f940-480c-86b1-81943c83f3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033413031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.3033413031
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.3054488481
Short name T592
Test name
Test status
Simulation time 98092349 ps
CPU time 1.33 seconds
Started Aug 15 06:33:58 PM PDT 24
Finished Aug 15 06:33:59 PM PDT 24
Peak memory 215712 kb
Host smart-dce8850f-45bc-4a73-8a01-66de4cbb019f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054488481 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.3054488481
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.2447893167
Short name T656
Test name
Test status
Simulation time 59377546 ps
CPU time 1.51 seconds
Started Aug 15 06:33:53 PM PDT 24
Finished Aug 15 06:33:54 PM PDT 24
Peak memory 218596 kb
Host smart-1301b646-d9cd-4864-9413-091ea05c236e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447893167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2447893167
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.1877223602
Short name T799
Test name
Test status
Simulation time 70473006 ps
CPU time 1.11 seconds
Started Aug 15 06:32:19 PM PDT 24
Finished Aug 15 06:32:21 PM PDT 24
Peak memory 218496 kb
Host smart-df4ff160-c8d4-4e79-9098-b5bf47ec9946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877223602 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.1877223602
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.2528507951
Short name T394
Test name
Test status
Simulation time 21132667 ps
CPU time 0.92 seconds
Started Aug 15 06:32:29 PM PDT 24
Finished Aug 15 06:32:30 PM PDT 24
Peak memory 206588 kb
Host smart-9ca89a1e-0531-452f-be02-58311faaed11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528507951 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2528507951
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.1735483868
Short name T857
Test name
Test status
Simulation time 30488282 ps
CPU time 0.88 seconds
Started Aug 15 06:32:23 PM PDT 24
Finished Aug 15 06:32:24 PM PDT 24
Peak memory 207036 kb
Host smart-559cf24a-2b1d-4bcb-a9ab-e39b39f60464
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735483868 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1735483868
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2481924861
Short name T519
Test name
Test status
Simulation time 44163039 ps
CPU time 1.03 seconds
Started Aug 15 06:32:19 PM PDT 24
Finished Aug 15 06:32:21 PM PDT 24
Peak memory 218624 kb
Host smart-d3447206-c847-460b-96fe-571153e28bff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481924861 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2481924861
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.2452767970
Short name T819
Test name
Test status
Simulation time 25940637 ps
CPU time 0.86 seconds
Started Aug 15 06:32:20 PM PDT 24
Finished Aug 15 06:32:21 PM PDT 24
Peak memory 218144 kb
Host smart-c9844fe3-0edf-4aa2-9d7b-438e38781bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452767970 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2452767970
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.134162889
Short name T43
Test name
Test status
Simulation time 63248938 ps
CPU time 1.62 seconds
Started Aug 15 06:32:24 PM PDT 24
Finished Aug 15 06:32:25 PM PDT 24
Peak memory 218824 kb
Host smart-9d4c3e6c-3d4f-4c93-8738-cd18e087b478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134162889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.134162889
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.577182272
Short name T436
Test name
Test status
Simulation time 37097238 ps
CPU time 0.99 seconds
Started Aug 15 06:32:23 PM PDT 24
Finished Aug 15 06:32:25 PM PDT 24
Peak memory 224080 kb
Host smart-f9d3c6be-af81-40e9-89ff-a2e2335e1213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577182272 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.577182272
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.1788125498
Short name T874
Test name
Test status
Simulation time 32256847 ps
CPU time 0.9 seconds
Started Aug 15 06:32:20 PM PDT 24
Finished Aug 15 06:32:21 PM PDT 24
Peak memory 215372 kb
Host smart-821ad920-10bc-413e-a18a-00f6c85aba34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788125498 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.1788125498
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.3111540016
Short name T478
Test name
Test status
Simulation time 793254107 ps
CPU time 4.44 seconds
Started Aug 15 06:32:20 PM PDT 24
Finished Aug 15 06:32:24 PM PDT 24
Peak memory 217300 kb
Host smart-b13128f4-2644-4128-8651-54911af1028a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111540016 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.3111540016
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2816711760
Short name T95
Test name
Test status
Simulation time 9994524863 ps
CPU time 72.32 seconds
Started Aug 15 06:32:19 PM PDT 24
Finished Aug 15 06:33:31 PM PDT 24
Peak memory 218832 kb
Host smart-08ed29a8-773d-4321-8769-5d30fc65d3ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816711760 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2816711760
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.1420717349
Short name T175
Test name
Test status
Simulation time 185635085 ps
CPU time 1.19 seconds
Started Aug 15 06:34:05 PM PDT 24
Finished Aug 15 06:34:06 PM PDT 24
Peak memory 219536 kb
Host smart-59b748bc-5478-4c4d-b88a-14e1a3ab6eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420717349 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.1420717349
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/151.edn_alert.1452037957
Short name T452
Test name
Test status
Simulation time 28461232 ps
CPU time 1.17 seconds
Started Aug 15 06:33:48 PM PDT 24
Finished Aug 15 06:33:49 PM PDT 24
Peak memory 219676 kb
Host smart-99b0d490-1e57-4f8f-97cc-91689b064309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452037957 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.1452037957
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.1656276806
Short name T511
Test name
Test status
Simulation time 54894827 ps
CPU time 1.44 seconds
Started Aug 15 06:34:00 PM PDT 24
Finished Aug 15 06:34:02 PM PDT 24
Peak memory 218824 kb
Host smart-73405ce1-12c3-4ec9-b901-73fecc3e97a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656276806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1656276806
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.4107179627
Short name T549
Test name
Test status
Simulation time 27929930 ps
CPU time 1.18 seconds
Started Aug 15 06:33:55 PM PDT 24
Finished Aug 15 06:33:56 PM PDT 24
Peak memory 219324 kb
Host smart-274b4124-5c6e-4416-a67a-078ab03f40f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107179627 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.4107179627
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.32875768
Short name T828
Test name
Test status
Simulation time 25877672 ps
CPU time 1.24 seconds
Started Aug 15 06:33:55 PM PDT 24
Finished Aug 15 06:33:56 PM PDT 24
Peak memory 219616 kb
Host smart-4899e633-1c4a-4fcd-9218-73a95e332b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32875768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.32875768
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.1067135928
Short name T108
Test name
Test status
Simulation time 47268893 ps
CPU time 1.25 seconds
Started Aug 15 06:33:52 PM PDT 24
Finished Aug 15 06:33:53 PM PDT 24
Peak memory 219872 kb
Host smart-72eb0786-6588-4a1a-af2f-d3a426efeefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067135928 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.1067135928
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.2299636602
Short name T606
Test name
Test status
Simulation time 37315721 ps
CPU time 1.37 seconds
Started Aug 15 06:33:58 PM PDT 24
Finished Aug 15 06:34:00 PM PDT 24
Peak memory 218364 kb
Host smart-8fdabeeb-97bc-4b6a-8d95-4ec0fd1f8b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299636602 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2299636602
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.4010493214
Short name T221
Test name
Test status
Simulation time 47726161 ps
CPU time 1.28 seconds
Started Aug 15 06:33:56 PM PDT 24
Finished Aug 15 06:33:58 PM PDT 24
Peak memory 221320 kb
Host smart-c6ad4cf2-6c5b-4a67-9205-22e5857f2702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010493214 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.4010493214
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.3473885564
Short name T489
Test name
Test status
Simulation time 53228651 ps
CPU time 1.64 seconds
Started Aug 15 06:33:50 PM PDT 24
Finished Aug 15 06:33:52 PM PDT 24
Peak memory 217348 kb
Host smart-0145b144-b5d9-41ef-9568-13248238162e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473885564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.3473885564
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.248231314
Short name T514
Test name
Test status
Simulation time 160905087 ps
CPU time 1.26 seconds
Started Aug 15 06:33:58 PM PDT 24
Finished Aug 15 06:34:00 PM PDT 24
Peak memory 219464 kb
Host smart-c29137d7-758f-4cbd-be9c-09b0d1f09728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248231314 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.248231314
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.2116067299
Short name T612
Test name
Test status
Simulation time 82099757 ps
CPU time 1.28 seconds
Started Aug 15 06:34:00 PM PDT 24
Finished Aug 15 06:34:01 PM PDT 24
Peak memory 217408 kb
Host smart-68d7f9d1-a1b4-4da6-989b-4586bf301d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116067299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2116067299
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.4191774091
Short name T185
Test name
Test status
Simulation time 76427445 ps
CPU time 1.17 seconds
Started Aug 15 06:34:02 PM PDT 24
Finished Aug 15 06:34:03 PM PDT 24
Peak memory 220596 kb
Host smart-d7b13406-cd94-411a-816c-ce9a2bafa873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191774091 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.4191774091
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.1033564594
Short name T311
Test name
Test status
Simulation time 81609665 ps
CPU time 2.09 seconds
Started Aug 15 06:33:57 PM PDT 24
Finished Aug 15 06:34:00 PM PDT 24
Peak memory 220596 kb
Host smart-28816221-8358-4076-bae4-feea3682d2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033564594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.1033564594
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.3491533600
Short name T609
Test name
Test status
Simulation time 27230592 ps
CPU time 1.22 seconds
Started Aug 15 06:33:56 PM PDT 24
Finished Aug 15 06:33:57 PM PDT 24
Peak memory 219852 kb
Host smart-6b6d3e35-4f82-40b5-97cc-611ef36a6a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491533600 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.3491533600
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.4133274299
Short name T739
Test name
Test status
Simulation time 33481766 ps
CPU time 1.25 seconds
Started Aug 15 06:34:04 PM PDT 24
Finished Aug 15 06:34:06 PM PDT 24
Peak memory 215364 kb
Host smart-dcfa67d3-14f9-4030-9b45-fe1fda1de3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133274299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.4133274299
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.2698986415
Short name T559
Test name
Test status
Simulation time 85960077 ps
CPU time 1.18 seconds
Started Aug 15 06:34:02 PM PDT 24
Finished Aug 15 06:34:03 PM PDT 24
Peak memory 218920 kb
Host smart-db62c23b-1ebe-4b2c-845d-a2759abe9851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698986415 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.2698986415
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/159.edn_alert.2494332849
Short name T533
Test name
Test status
Simulation time 46445394 ps
CPU time 1.1 seconds
Started Aug 15 06:33:58 PM PDT 24
Finished Aug 15 06:34:00 PM PDT 24
Peak memory 218820 kb
Host smart-cd7cbdfe-7d14-487c-9bb6-278d3c91a484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494332849 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.2494332849
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.396554457
Short name T868
Test name
Test status
Simulation time 183905187 ps
CPU time 1.44 seconds
Started Aug 15 06:33:59 PM PDT 24
Finished Aug 15 06:34:00 PM PDT 24
Peak memory 218812 kb
Host smart-be76e1b1-6333-4a6b-978e-451c82ea2733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396554457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.396554457
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.3093289169
Short name T303
Test name
Test status
Simulation time 27729273 ps
CPU time 1.17 seconds
Started Aug 15 06:32:20 PM PDT 24
Finished Aug 15 06:32:22 PM PDT 24
Peak memory 215740 kb
Host smart-6b57c085-3574-4ead-b6e3-da7073957dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093289169 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3093289169
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.1160442692
Short name T937
Test name
Test status
Simulation time 49267722 ps
CPU time 0.89 seconds
Started Aug 15 06:32:18 PM PDT 24
Finished Aug 15 06:32:19 PM PDT 24
Peak memory 214940 kb
Host smart-f46836ed-bb65-41d7-9e7f-98e062a9eb44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160442692 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1160442692
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.1972488331
Short name T577
Test name
Test status
Simulation time 11623203 ps
CPU time 0.93 seconds
Started Aug 15 06:32:20 PM PDT 24
Finished Aug 15 06:32:21 PM PDT 24
Peak memory 215172 kb
Host smart-813b5541-4ec6-4723-a21e-219d44e07e1a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972488331 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.1972488331
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2893444909
Short name T39
Test name
Test status
Simulation time 32823401 ps
CPU time 0.99 seconds
Started Aug 15 06:32:19 PM PDT 24
Finished Aug 15 06:32:21 PM PDT 24
Peak memory 216824 kb
Host smart-d86e445d-c8b6-4ac0-a829-e67f31b3fc1f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893444909 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2893444909
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.3241156279
Short name T827
Test name
Test status
Simulation time 28715186 ps
CPU time 0.94 seconds
Started Aug 15 06:32:21 PM PDT 24
Finished Aug 15 06:32:22 PM PDT 24
Peak memory 223992 kb
Host smart-4e47cfae-ab6c-454f-aadc-98dd624e9579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241156279 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.3241156279
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.4054603856
Short name T657
Test name
Test status
Simulation time 43336411 ps
CPU time 1.39 seconds
Started Aug 15 06:32:19 PM PDT 24
Finished Aug 15 06:32:21 PM PDT 24
Peak memory 218760 kb
Host smart-64601356-48b1-4f62-80a5-0b8783b8125b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054603856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.4054603856
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.1442190602
Short name T53
Test name
Test status
Simulation time 53866426 ps
CPU time 0.95 seconds
Started Aug 15 06:32:21 PM PDT 24
Finished Aug 15 06:32:22 PM PDT 24
Peak memory 224068 kb
Host smart-e4826e36-c4ea-4d59-a063-543a1864ae76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442190602 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.1442190602
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.3563672694
Short name T406
Test name
Test status
Simulation time 35687689 ps
CPU time 0.91 seconds
Started Aug 15 06:32:29 PM PDT 24
Finished Aug 15 06:32:30 PM PDT 24
Peak memory 215324 kb
Host smart-62934f37-140e-4e26-9fb5-ad2232787915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563672694 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.3563672694
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.545101835
Short name T940
Test name
Test status
Simulation time 494522891 ps
CPU time 4.98 seconds
Started Aug 15 06:32:23 PM PDT 24
Finished Aug 15 06:32:28 PM PDT 24
Peak memory 217504 kb
Host smart-2eb35edc-8cc1-45af-a43f-41f0f4854ed9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545101835 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.545101835
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.733487395
Short name T230
Test name
Test status
Simulation time 15826456830 ps
CPU time 94.59 seconds
Started Aug 15 06:32:22 PM PDT 24
Finished Aug 15 06:33:57 PM PDT 24
Peak memory 222008 kb
Host smart-0dc3a476-2965-4293-99e1-a19eb63ae407
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733487395 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.733487395
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.2334052137
Short name T864
Test name
Test status
Simulation time 124034350 ps
CPU time 2.83 seconds
Started Aug 15 06:34:01 PM PDT 24
Finished Aug 15 06:34:05 PM PDT 24
Peak memory 217476 kb
Host smart-a6d45512-35bc-4495-956c-3c5ca4dfc06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334052137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.2334052137
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.3341758286
Short name T808
Test name
Test status
Simulation time 41509332 ps
CPU time 1.14 seconds
Started Aug 15 06:33:59 PM PDT 24
Finished Aug 15 06:34:01 PM PDT 24
Peak memory 218720 kb
Host smart-d6a66763-7544-4046-b542-c758dec80965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341758286 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.3341758286
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.1081485140
Short name T673
Test name
Test status
Simulation time 240388513 ps
CPU time 3.26 seconds
Started Aug 15 06:34:00 PM PDT 24
Finished Aug 15 06:34:04 PM PDT 24
Peak memory 220672 kb
Host smart-048b7640-4b94-4bc3-8d21-d8a972bb9ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081485140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1081485140
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.539014842
Short name T638
Test name
Test status
Simulation time 125822347 ps
CPU time 1.06 seconds
Started Aug 15 06:33:57 PM PDT 24
Finished Aug 15 06:33:58 PM PDT 24
Peak memory 218636 kb
Host smart-5786a690-685a-4d64-abd4-b5f551e58c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539014842 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.539014842
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.374793456
Short name T554
Test name
Test status
Simulation time 55376882 ps
CPU time 1.04 seconds
Started Aug 15 06:34:03 PM PDT 24
Finished Aug 15 06:34:04 PM PDT 24
Peak memory 217876 kb
Host smart-369e80c0-f4b6-4a76-acc6-ffb3eac339bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374793456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.374793456
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.1953788420
Short name T732
Test name
Test status
Simulation time 123133934 ps
CPU time 1.12 seconds
Started Aug 15 06:34:01 PM PDT 24
Finished Aug 15 06:34:02 PM PDT 24
Peak memory 220220 kb
Host smart-463be0eb-37b2-4172-9e88-4e3853dac697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953788420 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.1953788420
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.760003555
Short name T917
Test name
Test status
Simulation time 305227122 ps
CPU time 1.69 seconds
Started Aug 15 06:34:07 PM PDT 24
Finished Aug 15 06:34:08 PM PDT 24
Peak memory 218940 kb
Host smart-41834351-d5f7-4e7f-aaeb-3ddf02ddfda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760003555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.760003555
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.2453686717
Short name T816
Test name
Test status
Simulation time 29233617 ps
CPU time 1.32 seconds
Started Aug 15 06:34:02 PM PDT 24
Finished Aug 15 06:34:03 PM PDT 24
Peak memory 218760 kb
Host smart-10af62e2-6354-4051-b05c-c7cd7f26c4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453686717 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.2453686717
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.3472043771
Short name T717
Test name
Test status
Simulation time 27144147 ps
CPU time 1.26 seconds
Started Aug 15 06:33:59 PM PDT 24
Finished Aug 15 06:34:01 PM PDT 24
Peak memory 217496 kb
Host smart-70b10c25-856b-4696-98cf-fae13919b732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472043771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3472043771
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.1311948352
Short name T147
Test name
Test status
Simulation time 25856116 ps
CPU time 1.2 seconds
Started Aug 15 06:33:58 PM PDT 24
Finished Aug 15 06:33:59 PM PDT 24
Peak memory 218868 kb
Host smart-0dcb856c-d84d-4d38-a486-308614ad9c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311948352 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.1311948352
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.3674887116
Short name T75
Test name
Test status
Simulation time 55732492 ps
CPU time 2.02 seconds
Started Aug 15 06:34:00 PM PDT 24
Finished Aug 15 06:34:02 PM PDT 24
Peak memory 218440 kb
Host smart-7eab9e83-1e81-4c42-8538-b6b0019514bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674887116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3674887116
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.735446028
Short name T608
Test name
Test status
Simulation time 79096570 ps
CPU time 1.68 seconds
Started Aug 15 06:34:00 PM PDT 24
Finished Aug 15 06:34:02 PM PDT 24
Peak memory 219372 kb
Host smart-82d83b22-155a-48ef-8891-82277063cf78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735446028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.735446028
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.2071178623
Short name T351
Test name
Test status
Simulation time 25748227 ps
CPU time 1.24 seconds
Started Aug 15 06:33:59 PM PDT 24
Finished Aug 15 06:34:00 PM PDT 24
Peak memory 218692 kb
Host smart-b899e121-d1ce-454e-a59b-47330e4acc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071178623 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.2071178623
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.3378074286
Short name T764
Test name
Test status
Simulation time 84686336 ps
CPU time 1.09 seconds
Started Aug 15 06:33:59 PM PDT 24
Finished Aug 15 06:34:01 PM PDT 24
Peak memory 217564 kb
Host smart-d1c6628d-e8b2-4da6-b884-9b8e1c2524e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378074286 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.3378074286
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.968775008
Short name T59
Test name
Test status
Simulation time 25533490 ps
CPU time 1.14 seconds
Started Aug 15 06:33:59 PM PDT 24
Finished Aug 15 06:34:01 PM PDT 24
Peak memory 218744 kb
Host smart-92a2e831-b8b2-488d-89ce-c0042574af6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968775008 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.968775008
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/169.edn_alert.1739302352
Short name T510
Test name
Test status
Simulation time 181204197 ps
CPU time 1.21 seconds
Started Aug 15 06:33:59 PM PDT 24
Finished Aug 15 06:34:00 PM PDT 24
Peak memory 220812 kb
Host smart-91d47e31-43e0-4b34-b4ac-a1be5488f7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739302352 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.1739302352
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.1377094650
Short name T891
Test name
Test status
Simulation time 37749075 ps
CPU time 1.44 seconds
Started Aug 15 06:34:00 PM PDT 24
Finished Aug 15 06:34:02 PM PDT 24
Peak memory 217428 kb
Host smart-12008154-7393-4c11-916d-19c735c98db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377094650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.1377094650
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.3434850933
Short name T831
Test name
Test status
Simulation time 88067241 ps
CPU time 1.24 seconds
Started Aug 15 06:32:20 PM PDT 24
Finished Aug 15 06:32:21 PM PDT 24
Peak memory 218592 kb
Host smart-deafff21-db19-47cc-89b4-aab632bd3a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434850933 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.3434850933
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.179196873
Short name T314
Test name
Test status
Simulation time 24897086 ps
CPU time 0.9 seconds
Started Aug 15 06:32:29 PM PDT 24
Finished Aug 15 06:32:30 PM PDT 24
Peak memory 214940 kb
Host smart-b0e215e9-d087-4fdf-aa93-7429dd2a1415
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179196873 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.179196873
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.1872387546
Short name T803
Test name
Test status
Simulation time 15457425 ps
CPU time 0.92 seconds
Started Aug 15 06:32:29 PM PDT 24
Finished Aug 15 06:32:30 PM PDT 24
Peak memory 215152 kb
Host smart-c37e7253-28c6-45ec-886c-a2944f246b45
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872387546 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.1872387546
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.104290996
Short name T597
Test name
Test status
Simulation time 32887493 ps
CPU time 1.19 seconds
Started Aug 15 06:32:18 PM PDT 24
Finished Aug 15 06:32:19 PM PDT 24
Peak memory 218292 kb
Host smart-05dfca27-0b96-498b-98da-ee137a464582
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104290996 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_di
sable_auto_req_mode.104290996
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.2643912559
Short name T178
Test name
Test status
Simulation time 24493514 ps
CPU time 0.95 seconds
Started Aug 15 06:32:29 PM PDT 24
Finished Aug 15 06:32:30 PM PDT 24
Peak memory 218388 kb
Host smart-12a7e399-cd55-4520-be70-b8b0470cc5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643912559 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.2643912559
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.3855392742
Short name T909
Test name
Test status
Simulation time 39120942 ps
CPU time 1.36 seconds
Started Aug 15 06:32:21 PM PDT 24
Finished Aug 15 06:32:22 PM PDT 24
Peak memory 218544 kb
Host smart-d1aadc24-03ca-4b52-839e-6d1b6d8c0e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855392742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3855392742
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.342069999
Short name T589
Test name
Test status
Simulation time 55982135 ps
CPU time 0.91 seconds
Started Aug 15 06:32:18 PM PDT 24
Finished Aug 15 06:32:19 PM PDT 24
Peak memory 215308 kb
Host smart-a0e79fa7-9c67-4093-bfec-101e78f51519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342069999 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.342069999
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.424863670
Short name T25
Test name
Test status
Simulation time 17244936 ps
CPU time 1.01 seconds
Started Aug 15 06:32:30 PM PDT 24
Finished Aug 15 06:32:31 PM PDT 24
Peak memory 207144 kb
Host smart-d0e5e71d-44f9-4869-9fa2-2fa8afe26b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424863670 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.424863670
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.394999579
Short name T506
Test name
Test status
Simulation time 831913261 ps
CPU time 4.36 seconds
Started Aug 15 06:32:18 PM PDT 24
Finished Aug 15 06:32:23 PM PDT 24
Peak memory 217268 kb
Host smart-bc825d13-2ec0-45a4-8eec-b6b5c20da792
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394999579 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.394999579
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/170.edn_alert.1850975324
Short name T188
Test name
Test status
Simulation time 48781422 ps
CPU time 1.14 seconds
Started Aug 15 06:34:04 PM PDT 24
Finished Aug 15 06:34:05 PM PDT 24
Peak memory 220260 kb
Host smart-38758df6-5545-4026-9d70-2b29d7423074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850975324 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.1850975324
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.2065792810
Short name T484
Test name
Test status
Simulation time 77539981 ps
CPU time 1.75 seconds
Started Aug 15 06:33:57 PM PDT 24
Finished Aug 15 06:33:59 PM PDT 24
Peak memory 218840 kb
Host smart-8c921eca-b5af-4519-af55-a6fd89df7f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065792810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2065792810
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.651107840
Short name T28
Test name
Test status
Simulation time 132185555 ps
CPU time 1.11 seconds
Started Aug 15 06:34:04 PM PDT 24
Finished Aug 15 06:34:06 PM PDT 24
Peak memory 218420 kb
Host smart-68ac726b-12a5-41a0-89d4-7c18d30323d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651107840 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.651107840
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.648429098
Short name T798
Test name
Test status
Simulation time 54596082 ps
CPU time 1.35 seconds
Started Aug 15 06:33:56 PM PDT 24
Finished Aug 15 06:33:58 PM PDT 24
Peak memory 217452 kb
Host smart-b0ea8f69-6097-4479-9beb-efd08cd7cd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648429098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.648429098
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.1639422534
Short name T391
Test name
Test status
Simulation time 25833037 ps
CPU time 1.27 seconds
Started Aug 15 06:33:55 PM PDT 24
Finished Aug 15 06:33:57 PM PDT 24
Peak memory 219624 kb
Host smart-57cf57af-d156-4358-849b-f73a3a89329f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639422534 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.1639422534
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.2437192683
Short name T21
Test name
Test status
Simulation time 87212086 ps
CPU time 2.88 seconds
Started Aug 15 06:33:52 PM PDT 24
Finished Aug 15 06:33:55 PM PDT 24
Peak memory 219804 kb
Host smart-7ba24116-cb61-4795-9284-43e74d971462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437192683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.2437192683
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.2744262182
Short name T855
Test name
Test status
Simulation time 23938650 ps
CPU time 1.28 seconds
Started Aug 15 06:34:01 PM PDT 24
Finished Aug 15 06:34:02 PM PDT 24
Peak memory 219316 kb
Host smart-6494b675-99fd-43d4-b788-117380cc5a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744262182 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.2744262182
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.1048426784
Short name T411
Test name
Test status
Simulation time 82039232 ps
CPU time 1.46 seconds
Started Aug 15 06:33:56 PM PDT 24
Finished Aug 15 06:33:57 PM PDT 24
Peak memory 218688 kb
Host smart-12d2d0b7-de9c-4e66-ac87-53e3e82ff8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048426784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1048426784
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.219061358
Short name T309
Test name
Test status
Simulation time 32972528 ps
CPU time 1.39 seconds
Started Aug 15 06:34:06 PM PDT 24
Finished Aug 15 06:34:08 PM PDT 24
Peak memory 215676 kb
Host smart-4f99f534-a7d1-455c-9d47-0e895a86393c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219061358 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.219061358
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.2147809047
Short name T432
Test name
Test status
Simulation time 92835761 ps
CPU time 1.2 seconds
Started Aug 15 06:33:54 PM PDT 24
Finished Aug 15 06:33:55 PM PDT 24
Peak memory 217240 kb
Host smart-a6dc53d7-07a8-4775-a09d-7568a7f684fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147809047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2147809047
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.3499094547
Short name T922
Test name
Test status
Simulation time 37281654 ps
CPU time 1.14 seconds
Started Aug 15 06:34:04 PM PDT 24
Finished Aug 15 06:34:06 PM PDT 24
Peak memory 219428 kb
Host smart-991b83c9-a05b-4bf0-b12a-eb715f3c9950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499094547 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.3499094547
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.1325121132
Short name T363
Test name
Test status
Simulation time 87895077 ps
CPU time 1.3 seconds
Started Aug 15 06:34:07 PM PDT 24
Finished Aug 15 06:34:09 PM PDT 24
Peak memory 218776 kb
Host smart-9526666d-3cf0-4099-9444-da58f6678bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325121132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.1325121132
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.2020181234
Short name T168
Test name
Test status
Simulation time 44410480 ps
CPU time 1.18 seconds
Started Aug 15 06:34:04 PM PDT 24
Finished Aug 15 06:34:06 PM PDT 24
Peak memory 219828 kb
Host smart-9ce58bf7-576e-4880-b82f-62a9e374eb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020181234 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.2020181234
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.882517450
Short name T430
Test name
Test status
Simulation time 276915590 ps
CPU time 3.95 seconds
Started Aug 15 06:34:04 PM PDT 24
Finished Aug 15 06:34:08 PM PDT 24
Peak memory 219180 kb
Host smart-3a9ae99e-5dfb-44d7-9729-470794983488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882517450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.882517450
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.2525924017
Short name T84
Test name
Test status
Simulation time 62264649 ps
CPU time 1.24 seconds
Started Aug 15 06:34:02 PM PDT 24
Finished Aug 15 06:34:03 PM PDT 24
Peak memory 220212 kb
Host smart-6a99f598-1a08-4363-89aa-d05f973ac117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525924017 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.2525924017
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.4147027355
Short name T733
Test name
Test status
Simulation time 76292047 ps
CPU time 1.22 seconds
Started Aug 15 06:34:01 PM PDT 24
Finished Aug 15 06:34:02 PM PDT 24
Peak memory 218912 kb
Host smart-0e428709-1645-4c6d-bd5f-568095213628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147027355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.4147027355
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.1644870209
Short name T166
Test name
Test status
Simulation time 45492929 ps
CPU time 1.18 seconds
Started Aug 15 06:34:05 PM PDT 24
Finished Aug 15 06:34:06 PM PDT 24
Peak memory 221044 kb
Host smart-3047ddcd-3ae2-418d-892e-906755ea547b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644870209 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.1644870209
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.3920082167
Short name T758
Test name
Test status
Simulation time 39980654 ps
CPU time 1.37 seconds
Started Aug 15 06:34:07 PM PDT 24
Finished Aug 15 06:34:09 PM PDT 24
Peak memory 218480 kb
Host smart-a199e508-1c1b-43f8-911d-e1cdb7ac762f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920082167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3920082167
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.2740540637
Short name T613
Test name
Test status
Simulation time 75405254 ps
CPU time 1.22 seconds
Started Aug 15 06:34:03 PM PDT 24
Finished Aug 15 06:34:04 PM PDT 24
Peak memory 218660 kb
Host smart-4c41cf50-c437-4fb5-8f8f-a767ea85b03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740540637 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.2740540637
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.3952016519
Short name T467
Test name
Test status
Simulation time 48258501 ps
CPU time 1.46 seconds
Started Aug 15 06:34:01 PM PDT 24
Finished Aug 15 06:34:02 PM PDT 24
Peak memory 220284 kb
Host smart-70d36597-2a85-4453-a3ec-1f5eb733936e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952016519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3952016519
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.3599515120
Short name T813
Test name
Test status
Simulation time 44201944 ps
CPU time 1.17 seconds
Started Aug 15 06:32:26 PM PDT 24
Finished Aug 15 06:32:28 PM PDT 24
Peak memory 219184 kb
Host smart-2e76fb01-9745-4c00-9855-dfa880772e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599515120 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.3599515120
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.456100330
Short name T24
Test name
Test status
Simulation time 12749298 ps
CPU time 0.93 seconds
Started Aug 15 06:32:28 PM PDT 24
Finished Aug 15 06:32:29 PM PDT 24
Peak memory 207004 kb
Host smart-cd49fba8-0114-43fd-acea-ac4c6dcb4c4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456100330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.456100330
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.1433477641
Short name T927
Test name
Test status
Simulation time 82342598 ps
CPU time 0.85 seconds
Started Aug 15 06:32:28 PM PDT 24
Finished Aug 15 06:32:29 PM PDT 24
Peak memory 215204 kb
Host smart-3b8eadd4-4614-4c1f-a5b8-e94575e35e62
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433477641 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1433477641
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.365914435
Short name T713
Test name
Test status
Simulation time 82018832 ps
CPU time 1.07 seconds
Started Aug 15 06:32:31 PM PDT 24
Finished Aug 15 06:32:32 PM PDT 24
Peak memory 216948 kb
Host smart-291b3c1a-10eb-4ef4-a72d-0b6ace187c82
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365914435 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_di
sable_auto_req_mode.365914435
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.293152047
Short name T106
Test name
Test status
Simulation time 24244545 ps
CPU time 1.32 seconds
Started Aug 15 06:32:29 PM PDT 24
Finished Aug 15 06:32:31 PM PDT 24
Peak memory 229804 kb
Host smart-45dcc47e-a8d0-46a8-9167-ea884bd131a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293152047 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.293152047
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.2736538618
Short name T645
Test name
Test status
Simulation time 62462718 ps
CPU time 1.33 seconds
Started Aug 15 06:32:23 PM PDT 24
Finished Aug 15 06:32:24 PM PDT 24
Peak memory 217304 kb
Host smart-5007a43a-468e-42f8-9551-507539cf8736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736538618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2736538618
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_smoke.2841252979
Short name T236
Test name
Test status
Simulation time 56303837 ps
CPU time 0.94 seconds
Started Aug 15 06:32:24 PM PDT 24
Finished Aug 15 06:32:25 PM PDT 24
Peak memory 207188 kb
Host smart-d6a90b17-226f-4bec-b588-38fec94a23f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841252979 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2841252979
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1843823638
Short name T507
Test name
Test status
Simulation time 164623371 ps
CPU time 0.96 seconds
Started Aug 15 06:32:26 PM PDT 24
Finished Aug 15 06:32:27 PM PDT 24
Peak memory 206448 kb
Host smart-952b3485-0fff-45c1-9ff6-cf35e8086436
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843823638 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1843823638
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1584853481
Short name T232
Test name
Test status
Simulation time 3239108450 ps
CPU time 74.32 seconds
Started Aug 15 06:32:29 PM PDT 24
Finished Aug 15 06:33:44 PM PDT 24
Peak memory 217996 kb
Host smart-7da99657-43bc-4b22-9860-cad7b29065c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584853481 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1584853481
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.3795196334
Short name T427
Test name
Test status
Simulation time 63605804 ps
CPU time 1.16 seconds
Started Aug 15 06:34:10 PM PDT 24
Finished Aug 15 06:34:11 PM PDT 24
Peak memory 215736 kb
Host smart-ae18cd98-fa8d-46d7-80a5-04e28b3e9d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795196334 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.3795196334
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.2093106411
Short name T275
Test name
Test status
Simulation time 97540406 ps
CPU time 1.49 seconds
Started Aug 15 06:34:11 PM PDT 24
Finished Aug 15 06:34:13 PM PDT 24
Peak memory 218720 kb
Host smart-2deeee03-3653-4f8c-a57f-ac23678d5925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093106411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.2093106411
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.4134982263
Short name T631
Test name
Test status
Simulation time 42149771 ps
CPU time 1.15 seconds
Started Aug 15 06:34:14 PM PDT 24
Finished Aug 15 06:34:16 PM PDT 24
Peak memory 220752 kb
Host smart-d8526bc4-d074-45d1-a0fd-0d40f8fc2f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134982263 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.4134982263
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.3507616090
Short name T726
Test name
Test status
Simulation time 89574371 ps
CPU time 1.15 seconds
Started Aug 15 06:34:04 PM PDT 24
Finished Aug 15 06:34:05 PM PDT 24
Peak memory 217312 kb
Host smart-b5d3e461-42e8-48ae-b1ee-93c578d5df31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507616090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3507616090
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.3375298712
Short name T122
Test name
Test status
Simulation time 28987223 ps
CPU time 1.31 seconds
Started Aug 15 06:33:59 PM PDT 24
Finished Aug 15 06:34:01 PM PDT 24
Peak memory 219480 kb
Host smart-98fb2f3c-6ed8-4c65-b802-d2248861ee0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375298712 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.3375298712
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.672937223
Short name T458
Test name
Test status
Simulation time 48556004 ps
CPU time 1.25 seconds
Started Aug 15 06:34:08 PM PDT 24
Finished Aug 15 06:34:09 PM PDT 24
Peak memory 218928 kb
Host smart-8e10130e-157d-418b-9b5b-bdae8ee7ef63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672937223 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.672937223
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.1758909952
Short name T154
Test name
Test status
Simulation time 76063352 ps
CPU time 1.14 seconds
Started Aug 15 06:34:06 PM PDT 24
Finished Aug 15 06:34:07 PM PDT 24
Peak memory 218600 kb
Host smart-d8b6db24-3a9a-4a33-a1ac-4ab34043a5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758909952 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.1758909952
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.3944352138
Short name T321
Test name
Test status
Simulation time 258240897 ps
CPU time 1.02 seconds
Started Aug 15 06:34:05 PM PDT 24
Finished Aug 15 06:34:06 PM PDT 24
Peak memory 217512 kb
Host smart-8fab908e-f690-48d0-9dc0-ae5ccc2e5c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944352138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.3944352138
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.1504876623
Short name T305
Test name
Test status
Simulation time 50382403 ps
CPU time 1.2 seconds
Started Aug 15 06:34:00 PM PDT 24
Finished Aug 15 06:34:01 PM PDT 24
Peak memory 218828 kb
Host smart-261ff0a0-8bae-46b1-b10e-16de63b9ea99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504876623 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.1504876623
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.263322204
Short name T481
Test name
Test status
Simulation time 30453525 ps
CPU time 1.19 seconds
Started Aug 15 06:34:12 PM PDT 24
Finished Aug 15 06:34:13 PM PDT 24
Peak memory 218584 kb
Host smart-6658a2de-2d0a-4bd8-addb-f45aa12c879d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263322204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.263322204
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.3671931039
Short name T242
Test name
Test status
Simulation time 101585293 ps
CPU time 1.13 seconds
Started Aug 15 06:34:02 PM PDT 24
Finished Aug 15 06:34:04 PM PDT 24
Peak memory 219504 kb
Host smart-c0e7844e-c5ec-46a5-9e16-a8490177d3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671931039 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.3671931039
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.2982256403
Short name T587
Test name
Test status
Simulation time 71561056 ps
CPU time 1.2 seconds
Started Aug 15 06:34:02 PM PDT 24
Finished Aug 15 06:34:03 PM PDT 24
Peak memory 218596 kb
Host smart-4cd18112-94c9-4894-a8a0-0f9ecdff7d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982256403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2982256403
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.3160346555
Short name T19
Test name
Test status
Simulation time 70021916 ps
CPU time 1.12 seconds
Started Aug 15 06:34:01 PM PDT 24
Finished Aug 15 06:34:03 PM PDT 24
Peak memory 218988 kb
Host smart-3bcc8883-7dd7-413c-9e2a-31a298ae023c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160346555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3160346555
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.4203808870
Short name T688
Test name
Test status
Simulation time 126172980 ps
CPU time 1.12 seconds
Started Aug 15 06:34:15 PM PDT 24
Finished Aug 15 06:34:16 PM PDT 24
Peak memory 215728 kb
Host smart-7cbfd490-e8f9-4423-b012-80619bb3c26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203808870 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.4203808870
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.60739679
Short name T701
Test name
Test status
Simulation time 59781573 ps
CPU time 1.09 seconds
Started Aug 15 06:34:19 PM PDT 24
Finished Aug 15 06:34:20 PM PDT 24
Peak memory 215332 kb
Host smart-1dbbe01a-1585-4fa9-9df1-208cb38d9df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60739679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.60739679
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.1958970748
Short name T134
Test name
Test status
Simulation time 50796171 ps
CPU time 1.27 seconds
Started Aug 15 06:34:06 PM PDT 24
Finished Aug 15 06:34:07 PM PDT 24
Peak memory 218748 kb
Host smart-2b026a67-943a-479c-a55e-a1d4e4bf6338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958970748 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.1958970748
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.710264285
Short name T615
Test name
Test status
Simulation time 68355050 ps
CPU time 1.42 seconds
Started Aug 15 06:34:06 PM PDT 24
Finished Aug 15 06:34:07 PM PDT 24
Peak memory 217268 kb
Host smart-0839841e-75ba-4b77-9257-c33117109a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710264285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.710264285
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.2682666055
Short name T177
Test name
Test status
Simulation time 22708310 ps
CPU time 1.17 seconds
Started Aug 15 06:34:22 PM PDT 24
Finished Aug 15 06:34:24 PM PDT 24
Peak memory 219784 kb
Host smart-b53dfa9b-f726-4174-b1a8-6b5e3d1ae463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682666055 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.2682666055
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.3650504444
Short name T456
Test name
Test status
Simulation time 33896814 ps
CPU time 1.44 seconds
Started Aug 15 06:34:01 PM PDT 24
Finished Aug 15 06:34:03 PM PDT 24
Peak memory 218704 kb
Host smart-593adc55-b32f-4101-a2d9-4ef503869167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650504444 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.3650504444
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.1304080310
Short name T383
Test name
Test status
Simulation time 91166684 ps
CPU time 1.21 seconds
Started Aug 15 06:32:28 PM PDT 24
Finished Aug 15 06:32:29 PM PDT 24
Peak memory 219964 kb
Host smart-3c6c4105-574e-4155-a57d-c8afa30279b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304080310 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.1304080310
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.1136160981
Short name T841
Test name
Test status
Simulation time 25508979 ps
CPU time 0.94 seconds
Started Aug 15 06:32:28 PM PDT 24
Finished Aug 15 06:32:29 PM PDT 24
Peak memory 206744 kb
Host smart-16f3f4ee-6a5b-4b00-a661-caa1601859a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136160981 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.1136160981
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2252033187
Short name T719
Test name
Test status
Simulation time 78520321 ps
CPU time 1.07 seconds
Started Aug 15 06:32:29 PM PDT 24
Finished Aug 15 06:32:30 PM PDT 24
Peak memory 218696 kb
Host smart-b1a5bc77-64fc-42a1-9529-8c0fd0ee1eb3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252033187 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2252033187
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.1769360960
Short name T13
Test name
Test status
Simulation time 18723829 ps
CPU time 1.15 seconds
Started Aug 15 06:32:28 PM PDT 24
Finished Aug 15 06:32:29 PM PDT 24
Peak memory 224132 kb
Host smart-efc93f8d-4a60-449b-91cc-2f48ba4fe0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769360960 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1769360960
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.2061329182
Short name T890
Test name
Test status
Simulation time 334925170 ps
CPU time 2.18 seconds
Started Aug 15 06:32:25 PM PDT 24
Finished Aug 15 06:32:28 PM PDT 24
Peak memory 218792 kb
Host smart-17e90b8e-f35d-46b5-92c4-bd987375f37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061329182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2061329182
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.179866454
Short name T33
Test name
Test status
Simulation time 21310532 ps
CPU time 1.17 seconds
Started Aug 15 06:32:27 PM PDT 24
Finished Aug 15 06:32:29 PM PDT 24
Peak memory 215900 kb
Host smart-938f9a1f-2965-4013-ac76-c8d0e41304a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179866454 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.179866454
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.2721581817
Short name T400
Test name
Test status
Simulation time 15602694 ps
CPU time 1.03 seconds
Started Aug 15 06:32:29 PM PDT 24
Finished Aug 15 06:32:31 PM PDT 24
Peak memory 215612 kb
Host smart-22dc48a6-6021-4943-8114-5e5fab0c1473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721581817 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.2721581817
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.4049766564
Short name T337
Test name
Test status
Simulation time 74473417 ps
CPU time 1.88 seconds
Started Aug 15 06:32:26 PM PDT 24
Finished Aug 15 06:32:28 PM PDT 24
Peak memory 217332 kb
Host smart-433f8f19-84f4-4761-a064-12f82741df9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049766564 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.4049766564
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/190.edn_alert.1025330867
Short name T930
Test name
Test status
Simulation time 44533197 ps
CPU time 1.18 seconds
Started Aug 15 06:34:05 PM PDT 24
Finished Aug 15 06:34:06 PM PDT 24
Peak memory 220100 kb
Host smart-f9545e84-ae10-4f5b-b4ed-994e0ebd0304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025330867 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.1025330867
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.831287244
Short name T900
Test name
Test status
Simulation time 85395436 ps
CPU time 1.49 seconds
Started Aug 15 06:34:05 PM PDT 24
Finished Aug 15 06:34:07 PM PDT 24
Peak memory 218896 kb
Host smart-8dfa22ca-5bba-4b22-ab73-62e8c8d46189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831287244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.831287244
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.2100406564
Short name T672
Test name
Test status
Simulation time 102895341 ps
CPU time 1.13 seconds
Started Aug 15 06:34:14 PM PDT 24
Finished Aug 15 06:34:16 PM PDT 24
Peak memory 219528 kb
Host smart-b8ec267d-68ed-443f-9ef0-27d4a8046721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100406564 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.2100406564
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.3673371987
Short name T679
Test name
Test status
Simulation time 37911271 ps
CPU time 1.58 seconds
Started Aug 15 06:34:14 PM PDT 24
Finished Aug 15 06:34:16 PM PDT 24
Peak memory 218716 kb
Host smart-a1260269-acd9-4d15-b9a7-851cc6df7bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673371987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.3673371987
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.239482604
Short name T269
Test name
Test status
Simulation time 51573681 ps
CPU time 1.21 seconds
Started Aug 15 06:34:05 PM PDT 24
Finished Aug 15 06:34:06 PM PDT 24
Peak memory 218580 kb
Host smart-dcae406d-709c-4f76-b142-56dba8492422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239482604 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.239482604
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.2904996680
Short name T901
Test name
Test status
Simulation time 38430522 ps
CPU time 1.44 seconds
Started Aug 15 06:34:04 PM PDT 24
Finished Aug 15 06:34:06 PM PDT 24
Peak memory 219568 kb
Host smart-593acc18-5def-4069-97d6-6403fe85c7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904996680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2904996680
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.2797143525
Short name T740
Test name
Test status
Simulation time 37360437 ps
CPU time 1.18 seconds
Started Aug 15 06:34:01 PM PDT 24
Finished Aug 15 06:34:03 PM PDT 24
Peak memory 219772 kb
Host smart-9cf85306-c6f1-4a4d-8122-e8f62980c2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797143525 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.2797143525
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.3989833778
Short name T97
Test name
Test status
Simulation time 52748112 ps
CPU time 1.33 seconds
Started Aug 15 06:34:10 PM PDT 24
Finished Aug 15 06:34:12 PM PDT 24
Peak memory 218776 kb
Host smart-24a33c1c-b1b7-49f1-bb19-129fbcd8420f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989833778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3989833778
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.3546616250
Short name T167
Test name
Test status
Simulation time 241780544 ps
CPU time 1.28 seconds
Started Aug 15 06:33:58 PM PDT 24
Finished Aug 15 06:34:00 PM PDT 24
Peak memory 220248 kb
Host smart-b5eec76c-4b5b-42ad-bfa5-b081fca400c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546616250 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.3546616250
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.3197430950
Short name T682
Test name
Test status
Simulation time 46535674 ps
CPU time 1.61 seconds
Started Aug 15 06:34:03 PM PDT 24
Finished Aug 15 06:34:05 PM PDT 24
Peak memory 218696 kb
Host smart-cdd7bb5e-8949-4a64-8156-959ba99f94d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197430950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3197430950
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.2717575643
Short name T869
Test name
Test status
Simulation time 27822104 ps
CPU time 1.22 seconds
Started Aug 15 06:34:06 PM PDT 24
Finished Aug 15 06:34:08 PM PDT 24
Peak memory 218732 kb
Host smart-6d869086-8bb7-40f7-a2ee-59bf79560fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717575643 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.2717575643
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.2512317534
Short name T700
Test name
Test status
Simulation time 65366652 ps
CPU time 1.22 seconds
Started Aug 15 06:34:01 PM PDT 24
Finished Aug 15 06:34:03 PM PDT 24
Peak memory 217340 kb
Host smart-217d7d7b-0aaf-488c-8eac-3a9b8287d1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512317534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.2512317534
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.2768892180
Short name T896
Test name
Test status
Simulation time 34742179 ps
CPU time 1.54 seconds
Started Aug 15 06:34:04 PM PDT 24
Finished Aug 15 06:34:06 PM PDT 24
Peak memory 217652 kb
Host smart-50bd4b90-465b-49bf-84a5-4f0f4ddc125d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768892180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2768892180
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.1235497338
Short name T244
Test name
Test status
Simulation time 51391955 ps
CPU time 1.23 seconds
Started Aug 15 06:34:09 PM PDT 24
Finished Aug 15 06:34:11 PM PDT 24
Peak memory 218640 kb
Host smart-f833c8b0-b49a-4eb7-a804-12d64636abba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235497338 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.1235497338
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.3154449633
Short name T579
Test name
Test status
Simulation time 41660653 ps
CPU time 1.38 seconds
Started Aug 15 06:34:14 PM PDT 24
Finished Aug 15 06:34:16 PM PDT 24
Peak memory 218560 kb
Host smart-ce8034de-32c4-4ad5-b681-ffdc2ae64183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154449633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3154449633
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.2229680997
Short name T893
Test name
Test status
Simulation time 84594621 ps
CPU time 1.15 seconds
Started Aug 15 06:34:07 PM PDT 24
Finished Aug 15 06:34:09 PM PDT 24
Peak memory 220128 kb
Host smart-a53801ce-9f37-415d-a762-579560c0d271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229680997 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.2229680997
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.3171403876
Short name T881
Test name
Test status
Simulation time 52396667 ps
CPU time 1.03 seconds
Started Aug 15 06:34:01 PM PDT 24
Finished Aug 15 06:34:02 PM PDT 24
Peak memory 217496 kb
Host smart-07d84e40-5cb5-4f81-b8f2-71ccd4147fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171403876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3171403876
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.2441284275
Short name T775
Test name
Test status
Simulation time 26790535 ps
CPU time 1.21 seconds
Started Aug 15 06:34:09 PM PDT 24
Finished Aug 15 06:34:11 PM PDT 24
Peak memory 219828 kb
Host smart-b41cc820-c427-4444-9a2e-31c357447546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441284275 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.2441284275
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert.1138311409
Short name T908
Test name
Test status
Simulation time 40916095 ps
CPU time 1.15 seconds
Started Aug 15 06:31:57 PM PDT 24
Finished Aug 15 06:31:58 PM PDT 24
Peak memory 218780 kb
Host smart-eb2383a7-5a58-4801-8848-bbc385b64bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138311409 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.1138311409
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.396294634
Short name T61
Test name
Test status
Simulation time 14452702 ps
CPU time 0.91 seconds
Started Aug 15 06:32:08 PM PDT 24
Finished Aug 15 06:32:09 PM PDT 24
Peak memory 206784 kb
Host smart-4bc579a3-b9e4-4e03-a68d-090b38eba5fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396294634 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.396294634
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.2541255078
Short name T371
Test name
Test status
Simulation time 11592406 ps
CPU time 0.95 seconds
Started Aug 15 06:31:58 PM PDT 24
Finished Aug 15 06:31:59 PM PDT 24
Peak memory 215212 kb
Host smart-ce27d170-d0b6-4221-9a2a-0d1fc354998c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541255078 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2541255078
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.3246568119
Short name T844
Test name
Test status
Simulation time 70950856 ps
CPU time 1.24 seconds
Started Aug 15 06:31:56 PM PDT 24
Finished Aug 15 06:31:58 PM PDT 24
Peak memory 217076 kb
Host smart-761bdc7c-40ae-47b0-98db-4900001b89d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246568119 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.3246568119
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.573020061
Short name T801
Test name
Test status
Simulation time 27620333 ps
CPU time 1.01 seconds
Started Aug 15 06:31:57 PM PDT 24
Finished Aug 15 06:31:58 PM PDT 24
Peak memory 223964 kb
Host smart-8d1280f2-ec96-4972-af34-af4706f34d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573020061 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.573020061
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.827542810
Short name T333
Test name
Test status
Simulation time 49388713 ps
CPU time 1.26 seconds
Started Aug 15 06:32:01 PM PDT 24
Finished Aug 15 06:32:02 PM PDT 24
Peak memory 217404 kb
Host smart-e77f8d39-3a7f-48a4-85fa-a4f294f7b3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827542810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.827542810
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.377106616
Short name T91
Test name
Test status
Simulation time 29282979 ps
CPU time 0.98 seconds
Started Aug 15 06:32:02 PM PDT 24
Finished Aug 15 06:32:03 PM PDT 24
Peak memory 215956 kb
Host smart-c380ea88-9003-4b76-8e22-482d8e7a47ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377106616 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.377106616
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.1907837406
Short name T882
Test name
Test status
Simulation time 20001973 ps
CPU time 0.99 seconds
Started Aug 15 06:31:58 PM PDT 24
Finished Aug 15 06:31:59 PM PDT 24
Peak memory 207136 kb
Host smart-2cc7badc-0414-443d-9c4c-7355161e168b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907837406 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.1907837406
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_smoke.2549406505
Short name T326
Test name
Test status
Simulation time 17276808 ps
CPU time 1 seconds
Started Aug 15 06:32:02 PM PDT 24
Finished Aug 15 06:32:03 PM PDT 24
Peak memory 215352 kb
Host smart-ba897465-cb8e-4b06-99cd-ab2c30f37436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549406505 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.2549406505
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.1630039102
Short name T544
Test name
Test status
Simulation time 1356428116 ps
CPU time 4.69 seconds
Started Aug 15 06:31:58 PM PDT 24
Finished Aug 15 06:32:03 PM PDT 24
Peak memory 217392 kb
Host smart-2009ddd1-c49c-4a7a-9da9-7a0e904bf677
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630039102 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1630039102
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.2684587191
Short name T487
Test name
Test status
Simulation time 21969138075 ps
CPU time 133.02 seconds
Started Aug 15 06:31:57 PM PDT 24
Finished Aug 15 06:34:11 PM PDT 24
Peak memory 219112 kb
Host smart-71cb3a9a-7c09-4bf1-883b-8271be031f11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684587191 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.2684587191
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.1035210585
Short name T604
Test name
Test status
Simulation time 25659571 ps
CPU time 1.2 seconds
Started Aug 15 06:32:29 PM PDT 24
Finished Aug 15 06:32:31 PM PDT 24
Peak memory 218644 kb
Host smart-baa10e63-dfe3-417f-a391-826484886979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035210585 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.1035210585
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.382535595
Short name T361
Test name
Test status
Simulation time 67546478 ps
CPU time 0.98 seconds
Started Aug 15 06:32:27 PM PDT 24
Finished Aug 15 06:32:28 PM PDT 24
Peak memory 214960 kb
Host smart-782ed497-3e89-41a3-a0e6-ffd03bc88de0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382535595 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.382535595
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.3030011597
Short name T173
Test name
Test status
Simulation time 161574729 ps
CPU time 0.89 seconds
Started Aug 15 06:32:29 PM PDT 24
Finished Aug 15 06:32:31 PM PDT 24
Peak memory 215476 kb
Host smart-4701ab9a-b69f-47b7-b802-a075e87b8502
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030011597 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3030011597
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.3558515358
Short name T461
Test name
Test status
Simulation time 176465520 ps
CPU time 1.24 seconds
Started Aug 15 06:32:27 PM PDT 24
Finished Aug 15 06:32:29 PM PDT 24
Peak memory 219612 kb
Host smart-2ae63f79-db91-4fd2-bd49-52855b5788a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558515358 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.3558515358
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.1319778649
Short name T622
Test name
Test status
Simulation time 106846977 ps
CPU time 1.07 seconds
Started Aug 15 06:32:30 PM PDT 24
Finished Aug 15 06:32:31 PM PDT 24
Peak memory 215352 kb
Host smart-a4ff7421-9344-41d3-ab1b-0065658a31bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319778649 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.1319778649
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.2606134475
Short name T883
Test name
Test status
Simulation time 31029359 ps
CPU time 1.47 seconds
Started Aug 15 06:32:27 PM PDT 24
Finished Aug 15 06:32:28 PM PDT 24
Peak memory 218956 kb
Host smart-0651c894-fcd9-4ee1-8fd6-8f90b3445dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606134475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.2606134475
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.2658028956
Short name T648
Test name
Test status
Simulation time 27323735 ps
CPU time 0.93 seconds
Started Aug 15 06:32:27 PM PDT 24
Finished Aug 15 06:32:28 PM PDT 24
Peak memory 215492 kb
Host smart-b110d78c-1b93-45e1-ac4a-eba18273ca66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658028956 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.2658028956
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.203263883
Short name T537
Test name
Test status
Simulation time 15024661 ps
CPU time 1.01 seconds
Started Aug 15 06:32:27 PM PDT 24
Finished Aug 15 06:32:28 PM PDT 24
Peak memory 215348 kb
Host smart-23874d57-c229-4926-946a-e6775d5e4275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203263883 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.203263883
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.523450900
Short name T197
Test name
Test status
Simulation time 300719857 ps
CPU time 3.85 seconds
Started Aug 15 06:32:27 PM PDT 24
Finished Aug 15 06:32:31 PM PDT 24
Peak memory 218548 kb
Host smart-c0cfd7b0-3b07-48af-a877-b5ea636fa1a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523450900 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.523450900
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/200.edn_genbits.1563693730
Short name T18
Test name
Test status
Simulation time 226737495 ps
CPU time 3.04 seconds
Started Aug 15 06:34:14 PM PDT 24
Finished Aug 15 06:34:17 PM PDT 24
Peak memory 218648 kb
Host smart-abc0dbb5-41fa-4687-a244-b33e8778c097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563693730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.1563693730
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.3880139654
Short name T675
Test name
Test status
Simulation time 40549584 ps
CPU time 1.48 seconds
Started Aug 15 06:34:02 PM PDT 24
Finished Aug 15 06:34:04 PM PDT 24
Peak memory 218880 kb
Host smart-ac798839-1400-46d4-abdf-60eb6173a6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880139654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.3880139654
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.2610434954
Short name T298
Test name
Test status
Simulation time 67370401 ps
CPU time 1.19 seconds
Started Aug 15 06:34:07 PM PDT 24
Finished Aug 15 06:34:09 PM PDT 24
Peak memory 218912 kb
Host smart-0b314508-c7f3-4bcc-ba6f-edf9e35a9415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610434954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.2610434954
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.142247876
Short name T921
Test name
Test status
Simulation time 62081219 ps
CPU time 1.49 seconds
Started Aug 15 06:34:01 PM PDT 24
Finished Aug 15 06:34:03 PM PDT 24
Peak memory 218836 kb
Host smart-fb7f1912-dc89-4a18-9d43-5df5fd959148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142247876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.142247876
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.1328808697
Short name T817
Test name
Test status
Simulation time 140504426 ps
CPU time 1.07 seconds
Started Aug 15 06:34:04 PM PDT 24
Finished Aug 15 06:34:05 PM PDT 24
Peak memory 217464 kb
Host smart-58ede219-29e4-4607-bbe1-12c20f816237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328808697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.1328808697
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.1292564917
Short name T77
Test name
Test status
Simulation time 115424555 ps
CPU time 2.8 seconds
Started Aug 15 06:34:11 PM PDT 24
Finished Aug 15 06:34:14 PM PDT 24
Peak memory 220796 kb
Host smart-1cb15491-22cb-4823-8bb1-9b550ad74a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292564917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1292564917
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.1395117254
Short name T460
Test name
Test status
Simulation time 197367472 ps
CPU time 2.65 seconds
Started Aug 15 06:34:06 PM PDT 24
Finished Aug 15 06:34:09 PM PDT 24
Peak memory 220556 kb
Host smart-f27773c9-e03b-4ea9-9f1f-f26f0ad6f6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395117254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.1395117254
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3658621224
Short name T735
Test name
Test status
Simulation time 56000877 ps
CPU time 1.21 seconds
Started Aug 15 06:34:06 PM PDT 24
Finished Aug 15 06:34:08 PM PDT 24
Peak memory 217428 kb
Host smart-59b95a5f-68e2-4e3e-8778-d87c79bb4381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658621224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3658621224
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.4161741712
Short name T336
Test name
Test status
Simulation time 159657723 ps
CPU time 1.29 seconds
Started Aug 15 06:34:12 PM PDT 24
Finished Aug 15 06:34:13 PM PDT 24
Peak memory 218932 kb
Host smart-041439a7-da89-4439-a8f0-3c40fae31c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161741712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.4161741712
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.2642337533
Short name T595
Test name
Test status
Simulation time 75521778 ps
CPU time 2.49 seconds
Started Aug 15 06:34:06 PM PDT 24
Finished Aug 15 06:34:09 PM PDT 24
Peak memory 218936 kb
Host smart-39c4821c-08e9-4259-a03b-042c06a51c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642337533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2642337533
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3916420137
Short name T768
Test name
Test status
Simulation time 148159171 ps
CPU time 1.13 seconds
Started Aug 15 06:32:31 PM PDT 24
Finished Aug 15 06:32:32 PM PDT 24
Peak memory 218656 kb
Host smart-74c8b364-1738-4eae-b8eb-a674159c54c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916420137 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3916420137
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.490667976
Short name T318
Test name
Test status
Simulation time 13364204 ps
CPU time 0.98 seconds
Started Aug 15 06:32:34 PM PDT 24
Finished Aug 15 06:32:35 PM PDT 24
Peak memory 206760 kb
Host smart-5a8740da-ea12-4aca-8d40-1abbc5ea769f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490667976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.490667976
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.3062625528
Short name T392
Test name
Test status
Simulation time 12420205 ps
CPU time 0.93 seconds
Started Aug 15 06:32:35 PM PDT 24
Finished Aug 15 06:32:36 PM PDT 24
Peak memory 215776 kb
Host smart-0fdb2fc0-5186-460c-a72f-723d112f5211
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062625528 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3062625528
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_err.3133881620
Short name T7
Test name
Test status
Simulation time 26519361 ps
CPU time 1.14 seconds
Started Aug 15 06:32:37 PM PDT 24
Finished Aug 15 06:32:39 PM PDT 24
Peak memory 220604 kb
Host smart-428afc0b-62c0-4c3e-b960-de230565b1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133881620 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3133881620
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.1671727361
Short name T948
Test name
Test status
Simulation time 24877303 ps
CPU time 1.07 seconds
Started Aug 15 06:32:29 PM PDT 24
Finished Aug 15 06:32:30 PM PDT 24
Peak memory 217344 kb
Host smart-f90affbd-5632-48c3-a9a6-03626b38b013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671727361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.1671727361
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3801218783
Short name T624
Test name
Test status
Simulation time 24340640 ps
CPU time 1.07 seconds
Started Aug 15 06:32:29 PM PDT 24
Finished Aug 15 06:32:31 PM PDT 24
Peak memory 215672 kb
Host smart-44a1cec2-7ad8-4ea0-8e56-ee3a8a0579a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801218783 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3801218783
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.3496628902
Short name T319
Test name
Test status
Simulation time 46913520 ps
CPU time 0.95 seconds
Started Aug 15 06:32:27 PM PDT 24
Finished Aug 15 06:32:29 PM PDT 24
Peak memory 215380 kb
Host smart-3ba22e0d-2b52-4de1-97f4-0d6c66dd4406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496628902 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.3496628902
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.962284120
Short name T547
Test name
Test status
Simulation time 43367085 ps
CPU time 1.14 seconds
Started Aug 15 06:32:28 PM PDT 24
Finished Aug 15 06:32:29 PM PDT 24
Peak memory 215256 kb
Host smart-e33a3dc5-445a-4277-9a8c-ca242f735d7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962284120 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.962284120
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/210.edn_genbits.1751215511
Short name T56
Test name
Test status
Simulation time 58250529 ps
CPU time 1.24 seconds
Started Aug 15 06:34:00 PM PDT 24
Finished Aug 15 06:34:02 PM PDT 24
Peak memory 217404 kb
Host smart-5f40d7a4-8cab-429d-adfb-dc93a4fd22bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751215511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.1751215511
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.2502585285
Short name T933
Test name
Test status
Simulation time 83506975 ps
CPU time 1.1 seconds
Started Aug 15 06:34:16 PM PDT 24
Finished Aug 15 06:34:17 PM PDT 24
Peak memory 218728 kb
Host smart-fcd6828f-aff1-4688-8727-b00455694f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502585285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2502585285
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.2617136877
Short name T23
Test name
Test status
Simulation time 98629927 ps
CPU time 1.08 seconds
Started Aug 15 06:34:17 PM PDT 24
Finished Aug 15 06:34:18 PM PDT 24
Peak memory 217532 kb
Host smart-7304bf83-3f18-4e2a-8f80-6852294ea5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617136877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2617136877
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.1872121396
Short name T296
Test name
Test status
Simulation time 84184803 ps
CPU time 1.44 seconds
Started Aug 15 06:34:10 PM PDT 24
Finished Aug 15 06:34:11 PM PDT 24
Peak memory 219016 kb
Host smart-449c817a-da64-40e5-9349-3d31d219970b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872121396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1872121396
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.2878136577
Short name T742
Test name
Test status
Simulation time 50406585 ps
CPU time 1.17 seconds
Started Aug 15 06:34:08 PM PDT 24
Finished Aug 15 06:34:09 PM PDT 24
Peak memory 217392 kb
Host smart-eca890ad-9be2-4029-ae7c-f998a468d912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878136577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.2878136577
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1464928274
Short name T923
Test name
Test status
Simulation time 27180746 ps
CPU time 1.31 seconds
Started Aug 15 06:34:16 PM PDT 24
Finished Aug 15 06:34:18 PM PDT 24
Peak memory 218536 kb
Host smart-1b6cf5c4-3d8b-43b7-adaa-ed49a411d4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464928274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1464928274
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.4269570992
Short name T291
Test name
Test status
Simulation time 42143037 ps
CPU time 1.46 seconds
Started Aug 15 06:34:21 PM PDT 24
Finished Aug 15 06:34:23 PM PDT 24
Peak memory 218376 kb
Host smart-8b19dd34-d434-44a8-a84d-785b779365b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269570992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.4269570992
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.1877873299
Short name T370
Test name
Test status
Simulation time 289532978 ps
CPU time 3.72 seconds
Started Aug 15 06:34:08 PM PDT 24
Finished Aug 15 06:34:12 PM PDT 24
Peak memory 220712 kb
Host smart-9b75b6a0-39e8-4ea0-a560-74da0ead2be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877873299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1877873299
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.510284012
Short name T327
Test name
Test status
Simulation time 68520236 ps
CPU time 2.37 seconds
Started Aug 15 06:34:06 PM PDT 24
Finished Aug 15 06:34:09 PM PDT 24
Peak memory 220008 kb
Host smart-44aee906-227c-47a0-a4aa-bf8b87c5d7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510284012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.510284012
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.2504380902
Short name T133
Test name
Test status
Simulation time 24055451 ps
CPU time 1.15 seconds
Started Aug 15 06:32:42 PM PDT 24
Finished Aug 15 06:32:43 PM PDT 24
Peak memory 221012 kb
Host smart-5c4cb48a-53bf-4381-abe7-f0d80bb0561f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504380902 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2504380902
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.1709064401
Short name T325
Test name
Test status
Simulation time 75064090 ps
CPU time 0.98 seconds
Started Aug 15 06:32:39 PM PDT 24
Finished Aug 15 06:32:40 PM PDT 24
Peak memory 215224 kb
Host smart-b707bd76-1dcc-4428-b0f2-37f7593859ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709064401 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1709064401
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.1673433359
Short name T195
Test name
Test status
Simulation time 21054735 ps
CPU time 0.9 seconds
Started Aug 15 06:32:36 PM PDT 24
Finished Aug 15 06:32:37 PM PDT 24
Peak memory 215416 kb
Host smart-f102ee5a-1549-42d0-9ce3-cb28a205d3b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673433359 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.1673433359
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.2001012712
Short name T382
Test name
Test status
Simulation time 32758689 ps
CPU time 1.27 seconds
Started Aug 15 06:32:33 PM PDT 24
Finished Aug 15 06:32:35 PM PDT 24
Peak memory 217076 kb
Host smart-95042803-f832-4fa9-b8eb-f8c637da3d57
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001012712 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.2001012712
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.1850848451
Short name T491
Test name
Test status
Simulation time 18590586 ps
CPU time 1.03 seconds
Started Aug 15 06:32:34 PM PDT 24
Finished Aug 15 06:32:35 PM PDT 24
Peak memory 218612 kb
Host smart-9159d473-9581-4245-9e8d-50d073d015c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850848451 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.1850848451
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_intr.3943536209
Short name T706
Test name
Test status
Simulation time 25485367 ps
CPU time 1.01 seconds
Started Aug 15 06:32:39 PM PDT 24
Finished Aug 15 06:32:40 PM PDT 24
Peak memory 215600 kb
Host smart-b4a8180b-a20f-4fe2-8df7-84c83cbf0b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943536209 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3943536209
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.2109613748
Short name T562
Test name
Test status
Simulation time 35955572 ps
CPU time 0.9 seconds
Started Aug 15 06:32:34 PM PDT 24
Finished Aug 15 06:32:35 PM PDT 24
Peak memory 215316 kb
Host smart-a3870414-a37f-496e-ab83-d5f440a97c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109613748 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2109613748
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2441308425
Short name T323
Test name
Test status
Simulation time 197510069 ps
CPU time 4.05 seconds
Started Aug 15 06:32:37 PM PDT 24
Finished Aug 15 06:32:41 PM PDT 24
Peak memory 215348 kb
Host smart-3a6ad848-e185-4bf4-a2c9-61781cd8f6ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441308425 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2441308425
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/220.edn_genbits.3081669864
Short name T666
Test name
Test status
Simulation time 113571308 ps
CPU time 2.41 seconds
Started Aug 15 06:34:08 PM PDT 24
Finished Aug 15 06:34:11 PM PDT 24
Peak memory 220504 kb
Host smart-32603ec6-e48e-4502-984c-6480b1303ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081669864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.3081669864
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.3099816726
Short name T943
Test name
Test status
Simulation time 46432138 ps
CPU time 1.08 seconds
Started Aug 15 06:34:15 PM PDT 24
Finished Aug 15 06:34:21 PM PDT 24
Peak memory 217356 kb
Host smart-362b7b7a-e1ec-4586-beac-69c1572f4ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099816726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3099816726
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.796247352
Short name T725
Test name
Test status
Simulation time 44131714 ps
CPU time 1.11 seconds
Started Aug 15 06:34:05 PM PDT 24
Finished Aug 15 06:34:06 PM PDT 24
Peak memory 220328 kb
Host smart-7825b17e-97f7-4b0a-9244-089d8a995ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796247352 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.796247352
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.3467831840
Short name T426
Test name
Test status
Simulation time 88119921 ps
CPU time 3.19 seconds
Started Aug 15 06:34:21 PM PDT 24
Finished Aug 15 06:34:24 PM PDT 24
Peak memory 218736 kb
Host smart-c22950ef-ad22-4db8-bfd6-c95e11ece6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467831840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.3467831840
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.3015065351
Short name T617
Test name
Test status
Simulation time 345585169 ps
CPU time 1.44 seconds
Started Aug 15 06:34:07 PM PDT 24
Finished Aug 15 06:34:08 PM PDT 24
Peak memory 219268 kb
Host smart-688c7db4-658f-4aca-9d57-afdbcb7c5cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015065351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.3015065351
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.1533302848
Short name T515
Test name
Test status
Simulation time 42984928 ps
CPU time 1.33 seconds
Started Aug 15 06:34:09 PM PDT 24
Finished Aug 15 06:34:10 PM PDT 24
Peak memory 218740 kb
Host smart-e221fa74-fbf3-42bc-8d3a-790990e1a56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533302848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.1533302848
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.1458902869
Short name T593
Test name
Test status
Simulation time 33913467 ps
CPU time 1.4 seconds
Started Aug 15 06:34:07 PM PDT 24
Finished Aug 15 06:34:09 PM PDT 24
Peak memory 219016 kb
Host smart-1c11c804-6036-4368-9aab-137de969525b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458902869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.1458902869
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.468518644
Short name T277
Test name
Test status
Simulation time 70652362 ps
CPU time 1.15 seconds
Started Aug 15 06:34:15 PM PDT 24
Finished Aug 15 06:34:16 PM PDT 24
Peak memory 217272 kb
Host smart-33fa42ca-f60e-4725-8c1a-c7f3b0d57628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468518644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.468518644
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.3322010827
Short name T743
Test name
Test status
Simulation time 135958354 ps
CPU time 1.08 seconds
Started Aug 15 06:34:14 PM PDT 24
Finished Aug 15 06:34:15 PM PDT 24
Peak memory 217412 kb
Host smart-9a40d5f3-3bef-44d0-8484-eb35284c63de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322010827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.3322010827
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1042485205
Short name T338
Test name
Test status
Simulation time 40957907 ps
CPU time 1.39 seconds
Started Aug 15 06:34:10 PM PDT 24
Finished Aug 15 06:34:12 PM PDT 24
Peak memory 218524 kb
Host smart-755d53fc-cd01-4c66-8036-27649dd2a841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042485205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1042485205
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.2077402379
Short name T240
Test name
Test status
Simulation time 193526276 ps
CPU time 1.29 seconds
Started Aug 15 06:32:35 PM PDT 24
Finished Aug 15 06:32:37 PM PDT 24
Peak memory 219412 kb
Host smart-951a5179-4d86-4c04-95a1-8afe2f73721f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077402379 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.2077402379
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.2848242390
Short name T823
Test name
Test status
Simulation time 38388651 ps
CPU time 0.86 seconds
Started Aug 15 06:32:33 PM PDT 24
Finished Aug 15 06:32:34 PM PDT 24
Peak memory 206848 kb
Host smart-4f6de988-43de-40cd-9337-79dc9b9b7a5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848242390 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.2848242390
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.2830831833
Short name T529
Test name
Test status
Simulation time 28842129 ps
CPU time 0.81 seconds
Started Aug 15 06:32:36 PM PDT 24
Finished Aug 15 06:32:37 PM PDT 24
Peak memory 215348 kb
Host smart-225b7003-15fe-491d-a2cf-991361731e08
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830831833 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2830831833
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.1596500098
Short name T815
Test name
Test status
Simulation time 85890037 ps
CPU time 1.09 seconds
Started Aug 15 06:32:34 PM PDT 24
Finished Aug 15 06:32:35 PM PDT 24
Peak memory 216768 kb
Host smart-5ef74192-1961-41b1-9c40-8e81a4f098df
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596500098 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.1596500098
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.5704472
Short name T402
Test name
Test status
Simulation time 53199967 ps
CPU time 0.83 seconds
Started Aug 15 06:32:39 PM PDT 24
Finished Aug 15 06:32:40 PM PDT 24
Peak memory 218112 kb
Host smart-002f1887-224f-4098-95b1-1b2b50152ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5704472 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.5704472
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.2599418602
Short name T297
Test name
Test status
Simulation time 188281104 ps
CPU time 1.65 seconds
Started Aug 15 06:32:39 PM PDT 24
Finished Aug 15 06:32:40 PM PDT 24
Peak memory 219136 kb
Host smart-e3b0cc54-fa99-4088-912a-1a975a4fc2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599418602 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2599418602
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.3868864727
Short name T807
Test name
Test status
Simulation time 23455515 ps
CPU time 1.04 seconds
Started Aug 15 06:32:42 PM PDT 24
Finished Aug 15 06:32:43 PM PDT 24
Peak memory 215456 kb
Host smart-f5a91f3d-b70a-458b-b241-a09ebcad8769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868864727 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3868864727
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.1387771803
Short name T774
Test name
Test status
Simulation time 22536557 ps
CPU time 0.93 seconds
Started Aug 15 06:32:36 PM PDT 24
Finished Aug 15 06:32:37 PM PDT 24
Peak memory 215340 kb
Host smart-b15b115b-b633-4ecb-8982-5bc392525122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387771803 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.1387771803
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.2565970548
Short name T639
Test name
Test status
Simulation time 270193016 ps
CPU time 1.54 seconds
Started Aug 15 06:32:36 PM PDT 24
Finished Aug 15 06:32:37 PM PDT 24
Peak memory 217336 kb
Host smart-970c81ba-2188-46f7-ab30-9fa072fb11d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565970548 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.2565970548
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/230.edn_genbits.754101481
Short name T457
Test name
Test status
Simulation time 51508801 ps
CPU time 1.44 seconds
Started Aug 15 06:34:08 PM PDT 24
Finished Aug 15 06:34:09 PM PDT 24
Peak memory 218404 kb
Host smart-618cb57b-a595-4833-8771-b5b198601297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754101481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.754101481
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.3900724291
Short name T442
Test name
Test status
Simulation time 38824838 ps
CPU time 1.38 seconds
Started Aug 15 06:34:17 PM PDT 24
Finished Aug 15 06:34:19 PM PDT 24
Peak memory 218516 kb
Host smart-fb7a5cb3-d567-41f7-9c9a-e15e140568fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900724291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3900724291
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.23342613
Short name T344
Test name
Test status
Simulation time 62216580 ps
CPU time 1.22 seconds
Started Aug 15 06:34:10 PM PDT 24
Finished Aug 15 06:34:12 PM PDT 24
Peak memory 218780 kb
Host smart-9c866ced-f312-4193-8869-0026b23c2263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23342613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.23342613
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.1295840166
Short name T825
Test name
Test status
Simulation time 61661911 ps
CPU time 1.52 seconds
Started Aug 15 06:34:10 PM PDT 24
Finished Aug 15 06:34:12 PM PDT 24
Peak memory 217412 kb
Host smart-a86d57fd-1860-4838-99a3-4c5593d67528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295840166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1295840166
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.3101251043
Short name T702
Test name
Test status
Simulation time 58738701 ps
CPU time 1.32 seconds
Started Aug 15 06:34:07 PM PDT 24
Finished Aug 15 06:34:08 PM PDT 24
Peak memory 217504 kb
Host smart-4949d157-4b0b-498a-bb20-e2ade58ec576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101251043 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.3101251043
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.433547026
Short name T773
Test name
Test status
Simulation time 76903194 ps
CPU time 1.42 seconds
Started Aug 15 06:34:20 PM PDT 24
Finished Aug 15 06:34:22 PM PDT 24
Peak memory 218580 kb
Host smart-c4e8dbe2-a9d0-498c-a91a-d75345a15515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433547026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.433547026
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.3713988349
Short name T820
Test name
Test status
Simulation time 39514560 ps
CPU time 1.48 seconds
Started Aug 15 06:34:17 PM PDT 24
Finished Aug 15 06:34:18 PM PDT 24
Peak memory 218764 kb
Host smart-12cddee7-f9c8-40bc-95bf-ffdfbfbf02d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713988349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3713988349
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.1806828594
Short name T781
Test name
Test status
Simulation time 33806689 ps
CPU time 1.41 seconds
Started Aug 15 06:34:07 PM PDT 24
Finished Aug 15 06:34:09 PM PDT 24
Peak memory 219736 kb
Host smart-c68a0bab-5767-4dc3-95de-4b331a093ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806828594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1806828594
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.1470321533
Short name T312
Test name
Test status
Simulation time 183699877 ps
CPU time 2.17 seconds
Started Aug 15 06:34:14 PM PDT 24
Finished Aug 15 06:34:16 PM PDT 24
Peak memory 220832 kb
Host smart-d554e247-1b98-470d-ab28-2188e9f57128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470321533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.1470321533
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.4288357614
Short name T745
Test name
Test status
Simulation time 72622396 ps
CPU time 1.02 seconds
Started Aug 15 06:34:12 PM PDT 24
Finished Aug 15 06:34:13 PM PDT 24
Peak memory 217444 kb
Host smart-8f299be4-4e25-41a6-8759-689e0d35b79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288357614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.4288357614
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.4124205679
Short name T270
Test name
Test status
Simulation time 78914866 ps
CPU time 1.3 seconds
Started Aug 15 06:32:41 PM PDT 24
Finished Aug 15 06:32:42 PM PDT 24
Peak memory 219460 kb
Host smart-380c17ba-f81c-419d-9f9b-d408970b94ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124205679 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.4124205679
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.2996416235
Short name T694
Test name
Test status
Simulation time 25809571 ps
CPU time 0.89 seconds
Started Aug 15 06:32:37 PM PDT 24
Finished Aug 15 06:32:38 PM PDT 24
Peak memory 206736 kb
Host smart-85ec00ea-ebc4-4107-9eb7-39aee42e9466
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996416235 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2996416235
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.3757521650
Short name T653
Test name
Test status
Simulation time 13363745 ps
CPU time 0.92 seconds
Started Aug 15 06:32:37 PM PDT 24
Finished Aug 15 06:32:38 PM PDT 24
Peak memory 215588 kb
Host smart-50fb2e7f-2afe-4706-8cbf-f96bf7b99835
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757521650 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.3757521650
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.4234056398
Short name T873
Test name
Test status
Simulation time 60492789 ps
CPU time 1.05 seconds
Started Aug 15 06:32:35 PM PDT 24
Finished Aug 15 06:32:37 PM PDT 24
Peak memory 216772 kb
Host smart-10631553-eed4-4e28-91d1-cbe037e2f4a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234056398 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.4234056398
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.3350081641
Short name T209
Test name
Test status
Simulation time 48765052 ps
CPU time 0.93 seconds
Started Aug 15 06:32:39 PM PDT 24
Finished Aug 15 06:32:40 PM PDT 24
Peak memory 223908 kb
Host smart-e7e71618-cbe9-4673-817b-8861b035021a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350081641 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.3350081641
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.1643421297
Short name T704
Test name
Test status
Simulation time 23086322 ps
CPU time 1.15 seconds
Started Aug 15 06:32:35 PM PDT 24
Finished Aug 15 06:32:37 PM PDT 24
Peak memory 220260 kb
Host smart-629e5b7b-459e-4d70-81a0-8b0bb60d74bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643421297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1643421297
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.4179815766
Short name T88
Test name
Test status
Simulation time 21745370 ps
CPU time 1.04 seconds
Started Aug 15 06:32:35 PM PDT 24
Finished Aug 15 06:32:36 PM PDT 24
Peak memory 215984 kb
Host smart-f3d2bac0-bf93-4c45-8b69-9875e0ad686e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179815766 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.4179815766
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.2637977340
Short name T667
Test name
Test status
Simulation time 16568725 ps
CPU time 1 seconds
Started Aug 15 06:32:34 PM PDT 24
Finished Aug 15 06:32:36 PM PDT 24
Peak memory 215372 kb
Host smart-33d51511-b235-4258-8c2d-6f2e78a801da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637977340 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.2637977340
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.3063911494
Short name T239
Test name
Test status
Simulation time 43086908 ps
CPU time 1.11 seconds
Started Aug 15 06:32:37 PM PDT 24
Finished Aug 15 06:32:38 PM PDT 24
Peak memory 206576 kb
Host smart-bd7e772d-21a9-4d4c-a294-5d0b9d69aca3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063911494 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3063911494
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/240.edn_genbits.571289116
Short name T918
Test name
Test status
Simulation time 86687113 ps
CPU time 1.05 seconds
Started Aug 15 06:34:16 PM PDT 24
Finished Aug 15 06:34:17 PM PDT 24
Peak memory 217388 kb
Host smart-abebf6e2-6a61-4624-8ddb-5fb8d74b4408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571289116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.571289116
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1521362055
Short name T329
Test name
Test status
Simulation time 60875578 ps
CPU time 1.14 seconds
Started Aug 15 06:34:06 PM PDT 24
Finished Aug 15 06:34:07 PM PDT 24
Peak memory 217312 kb
Host smart-570331c0-9e19-4e47-a05e-ece472e269a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521362055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1521362055
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.3841329194
Short name T274
Test name
Test status
Simulation time 35630775 ps
CPU time 1.28 seconds
Started Aug 15 06:34:31 PM PDT 24
Finished Aug 15 06:34:32 PM PDT 24
Peak memory 217308 kb
Host smart-cf500aaa-c09b-4ef2-ad74-ad22dcd77bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841329194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.3841329194
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.758994979
Short name T878
Test name
Test status
Simulation time 86637817 ps
CPU time 1.3 seconds
Started Aug 15 06:34:18 PM PDT 24
Finished Aug 15 06:34:20 PM PDT 24
Peak memory 219236 kb
Host smart-8f525bbc-8db0-48ff-88af-fdda65aab7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758994979 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.758994979
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.2489093352
Short name T636
Test name
Test status
Simulation time 60582950 ps
CPU time 1.5 seconds
Started Aug 15 06:34:22 PM PDT 24
Finished Aug 15 06:34:24 PM PDT 24
Peak memory 218812 kb
Host smart-5a297f42-4f8a-4e0d-925d-f5578a498c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489093352 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.2489093352
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.1009206048
Short name T417
Test name
Test status
Simulation time 28703240 ps
CPU time 1.18 seconds
Started Aug 15 06:34:11 PM PDT 24
Finished Aug 15 06:34:12 PM PDT 24
Peak memory 218432 kb
Host smart-3f8ccf41-196f-4036-9e0f-35de3bf91ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009206048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.1009206048
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.1066715951
Short name T80
Test name
Test status
Simulation time 28238866 ps
CPU time 1.31 seconds
Started Aug 15 06:34:16 PM PDT 24
Finished Aug 15 06:34:18 PM PDT 24
Peak memory 219828 kb
Host smart-ed8a486f-3b59-41c2-b177-d3142443525d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066715951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1066715951
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.3401046754
Short name T709
Test name
Test status
Simulation time 46383258 ps
CPU time 1.25 seconds
Started Aug 15 06:34:16 PM PDT 24
Finished Aug 15 06:34:17 PM PDT 24
Peak memory 218900 kb
Host smart-d434cd20-ddf5-46e5-82fc-2e68fa477093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401046754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.3401046754
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.970007068
Short name T854
Test name
Test status
Simulation time 80134360 ps
CPU time 1.12 seconds
Started Aug 15 06:34:16 PM PDT 24
Finished Aug 15 06:34:17 PM PDT 24
Peak memory 217440 kb
Host smart-a37169db-628c-4267-9d4e-91054a13ec83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970007068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.970007068
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1780322387
Short name T11
Test name
Test status
Simulation time 31539495 ps
CPU time 1.37 seconds
Started Aug 15 06:34:16 PM PDT 24
Finished Aug 15 06:34:17 PM PDT 24
Peak memory 220396 kb
Host smart-2a0a3343-0dae-47f5-a63d-b3a6c8306634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780322387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1780322387
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.2601127877
Short name T791
Test name
Test status
Simulation time 104001622 ps
CPU time 1.22 seconds
Started Aug 15 06:32:40 PM PDT 24
Finished Aug 15 06:32:41 PM PDT 24
Peak memory 218652 kb
Host smart-c25fcb82-2a95-4bbe-b514-1fc4848e81ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601127877 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.2601127877
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.3205090598
Short name T362
Test name
Test status
Simulation time 55475858 ps
CPU time 1.52 seconds
Started Aug 15 06:32:43 PM PDT 24
Finished Aug 15 06:32:44 PM PDT 24
Peak memory 206944 kb
Host smart-73cceaad-b235-42c7-85e3-658b506cf7f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205090598 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3205090598
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.4024258714
Short name T204
Test name
Test status
Simulation time 24804689 ps
CPU time 0.83 seconds
Started Aug 15 06:32:41 PM PDT 24
Finished Aug 15 06:32:42 PM PDT 24
Peak memory 215616 kb
Host smart-d6665e2c-3a80-4da3-a7f7-b6e069975313
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024258714 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.4024258714
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.2235369303
Short name T404
Test name
Test status
Simulation time 33185664 ps
CPU time 0.98 seconds
Started Aug 15 06:32:45 PM PDT 24
Finished Aug 15 06:32:46 PM PDT 24
Peak memory 216768 kb
Host smart-13614d6e-af3d-4b54-92bc-20b8f4975937
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235369303 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.2235369303
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.1014868929
Short name T132
Test name
Test status
Simulation time 41929225 ps
CPU time 1.12 seconds
Started Aug 15 06:32:38 PM PDT 24
Finished Aug 15 06:32:39 PM PDT 24
Peak memory 220576 kb
Host smart-d1eed25c-3027-49b7-8a5c-7a20aeeb5d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014868929 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.1014868929
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3090885198
Short name T408
Test name
Test status
Simulation time 48996675 ps
CPU time 1.09 seconds
Started Aug 15 06:32:33 PM PDT 24
Finished Aug 15 06:32:34 PM PDT 24
Peak memory 217416 kb
Host smart-946ffba6-c2b0-4608-91ac-37a6d8e42fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090885198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3090885198
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.2673330021
Short name T37
Test name
Test status
Simulation time 19852081 ps
CPU time 1.04 seconds
Started Aug 15 06:32:41 PM PDT 24
Finished Aug 15 06:32:43 PM PDT 24
Peak memory 215888 kb
Host smart-b9a22ed6-ac7b-47ec-8ff4-d9876bb7fbfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673330021 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2673330021
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.3174766821
Short name T407
Test name
Test status
Simulation time 25203222 ps
CPU time 0.92 seconds
Started Aug 15 06:32:37 PM PDT 24
Finished Aug 15 06:32:38 PM PDT 24
Peak memory 215284 kb
Host smart-7f37a4eb-a9d3-4965-a8de-836eb72a046b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174766821 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.3174766821
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.3315583043
Short name T845
Test name
Test status
Simulation time 94470976 ps
CPU time 2.41 seconds
Started Aug 15 06:32:36 PM PDT 24
Finished Aug 15 06:32:38 PM PDT 24
Peak memory 217240 kb
Host smart-0bb2f0b6-e4ee-4cb2-8e5f-be41efbd4c83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315583043 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.3315583043
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.1916411115
Short name T229
Test name
Test status
Simulation time 3616790796 ps
CPU time 85.36 seconds
Started Aug 15 06:32:42 PM PDT 24
Finished Aug 15 06:34:07 PM PDT 24
Peak memory 221200 kb
Host smart-eace6302-3a34-49db-8ecb-c83dbc16e4be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916411115 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.1916411115
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.1813712929
Short name T74
Test name
Test status
Simulation time 102091825 ps
CPU time 1.15 seconds
Started Aug 15 06:34:06 PM PDT 24
Finished Aug 15 06:34:07 PM PDT 24
Peak memory 217404 kb
Host smart-61fbff12-d5bc-4d8c-ad9b-71e82c9c5144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813712929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.1813712929
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.967797880
Short name T316
Test name
Test status
Simulation time 77535815 ps
CPU time 1.06 seconds
Started Aug 15 06:34:09 PM PDT 24
Finished Aug 15 06:34:10 PM PDT 24
Peak memory 217480 kb
Host smart-ea80592f-2d99-4474-bd41-55eae4d68678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967797880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.967797880
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2048612975
Short name T44
Test name
Test status
Simulation time 43109619 ps
CPU time 1.6 seconds
Started Aug 15 06:34:11 PM PDT 24
Finished Aug 15 06:34:13 PM PDT 24
Peak memory 218408 kb
Host smart-f6b06bca-ea86-4f95-b4fb-8dc44e9a44e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048612975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2048612975
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.285296802
Short name T899
Test name
Test status
Simulation time 101798765 ps
CPU time 1.51 seconds
Started Aug 15 06:34:21 PM PDT 24
Finished Aug 15 06:34:23 PM PDT 24
Peak memory 218716 kb
Host smart-5e393ace-a099-42c1-be5c-b6a75ff85c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285296802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.285296802
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.2442622879
Short name T469
Test name
Test status
Simulation time 39422229 ps
CPU time 1.57 seconds
Started Aug 15 06:34:30 PM PDT 24
Finished Aug 15 06:34:31 PM PDT 24
Peak memory 218700 kb
Host smart-66e132d7-0b49-4d9a-8882-15f7c99297e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442622879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2442622879
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.1595652748
Short name T490
Test name
Test status
Simulation time 126961414 ps
CPU time 1.09 seconds
Started Aug 15 06:34:11 PM PDT 24
Finished Aug 15 06:34:13 PM PDT 24
Peak memory 217564 kb
Host smart-b97bcf22-1bce-4fd6-8c15-7088cd7cf6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595652748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.1595652748
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.2210598225
Short name T359
Test name
Test status
Simulation time 38954486 ps
CPU time 1.74 seconds
Started Aug 15 06:34:11 PM PDT 24
Finished Aug 15 06:34:12 PM PDT 24
Peak memory 218508 kb
Host smart-37a2f5a7-783e-423b-804e-0620caff7a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210598225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.2210598225
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.9182659
Short name T951
Test name
Test status
Simulation time 64272209 ps
CPU time 1.13 seconds
Started Aug 15 06:34:09 PM PDT 24
Finished Aug 15 06:34:10 PM PDT 24
Peak memory 217200 kb
Host smart-c286652c-5fd6-41f2-a770-05a55a15c7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9182659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.9182659
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1248555518
Short name T611
Test name
Test status
Simulation time 44325453 ps
CPU time 1.5 seconds
Started Aug 15 06:34:09 PM PDT 24
Finished Aug 15 06:34:10 PM PDT 24
Peak memory 218600 kb
Host smart-497bc963-05be-4792-977b-3deae7e4d1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248555518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1248555518
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.1477394699
Short name T472
Test name
Test status
Simulation time 35146857 ps
CPU time 1.3 seconds
Started Aug 15 06:34:07 PM PDT 24
Finished Aug 15 06:34:08 PM PDT 24
Peak memory 218524 kb
Host smart-1527a1fb-6d5a-4b38-a090-42dc3ae3f995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477394699 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1477394699
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.1260180954
Short name T959
Test name
Test status
Simulation time 86045608 ps
CPU time 1.32 seconds
Started Aug 15 06:32:42 PM PDT 24
Finished Aug 15 06:32:44 PM PDT 24
Peak memory 219880 kb
Host smart-5f15012e-b774-4089-b5a7-2209a4bb07fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260180954 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.1260180954
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.2465197934
Short name T585
Test name
Test status
Simulation time 20445749 ps
CPU time 0.85 seconds
Started Aug 15 06:32:44 PM PDT 24
Finished Aug 15 06:32:45 PM PDT 24
Peak memory 206844 kb
Host smart-d2fc794d-12a9-4815-9d68-07f87ff835d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465197934 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2465197934
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.1961551502
Short name T206
Test name
Test status
Simulation time 39139428 ps
CPU time 0.85 seconds
Started Aug 15 06:32:43 PM PDT 24
Finished Aug 15 06:32:44 PM PDT 24
Peak memory 215384 kb
Host smart-be268881-6939-4c34-934e-41ec3bbf04e3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961551502 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1961551502
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.925449045
Short name T767
Test name
Test status
Simulation time 439979425 ps
CPU time 1.12 seconds
Started Aug 15 06:32:42 PM PDT 24
Finished Aug 15 06:32:44 PM PDT 24
Peak memory 216792 kb
Host smart-70e35a3b-3e55-4d61-a4a3-4c12b7894a7f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925449045 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_di
sable_auto_req_mode.925449045
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_genbits.2626278519
Short name T957
Test name
Test status
Simulation time 159375675 ps
CPU time 2.94 seconds
Started Aug 15 06:32:42 PM PDT 24
Finished Aug 15 06:32:45 PM PDT 24
Peak memory 220308 kb
Host smart-faa3671a-ada1-4c35-a644-451b7eac922f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626278519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.2626278519
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_smoke.2865400354
Short name T913
Test name
Test status
Simulation time 55604831 ps
CPU time 0.88 seconds
Started Aug 15 06:32:43 PM PDT 24
Finished Aug 15 06:32:44 PM PDT 24
Peak memory 215324 kb
Host smart-71cc9228-532d-44cc-85e5-9b406045f877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865400354 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.2865400354
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.3544002475
Short name T722
Test name
Test status
Simulation time 1778258440 ps
CPU time 5.33 seconds
Started Aug 15 06:32:44 PM PDT 24
Finished Aug 15 06:32:49 PM PDT 24
Peak memory 215328 kb
Host smart-70973fc7-fef0-4fb3-bcb5-00d230ed07b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544002475 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3544002475
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.4185706317
Short name T225
Test name
Test status
Simulation time 3933255020 ps
CPU time 93.79 seconds
Started Aug 15 06:32:44 PM PDT 24
Finished Aug 15 06:34:18 PM PDT 24
Peak memory 217916 kb
Host smart-d14171d9-44b0-49cb-97d9-6f526962a1dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185706317 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.4185706317
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.2048848577
Short name T46
Test name
Test status
Simulation time 96777382 ps
CPU time 1.27 seconds
Started Aug 15 06:34:21 PM PDT 24
Finished Aug 15 06:34:22 PM PDT 24
Peak memory 220268 kb
Host smart-32d26935-937f-47b0-9caa-21c2161d7ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048848577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.2048848577
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.3374187237
Short name T278
Test name
Test status
Simulation time 124554692 ps
CPU time 1.34 seconds
Started Aug 15 06:34:08 PM PDT 24
Finished Aug 15 06:34:10 PM PDT 24
Peak memory 218936 kb
Host smart-53e92cfb-1c2e-41ed-8c57-a012e54ae677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374187237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3374187237
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.3441538677
Short name T317
Test name
Test status
Simulation time 41854597 ps
CPU time 1.17 seconds
Started Aug 15 06:34:11 PM PDT 24
Finished Aug 15 06:34:12 PM PDT 24
Peak memory 217288 kb
Host smart-41521a17-7e81-4472-9230-a62f0f242ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441538677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3441538677
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.2845696011
Short name T293
Test name
Test status
Simulation time 49499701 ps
CPU time 1.28 seconds
Started Aug 15 06:34:09 PM PDT 24
Finished Aug 15 06:34:10 PM PDT 24
Peak memory 218652 kb
Host smart-76daf74f-a7f8-4b2b-b2ee-13a9c5188872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845696011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.2845696011
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.287910305
Short name T47
Test name
Test status
Simulation time 31376590 ps
CPU time 1.22 seconds
Started Aug 15 06:34:16 PM PDT 24
Finished Aug 15 06:34:17 PM PDT 24
Peak memory 217348 kb
Host smart-6ea0857c-fe56-4da7-bf26-c67203e6d080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287910305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.287910305
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.3208328794
Short name T583
Test name
Test status
Simulation time 30127507 ps
CPU time 1.29 seconds
Started Aug 15 06:34:21 PM PDT 24
Finished Aug 15 06:34:23 PM PDT 24
Peak memory 219908 kb
Host smart-39677c72-ab28-4f75-9194-01ee4b1733e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208328794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3208328794
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.537256422
Short name T464
Test name
Test status
Simulation time 66387246 ps
CPU time 1.3 seconds
Started Aug 15 06:34:16 PM PDT 24
Finished Aug 15 06:34:22 PM PDT 24
Peak memory 218592 kb
Host smart-92b1c5a8-a242-4b10-9ed0-e5c7be83a4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537256422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.537256422
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1408673228
Short name T785
Test name
Test status
Simulation time 34342696 ps
CPU time 1.49 seconds
Started Aug 15 06:34:09 PM PDT 24
Finished Aug 15 06:34:10 PM PDT 24
Peak memory 217576 kb
Host smart-cd32c394-e4ba-472a-88b7-45e413cd5666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408673228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1408673228
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.1357970092
Short name T961
Test name
Test status
Simulation time 76224282 ps
CPU time 1.18 seconds
Started Aug 15 06:34:11 PM PDT 24
Finished Aug 15 06:34:12 PM PDT 24
Peak memory 219004 kb
Host smart-fa8476e2-28dd-4138-981f-1147468ffd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357970092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.1357970092
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.1373568086
Short name T435
Test name
Test status
Simulation time 25947995 ps
CPU time 1.2 seconds
Started Aug 15 06:32:40 PM PDT 24
Finished Aug 15 06:32:41 PM PDT 24
Peak memory 219480 kb
Host smart-0c6432e7-c4c3-492b-97e8-67c6ddd947b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373568086 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.1373568086
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1924133542
Short name T525
Test name
Test status
Simulation time 39339989 ps
CPU time 0.95 seconds
Started Aug 15 06:32:43 PM PDT 24
Finished Aug 15 06:32:44 PM PDT 24
Peak memory 214980 kb
Host smart-ee217c94-dc1e-4ed0-b517-aa522ea6dbc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924133542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1924133542
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.2252144100
Short name T665
Test name
Test status
Simulation time 33248625 ps
CPU time 0.82 seconds
Started Aug 15 06:32:42 PM PDT 24
Finished Aug 15 06:32:43 PM PDT 24
Peak memory 215408 kb
Host smart-9d87d5d0-df8b-425a-aaa1-14c5e88048f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252144100 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.2252144100
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.2524901740
Short name T451
Test name
Test status
Simulation time 56293323 ps
CPU time 1 seconds
Started Aug 15 06:32:43 PM PDT 24
Finished Aug 15 06:32:44 PM PDT 24
Peak memory 216920 kb
Host smart-ee81d712-000a-4d04-ba55-2ea22a1bb057
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524901740 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.2524901740
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.162884777
Short name T6
Test name
Test status
Simulation time 24199357 ps
CPU time 1.17 seconds
Started Aug 15 06:32:43 PM PDT 24
Finished Aug 15 06:32:44 PM PDT 24
Peak memory 220760 kb
Host smart-b69cbb0d-c2b8-44f4-a20f-93eddb45317c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162884777 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.162884777
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.2988972097
Short name T369
Test name
Test status
Simulation time 71389733 ps
CPU time 1.32 seconds
Started Aug 15 06:32:41 PM PDT 24
Finished Aug 15 06:32:42 PM PDT 24
Peak memory 218928 kb
Host smart-5dc9a02f-61e8-4c23-a542-0f5c46027941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988972097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2988972097
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.743271794
Short name T952
Test name
Test status
Simulation time 44760493 ps
CPU time 0.91 seconds
Started Aug 15 06:32:46 PM PDT 24
Finished Aug 15 06:32:47 PM PDT 24
Peak memory 215352 kb
Host smart-9df07c8d-752a-4ad8-8532-571b77998360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743271794 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.743271794
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.3650133880
Short name T355
Test name
Test status
Simulation time 17575319 ps
CPU time 1.02 seconds
Started Aug 15 06:32:42 PM PDT 24
Finished Aug 15 06:32:43 PM PDT 24
Peak memory 207188 kb
Host smart-427991fc-6ce7-4f1c-9b7b-e585d1747f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650133880 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.3650133880
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.3353383930
Short name T553
Test name
Test status
Simulation time 203666138 ps
CPU time 2.8 seconds
Started Aug 15 06:32:43 PM PDT 24
Finished Aug 15 06:32:46 PM PDT 24
Peak memory 219588 kb
Host smart-067c58f8-1538-43cd-824d-4ff30a4a6ee7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353383930 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3353383930
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/270.edn_genbits.2471237552
Short name T300
Test name
Test status
Simulation time 126541825 ps
CPU time 1.33 seconds
Started Aug 15 06:34:27 PM PDT 24
Finished Aug 15 06:34:28 PM PDT 24
Peak memory 219404 kb
Host smart-9be451c9-b6f9-4238-a70c-ce42b05e7152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471237552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2471237552
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.3212328378
Short name T911
Test name
Test status
Simulation time 343133328 ps
CPU time 1.35 seconds
Started Aug 15 06:34:12 PM PDT 24
Finished Aug 15 06:34:13 PM PDT 24
Peak memory 217464 kb
Host smart-3cc03f98-67f8-4a56-8573-357fce56527e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212328378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.3212328378
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1657119946
Short name T756
Test name
Test status
Simulation time 72778027 ps
CPU time 1.19 seconds
Started Aug 15 06:34:15 PM PDT 24
Finished Aug 15 06:34:16 PM PDT 24
Peak memory 218764 kb
Host smart-fe376e1d-b6a9-4a79-a31a-4aeb42cd8870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657119946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1657119946
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.2809661479
Short name T707
Test name
Test status
Simulation time 42621133 ps
CPU time 1.42 seconds
Started Aug 15 06:34:21 PM PDT 24
Finished Aug 15 06:34:23 PM PDT 24
Peak memory 217476 kb
Host smart-f19edf38-69da-4c21-97cc-267662cef5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809661479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2809661479
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.1055978291
Short name T898
Test name
Test status
Simulation time 49514350 ps
CPU time 1.53 seconds
Started Aug 15 06:34:29 PM PDT 24
Finished Aug 15 06:34:31 PM PDT 24
Peak memory 218644 kb
Host smart-acc61667-752d-40b1-9826-7a0331e93a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055978291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.1055978291
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.196791696
Short name T470
Test name
Test status
Simulation time 119474659 ps
CPU time 2.51 seconds
Started Aug 15 06:34:24 PM PDT 24
Finished Aug 15 06:34:27 PM PDT 24
Peak memory 220884 kb
Host smart-ab09726f-9d46-43b0-b7bd-9a40f4e6dae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196791696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.196791696
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.1037456243
Short name T649
Test name
Test status
Simulation time 41641821 ps
CPU time 1.4 seconds
Started Aug 15 06:34:19 PM PDT 24
Finished Aug 15 06:34:21 PM PDT 24
Peak memory 218528 kb
Host smart-851aa12a-e089-4e4f-86fa-a49b82f34524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037456243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1037456243
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.4071403081
Short name T381
Test name
Test status
Simulation time 43264591 ps
CPU time 1.24 seconds
Started Aug 15 06:34:20 PM PDT 24
Finished Aug 15 06:34:21 PM PDT 24
Peak memory 218864 kb
Host smart-7d856328-576c-4c44-be1b-a8339456e24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071403081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.4071403081
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.3719183363
Short name T502
Test name
Test status
Simulation time 59919104 ps
CPU time 1.04 seconds
Started Aug 15 06:34:16 PM PDT 24
Finished Aug 15 06:34:18 PM PDT 24
Peak memory 217568 kb
Host smart-11f51173-d3cd-4295-8819-ec58207805c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719183363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3719183363
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.2003022396
Short name T777
Test name
Test status
Simulation time 79275969 ps
CPU time 1.32 seconds
Started Aug 15 06:34:30 PM PDT 24
Finished Aug 15 06:34:31 PM PDT 24
Peak memory 218980 kb
Host smart-982e5dbe-4ee5-4d41-92b4-d770ce9afb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003022396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2003022396
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.3341438963
Short name T429
Test name
Test status
Simulation time 38183668 ps
CPU time 1.16 seconds
Started Aug 15 06:32:42 PM PDT 24
Finished Aug 15 06:32:43 PM PDT 24
Peak memory 220620 kb
Host smart-c6a03b7f-f9cc-4b62-be00-47e88505e12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341438963 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.3341438963
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.2804325299
Short name T833
Test name
Test status
Simulation time 34037006 ps
CPU time 0.98 seconds
Started Aug 15 06:32:47 PM PDT 24
Finished Aug 15 06:32:48 PM PDT 24
Peak memory 206840 kb
Host smart-54810309-5620-4da1-912d-56488c7a6e67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804325299 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2804325299
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.541523141
Short name T164
Test name
Test status
Simulation time 50822995 ps
CPU time 0.88 seconds
Started Aug 15 06:32:44 PM PDT 24
Finished Aug 15 06:32:45 PM PDT 24
Peak memory 215412 kb
Host smart-2bf4117d-6fb4-469a-994f-1b0974ce203c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541523141 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.541523141
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.2889818420
Short name T151
Test name
Test status
Simulation time 109622748 ps
CPU time 1.16 seconds
Started Aug 15 06:32:43 PM PDT 24
Finished Aug 15 06:32:45 PM PDT 24
Peak memory 216916 kb
Host smart-f64859ef-380e-4757-bd0e-c6ac1ad7a8d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889818420 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.2889818420
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.932117895
Short name T169
Test name
Test status
Simulation time 109076352 ps
CPU time 1.12 seconds
Started Aug 15 06:32:41 PM PDT 24
Finished Aug 15 06:32:43 PM PDT 24
Peak memory 225760 kb
Host smart-3103c6fe-441d-4777-bb36-6bb650f4e809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932117895 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.932117895
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.300797150
Short name T50
Test name
Test status
Simulation time 43607182 ps
CPU time 1.7 seconds
Started Aug 15 06:32:46 PM PDT 24
Finished Aug 15 06:32:48 PM PDT 24
Peak memory 220572 kb
Host smart-1a1798ea-46e8-418b-ae6b-056fd82059d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300797150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.300797150
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.2838573579
Short name T454
Test name
Test status
Simulation time 28028623 ps
CPU time 0.88 seconds
Started Aug 15 06:32:40 PM PDT 24
Finished Aug 15 06:32:42 PM PDT 24
Peak memory 215744 kb
Host smart-49287442-f92a-47b2-b187-45562986a68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838573579 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2838573579
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.615412991
Short name T542
Test name
Test status
Simulation time 122302769 ps
CPU time 0.95 seconds
Started Aug 15 06:32:44 PM PDT 24
Finished Aug 15 06:32:45 PM PDT 24
Peak memory 215356 kb
Host smart-96ed9232-d43e-4834-b19d-55e5e856fc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615412991 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.615412991
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.1760793337
Short name T902
Test name
Test status
Simulation time 240624994 ps
CPU time 4.94 seconds
Started Aug 15 06:32:42 PM PDT 24
Finished Aug 15 06:32:47 PM PDT 24
Peak memory 218528 kb
Host smart-793fa184-3dbf-40a8-8db3-1b1c817a5044
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760793337 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1760793337
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.996659790
Short name T555
Test name
Test status
Simulation time 3633703074 ps
CPU time 99.04 seconds
Started Aug 15 06:32:45 PM PDT 24
Finished Aug 15 06:34:24 PM PDT 24
Peak memory 218160 kb
Host smart-7d3447fa-b84c-4b66-acee-b6fcbe8c8612
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996659790 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.996659790
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.995902270
Short name T512
Test name
Test status
Simulation time 177762988 ps
CPU time 1.37 seconds
Started Aug 15 06:34:27 PM PDT 24
Finished Aug 15 06:34:29 PM PDT 24
Peak memory 220444 kb
Host smart-ab76128f-654d-4359-a9d9-c4d8535b24dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995902270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.995902270
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.1107969200
Short name T49
Test name
Test status
Simulation time 291653831 ps
CPU time 3.83 seconds
Started Aug 15 06:34:15 PM PDT 24
Finished Aug 15 06:34:19 PM PDT 24
Peak memory 220648 kb
Host smart-afa6ef76-6f54-49ae-8c08-088ee629a3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107969200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1107969200
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.1101256840
Short name T360
Test name
Test status
Simulation time 39013519 ps
CPU time 1.45 seconds
Started Aug 15 06:34:17 PM PDT 24
Finished Aug 15 06:34:18 PM PDT 24
Peak memory 215332 kb
Host smart-6eaf36a1-e354-4f98-9341-f40c5892c733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101256840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.1101256840
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.629770938
Short name T390
Test name
Test status
Simulation time 48038500 ps
CPU time 1.9 seconds
Started Aug 15 06:34:14 PM PDT 24
Finished Aug 15 06:34:16 PM PDT 24
Peak memory 220620 kb
Host smart-168d324a-e96b-41ab-9fe5-4f77e31561c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629770938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.629770938
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.3457828718
Short name T784
Test name
Test status
Simulation time 32810680 ps
CPU time 1.05 seconds
Started Aug 15 06:34:20 PM PDT 24
Finished Aug 15 06:34:26 PM PDT 24
Peak memory 220436 kb
Host smart-8017c988-3752-4cc5-9ae0-1b2feffb76de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457828718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3457828718
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.658558385
Short name T266
Test name
Test status
Simulation time 65164568 ps
CPU time 2.16 seconds
Started Aug 15 06:34:28 PM PDT 24
Finished Aug 15 06:34:30 PM PDT 24
Peak memory 220596 kb
Host smart-3715737a-cc54-4086-a1a3-5f16ecd59d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658558385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.658558385
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.1082217387
Short name T455
Test name
Test status
Simulation time 72963704 ps
CPU time 2.46 seconds
Started Aug 15 06:34:22 PM PDT 24
Finished Aug 15 06:34:24 PM PDT 24
Peak memory 220092 kb
Host smart-df74fdd6-874f-4485-abc9-037bf334f844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082217387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.1082217387
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.3197032659
Short name T630
Test name
Test status
Simulation time 44911772 ps
CPU time 1.32 seconds
Started Aug 15 06:34:24 PM PDT 24
Finished Aug 15 06:34:26 PM PDT 24
Peak memory 218760 kb
Host smart-35898520-e802-498a-bae7-67c9efaeb15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197032659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.3197032659
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.175723705
Short name T824
Test name
Test status
Simulation time 73272526 ps
CPU time 1.57 seconds
Started Aug 15 06:34:20 PM PDT 24
Finished Aug 15 06:34:22 PM PDT 24
Peak memory 218860 kb
Host smart-6ef475bf-40b5-43cf-ab1f-84b1349621cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175723705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.175723705
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.3075869340
Short name T662
Test name
Test status
Simulation time 55168767 ps
CPU time 1.56 seconds
Started Aug 15 06:34:23 PM PDT 24
Finished Aug 15 06:34:25 PM PDT 24
Peak memory 218396 kb
Host smart-c986fb8f-1a02-4f95-885b-e2a680b22a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075869340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.3075869340
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.2819737070
Short name T215
Test name
Test status
Simulation time 23342324 ps
CPU time 1.17 seconds
Started Aug 15 06:32:44 PM PDT 24
Finished Aug 15 06:32:45 PM PDT 24
Peak memory 219980 kb
Host smart-0cd5dadb-7511-4528-a8bc-2f0da6c36d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819737070 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.2819737070
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.591745130
Short name T332
Test name
Test status
Simulation time 28686055 ps
CPU time 0.8 seconds
Started Aug 15 06:32:44 PM PDT 24
Finished Aug 15 06:32:45 PM PDT 24
Peak memory 206400 kb
Host smart-efcfbfa9-f301-463d-9059-b7946cff72ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591745130 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.591745130
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.2659459166
Short name T924
Test name
Test status
Simulation time 42569278 ps
CPU time 0.88 seconds
Started Aug 15 06:32:44 PM PDT 24
Finished Aug 15 06:32:45 PM PDT 24
Peak memory 215432 kb
Host smart-94402a04-c03c-4c94-bdcc-9a3da9a8f8a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659459166 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2659459166
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_err.66812577
Short name T365
Test name
Test status
Simulation time 19949455 ps
CPU time 1.08 seconds
Started Aug 15 06:32:46 PM PDT 24
Finished Aug 15 06:32:47 PM PDT 24
Peak memory 224152 kb
Host smart-0ecb8c73-d510-48d7-91a8-295d58909491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66812577 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.66812577
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.2417269203
Short name T100
Test name
Test status
Simulation time 123397370 ps
CPU time 1.24 seconds
Started Aug 15 06:32:43 PM PDT 24
Finished Aug 15 06:32:45 PM PDT 24
Peak memory 218892 kb
Host smart-b276a5c8-0fd7-48c1-a33e-7c4b68e9e96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417269203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2417269203
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.673628573
Short name T90
Test name
Test status
Simulation time 38320842 ps
CPU time 0.9 seconds
Started Aug 15 06:32:44 PM PDT 24
Finished Aug 15 06:32:45 PM PDT 24
Peak memory 215932 kb
Host smart-6546c45b-c78e-4361-8907-1db3d7e7bf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673628573 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.673628573
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.432481443
Short name T677
Test name
Test status
Simulation time 17446591 ps
CPU time 1.09 seconds
Started Aug 15 06:32:46 PM PDT 24
Finished Aug 15 06:32:47 PM PDT 24
Peak memory 215404 kb
Host smart-409d6cd6-853f-46b4-8d97-3355c8ddd73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432481443 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.432481443
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.3548245572
Short name T364
Test name
Test status
Simulation time 749024514 ps
CPU time 4.35 seconds
Started Aug 15 06:32:41 PM PDT 24
Finished Aug 15 06:32:46 PM PDT 24
Peak memory 217260 kb
Host smart-00e31748-e9dd-4049-bbcc-10fb754ad230
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548245572 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3548245572
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/290.edn_genbits.138942465
Short name T865
Test name
Test status
Simulation time 37440917 ps
CPU time 1.51 seconds
Started Aug 15 06:34:20 PM PDT 24
Finished Aug 15 06:34:22 PM PDT 24
Peak memory 218608 kb
Host smart-25456f54-327e-470d-963f-77e644359929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138942465 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.138942465
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.2583171970
Short name T849
Test name
Test status
Simulation time 161969772 ps
CPU time 1.34 seconds
Started Aug 15 06:34:19 PM PDT 24
Finished Aug 15 06:34:20 PM PDT 24
Peak memory 217592 kb
Host smart-e7e169d0-b28d-4b7c-ab52-015f0bc751bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583171970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2583171970
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.2355773946
Short name T671
Test name
Test status
Simulation time 40406210 ps
CPU time 1.13 seconds
Started Aug 15 06:34:17 PM PDT 24
Finished Aug 15 06:34:19 PM PDT 24
Peak memory 218828 kb
Host smart-296c2bfd-9633-4a82-b314-edcc5b0f6ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355773946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.2355773946
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.934068386
Short name T843
Test name
Test status
Simulation time 65459162 ps
CPU time 1.38 seconds
Started Aug 15 06:34:20 PM PDT 24
Finished Aug 15 06:34:22 PM PDT 24
Peak memory 217588 kb
Host smart-7edda2a9-7c3b-4e1a-8ddf-4db9a4d85112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934068386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.934068386
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.17919588
Short name T557
Test name
Test status
Simulation time 42886611 ps
CPU time 1.41 seconds
Started Aug 15 06:34:19 PM PDT 24
Finished Aug 15 06:34:20 PM PDT 24
Peak memory 220492 kb
Host smart-a6181bba-89aa-419a-a6a4-7093b24ffd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17919588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.17919588
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.3134028990
Short name T388
Test name
Test status
Simulation time 57813813 ps
CPU time 1.12 seconds
Started Aug 15 06:34:19 PM PDT 24
Finished Aug 15 06:34:20 PM PDT 24
Peak memory 219060 kb
Host smart-11ee7990-4b9d-47a3-9ff3-04db697fb610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134028990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.3134028990
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.488463880
Short name T728
Test name
Test status
Simulation time 75483690 ps
CPU time 1.06 seconds
Started Aug 15 06:34:19 PM PDT 24
Finished Aug 15 06:34:20 PM PDT 24
Peak memory 217400 kb
Host smart-a5854450-508e-466d-af06-ec7225f4bf78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488463880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.488463880
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.1154514858
Short name T708
Test name
Test status
Simulation time 86979937 ps
CPU time 1.28 seconds
Started Aug 15 06:34:16 PM PDT 24
Finished Aug 15 06:34:17 PM PDT 24
Peak memory 218828 kb
Host smart-5dc455d0-baba-42ee-ba04-71ef9b03af24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154514858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1154514858
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.1327474257
Short name T342
Test name
Test status
Simulation time 88885814 ps
CPU time 1.78 seconds
Started Aug 15 06:34:19 PM PDT 24
Finished Aug 15 06:34:21 PM PDT 24
Peak memory 219368 kb
Host smart-b7129a2f-4bf7-4dc0-b2ee-edcec2129434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327474257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1327474257
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.1840208896
Short name T926
Test name
Test status
Simulation time 40229107 ps
CPU time 1.24 seconds
Started Aug 15 06:34:15 PM PDT 24
Finished Aug 15 06:34:17 PM PDT 24
Peak memory 218924 kb
Host smart-089a26f8-ed10-4834-8b7e-55c81a12983d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840208896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1840208896
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.98085433
Short name T687
Test name
Test status
Simulation time 39079002 ps
CPU time 1.16 seconds
Started Aug 15 06:32:08 PM PDT 24
Finished Aug 15 06:32:10 PM PDT 24
Peak memory 218652 kb
Host smart-3a602176-cd14-4f30-9259-e4df3bd5f683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98085433 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.98085433
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.1297016327
Short name T315
Test name
Test status
Simulation time 65777533 ps
CPU time 0.82 seconds
Started Aug 15 06:32:06 PM PDT 24
Finished Aug 15 06:32:07 PM PDT 24
Peak memory 206600 kb
Host smart-6b9d4e92-6dfe-4bd2-8614-0d0459de1303
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297016327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.1297016327
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.2904112138
Short name T760
Test name
Test status
Simulation time 32792122 ps
CPU time 0.86 seconds
Started Aug 15 06:32:09 PM PDT 24
Finished Aug 15 06:32:10 PM PDT 24
Peak memory 215400 kb
Host smart-e7b5496b-27ad-4586-96b3-fe55ff5ee249
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904112138 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.2904112138
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.1414138064
Short name T580
Test name
Test status
Simulation time 81775728 ps
CPU time 1.07 seconds
Started Aug 15 06:32:09 PM PDT 24
Finished Aug 15 06:32:11 PM PDT 24
Peak memory 216876 kb
Host smart-b238652a-3df8-4325-88f2-1533cc05423a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414138064 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.1414138064
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.2495421948
Short name T54
Test name
Test status
Simulation time 45793469 ps
CPU time 0.99 seconds
Started Aug 15 06:32:09 PM PDT 24
Finished Aug 15 06:32:11 PM PDT 24
Peak memory 223924 kb
Host smart-ea81744d-8657-49d1-9a78-aa45fe4560b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495421948 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2495421948
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.3541822658
Short name T685
Test name
Test status
Simulation time 70404361 ps
CPU time 1.12 seconds
Started Aug 15 06:32:10 PM PDT 24
Finished Aug 15 06:32:11 PM PDT 24
Peak memory 217540 kb
Host smart-b49ed94a-3bea-403e-abaf-474ff9351eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541822658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3541822658
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.413695884
Short name T714
Test name
Test status
Simulation time 28836352 ps
CPU time 0.97 seconds
Started Aug 15 06:32:08 PM PDT 24
Finished Aug 15 06:32:10 PM PDT 24
Peak memory 215532 kb
Host smart-826534ce-a50f-4182-b1dd-aec891f8c242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413695884 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.413695884
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.3868946758
Short name T693
Test name
Test status
Simulation time 33682762 ps
CPU time 0.89 seconds
Started Aug 15 06:32:07 PM PDT 24
Finished Aug 15 06:32:08 PM PDT 24
Peak memory 207136 kb
Host smart-0a6d3db9-62c5-4d6b-ba1b-dffb1a59d359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868946758 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.3868946758
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.1114894948
Short name T17
Test name
Test status
Simulation time 255790983 ps
CPU time 4.37 seconds
Started Aug 15 06:32:03 PM PDT 24
Finished Aug 15 06:32:08 PM PDT 24
Peak memory 235264 kb
Host smart-bf603de4-6ca9-4219-a83d-821a3b57851e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114894948 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.1114894948
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.374517841
Short name T488
Test name
Test status
Simulation time 18578681 ps
CPU time 0.97 seconds
Started Aug 15 06:32:07 PM PDT 24
Finished Aug 15 06:32:08 PM PDT 24
Peak memory 215356 kb
Host smart-ddbdb589-720b-429d-852b-bb3ea51daae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374517841 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.374517841
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.2075985404
Short name T477
Test name
Test status
Simulation time 377905499 ps
CPU time 6.8 seconds
Started Aug 15 06:32:08 PM PDT 24
Finished Aug 15 06:32:15 PM PDT 24
Peak memory 215356 kb
Host smart-32682e31-7a2d-4bda-bf8b-0fb9882c338c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075985404 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2075985404
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.1149512641
Short name T754
Test name
Test status
Simulation time 5183847906 ps
CPU time 127.88 seconds
Started Aug 15 06:32:07 PM PDT 24
Finished Aug 15 06:34:15 PM PDT 24
Peak memory 222728 kb
Host smart-a053582d-30d5-4926-8ea1-7df979dbd484
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149512641 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.1149512641
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert_test.2034601586
Short name T322
Test name
Test status
Simulation time 22974478 ps
CPU time 0.89 seconds
Started Aug 15 06:32:53 PM PDT 24
Finished Aug 15 06:32:54 PM PDT 24
Peak memory 206756 kb
Host smart-c0b29ae6-2d31-40de-975e-0f7904f722f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034601586 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.2034601586
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.2930314437
Short name T962
Test name
Test status
Simulation time 20381355 ps
CPU time 0.85 seconds
Started Aug 15 06:32:53 PM PDT 24
Finished Aug 15 06:32:54 PM PDT 24
Peak memory 215140 kb
Host smart-6aa4ed7e-9a30-4927-908f-ea5c5e2fd258
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930314437 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.2930314437
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.3325328274
Short name T142
Test name
Test status
Simulation time 29848598 ps
CPU time 0.98 seconds
Started Aug 15 06:32:54 PM PDT 24
Finished Aug 15 06:32:55 PM PDT 24
Peak memory 216896 kb
Host smart-c087e05d-5cfd-4c57-bac5-c7c807d413f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325328274 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.3325328274
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_genbits.1868132232
Short name T605
Test name
Test status
Simulation time 49257745 ps
CPU time 1.05 seconds
Started Aug 15 06:32:45 PM PDT 24
Finished Aug 15 06:32:46 PM PDT 24
Peak memory 219004 kb
Host smart-60a58cdf-5170-4142-99f5-68cc6929df4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868132232 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1868132232
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3537746467
Short name T36
Test name
Test status
Simulation time 32911908 ps
CPU time 0.89 seconds
Started Aug 15 06:32:52 PM PDT 24
Finished Aug 15 06:32:53 PM PDT 24
Peak memory 215624 kb
Host smart-41a62d5e-94ac-4cd1-95b4-317da03ffa2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537746467 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3537746467
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.4053145230
Short name T853
Test name
Test status
Simulation time 26387923 ps
CPU time 0.94 seconds
Started Aug 15 06:32:43 PM PDT 24
Finished Aug 15 06:32:44 PM PDT 24
Peak memory 215340 kb
Host smart-faf1dbfd-9fc9-4c8e-a4c3-4ad78aa679a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053145230 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.4053145230
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.3087341017
Short name T51
Test name
Test status
Simulation time 1045595040 ps
CPU time 5.54 seconds
Started Aug 15 06:32:43 PM PDT 24
Finished Aug 15 06:32:49 PM PDT 24
Peak memory 217272 kb
Host smart-dd464d15-20f7-4671-86db-cf7dd89572c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087341017 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.3087341017
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.3362741316
Short name T601
Test name
Test status
Simulation time 11458541542 ps
CPU time 38.08 seconds
Started Aug 15 06:32:42 PM PDT 24
Finished Aug 15 06:33:20 PM PDT 24
Peak memory 215580 kb
Host smart-54cbff6d-15b0-48bd-8b62-e973824c08bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362741316 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.3362741316
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.1929518915
Short name T794
Test name
Test status
Simulation time 45033636 ps
CPU time 1.19 seconds
Started Aug 15 06:32:54 PM PDT 24
Finished Aug 15 06:32:55 PM PDT 24
Peak memory 220372 kb
Host smart-8b2aa4a2-bff2-460a-ade8-aea8cd8ccfc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929518915 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1929518915
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.1980855136
Short name T63
Test name
Test status
Simulation time 27649690 ps
CPU time 1.07 seconds
Started Aug 15 06:32:53 PM PDT 24
Finished Aug 15 06:32:54 PM PDT 24
Peak memory 206812 kb
Host smart-7f44e27e-9955-45e0-9cf0-7407323f1905
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980855136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.1980855136
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.1491070037
Short name T399
Test name
Test status
Simulation time 15586092 ps
CPU time 0.96 seconds
Started Aug 15 06:32:52 PM PDT 24
Finished Aug 15 06:32:53 PM PDT 24
Peak memory 215552 kb
Host smart-2dc2bf73-57ee-4684-a3a1-5f368ca0e779
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491070037 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.1491070037
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2900641040
Short name T150
Test name
Test status
Simulation time 54755702 ps
CPU time 1.17 seconds
Started Aug 15 06:32:55 PM PDT 24
Finished Aug 15 06:32:57 PM PDT 24
Peak memory 216816 kb
Host smart-5b7baa80-101e-4141-9ab5-cea90468e596
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900641040 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2900641040
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.3906603615
Short name T892
Test name
Test status
Simulation time 21127324 ps
CPU time 0.91 seconds
Started Aug 15 06:32:56 PM PDT 24
Finished Aug 15 06:32:57 PM PDT 24
Peak memory 218560 kb
Host smart-d2f0a2c9-20b5-4846-9b2c-167b0d7b1bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906603615 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3906603615
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.2206303315
Short name T618
Test name
Test status
Simulation time 89550498 ps
CPU time 1.16 seconds
Started Aug 15 06:32:51 PM PDT 24
Finished Aug 15 06:32:52 PM PDT 24
Peak memory 217348 kb
Host smart-6450b3cd-0d1f-4fe7-9074-0dddc840f72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206303315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.2206303315
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.3819165434
Short name T111
Test name
Test status
Simulation time 22352249 ps
CPU time 1.02 seconds
Started Aug 15 06:32:55 PM PDT 24
Finished Aug 15 06:32:56 PM PDT 24
Peak memory 215908 kb
Host smart-116b5206-bb87-4629-86e1-0384cf959971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819165434 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3819165434
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.2968486651
Short name T265
Test name
Test status
Simulation time 50863316 ps
CPU time 0.93 seconds
Started Aug 15 06:32:56 PM PDT 24
Finished Aug 15 06:32:57 PM PDT 24
Peak memory 215388 kb
Host smart-4eae9963-7751-4239-9c81-7675ffc570f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968486651 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.2968486651
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.1425227201
Short name T596
Test name
Test status
Simulation time 193709908 ps
CPU time 4.44 seconds
Started Aug 15 06:32:51 PM PDT 24
Finished Aug 15 06:32:55 PM PDT 24
Peak memory 217108 kb
Host smart-d4e29e9e-6887-4a40-9958-41963c2bc873
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425227201 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1425227201
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_alert.899261298
Short name T9
Test name
Test status
Simulation time 72518322 ps
CPU time 1.12 seconds
Started Aug 15 06:32:52 PM PDT 24
Finished Aug 15 06:32:53 PM PDT 24
Peak memory 218824 kb
Host smart-661c1d35-061e-40b3-8e34-37f8038b518d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899261298 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.899261298
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.1363252955
Short name T839
Test name
Test status
Simulation time 22732104 ps
CPU time 1.02 seconds
Started Aug 15 06:32:54 PM PDT 24
Finished Aug 15 06:32:55 PM PDT 24
Peak memory 206804 kb
Host smart-44ee8cae-1119-4de4-95ad-c2bf36ead63b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363252955 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.1363252955
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.3077832298
Short name T778
Test name
Test status
Simulation time 35055857 ps
CPU time 1.23 seconds
Started Aug 15 06:32:54 PM PDT 24
Finished Aug 15 06:32:56 PM PDT 24
Peak memory 215292 kb
Host smart-9e25d76a-0ad5-4a8d-b5d4-cdc5400f7c1a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077832298 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.3077832298
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.700185412
Short name T749
Test name
Test status
Simulation time 32828151 ps
CPU time 1.04 seconds
Started Aug 15 06:32:53 PM PDT 24
Finished Aug 15 06:32:59 PM PDT 24
Peak memory 218432 kb
Host smart-723d2dfc-8b18-46cd-b92a-e2ff974497b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700185412 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.700185412
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.3208693244
Short name T546
Test name
Test status
Simulation time 124893823 ps
CPU time 1.41 seconds
Started Aug 15 06:32:53 PM PDT 24
Finished Aug 15 06:32:55 PM PDT 24
Peak memory 219992 kb
Host smart-6585f2f8-9067-45b0-aba4-a754a677dbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208693244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3208693244
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.3890242646
Short name T748
Test name
Test status
Simulation time 26305199 ps
CPU time 0.98 seconds
Started Aug 15 06:33:03 PM PDT 24
Finished Aug 15 06:33:05 PM PDT 24
Peak memory 215488 kb
Host smart-550bca2f-1d53-44dc-9b4e-861c9900d687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890242646 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3890242646
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.2624627569
Short name T698
Test name
Test status
Simulation time 18255884 ps
CPU time 0.97 seconds
Started Aug 15 06:32:52 PM PDT 24
Finished Aug 15 06:32:53 PM PDT 24
Peak memory 215328 kb
Host smart-d9781715-454a-44de-9540-6512b54c85dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624627569 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.2624627569
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.1636476173
Short name T877
Test name
Test status
Simulation time 233588658 ps
CPU time 5.05 seconds
Started Aug 15 06:32:55 PM PDT 24
Finished Aug 15 06:33:00 PM PDT 24
Peak memory 217376 kb
Host smart-9bec3d26-908c-4866-9c92-eed84c01a2cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636476173 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1636476173
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_alert.108453722
Short name T712
Test name
Test status
Simulation time 89071712 ps
CPU time 1.2 seconds
Started Aug 15 06:32:51 PM PDT 24
Finished Aug 15 06:32:52 PM PDT 24
Peak memory 220504 kb
Host smart-7e8fb0dd-d614-470f-972d-e55eb3951794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108453722 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.108453722
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.981003592
Short name T378
Test name
Test status
Simulation time 25095910 ps
CPU time 1.08 seconds
Started Aug 15 06:32:56 PM PDT 24
Finished Aug 15 06:32:57 PM PDT 24
Peak memory 215092 kb
Host smart-efc4c499-3ee9-4c86-9a6c-06fa5aad6677
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981003592 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.981003592
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.1850098114
Short name T200
Test name
Test status
Simulation time 22336772 ps
CPU time 0.9 seconds
Started Aug 15 06:32:55 PM PDT 24
Finished Aug 15 06:32:56 PM PDT 24
Peak memory 215432 kb
Host smart-20957f33-21a8-4f94-accb-753eefc8009d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850098114 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1850098114
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2112435946
Short name T126
Test name
Test status
Simulation time 54649979 ps
CPU time 1.18 seconds
Started Aug 15 06:32:58 PM PDT 24
Finished Aug 15 06:32:59 PM PDT 24
Peak memory 216980 kb
Host smart-e2fb24c2-2f51-40ff-8c7d-3f5bc3193c2c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112435946 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2112435946
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.528703981
Short name T141
Test name
Test status
Simulation time 46375290 ps
CPU time 0.95 seconds
Started Aug 15 06:32:52 PM PDT 24
Finished Aug 15 06:32:53 PM PDT 24
Peak memory 219912 kb
Host smart-cb1a1c6e-26e4-489e-b165-ca7e2e22716a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528703981 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.528703981
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.2546999752
Short name T590
Test name
Test status
Simulation time 140012154 ps
CPU time 1.26 seconds
Started Aug 15 06:32:50 PM PDT 24
Finished Aug 15 06:32:51 PM PDT 24
Peak memory 218724 kb
Host smart-0395ab79-1891-48d8-8eba-aa8d1cb04e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546999752 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2546999752
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.1344909494
Short name T35
Test name
Test status
Simulation time 40689358 ps
CPU time 0.94 seconds
Started Aug 15 06:33:03 PM PDT 24
Finished Aug 15 06:33:05 PM PDT 24
Peak memory 215428 kb
Host smart-18c97874-e23d-43e0-81d0-27a8acde9cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344909494 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.1344909494
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.3428151044
Short name T445
Test name
Test status
Simulation time 43513945 ps
CPU time 0.97 seconds
Started Aug 15 06:32:53 PM PDT 24
Finished Aug 15 06:32:55 PM PDT 24
Peak memory 215332 kb
Host smart-5d61d7e3-3cda-49cc-93b5-708487eb1388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428151044 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.3428151044
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.2906187881
Short name T716
Test name
Test status
Simulation time 107382498 ps
CPU time 2.39 seconds
Started Aug 15 06:32:54 PM PDT 24
Finished Aug 15 06:32:57 PM PDT 24
Peak memory 215448 kb
Host smart-899cac2d-3b06-4f7e-a506-7e661c429357
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906187881 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.2906187881
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3561611984
Short name T231
Test name
Test status
Simulation time 31596864192 ps
CPU time 73.57 seconds
Started Aug 15 06:32:52 PM PDT 24
Finished Aug 15 06:34:06 PM PDT 24
Peak memory 219104 kb
Host smart-4812c172-7dec-476b-8d37-88a790d50d7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561611984 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3561611984
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.2843131180
Short name T809
Test name
Test status
Simulation time 34645687 ps
CPU time 1.14 seconds
Started Aug 15 06:32:49 PM PDT 24
Finished Aug 15 06:32:51 PM PDT 24
Peak memory 215752 kb
Host smart-053c686b-0392-4aa9-bfa3-5fa6962f107e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843131180 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2843131180
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.1946190275
Short name T503
Test name
Test status
Simulation time 34114578 ps
CPU time 0.98 seconds
Started Aug 15 06:32:53 PM PDT 24
Finished Aug 15 06:32:54 PM PDT 24
Peak memory 214964 kb
Host smart-6a5a6b1b-25d7-4ecd-b989-03105e838a11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946190275 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1946190275
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.162069429
Short name T181
Test name
Test status
Simulation time 31659972 ps
CPU time 0.87 seconds
Started Aug 15 06:32:53 PM PDT 24
Finished Aug 15 06:32:55 PM PDT 24
Peak memory 215428 kb
Host smart-5ce84b64-3ee6-478a-abf4-479301e1f9f3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162069429 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.162069429
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.1585642071
Short name T331
Test name
Test status
Simulation time 55634200 ps
CPU time 1.15 seconds
Started Aug 15 06:33:03 PM PDT 24
Finished Aug 15 06:33:05 PM PDT 24
Peak memory 218516 kb
Host smart-48b1caa1-bfee-4c81-9c4e-8c4e25b3e2e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585642071 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.1585642071
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.538732994
Short name T116
Test name
Test status
Simulation time 20931414 ps
CPU time 1.23 seconds
Started Aug 15 06:32:53 PM PDT 24
Finished Aug 15 06:32:54 PM PDT 24
Peak memory 229704 kb
Host smart-e712f506-2664-4479-812a-62e5e1554138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538732994 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.538732994
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.1712081970
Short name T837
Test name
Test status
Simulation time 90143709 ps
CPU time 1.16 seconds
Started Aug 15 06:32:55 PM PDT 24
Finished Aug 15 06:32:56 PM PDT 24
Peak memory 217364 kb
Host smart-b252520a-2f24-4cf6-92ed-a48e4ff27214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712081970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1712081970
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.1491165057
Short name T870
Test name
Test status
Simulation time 36914782 ps
CPU time 1.01 seconds
Started Aug 15 06:32:55 PM PDT 24
Finished Aug 15 06:32:56 PM PDT 24
Peak memory 223976 kb
Host smart-a3a876eb-3eed-484d-8f2b-55d436749532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491165057 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1491165057
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.3264938087
Short name T446
Test name
Test status
Simulation time 17059478 ps
CPU time 1.03 seconds
Started Aug 15 06:32:51 PM PDT 24
Finished Aug 15 06:32:52 PM PDT 24
Peak memory 215304 kb
Host smart-46bcb05b-4d3d-4eb9-8973-e31c13f0078a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264938087 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.3264938087
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.100281086
Short name T479
Test name
Test status
Simulation time 351774775 ps
CPU time 6.92 seconds
Started Aug 15 06:32:53 PM PDT 24
Finished Aug 15 06:33:00 PM PDT 24
Peak memory 217112 kb
Host smart-3ffba553-d102-485d-b0f0-48303081e8de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100281086 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.100281086
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.652838796
Short name T228
Test name
Test status
Simulation time 2365374669 ps
CPU time 54.33 seconds
Started Aug 15 06:32:52 PM PDT 24
Finished Aug 15 06:33:47 PM PDT 24
Peak memory 219040 kb
Host smart-c09b4ccf-f388-48b8-b897-28b09e290686
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652838796 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.652838796
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.2515918317
Short name T949
Test name
Test status
Simulation time 221731446 ps
CPU time 1.08 seconds
Started Aug 15 06:32:53 PM PDT 24
Finished Aug 15 06:32:54 PM PDT 24
Peak memory 219712 kb
Host smart-6eae780e-df0a-4a8e-b340-6e8c8dce69cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515918317 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.2515918317
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.1578054700
Short name T960
Test name
Test status
Simulation time 42261624 ps
CPU time 0.73 seconds
Started Aug 15 06:32:52 PM PDT 24
Finished Aug 15 06:32:53 PM PDT 24
Peak memory 206368 kb
Host smart-1c063b89-12c6-4414-bc5c-f01e5716a0e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578054700 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1578054700
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.1094257062
Short name T588
Test name
Test status
Simulation time 23317980 ps
CPU time 0.88 seconds
Started Aug 15 06:32:51 PM PDT 24
Finished Aug 15 06:32:52 PM PDT 24
Peak memory 215448 kb
Host smart-a77e980c-f13d-437c-8b42-cd2a2decafd1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094257062 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1094257062
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.3564909496
Short name T603
Test name
Test status
Simulation time 37083872 ps
CPU time 1.23 seconds
Started Aug 15 06:32:55 PM PDT 24
Finished Aug 15 06:32:56 PM PDT 24
Peak memory 217092 kb
Host smart-d6f602df-e7a7-4c2e-88b5-3a8e97b937a3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564909496 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.3564909496
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.307570761
Short name T136
Test name
Test status
Simulation time 35154012 ps
CPU time 1.07 seconds
Started Aug 15 06:32:53 PM PDT 24
Finished Aug 15 06:32:54 PM PDT 24
Peak memory 218556 kb
Host smart-68bc81ee-21ff-4e1f-884e-2782b92359c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307570761 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.307570761
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.925335280
Short name T715
Test name
Test status
Simulation time 88012551 ps
CPU time 1.21 seconds
Started Aug 15 06:32:55 PM PDT 24
Finished Aug 15 06:32:56 PM PDT 24
Peak memory 219652 kb
Host smart-76accd01-1741-45e9-8377-c1c1ca9af338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925335280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.925335280
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.1001921081
Short name T805
Test name
Test status
Simulation time 22015641 ps
CPU time 0.92 seconds
Started Aug 15 06:32:58 PM PDT 24
Finished Aug 15 06:32:59 PM PDT 24
Peak memory 215904 kb
Host smart-11b0de5f-fd30-4448-ade7-83463d690d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001921081 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1001921081
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.1740395771
Short name T769
Test name
Test status
Simulation time 82288374 ps
CPU time 0.93 seconds
Started Aug 15 06:32:54 PM PDT 24
Finished Aug 15 06:32:55 PM PDT 24
Peak memory 215380 kb
Host smart-2b8d1638-1c61-4093-9a20-e2ba468b9632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740395771 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.1740395771
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2950502499
Short name T501
Test name
Test status
Simulation time 1069948905 ps
CPU time 5.21 seconds
Started Aug 15 06:32:51 PM PDT 24
Finished Aug 15 06:32:57 PM PDT 24
Peak memory 217240 kb
Host smart-205df422-1967-4b79-8255-4b7b16e12f1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950502499 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2950502499
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_alert.2555715242
Short name T527
Test name
Test status
Simulation time 41301349 ps
CPU time 1.14 seconds
Started Aug 15 06:32:52 PM PDT 24
Finished Aug 15 06:32:54 PM PDT 24
Peak memory 219968 kb
Host smart-febca832-7c19-465b-87f5-d5167c3c51a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555715242 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.2555715242
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.2992662710
Short name T895
Test name
Test status
Simulation time 56425673 ps
CPU time 0.86 seconds
Started Aug 15 06:32:58 PM PDT 24
Finished Aug 15 06:32:59 PM PDT 24
Peak memory 206840 kb
Host smart-b3af1fed-cd45-4575-89be-9e1dab3b4493
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992662710 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2992662710
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.2335644166
Short name T27
Test name
Test status
Simulation time 95173121 ps
CPU time 1.11 seconds
Started Aug 15 06:32:55 PM PDT 24
Finished Aug 15 06:32:57 PM PDT 24
Peak memory 215412 kb
Host smart-edb2609f-fd1d-490f-95b8-41ce93c35f01
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335644166 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.2335644166
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.915583173
Short name T191
Test name
Test status
Simulation time 35782812 ps
CPU time 0.85 seconds
Started Aug 15 06:32:53 PM PDT 24
Finished Aug 15 06:32:54 PM PDT 24
Peak memory 219272 kb
Host smart-10cbd4b4-30ed-4601-8aab-75ef1b1ae853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915583173 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.915583173
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.1488534228
Short name T772
Test name
Test status
Simulation time 58438487 ps
CPU time 1.51 seconds
Started Aug 15 06:32:54 PM PDT 24
Finished Aug 15 06:32:56 PM PDT 24
Peak memory 218780 kb
Host smart-d8fe6195-34ae-49ed-9bb7-902b27ba69a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488534228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1488534228
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.769954823
Short name T448
Test name
Test status
Simulation time 20075069 ps
CPU time 1.08 seconds
Started Aug 15 06:32:51 PM PDT 24
Finished Aug 15 06:32:52 PM PDT 24
Peak memory 215840 kb
Host smart-59ff5d4a-5971-4d72-bb9a-417ac3ded895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769954823 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.769954823
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.3618391021
Short name T475
Test name
Test status
Simulation time 39308166 ps
CPU time 0.86 seconds
Started Aug 15 06:32:53 PM PDT 24
Finished Aug 15 06:32:54 PM PDT 24
Peak memory 207148 kb
Host smart-707cc202-6955-471f-a9f6-3e25923f9b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618391021 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.3618391021
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.396765847
Short name T711
Test name
Test status
Simulation time 233802496 ps
CPU time 4.25 seconds
Started Aug 15 06:32:50 PM PDT 24
Finished Aug 15 06:32:54 PM PDT 24
Peak memory 217124 kb
Host smart-b8d82432-8bab-42a9-bc6d-3fd414ed55c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396765847 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.396765847
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_alert.3608493005
Short name T184
Test name
Test status
Simulation time 76200882 ps
CPU time 1.35 seconds
Started Aug 15 06:32:58 PM PDT 24
Finished Aug 15 06:33:00 PM PDT 24
Peak memory 221176 kb
Host smart-2172b813-c5fa-42e3-b285-1dfce20ca5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608493005 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3608493005
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2615053173
Short name T885
Test name
Test status
Simulation time 77767860 ps
CPU time 0.9 seconds
Started Aug 15 06:33:01 PM PDT 24
Finished Aug 15 06:33:02 PM PDT 24
Peak memory 206768 kb
Host smart-d85bb636-f09a-4923-80f3-b153768f3043
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615053173 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2615053173
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.1692769234
Short name T186
Test name
Test status
Simulation time 79117480 ps
CPU time 0.89 seconds
Started Aug 15 06:32:57 PM PDT 24
Finished Aug 15 06:32:58 PM PDT 24
Peak memory 215416 kb
Host smart-75beb63f-0377-444c-91e7-5d60e1597682
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692769234 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1692769234
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.1367168551
Short name T565
Test name
Test status
Simulation time 268605730 ps
CPU time 1.09 seconds
Started Aug 15 06:33:01 PM PDT 24
Finished Aug 15 06:33:03 PM PDT 24
Peak memory 216880 kb
Host smart-227117ae-8f0d-456f-a3a1-7856b361c246
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367168551 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.1367168551
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.2473008137
Short name T208
Test name
Test status
Simulation time 38298564 ps
CPU time 0.83 seconds
Started Aug 15 06:33:05 PM PDT 24
Finished Aug 15 06:33:06 PM PDT 24
Peak memory 218304 kb
Host smart-d12f3bda-b632-4596-b0f1-8eb437deef73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473008137 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2473008137
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_intr.4160270123
Short name T398
Test name
Test status
Simulation time 20799820 ps
CPU time 1.24 seconds
Started Aug 15 06:33:01 PM PDT 24
Finished Aug 15 06:33:02 PM PDT 24
Peak memory 224204 kb
Host smart-54f702f0-fc60-4e17-86a0-29af22c4d16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160270123 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.4160270123
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.1683169392
Short name T343
Test name
Test status
Simulation time 108177579 ps
CPU time 0.96 seconds
Started Aug 15 06:32:59 PM PDT 24
Finished Aug 15 06:33:00 PM PDT 24
Peak memory 215360 kb
Host smart-2130cae1-6f7e-4730-bf05-cac942cf4577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683169392 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.1683169392
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.881652958
Short name T320
Test name
Test status
Simulation time 132929049 ps
CPU time 1.38 seconds
Started Aug 15 06:32:59 PM PDT 24
Finished Aug 15 06:33:01 PM PDT 24
Peak memory 219856 kb
Host smart-afe4fb53-0071-48a0-8d7d-77c827068022
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881652958 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.881652958
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_alert.190404246
Short name T786
Test name
Test status
Simulation time 24036141 ps
CPU time 1.21 seconds
Started Aug 15 06:33:00 PM PDT 24
Finished Aug 15 06:33:02 PM PDT 24
Peak memory 218724 kb
Host smart-0e6f518b-8dac-418c-a336-a65d245b9e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190404246 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.190404246
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.3892562940
Short name T790
Test name
Test status
Simulation time 118182770 ps
CPU time 0.81 seconds
Started Aug 15 06:32:58 PM PDT 24
Finished Aug 15 06:32:59 PM PDT 24
Peak memory 206368 kb
Host smart-ebac86f1-de55-4ee1-bac3-0cb64baaa17c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892562940 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3892562940
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.3002090851
Short name T264
Test name
Test status
Simulation time 27483202 ps
CPU time 1.09 seconds
Started Aug 15 06:32:57 PM PDT 24
Finished Aug 15 06:32:58 PM PDT 24
Peak memory 218620 kb
Host smart-2fa9c590-a19b-4f12-85a8-d67c6242af43
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002090851 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.3002090851
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.3115312565
Short name T117
Test name
Test status
Simulation time 24889432 ps
CPU time 1.09 seconds
Started Aug 15 06:32:56 PM PDT 24
Finished Aug 15 06:32:57 PM PDT 24
Peak memory 219716 kb
Host smart-01b2d193-732c-465e-b492-d19f587d9711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115312565 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3115312565
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.947240207
Short name T415
Test name
Test status
Simulation time 220459977 ps
CPU time 2.86 seconds
Started Aug 15 06:32:58 PM PDT 24
Finished Aug 15 06:33:01 PM PDT 24
Peak memory 219724 kb
Host smart-56583ca0-22df-4f8b-a7c8-03f082817f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947240207 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.947240207
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.4177713861
Short name T836
Test name
Test status
Simulation time 34057434 ps
CPU time 0.91 seconds
Started Aug 15 06:32:57 PM PDT 24
Finished Aug 15 06:32:58 PM PDT 24
Peak memory 215800 kb
Host smart-00a3eeee-6289-4e92-8f07-9a4b28c70e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177713861 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.4177713861
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.123805323
Short name T495
Test name
Test status
Simulation time 72887717 ps
CPU time 0.97 seconds
Started Aug 15 06:33:00 PM PDT 24
Finished Aug 15 06:33:01 PM PDT 24
Peak memory 207156 kb
Host smart-6feda508-e430-45e7-85c9-f391a7b0b8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123805323 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.123805323
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.31254274
Short name T349
Test name
Test status
Simulation time 220819452 ps
CPU time 4.42 seconds
Started Aug 15 06:33:04 PM PDT 24
Finished Aug 15 06:33:09 PM PDT 24
Peak memory 217244 kb
Host smart-f3c6441a-8be6-449e-94e5-e039668408eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31254274 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.31254274
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_alert.590707406
Short name T304
Test name
Test status
Simulation time 209803322 ps
CPU time 1.24 seconds
Started Aug 15 06:32:59 PM PDT 24
Finished Aug 15 06:33:01 PM PDT 24
Peak memory 218492 kb
Host smart-f55672cf-5e3f-4d3b-a782-5a9bd67cfeb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590707406 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.590707406
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.1107710480
Short name T570
Test name
Test status
Simulation time 147672234 ps
CPU time 0.97 seconds
Started Aug 15 06:33:08 PM PDT 24
Finished Aug 15 06:33:09 PM PDT 24
Peak memory 206868 kb
Host smart-d9ce93ff-892f-4131-953a-bba3e3f0d624
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107710480 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1107710480
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.672273315
Short name T41
Test name
Test status
Simulation time 34402750 ps
CPU time 0.85 seconds
Started Aug 15 06:32:59 PM PDT 24
Finished Aug 15 06:33:00 PM PDT 24
Peak memory 215172 kb
Host smart-a3bd7c30-9111-4c16-bd7a-ebfb379ffd01
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672273315 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.672273315
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_err.3395686797
Short name T468
Test name
Test status
Simulation time 38031617 ps
CPU time 0.9 seconds
Started Aug 15 06:33:01 PM PDT 24
Finished Aug 15 06:33:02 PM PDT 24
Peak memory 218188 kb
Host smart-9fe7d7c7-3a55-40d5-95a2-8bc00a068c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395686797 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3395686797
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.217051452
Short name T887
Test name
Test status
Simulation time 96912300 ps
CPU time 1.57 seconds
Started Aug 15 06:33:01 PM PDT 24
Finished Aug 15 06:33:03 PM PDT 24
Peak memory 218752 kb
Host smart-2abdb8ae-df70-4554-843b-b5cc67edf342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217051452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.217051452
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.898271228
Short name T517
Test name
Test status
Simulation time 24863060 ps
CPU time 1.06 seconds
Started Aug 15 06:33:01 PM PDT 24
Finished Aug 15 06:33:03 PM PDT 24
Peak memory 215864 kb
Host smart-0b73a820-e4e9-4bd3-a9fc-b68ced12448e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898271228 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.898271228
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.3919863385
Short name T729
Test name
Test status
Simulation time 53413698 ps
CPU time 0.9 seconds
Started Aug 15 06:33:08 PM PDT 24
Finished Aug 15 06:33:15 PM PDT 24
Peak memory 215304 kb
Host smart-14168680-19e8-4a16-a3f7-b28557493a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919863385 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.3919863385
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.759969058
Short name T654
Test name
Test status
Simulation time 151873320 ps
CPU time 1.47 seconds
Started Aug 15 06:32:58 PM PDT 24
Finished Aug 15 06:33:00 PM PDT 24
Peak memory 217428 kb
Host smart-0da57a50-f415-4089-a2c2-ba7675f0b0d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759969058 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.759969058
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_alert.1961235554
Short name T599
Test name
Test status
Simulation time 53500752 ps
CPU time 1.28 seconds
Started Aug 15 06:32:10 PM PDT 24
Finished Aug 15 06:32:12 PM PDT 24
Peak memory 220196 kb
Host smart-98527308-9676-4241-ac21-17d06cb27f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961235554 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1961235554
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.921474031
Short name T699
Test name
Test status
Simulation time 116810314 ps
CPU time 0.96 seconds
Started Aug 15 06:32:08 PM PDT 24
Finished Aug 15 06:32:09 PM PDT 24
Peak memory 206976 kb
Host smart-ba11602b-ae4e-4e5c-b3d1-868568f55086
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921474031 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.921474031
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.194686548
Short name T437
Test name
Test status
Simulation time 34049933 ps
CPU time 0.82 seconds
Started Aug 15 06:32:07 PM PDT 24
Finished Aug 15 06:32:08 PM PDT 24
Peak memory 215404 kb
Host smart-98274255-0c33-4262-879a-9b6aef2d80b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194686548 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.194686548
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.1069485525
Short name T545
Test name
Test status
Simulation time 230807172 ps
CPU time 1.19 seconds
Started Aug 15 06:32:09 PM PDT 24
Finished Aug 15 06:32:10 PM PDT 24
Peak memory 219636 kb
Host smart-185f85d5-a17e-49ec-9109-0d0a90e23060
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069485525 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.1069485525
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.1558162217
Short name T172
Test name
Test status
Simulation time 34685204 ps
CPU time 0.91 seconds
Started Aug 15 06:32:06 PM PDT 24
Finished Aug 15 06:32:07 PM PDT 24
Peak memory 218376 kb
Host smart-34eea71f-f478-4250-8eac-caade9d347b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558162217 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.1558162217
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.2376164154
Short name T812
Test name
Test status
Simulation time 49581105 ps
CPU time 1.12 seconds
Started Aug 15 06:32:15 PM PDT 24
Finished Aug 15 06:32:16 PM PDT 24
Peak memory 217224 kb
Host smart-dc9bd604-0573-419b-ade6-f13bef3f07fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376164154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.2376164154
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.599626249
Short name T536
Test name
Test status
Simulation time 40463426 ps
CPU time 1.04 seconds
Started Aug 15 06:32:09 PM PDT 24
Finished Aug 15 06:32:10 PM PDT 24
Peak memory 224160 kb
Host smart-a5fd2076-7112-42a3-b028-23edcec2a556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599626249 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.599626249
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.2275734806
Short name T681
Test name
Test status
Simulation time 17123010 ps
CPU time 0.94 seconds
Started Aug 15 06:32:07 PM PDT 24
Finished Aug 15 06:32:08 PM PDT 24
Peak memory 207160 kb
Host smart-8041a094-7513-488c-b6f6-4548dc1626f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275734806 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.2275734806
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.4099607469
Short name T443
Test name
Test status
Simulation time 27262608 ps
CPU time 0.94 seconds
Started Aug 15 06:32:07 PM PDT 24
Finished Aug 15 06:32:08 PM PDT 24
Peak memory 215340 kb
Host smart-a4382ce1-f715-49b8-8662-f3cd77a5de65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099607469 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.4099607469
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.2253650393
Short name T98
Test name
Test status
Simulation time 499683530 ps
CPU time 5.03 seconds
Started Aug 15 06:32:09 PM PDT 24
Finished Aug 15 06:32:14 PM PDT 24
Peak memory 219912 kb
Host smart-bd71bdec-e4e4-44e1-b331-c82048c5adcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253650393 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2253650393
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2099247244
Short name T233
Test name
Test status
Simulation time 8260502977 ps
CPU time 50.98 seconds
Started Aug 15 06:32:08 PM PDT 24
Finished Aug 15 06:32:59 PM PDT 24
Peak memory 218592 kb
Host smart-39275661-9cb8-4205-a90b-09173d69a54d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099247244 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2099247244
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.2839579151
Short name T880
Test name
Test status
Simulation time 91214533 ps
CPU time 1.21 seconds
Started Aug 15 06:32:59 PM PDT 24
Finished Aug 15 06:33:01 PM PDT 24
Peak memory 215712 kb
Host smart-2d91a04f-67a4-4dab-bc00-057f88b72ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839579151 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.2839579151
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.996916758
Short name T474
Test name
Test status
Simulation time 40514862 ps
CPU time 0.86 seconds
Started Aug 15 06:32:58 PM PDT 24
Finished Aug 15 06:32:59 PM PDT 24
Peak memory 206828 kb
Host smart-4f490d66-6ac8-4e25-902d-a3876ef4d893
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996916758 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.996916758
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.3005653953
Short name T220
Test name
Test status
Simulation time 12890008 ps
CPU time 0.91 seconds
Started Aug 15 06:32:59 PM PDT 24
Finished Aug 15 06:33:00 PM PDT 24
Peak memory 215576 kb
Host smart-90267e4c-7fc5-4d68-b2e4-81d633dcb845
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005653953 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.3005653953
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.2829080639
Short name T201
Test name
Test status
Simulation time 43692428 ps
CPU time 1.59 seconds
Started Aug 15 06:32:58 PM PDT 24
Finished Aug 15 06:32:59 PM PDT 24
Peak memory 217056 kb
Host smart-64fc3c76-c61c-44c6-b1b3-5a7a1d134428
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829080639 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.2829080639
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.2066532922
Short name T471
Test name
Test status
Simulation time 34720496 ps
CPU time 0.89 seconds
Started Aug 15 06:32:59 PM PDT 24
Finished Aug 15 06:33:00 PM PDT 24
Peak memory 218276 kb
Host smart-8c1e415f-78ec-42ce-bb7a-0140fd3aeeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066532922 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.2066532922
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.1326869503
Short name T69
Test name
Test status
Simulation time 205167678 ps
CPU time 1.16 seconds
Started Aug 15 06:33:01 PM PDT 24
Finished Aug 15 06:33:02 PM PDT 24
Peak memory 217328 kb
Host smart-21591ce0-ae30-4038-bc12-45bd48d1af05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326869503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1326869503
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.4203075784
Short name T938
Test name
Test status
Simulation time 19177659 ps
CPU time 1.1 seconds
Started Aug 15 06:33:04 PM PDT 24
Finished Aug 15 06:33:06 PM PDT 24
Peak memory 215912 kb
Host smart-be28b5c8-a717-4b5e-8e41-be96c8664851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203075784 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.4203075784
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.2532674314
Short name T94
Test name
Test status
Simulation time 14987719 ps
CPU time 0.97 seconds
Started Aug 15 06:32:59 PM PDT 24
Finished Aug 15 06:33:00 PM PDT 24
Peak memory 215316 kb
Host smart-f9e232a4-c851-4afc-88f4-84d4aa76e643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532674314 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.2532674314
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.4216049207
Short name T759
Test name
Test status
Simulation time 574040611 ps
CPU time 3.56 seconds
Started Aug 15 06:33:04 PM PDT 24
Finished Aug 15 06:33:07 PM PDT 24
Peak memory 217480 kb
Host smart-ae19b16c-9d42-402b-b420-c317ee457b9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216049207 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.4216049207
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_alert.153097287
Short name T947
Test name
Test status
Simulation time 29114056 ps
CPU time 1.26 seconds
Started Aug 15 06:32:59 PM PDT 24
Finished Aug 15 06:33:01 PM PDT 24
Peak memory 219548 kb
Host smart-c4753aec-715c-48cd-ad5b-8879540fb4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153097287 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.153097287
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.195419912
Short name T738
Test name
Test status
Simulation time 161179367 ps
CPU time 0.96 seconds
Started Aug 15 06:33:04 PM PDT 24
Finished Aug 15 06:33:05 PM PDT 24
Peak memory 206772 kb
Host smart-5d75a1eb-04d5-4582-a409-dddcf20517db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195419912 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.195419912
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.3715615181
Short name T473
Test name
Test status
Simulation time 30010751 ps
CPU time 0.81 seconds
Started Aug 15 06:32:57 PM PDT 24
Finished Aug 15 06:32:58 PM PDT 24
Peak memory 215444 kb
Host smart-7a985598-e845-4c8a-af06-f296e141ab14
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715615181 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3715615181
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.1227887441
Short name T925
Test name
Test status
Simulation time 25604840 ps
CPU time 1.08 seconds
Started Aug 15 06:32:59 PM PDT 24
Finished Aug 15 06:33:00 PM PDT 24
Peak memory 215320 kb
Host smart-87765292-fa48-4b65-bd97-3d4bc4b3e7ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227887441 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.1227887441
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.854795074
Short name T118
Test name
Test status
Simulation time 27222122 ps
CPU time 1.23 seconds
Started Aug 15 06:33:02 PM PDT 24
Finished Aug 15 06:33:04 PM PDT 24
Peak memory 217324 kb
Host smart-019da6e1-90ec-4b4b-a581-431bcb4de1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854795074 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.854795074
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.2934919894
Short name T942
Test name
Test status
Simulation time 71586840 ps
CPU time 1.03 seconds
Started Aug 15 06:32:58 PM PDT 24
Finished Aug 15 06:33:00 PM PDT 24
Peak memory 217208 kb
Host smart-f7712f1c-e555-4396-b5ec-e6d11d320a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934919894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2934919894
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.2701802084
Short name T634
Test name
Test status
Simulation time 32743985 ps
CPU time 0.86 seconds
Started Aug 15 06:32:58 PM PDT 24
Finished Aug 15 06:32:59 PM PDT 24
Peak memory 215392 kb
Host smart-de0f100d-e790-478b-bcbb-c9d46562b712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701802084 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2701802084
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.3312245997
Short name T509
Test name
Test status
Simulation time 60972549 ps
CPU time 0.89 seconds
Started Aug 15 06:32:58 PM PDT 24
Finished Aug 15 06:32:59 PM PDT 24
Peak memory 215336 kb
Host smart-7181bb6e-118b-4f22-9765-2eb1721daa18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312245997 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3312245997
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.1229762780
Short name T353
Test name
Test status
Simulation time 284881328 ps
CPU time 3.62 seconds
Started Aug 15 06:33:07 PM PDT 24
Finished Aug 15 06:33:11 PM PDT 24
Peak memory 218672 kb
Host smart-3166d96c-b0fd-4e59-8db8-8d615b0f0403
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229762780 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.1229762780
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1265882896
Short name T674
Test name
Test status
Simulation time 35784539858 ps
CPU time 94.47 seconds
Started Aug 15 06:33:01 PM PDT 24
Finished Aug 15 06:34:36 PM PDT 24
Peak memory 218084 kb
Host smart-2b9e325d-f044-4794-85d8-67b81e698322
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265882896 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1265882896
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.3755781307
Short name T523
Test name
Test status
Simulation time 84806509 ps
CPU time 1.11 seconds
Started Aug 15 06:33:00 PM PDT 24
Finished Aug 15 06:33:01 PM PDT 24
Peak memory 218660 kb
Host smart-462b62c4-4538-4eeb-ad2f-22230424e4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755781307 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3755781307
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.1081294841
Short name T567
Test name
Test status
Simulation time 13418085 ps
CPU time 0.87 seconds
Started Aug 15 06:33:09 PM PDT 24
Finished Aug 15 06:33:10 PM PDT 24
Peak memory 207024 kb
Host smart-84ed7f74-4a75-4d4a-b37e-a8b26c652663
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081294841 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1081294841
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.3913543623
Short name T561
Test name
Test status
Simulation time 14338540 ps
CPU time 0.87 seconds
Started Aug 15 06:32:57 PM PDT 24
Finished Aug 15 06:32:58 PM PDT 24
Peak memory 215172 kb
Host smart-c173085e-3c5b-4a0a-bba5-d8429e2bc150
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913543623 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3913543623
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3065940887
Short name T121
Test name
Test status
Simulation time 52156635 ps
CPU time 1.13 seconds
Started Aug 15 06:33:07 PM PDT 24
Finished Aug 15 06:33:09 PM PDT 24
Peak memory 217020 kb
Host smart-e7a912c7-1812-4b1a-bf70-408e9e59d4a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065940887 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3065940887
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.737590524
Short name T179
Test name
Test status
Simulation time 20540369 ps
CPU time 1.14 seconds
Started Aug 15 06:33:10 PM PDT 24
Finished Aug 15 06:33:11 PM PDT 24
Peak memory 224076 kb
Host smart-9ec79808-9998-4d95-a6df-1d42493c5a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737590524 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.737590524
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.4259893487
Short name T650
Test name
Test status
Simulation time 47110155 ps
CPU time 1.23 seconds
Started Aug 15 06:33:04 PM PDT 24
Finished Aug 15 06:33:05 PM PDT 24
Peak memory 217680 kb
Host smart-2652638a-271d-4009-af27-24f37de9d908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259893487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.4259893487
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.2447078862
Short name T539
Test name
Test status
Simulation time 38574444 ps
CPU time 0.87 seconds
Started Aug 15 06:33:02 PM PDT 24
Finished Aug 15 06:33:04 PM PDT 24
Peak memory 215676 kb
Host smart-e49cf7df-5934-4a12-83f4-bc87ffeff77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447078862 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.2447078862
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.440385908
Short name T422
Test name
Test status
Simulation time 22623885 ps
CPU time 1.05 seconds
Started Aug 15 06:32:59 PM PDT 24
Finished Aug 15 06:33:00 PM PDT 24
Peak memory 215324 kb
Host smart-3c14ef72-2519-441e-bb4a-3f14333692b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440385908 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.440385908
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.1390502943
Short name T224
Test name
Test status
Simulation time 2646012345 ps
CPU time 35.52 seconds
Started Aug 15 06:33:00 PM PDT 24
Finished Aug 15 06:33:36 PM PDT 24
Peak memory 220816 kb
Host smart-c50bf5e4-dc10-4a80-8e92-544a374d1d57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390502943 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.1390502943
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.1164009652
Short name T935
Test name
Test status
Simulation time 359206533 ps
CPU time 1.46 seconds
Started Aug 15 06:33:06 PM PDT 24
Finished Aug 15 06:33:08 PM PDT 24
Peak memory 218516 kb
Host smart-c589af63-0ca0-4254-9eb4-2325e37cb6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164009652 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.1164009652
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.441139824
Short name T616
Test name
Test status
Simulation time 59832256 ps
CPU time 0.96 seconds
Started Aug 15 06:33:06 PM PDT 24
Finished Aug 15 06:33:07 PM PDT 24
Peak memory 206840 kb
Host smart-690f2f66-29e0-4166-b33d-27b5ef0935fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441139824 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.441139824
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.781502597
Short name T163
Test name
Test status
Simulation time 16937525 ps
CPU time 0.97 seconds
Started Aug 15 06:33:01 PM PDT 24
Finished Aug 15 06:33:02 PM PDT 24
Peak memory 215576 kb
Host smart-c4aa2f3c-3235-44cb-a722-d0e3c5f53eca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781502597 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.781502597
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.2986724785
Short name T120
Test name
Test status
Simulation time 272036183 ps
CPU time 1.16 seconds
Started Aug 15 06:33:09 PM PDT 24
Finished Aug 15 06:33:11 PM PDT 24
Peak memory 216768 kb
Host smart-424a8b02-f98c-4d9b-ba41-31a16c7dae4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986724785 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.2986724785
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.1653079581
Short name T723
Test name
Test status
Simulation time 34732527 ps
CPU time 1.25 seconds
Started Aug 15 06:33:02 PM PDT 24
Finished Aug 15 06:33:04 PM PDT 24
Peak memory 219588 kb
Host smart-3ded817a-b1e0-4a10-8d24-b444a669a0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653079581 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.1653079581
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.639174894
Short name T573
Test name
Test status
Simulation time 59773799 ps
CPU time 1.59 seconds
Started Aug 15 06:32:56 PM PDT 24
Finished Aug 15 06:32:58 PM PDT 24
Peak memory 218956 kb
Host smart-a1bb8017-0727-45bd-80fa-ab9bb52c2af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639174894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.639174894
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.1753039661
Short name T380
Test name
Test status
Simulation time 30038341 ps
CPU time 0.89 seconds
Started Aug 15 06:33:00 PM PDT 24
Finished Aug 15 06:33:01 PM PDT 24
Peak memory 215448 kb
Host smart-8a8d986c-c8e9-4e9f-ac78-69e175fcf69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753039661 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.1753039661
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.3854558394
Short name T410
Test name
Test status
Simulation time 15859926 ps
CPU time 1 seconds
Started Aug 15 06:33:09 PM PDT 24
Finished Aug 15 06:33:10 PM PDT 24
Peak memory 215368 kb
Host smart-e6c2aa57-b662-486e-8f12-7a841f255d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854558394 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.3854558394
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.2066340950
Short name T238
Test name
Test status
Simulation time 642368745 ps
CPU time 4.34 seconds
Started Aug 15 06:33:02 PM PDT 24
Finished Aug 15 06:33:07 PM PDT 24
Peak memory 220496 kb
Host smart-1c1a11f7-3873-424c-91c4-9df4837f639e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066340950 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.2066340950
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_alert.3584419299
Short name T867
Test name
Test status
Simulation time 44442018 ps
CPU time 1.17 seconds
Started Aug 15 06:32:58 PM PDT 24
Finished Aug 15 06:32:59 PM PDT 24
Peak memory 221388 kb
Host smart-1eb1e5e8-11c6-44e3-8078-6d8f4b96a69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584419299 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.3584419299
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.1882710669
Short name T792
Test name
Test status
Simulation time 50364121 ps
CPU time 1.07 seconds
Started Aug 15 06:33:02 PM PDT 24
Finished Aug 15 06:33:03 PM PDT 24
Peak memory 214988 kb
Host smart-cefd74f1-0960-49f9-bc4d-5560eee1dea3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882710669 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.1882710669
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.4142374932
Short name T669
Test name
Test status
Simulation time 22122973 ps
CPU time 0.92 seconds
Started Aug 15 06:33:15 PM PDT 24
Finished Aug 15 06:33:16 PM PDT 24
Peak memory 215376 kb
Host smart-c3b39e4e-a9db-4f4c-adb8-8b53898cb401
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142374932 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.4142374932
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_genbits.3537359359
Short name T294
Test name
Test status
Simulation time 58247675 ps
CPU time 1.14 seconds
Started Aug 15 06:33:00 PM PDT 24
Finished Aug 15 06:33:02 PM PDT 24
Peak memory 218904 kb
Host smart-d5b9cfef-2fcf-4046-89a1-ab98f6839b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537359359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3537359359
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.3500209493
Short name T384
Test name
Test status
Simulation time 21318392 ps
CPU time 1.07 seconds
Started Aug 15 06:33:14 PM PDT 24
Finished Aug 15 06:33:15 PM PDT 24
Peak memory 215696 kb
Host smart-de82579f-5c63-4462-a412-79d60a0e3171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500209493 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.3500209493
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.2234591743
Short name T826
Test name
Test status
Simulation time 38652961 ps
CPU time 1.01 seconds
Started Aug 15 06:33:01 PM PDT 24
Finished Aug 15 06:33:02 PM PDT 24
Peak memory 215364 kb
Host smart-b53e1746-fe91-4f20-891a-8dfca07c5fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234591743 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.2234591743
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.2124411172
Short name T821
Test name
Test status
Simulation time 344455276 ps
CPU time 1.47 seconds
Started Aug 15 06:33:08 PM PDT 24
Finished Aug 15 06:33:10 PM PDT 24
Peak memory 217364 kb
Host smart-20f8e198-cd9e-4605-9581-70aede175430
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124411172 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2124411172
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.4006940257
Short name T285
Test name
Test status
Simulation time 4143585556 ps
CPU time 103.96 seconds
Started Aug 15 06:33:10 PM PDT 24
Finished Aug 15 06:34:54 PM PDT 24
Peak memory 218392 kb
Host smart-b9329f04-308d-4903-8e6a-17e29926ae22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006940257 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.4006940257
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.591937082
Short name T829
Test name
Test status
Simulation time 26340580 ps
CPU time 1.32 seconds
Started Aug 15 06:33:15 PM PDT 24
Finished Aug 15 06:33:16 PM PDT 24
Peak memory 220076 kb
Host smart-649d45ec-3b1c-4817-b2d5-74e8dbe0b20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591937082 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.591937082
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.2404143993
Short name T485
Test name
Test status
Simulation time 211852983 ps
CPU time 0.92 seconds
Started Aug 15 06:33:05 PM PDT 24
Finished Aug 15 06:33:06 PM PDT 24
Peak memory 214956 kb
Host smart-fa912cd4-a531-4558-9c4d-a10c85d19974
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404143993 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2404143993
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.2264430528
Short name T174
Test name
Test status
Simulation time 12272961 ps
CPU time 0.9 seconds
Started Aug 15 06:33:12 PM PDT 24
Finished Aug 15 06:33:13 PM PDT 24
Peak memory 215568 kb
Host smart-917b1cce-3887-4a33-b2b8-20eb3a470c52
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264430528 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2264430528
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1449085409
Short name T463
Test name
Test status
Simulation time 71883384 ps
CPU time 1.04 seconds
Started Aug 15 06:33:10 PM PDT 24
Finished Aug 15 06:33:12 PM PDT 24
Peak memory 216864 kb
Host smart-b3d9604b-3d78-4890-a083-4013088ef10b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449085409 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1449085409
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.142028072
Short name T915
Test name
Test status
Simulation time 19695673 ps
CPU time 1.07 seconds
Started Aug 15 06:33:06 PM PDT 24
Finished Aug 15 06:33:07 PM PDT 24
Peak memory 218724 kb
Host smart-9b57aa58-517b-4949-8c6a-8657a2fe7e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142028072 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.142028072
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.2870555904
Short name T862
Test name
Test status
Simulation time 77117082 ps
CPU time 1.45 seconds
Started Aug 15 06:33:07 PM PDT 24
Finished Aug 15 06:33:09 PM PDT 24
Peak memory 219000 kb
Host smart-f2aafb72-bd70-45a8-b59b-543d7d82fe57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870555904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.2870555904
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.3150777355
Short name T586
Test name
Test status
Simulation time 28810214 ps
CPU time 0.83 seconds
Started Aug 15 06:33:11 PM PDT 24
Finished Aug 15 06:33:12 PM PDT 24
Peak memory 215716 kb
Host smart-97f9cf65-5123-4a46-9eb3-493f6b83f9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150777355 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3150777355
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.2967708318
Short name T581
Test name
Test status
Simulation time 87701531 ps
CPU time 0.87 seconds
Started Aug 15 06:33:09 PM PDT 24
Finished Aug 15 06:33:11 PM PDT 24
Peak memory 215388 kb
Host smart-2df392e0-5f6a-4d44-ba98-4a901c1d9524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967708318 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2967708318
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1468313658
Short name T379
Test name
Test status
Simulation time 204451642 ps
CPU time 4.33 seconds
Started Aug 15 06:33:09 PM PDT 24
Finished Aug 15 06:33:14 PM PDT 24
Peak memory 218516 kb
Host smart-4e3f2a34-02f2-48f4-a30b-3ff2f48261b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468313658 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1468313658
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.634336192
Short name T872
Test name
Test status
Simulation time 1979613430 ps
CPU time 16.29 seconds
Started Aug 15 06:33:14 PM PDT 24
Finished Aug 15 06:33:30 PM PDT 24
Peak memory 218908 kb
Host smart-99200bd0-95b7-4a85-b178-1204ea1d4ba3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634336192 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.634336192
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.3596856278
Short name T104
Test name
Test status
Simulation time 48651258 ps
CPU time 1.2 seconds
Started Aug 15 06:33:11 PM PDT 24
Finished Aug 15 06:33:12 PM PDT 24
Peak memory 219704 kb
Host smart-b5d27057-5b1f-4bb1-beca-dd29486ff6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596856278 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.3596856278
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.148597320
Short name T459
Test name
Test status
Simulation time 61062800 ps
CPU time 0.93 seconds
Started Aug 15 06:33:05 PM PDT 24
Finished Aug 15 06:33:06 PM PDT 24
Peak memory 206784 kb
Host smart-7a5229d7-1e88-4a5b-b71d-2f0d3d6c10da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148597320 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.148597320
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.3578534520
Short name T76
Test name
Test status
Simulation time 13793166 ps
CPU time 0.91 seconds
Started Aug 15 06:33:05 PM PDT 24
Finished Aug 15 06:33:06 PM PDT 24
Peak memory 215720 kb
Host smart-eccebb9f-8c39-40f3-b249-630bdaa36efd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578534520 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3578534520
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.1514378012
Short name T341
Test name
Test status
Simulation time 49161048 ps
CPU time 1.19 seconds
Started Aug 15 06:33:09 PM PDT 24
Finished Aug 15 06:33:10 PM PDT 24
Peak memory 217032 kb
Host smart-81308982-b974-40f4-a1b1-4e93192dc3bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514378012 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.1514378012
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.1534342837
Short name T532
Test name
Test status
Simulation time 22714072 ps
CPU time 1.03 seconds
Started Aug 15 06:33:04 PM PDT 24
Finished Aug 15 06:33:05 PM PDT 24
Peak memory 229660 kb
Host smart-f32909c3-e296-4c4c-ba73-dab53d87cfef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534342837 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1534342837
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.353993380
Short name T81
Test name
Test status
Simulation time 64740060 ps
CPU time 1.18 seconds
Started Aug 15 06:33:14 PM PDT 24
Finished Aug 15 06:33:16 PM PDT 24
Peak memory 220452 kb
Host smart-6beb74df-4c8d-47fe-a1f3-6da230389052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353993380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.353993380
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3705463739
Short name T389
Test name
Test status
Simulation time 37020723 ps
CPU time 0.86 seconds
Started Aug 15 06:33:10 PM PDT 24
Finished Aug 15 06:33:11 PM PDT 24
Peak memory 215400 kb
Host smart-569cd9f7-4a8d-4e0b-98bd-a65a73a3f940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705463739 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3705463739
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.2521429780
Short name T548
Test name
Test status
Simulation time 20165750 ps
CPU time 1.02 seconds
Started Aug 15 06:33:14 PM PDT 24
Finished Aug 15 06:33:15 PM PDT 24
Peak memory 215364 kb
Host smart-1aefac8d-9804-4f94-8b13-bb3402cfa594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521429780 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.2521429780
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.3953154318
Short name T358
Test name
Test status
Simulation time 869770844 ps
CPU time 4.75 seconds
Started Aug 15 06:33:09 PM PDT 24
Finished Aug 15 06:33:14 PM PDT 24
Peak memory 217128 kb
Host smart-bc2c4e71-b6b3-4ab9-bd60-9e838b1cfde9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953154318 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.3953154318
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.80835541
Short name T223
Test name
Test status
Simulation time 12825940016 ps
CPU time 93.01 seconds
Started Aug 15 06:33:14 PM PDT 24
Finished Aug 15 06:34:48 PM PDT 24
Peak memory 218168 kb
Host smart-38e5ca59-324b-44a0-baf0-8bed7b2a7ca2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80835541 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.80835541
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2872417249
Short name T936
Test name
Test status
Simulation time 43936081 ps
CPU time 1.08 seconds
Started Aug 15 06:33:03 PM PDT 24
Finished Aug 15 06:33:04 PM PDT 24
Peak memory 218756 kb
Host smart-841e1d2c-7b06-469e-8683-6f251ff4b266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872417249 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2872417249
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.1409715115
Short name T737
Test name
Test status
Simulation time 16334393 ps
CPU time 1.08 seconds
Started Aug 15 06:33:10 PM PDT 24
Finished Aug 15 06:33:12 PM PDT 24
Peak memory 206828 kb
Host smart-b2f0be4f-af88-4c6f-a861-0d8b6c30a581
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409715115 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1409715115
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.1938893337
Short name T626
Test name
Test status
Simulation time 12727778 ps
CPU time 0.9 seconds
Started Aug 15 06:33:05 PM PDT 24
Finished Aug 15 06:33:07 PM PDT 24
Peak memory 215592 kb
Host smart-cf32c71c-2a9f-4502-be34-6d59f9be1cf7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938893337 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1938893337
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.521676613
Short name T210
Test name
Test status
Simulation time 51858917 ps
CPU time 1.13 seconds
Started Aug 15 06:33:15 PM PDT 24
Finished Aug 15 06:33:16 PM PDT 24
Peak memory 217000 kb
Host smart-2fe34430-ea4f-4926-a979-6276806caf75
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521676613 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_di
sable_auto_req_mode.521676613
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.1792782952
Short name T852
Test name
Test status
Simulation time 28957756 ps
CPU time 0.87 seconds
Started Aug 15 06:33:12 PM PDT 24
Finished Aug 15 06:33:13 PM PDT 24
Peak memory 218328 kb
Host smart-06e8d213-43a1-4086-8ab0-be75ba2b3419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792782952 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.1792782952
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3539661854
Short name T292
Test name
Test status
Simulation time 93589390 ps
CPU time 1.4 seconds
Started Aug 15 06:33:06 PM PDT 24
Finished Aug 15 06:33:08 PM PDT 24
Peak memory 219020 kb
Host smart-e3633b71-b91c-4e8e-aaa2-3aa621b33fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539661854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3539661854
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.4133940690
Short name T112
Test name
Test status
Simulation time 24613503 ps
CPU time 0.96 seconds
Started Aug 15 06:33:12 PM PDT 24
Finished Aug 15 06:33:13 PM PDT 24
Peak memory 215860 kb
Host smart-c549ad10-c5da-4173-bedb-8e5d85099982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133940690 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.4133940690
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.232614853
Short name T395
Test name
Test status
Simulation time 107422026 ps
CPU time 0.89 seconds
Started Aug 15 06:33:10 PM PDT 24
Finished Aug 15 06:33:11 PM PDT 24
Peak memory 215324 kb
Host smart-163a13d3-8b6d-4e2a-817a-da20249128ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232614853 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.232614853
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.583493607
Short name T198
Test name
Test status
Simulation time 247894009 ps
CPU time 4.88 seconds
Started Aug 15 06:33:15 PM PDT 24
Finished Aug 15 06:33:20 PM PDT 24
Peak memory 215332 kb
Host smart-c003e5ee-d054-471d-89a9-780bcbe9bbb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583493607 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.583493607
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_alert.2413517184
Short name T307
Test name
Test status
Simulation time 55557198 ps
CPU time 1.25 seconds
Started Aug 15 06:33:14 PM PDT 24
Finished Aug 15 06:33:16 PM PDT 24
Peak memory 215748 kb
Host smart-60280bf1-1a2d-4c2c-97c5-8ce83d446302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413517184 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2413517184
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1571600639
Short name T894
Test name
Test status
Simulation time 56024510 ps
CPU time 0.84 seconds
Started Aug 15 06:33:16 PM PDT 24
Finished Aug 15 06:33:17 PM PDT 24
Peak memory 214812 kb
Host smart-90e5752f-5a41-4a27-936f-375e2ad2a232
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571600639 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1571600639
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.959411009
Short name T796
Test name
Test status
Simulation time 49815029 ps
CPU time 0.92 seconds
Started Aug 15 06:33:12 PM PDT 24
Finished Aug 15 06:33:13 PM PDT 24
Peak memory 215436 kb
Host smart-5c82e9a6-5b28-4017-bb01-1c5e32afed7f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959411009 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.959411009
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.3001338491
Short name T330
Test name
Test status
Simulation time 46309425 ps
CPU time 1.32 seconds
Started Aug 15 06:33:05 PM PDT 24
Finished Aug 15 06:33:07 PM PDT 24
Peak memory 216916 kb
Host smart-24c03a0e-730c-4ac4-b1d2-b0d215bda360
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001338491 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.3001338491
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.4070630637
Short name T155
Test name
Test status
Simulation time 18993109 ps
CPU time 1.18 seconds
Started Aug 15 06:33:12 PM PDT 24
Finished Aug 15 06:33:13 PM PDT 24
Peak memory 224116 kb
Host smart-4f3f3314-b647-4b4e-8beb-6784554a6395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070630637 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.4070630637
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.2089012995
Short name T637
Test name
Test status
Simulation time 61517923 ps
CPU time 1.25 seconds
Started Aug 15 06:33:08 PM PDT 24
Finished Aug 15 06:33:09 PM PDT 24
Peak memory 218984 kb
Host smart-773fe9f1-b376-4dc0-a4eb-52ec250f132f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089012995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.2089012995
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.615511422
Short name T866
Test name
Test status
Simulation time 26426909 ps
CPU time 0.97 seconds
Started Aug 15 06:33:05 PM PDT 24
Finished Aug 15 06:33:07 PM PDT 24
Peak memory 215432 kb
Host smart-7501e651-f390-4f91-a164-9bc35c12ee27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615511422 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.615511422
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.3656249340
Short name T83
Test name
Test status
Simulation time 74728827 ps
CPU time 0.88 seconds
Started Aug 15 06:33:14 PM PDT 24
Finished Aug 15 06:33:15 PM PDT 24
Peak memory 215324 kb
Host smart-c43daf8f-7963-46ee-b0ed-4af65687610a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656249340 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3656249340
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1297007575
Short name T851
Test name
Test status
Simulation time 560295021 ps
CPU time 5.84 seconds
Started Aug 15 06:33:15 PM PDT 24
Finished Aug 15 06:33:21 PM PDT 24
Peak memory 217260 kb
Host smart-43b5422d-4973-458a-b3d1-4a296bb4ea27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297007575 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1297007575
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_alert.3719019943
Short name T563
Test name
Test status
Simulation time 46389159 ps
CPU time 1.13 seconds
Started Aug 15 06:33:14 PM PDT 24
Finished Aug 15 06:33:15 PM PDT 24
Peak memory 219916 kb
Host smart-21555ed0-e7c1-45ff-8208-52c3a1c4c7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719019943 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.3719019943
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.4162901435
Short name T401
Test name
Test status
Simulation time 65827944 ps
CPU time 0.89 seconds
Started Aug 15 06:33:12 PM PDT 24
Finished Aug 15 06:33:13 PM PDT 24
Peak memory 206812 kb
Host smart-1aa0284f-25bf-4a9c-ac75-125c09d1e1cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162901435 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.4162901435
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.1240473703
Short name T377
Test name
Test status
Simulation time 11073336 ps
CPU time 0.88 seconds
Started Aug 15 06:33:12 PM PDT 24
Finished Aug 15 06:33:13 PM PDT 24
Peak memory 215456 kb
Host smart-d455b4d8-99ff-4a48-88e7-00c74a57e379
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240473703 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.1240473703
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_err.2882539110
Short name T655
Test name
Test status
Simulation time 25786658 ps
CPU time 0.87 seconds
Started Aug 15 06:33:12 PM PDT 24
Finished Aug 15 06:33:13 PM PDT 24
Peak memory 218232 kb
Host smart-3a0ce169-9579-4f61-99b5-744e2746ae9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882539110 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.2882539110
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.1800456411
Short name T70
Test name
Test status
Simulation time 222828136 ps
CPU time 1.36 seconds
Started Aug 15 06:33:11 PM PDT 24
Finished Aug 15 06:33:13 PM PDT 24
Peak memory 220364 kb
Host smart-0c195d96-c11b-4f4f-83ec-965a29749922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800456411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1800456411
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.2011663948
Short name T444
Test name
Test status
Simulation time 39126515 ps
CPU time 1.04 seconds
Started Aug 15 06:33:14 PM PDT 24
Finished Aug 15 06:33:15 PM PDT 24
Peak memory 224120 kb
Host smart-80062f44-473a-4b77-b5ae-86cbbe1bf54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011663948 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2011663948
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.1809282011
Short name T413
Test name
Test status
Simulation time 65528263 ps
CPU time 0.94 seconds
Started Aug 15 06:33:16 PM PDT 24
Finished Aug 15 06:33:17 PM PDT 24
Peak memory 215376 kb
Host smart-34d10d3c-69ba-4a97-8c59-43e12429d92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809282011 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.1809282011
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2604514017
Short name T697
Test name
Test status
Simulation time 324090460 ps
CPU time 3.43 seconds
Started Aug 15 06:33:10 PM PDT 24
Finished Aug 15 06:33:14 PM PDT 24
Peak memory 215432 kb
Host smart-a073ecac-b3f5-4f81-93e9-027aa253f99c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604514017 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2604514017
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.354706029
Short name T441
Test name
Test status
Simulation time 12090739339 ps
CPU time 74.06 seconds
Started Aug 15 06:33:06 PM PDT 24
Finished Aug 15 06:34:20 PM PDT 24
Peak memory 221564 kb
Host smart-e8f202dc-78d8-4858-a16d-1831f35f5cd5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354706029 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.354706029
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.1846736619
Short name T575
Test name
Test status
Simulation time 26924801 ps
CPU time 1.22 seconds
Started Aug 15 06:32:04 PM PDT 24
Finished Aug 15 06:32:06 PM PDT 24
Peak memory 215740 kb
Host smart-fd149fe3-158b-4bdf-8186-2b188b63aca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846736619 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1846736619
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.3627233432
Short name T724
Test name
Test status
Simulation time 14666708 ps
CPU time 0.91 seconds
Started Aug 15 06:32:10 PM PDT 24
Finished Aug 15 06:32:11 PM PDT 24
Peak memory 214980 kb
Host smart-8ca36847-f7f9-42a2-abd7-ed4faa8a93fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627233432 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3627233432
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.1678759218
Short name T788
Test name
Test status
Simulation time 64643199 ps
CPU time 0.9 seconds
Started Aug 15 06:32:07 PM PDT 24
Finished Aug 15 06:32:08 PM PDT 24
Peak memory 215404 kb
Host smart-5a287670-5c8e-4391-84b8-474ed9eec268
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678759218 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1678759218
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.4029403364
Short name T569
Test name
Test status
Simulation time 170807502 ps
CPU time 1.04 seconds
Started Aug 15 06:32:08 PM PDT 24
Finished Aug 15 06:32:09 PM PDT 24
Peak memory 217016 kb
Host smart-e8fbf813-dab3-42ec-b8e9-518cb8770065
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029403364 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.4029403364
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.2299577957
Short name T92
Test name
Test status
Simulation time 30993300 ps
CPU time 0.91 seconds
Started Aug 15 06:32:13 PM PDT 24
Finished Aug 15 06:32:14 PM PDT 24
Peak memory 218452 kb
Host smart-4f9a63e7-b420-4615-b1d9-c1175d6b2c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299577957 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.2299577957
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.3480035917
Short name T958
Test name
Test status
Simulation time 25824452 ps
CPU time 1.32 seconds
Started Aug 15 06:32:10 PM PDT 24
Finished Aug 15 06:32:11 PM PDT 24
Peak memory 217372 kb
Host smart-2a5074b7-4323-4e1a-a202-729f15dfb470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480035917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3480035917
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.1703229227
Short name T428
Test name
Test status
Simulation time 20724550 ps
CPU time 1.08 seconds
Started Aug 15 06:32:08 PM PDT 24
Finished Aug 15 06:32:09 PM PDT 24
Peak memory 215468 kb
Host smart-49fadf40-96c0-46bf-9c1a-35a11a0af1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703229227 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1703229227
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.2436873645
Short name T810
Test name
Test status
Simulation time 22082963 ps
CPU time 0.97 seconds
Started Aug 15 06:32:08 PM PDT 24
Finished Aug 15 06:32:09 PM PDT 24
Peak memory 207140 kb
Host smart-9d04a422-553b-4390-bae1-710719063cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436873645 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2436873645
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.3490759122
Short name T345
Test name
Test status
Simulation time 25654871 ps
CPU time 0.94 seconds
Started Aug 15 06:32:07 PM PDT 24
Finished Aug 15 06:32:08 PM PDT 24
Peak memory 215360 kb
Host smart-d585f1e8-eac3-429f-806d-a7d152920f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490759122 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.3490759122
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.138936558
Short name T847
Test name
Test status
Simulation time 463923912 ps
CPU time 3.02 seconds
Started Aug 15 06:32:07 PM PDT 24
Finished Aug 15 06:32:10 PM PDT 24
Peak memory 217100 kb
Host smart-9482b5a9-c810-470e-922c-861df5441524
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138936558 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.138936558
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/50.edn_alert.1773690289
Short name T483
Test name
Test status
Simulation time 35088030 ps
CPU time 1.13 seconds
Started Aug 15 06:33:13 PM PDT 24
Finished Aug 15 06:33:14 PM PDT 24
Peak memory 218848 kb
Host smart-c8700037-102d-47d3-ae7a-019081b4f3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773690289 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.1773690289
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.2922377399
Short name T86
Test name
Test status
Simulation time 20122982 ps
CPU time 1.11 seconds
Started Aug 15 06:33:20 PM PDT 24
Finished Aug 15 06:33:22 PM PDT 24
Peak memory 219824 kb
Host smart-d7911149-b437-4e3d-831b-faf453ac6a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922377399 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.2922377399
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.4230043915
Short name T499
Test name
Test status
Simulation time 58768669 ps
CPU time 1.2 seconds
Started Aug 15 06:33:19 PM PDT 24
Finished Aug 15 06:33:20 PM PDT 24
Peak memory 219880 kb
Host smart-555d554a-7fdc-4d1a-a258-fe583a4de033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230043915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.4230043915
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.768390913
Short name T170
Test name
Test status
Simulation time 81881909 ps
CPU time 1.11 seconds
Started Aug 15 06:33:13 PM PDT 24
Finished Aug 15 06:33:15 PM PDT 24
Peak memory 218516 kb
Host smart-d8ecc919-f61c-43d5-9aa5-3f0aa856125f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768390913 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.768390913
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.873873779
Short name T5
Test name
Test status
Simulation time 33690573 ps
CPU time 0.99 seconds
Started Aug 15 06:33:13 PM PDT 24
Finished Aug 15 06:33:15 PM PDT 24
Peak memory 223896 kb
Host smart-a3fbe91e-4946-4046-beaf-3b7b657c4e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873873779 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.873873779
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.2876309620
Short name T453
Test name
Test status
Simulation time 45834470 ps
CPU time 1.71 seconds
Started Aug 15 06:33:20 PM PDT 24
Finished Aug 15 06:33:22 PM PDT 24
Peak memory 218516 kb
Host smart-3722ed2c-3572-474f-8ee9-a5ba1eb46429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876309620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2876309620
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.111322241
Short name T219
Test name
Test status
Simulation time 78657797 ps
CPU time 1.3 seconds
Started Aug 15 06:33:14 PM PDT 24
Finished Aug 15 06:33:15 PM PDT 24
Peak memory 220208 kb
Host smart-a3d1076a-6922-44c1-9563-af29f60bbf73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111322241 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.111322241
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.4016935686
Short name T731
Test name
Test status
Simulation time 37506867 ps
CPU time 1.03 seconds
Started Aug 15 06:33:14 PM PDT 24
Finished Aug 15 06:33:15 PM PDT 24
Peak memory 223976 kb
Host smart-d6b5439d-249e-4464-ac72-31efd9c31ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016935686 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.4016935686
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.3145888211
Short name T492
Test name
Test status
Simulation time 188762250 ps
CPU time 1.14 seconds
Started Aug 15 06:33:11 PM PDT 24
Finished Aug 15 06:33:12 PM PDT 24
Peak memory 217436 kb
Host smart-9e940554-7bd8-4605-aca7-49640f050570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145888211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3145888211
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.1610144428
Short name T161
Test name
Test status
Simulation time 86225158 ps
CPU time 1.13 seconds
Started Aug 15 06:33:13 PM PDT 24
Finished Aug 15 06:33:14 PM PDT 24
Peak memory 220036 kb
Host smart-ef2178f5-207c-4114-8fe2-c982d7643bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610144428 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.1610144428
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.4149551086
Short name T602
Test name
Test status
Simulation time 25497816 ps
CPU time 0.95 seconds
Started Aug 15 06:33:12 PM PDT 24
Finished Aug 15 06:33:13 PM PDT 24
Peak memory 219348 kb
Host smart-ef5c3450-82c6-4342-b7fa-6aec0e6fd1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149551086 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.4149551086
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.2674564516
Short name T310
Test name
Test status
Simulation time 46104506 ps
CPU time 1.48 seconds
Started Aug 15 06:33:12 PM PDT 24
Finished Aug 15 06:33:14 PM PDT 24
Peak memory 219720 kb
Host smart-f64b1cf7-ca0e-467f-976b-d5e8ea82d422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674564516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.2674564516
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.1936993615
Short name T508
Test name
Test status
Simulation time 25213703 ps
CPU time 1.14 seconds
Started Aug 15 06:33:20 PM PDT 24
Finished Aug 15 06:33:21 PM PDT 24
Peak memory 218700 kb
Host smart-bff7d148-a540-4e2c-80d6-e2b93487eb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936993615 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.1936993615
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.862095490
Short name T158
Test name
Test status
Simulation time 63096405 ps
CPU time 0.87 seconds
Started Aug 15 06:33:19 PM PDT 24
Finished Aug 15 06:33:21 PM PDT 24
Peak memory 218352 kb
Host smart-f0e53e92-4194-4d40-a10a-d7a5302774be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862095490 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.862095490
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.2585905674
Short name T48
Test name
Test status
Simulation time 56673096 ps
CPU time 1.53 seconds
Started Aug 15 06:33:19 PM PDT 24
Finished Aug 15 06:33:21 PM PDT 24
Peak memory 215404 kb
Host smart-15413331-36f3-4046-aaf1-efb8feabb427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585905674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2585905674
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.1620951769
Short name T524
Test name
Test status
Simulation time 47112049 ps
CPU time 1.18 seconds
Started Aug 15 06:33:16 PM PDT 24
Finished Aug 15 06:33:17 PM PDT 24
Peak memory 219876 kb
Host smart-8464b50f-bd43-4d0f-b2ac-86a7b274d843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620951769 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.1620951769
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.1552483076
Short name T822
Test name
Test status
Simulation time 35810611 ps
CPU time 1.31 seconds
Started Aug 15 06:33:20 PM PDT 24
Finished Aug 15 06:33:22 PM PDT 24
Peak memory 225864 kb
Host smart-4437d275-a9ed-4741-9a29-51a5c6ea136d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552483076 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.1552483076
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.465241917
Short name T449
Test name
Test status
Simulation time 98203166 ps
CPU time 1.21 seconds
Started Aug 15 06:33:18 PM PDT 24
Finished Aug 15 06:33:19 PM PDT 24
Peak memory 219492 kb
Host smart-e7643c80-f2e6-4a85-8b86-9a920ee6482e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465241917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.465241917
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.2204413814
Short name T176
Test name
Test status
Simulation time 71182947 ps
CPU time 1.09 seconds
Started Aug 15 06:33:16 PM PDT 24
Finished Aug 15 06:33:18 PM PDT 24
Peak memory 219820 kb
Host smart-791340a5-10fa-4635-86ed-410e8fdafa02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204413814 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.2204413814
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.809529659
Short name T165
Test name
Test status
Simulation time 34438281 ps
CPU time 0.87 seconds
Started Aug 15 06:33:21 PM PDT 24
Finished Aug 15 06:33:22 PM PDT 24
Peak memory 218360 kb
Host smart-9c682545-e665-425c-a5aa-da96c3bb1a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809529659 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.809529659
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.2281474244
Short name T522
Test name
Test status
Simulation time 51655031 ps
CPU time 1.63 seconds
Started Aug 15 06:33:18 PM PDT 24
Finished Aug 15 06:33:20 PM PDT 24
Peak memory 219644 kb
Host smart-e4108601-3f76-452a-8bd7-9df717fd6c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281474244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2281474244
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.1186985459
Short name T946
Test name
Test status
Simulation time 62449936 ps
CPU time 1.17 seconds
Started Aug 15 06:33:18 PM PDT 24
Finished Aug 15 06:33:19 PM PDT 24
Peak memory 218848 kb
Host smart-9b2f72ff-67d2-44f5-9f79-3c9ca1cb453b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186985459 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.1186985459
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.1817036111
Short name T834
Test name
Test status
Simulation time 24617603 ps
CPU time 0.96 seconds
Started Aug 15 06:33:17 PM PDT 24
Finished Aug 15 06:33:18 PM PDT 24
Peak memory 218756 kb
Host smart-76367f70-4895-4e7a-8e90-5c7a93e9006d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817036111 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.1817036111
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.1083295177
Short name T346
Test name
Test status
Simulation time 88175133 ps
CPU time 1.31 seconds
Started Aug 15 06:33:21 PM PDT 24
Finished Aug 15 06:33:23 PM PDT 24
Peak memory 217224 kb
Host smart-1dd186f1-26e9-47ab-929a-fbbf3d12b7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083295177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.1083295177
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.977290475
Short name T920
Test name
Test status
Simulation time 26116175 ps
CPU time 1.08 seconds
Started Aug 15 06:33:17 PM PDT 24
Finished Aug 15 06:33:18 PM PDT 24
Peak memory 218768 kb
Host smart-e7fb9de9-262d-4732-98c1-b5e547d60321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977290475 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.977290475
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.3941638332
Short name T101
Test name
Test status
Simulation time 28494724 ps
CPU time 0.88 seconds
Started Aug 15 06:33:14 PM PDT 24
Finished Aug 15 06:33:15 PM PDT 24
Peak memory 218408 kb
Host smart-87161c8a-8c43-4699-9de9-f9aecb1c6f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941638332 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.3941638332
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.1457131519
Short name T848
Test name
Test status
Simulation time 106154525 ps
CPU time 1.09 seconds
Started Aug 15 06:33:24 PM PDT 24
Finished Aug 15 06:33:25 PM PDT 24
Peak memory 218564 kb
Host smart-dd4a8462-930b-48ad-b52d-30835235d07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457131519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1457131519
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.1228226063
Short name T357
Test name
Test status
Simulation time 38863377 ps
CPU time 1.11 seconds
Started Aug 15 06:33:16 PM PDT 24
Finished Aug 15 06:33:17 PM PDT 24
Peak memory 218680 kb
Host smart-39dfab51-9518-4b8c-b280-bf2e459c7ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228226063 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.1228226063
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.2788941715
Short name T607
Test name
Test status
Simulation time 25131586 ps
CPU time 0.86 seconds
Started Aug 15 06:33:19 PM PDT 24
Finished Aug 15 06:33:20 PM PDT 24
Peak memory 218436 kb
Host smart-b9ed6c74-78cb-4e9f-b06f-cce4bae85b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788941715 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.2788941715
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.4079572527
Short name T288
Test name
Test status
Simulation time 102811873 ps
CPU time 1.48 seconds
Started Aug 15 06:33:13 PM PDT 24
Finished Aug 15 06:33:15 PM PDT 24
Peak memory 219100 kb
Host smart-aab84226-0fd5-4ab2-a186-fbca92a43844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079572527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.4079572527
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.4174745544
Short name T660
Test name
Test status
Simulation time 36479613 ps
CPU time 1.42 seconds
Started Aug 15 06:32:08 PM PDT 24
Finished Aug 15 06:32:09 PM PDT 24
Peak memory 215744 kb
Host smart-b87743c1-572b-4a52-87ef-9a2d4cabefa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174745544 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.4174745544
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3438930397
Short name T439
Test name
Test status
Simulation time 37560956 ps
CPU time 0.83 seconds
Started Aug 15 06:32:08 PM PDT 24
Finished Aug 15 06:32:09 PM PDT 24
Peak memory 206568 kb
Host smart-5b116d83-5d43-4ac1-a4f4-3c16c74297fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438930397 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3438930397
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.2053085632
Short name T752
Test name
Test status
Simulation time 144936697 ps
CPU time 0.82 seconds
Started Aug 15 06:32:04 PM PDT 24
Finished Aug 15 06:32:05 PM PDT 24
Peak memory 215376 kb
Host smart-1fae1736-61a2-4ca8-8032-0cc04f793eac
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053085632 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2053085632
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.3099382165
Short name T143
Test name
Test status
Simulation time 42436179 ps
CPU time 1.39 seconds
Started Aug 15 06:32:08 PM PDT 24
Finished Aug 15 06:32:10 PM PDT 24
Peak memory 216848 kb
Host smart-56395b70-d85e-4336-a1e3-aac67f8458b0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099382165 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.3099382165
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.1809597764
Short name T496
Test name
Test status
Simulation time 33824217 ps
CPU time 0.9 seconds
Started Aug 15 06:32:08 PM PDT 24
Finished Aug 15 06:32:09 PM PDT 24
Peak memory 219468 kb
Host smart-861cf219-5acd-4939-9207-262fe80e2b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809597764 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1809597764
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.851946232
Short name T500
Test name
Test status
Simulation time 52888959 ps
CPU time 1.4 seconds
Started Aug 15 06:32:05 PM PDT 24
Finished Aug 15 06:32:07 PM PDT 24
Peak memory 219876 kb
Host smart-7959e638-a627-4cdc-a28b-d692cb2833a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851946232 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.851946232
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.1271019211
Short name T627
Test name
Test status
Simulation time 28706021 ps
CPU time 1.02 seconds
Started Aug 15 06:32:09 PM PDT 24
Finished Aug 15 06:32:10 PM PDT 24
Peak memory 224208 kb
Host smart-c6301145-6bfb-474e-ad73-21c55e847898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271019211 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.1271019211
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.811196348
Short name T290
Test name
Test status
Simulation time 18254551 ps
CPU time 1.08 seconds
Started Aug 15 06:32:10 PM PDT 24
Finished Aug 15 06:32:11 PM PDT 24
Peak memory 207152 kb
Host smart-3ff1e072-1908-4605-8468-8b88b298d38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811196348 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.811196348
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.3603788521
Short name T418
Test name
Test status
Simulation time 35679954 ps
CPU time 0.92 seconds
Started Aug 15 06:32:04 PM PDT 24
Finished Aug 15 06:32:05 PM PDT 24
Peak memory 215404 kb
Host smart-10463c0e-f8e2-412b-9d0f-949f17652c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603788521 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.3603788521
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.713798730
Short name T763
Test name
Test status
Simulation time 24493971 ps
CPU time 1.08 seconds
Started Aug 15 06:32:08 PM PDT 24
Finished Aug 15 06:32:09 PM PDT 24
Peak memory 215384 kb
Host smart-04b0b5ee-0592-4f3a-a089-c65ea47ce6c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713798730 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.713798730
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1177147920
Short name T234
Test name
Test status
Simulation time 3665854876 ps
CPU time 44.86 seconds
Started Aug 15 06:32:07 PM PDT 24
Finished Aug 15 06:32:52 PM PDT 24
Peak memory 221136 kb
Host smart-24058ad8-8b27-41c8-8a84-2930402ab356
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177147920 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1177147920
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.961513163
Short name T860
Test name
Test status
Simulation time 28131443 ps
CPU time 1.1 seconds
Started Aug 15 06:33:15 PM PDT 24
Finished Aug 15 06:33:17 PM PDT 24
Peak memory 220036 kb
Host smart-5813b08e-9a9a-44d8-8194-49a11ca7720b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961513163 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.961513163
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.3909250119
Short name T199
Test name
Test status
Simulation time 20684761 ps
CPU time 1.11 seconds
Started Aug 15 06:33:13 PM PDT 24
Finished Aug 15 06:33:15 PM PDT 24
Peak memory 219912 kb
Host smart-5824e490-2722-44b1-944f-78f7e07e78e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909250119 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3909250119
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.3571574969
Short name T761
Test name
Test status
Simulation time 44635361 ps
CPU time 1.2 seconds
Started Aug 15 06:33:23 PM PDT 24
Finished Aug 15 06:33:25 PM PDT 24
Peak memory 217408 kb
Host smart-f9b25081-7653-40fd-806c-15389e570b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571574969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3571574969
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.1632102398
Short name T910
Test name
Test status
Simulation time 25712510 ps
CPU time 1.24 seconds
Started Aug 15 06:33:16 PM PDT 24
Finished Aug 15 06:33:17 PM PDT 24
Peak memory 219664 kb
Host smart-50d5f538-3c35-4425-99b7-469bf1a7f821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632102398 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.1632102398
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.2829597222
Short name T551
Test name
Test status
Simulation time 34319768 ps
CPU time 1.11 seconds
Started Aug 15 06:33:19 PM PDT 24
Finished Aug 15 06:33:20 PM PDT 24
Peak memory 218508 kb
Host smart-fae13507-d219-49f1-81d8-d7d1f866fb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829597222 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.2829597222
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.746248531
Short name T340
Test name
Test status
Simulation time 82968354 ps
CPU time 1.71 seconds
Started Aug 15 06:33:20 PM PDT 24
Finished Aug 15 06:33:22 PM PDT 24
Peak memory 219688 kb
Host smart-862e6019-4a6e-4839-ac3d-09aecf2651a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746248531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.746248531
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.4110513814
Short name T423
Test name
Test status
Simulation time 81708508 ps
CPU time 1.18 seconds
Started Aug 15 06:33:16 PM PDT 24
Finished Aug 15 06:33:17 PM PDT 24
Peak memory 220940 kb
Host smart-ad73c7ad-ff79-4c96-8262-2bae06935e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110513814 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.4110513814
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.615386159
Short name T884
Test name
Test status
Simulation time 36352665 ps
CPU time 0.91 seconds
Started Aug 15 06:33:19 PM PDT 24
Finished Aug 15 06:33:21 PM PDT 24
Peak memory 219308 kb
Host smart-550e5ea1-55ae-4c7f-a899-19cd2ff5a8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615386159 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.615386159
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.2910848994
Short name T530
Test name
Test status
Simulation time 47950739 ps
CPU time 1.06 seconds
Started Aug 15 06:33:19 PM PDT 24
Finished Aug 15 06:33:20 PM PDT 24
Peak memory 219152 kb
Host smart-537606fe-e6c4-4388-aed8-6d0e9ac0144e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910848994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2910848994
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.2165092813
Short name T771
Test name
Test status
Simulation time 63677879 ps
CPU time 1.08 seconds
Started Aug 15 06:33:22 PM PDT 24
Finished Aug 15 06:33:23 PM PDT 24
Peak memory 218872 kb
Host smart-ad75dc4c-a715-4785-8147-c237b44b98f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165092813 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.2165092813
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.3626413628
Short name T953
Test name
Test status
Simulation time 33917383 ps
CPU time 0.86 seconds
Started Aug 15 06:33:26 PM PDT 24
Finished Aug 15 06:33:28 PM PDT 24
Peak memory 218364 kb
Host smart-bbbf32ef-f97f-4941-b6da-26543094f658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626413628 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.3626413628
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.1695139633
Short name T498
Test name
Test status
Simulation time 74729869 ps
CPU time 2.58 seconds
Started Aug 15 06:33:20 PM PDT 24
Finished Aug 15 06:33:23 PM PDT 24
Peak memory 218672 kb
Host smart-8dd78cb2-dc78-4708-bf59-53009c79226b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695139633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.1695139633
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.2038875421
Short name T633
Test name
Test status
Simulation time 86480121 ps
CPU time 1.24 seconds
Started Aug 15 06:33:26 PM PDT 24
Finished Aug 15 06:33:28 PM PDT 24
Peak memory 219628 kb
Host smart-2f7eef77-aef5-4cbb-8652-6a3223ea7ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038875421 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.2038875421
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.3203850116
Short name T66
Test name
Test status
Simulation time 18511363 ps
CPU time 1.04 seconds
Started Aug 15 06:33:25 PM PDT 24
Finished Aug 15 06:33:26 PM PDT 24
Peak memory 218528 kb
Host smart-a25d3d31-6752-40ae-b4cf-62d912e53d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203850116 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.3203850116
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.2260501223
Short name T934
Test name
Test status
Simulation time 64112330 ps
CPU time 2.28 seconds
Started Aug 15 06:33:24 PM PDT 24
Finished Aug 15 06:33:27 PM PDT 24
Peak memory 220656 kb
Host smart-0dbde61a-6223-49c6-8133-a7a4bcc84036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260501223 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2260501223
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.3149007182
Short name T632
Test name
Test status
Simulation time 22804519 ps
CPU time 1.13 seconds
Started Aug 15 06:33:25 PM PDT 24
Finished Aug 15 06:33:27 PM PDT 24
Peak memory 219668 kb
Host smart-caf1a796-ed13-4fb5-b2cc-eb2f5bc6a4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149007182 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.3149007182
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.2374594644
Short name T135
Test name
Test status
Simulation time 58449547 ps
CPU time 1.11 seconds
Started Aug 15 06:33:30 PM PDT 24
Finished Aug 15 06:33:31 PM PDT 24
Peak memory 229732 kb
Host smart-0a329976-b047-46a2-a8ab-ea017ab026ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374594644 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.2374594644
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.2850455097
Short name T26
Test name
Test status
Simulation time 193241830 ps
CPU time 1.36 seconds
Started Aug 15 06:33:27 PM PDT 24
Finished Aug 15 06:33:29 PM PDT 24
Peak memory 217516 kb
Host smart-6146c8c0-0b12-47fd-a012-e67fde4a6733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850455097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.2850455097
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.2063929108
Short name T393
Test name
Test status
Simulation time 263973639 ps
CPU time 1.44 seconds
Started Aug 15 06:33:25 PM PDT 24
Finished Aug 15 06:33:27 PM PDT 24
Peak memory 220804 kb
Host smart-51b322d8-5a41-48b1-a666-522700364823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063929108 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.2063929108
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.2148355864
Short name T193
Test name
Test status
Simulation time 21346420 ps
CPU time 1.07 seconds
Started Aug 15 06:33:25 PM PDT 24
Finished Aug 15 06:33:27 PM PDT 24
Peak memory 219440 kb
Host smart-4c86358c-676d-4a13-b10a-7cd84afe643d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148355864 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.2148355864
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3611943098
Short name T747
Test name
Test status
Simulation time 59561630 ps
CPU time 1.43 seconds
Started Aug 15 06:33:29 PM PDT 24
Finished Aug 15 06:33:30 PM PDT 24
Peak memory 218884 kb
Host smart-d676e253-7877-41c9-b8c3-0664ecb1440f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611943098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3611943098
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.2014672617
Short name T954
Test name
Test status
Simulation time 27579320 ps
CPU time 1.12 seconds
Started Aug 15 06:33:31 PM PDT 24
Finished Aug 15 06:33:33 PM PDT 24
Peak memory 219976 kb
Host smart-1ffcedc8-0619-403d-b551-9324daa4e4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014672617 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.2014672617
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.465744432
Short name T162
Test name
Test status
Simulation time 29125215 ps
CPU time 0.95 seconds
Started Aug 15 06:33:34 PM PDT 24
Finished Aug 15 06:33:35 PM PDT 24
Peak memory 223924 kb
Host smart-ebeb3f66-7d52-4fe5-b664-56260e01d58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465744432 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.465744432
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.2789478271
Short name T482
Test name
Test status
Simulation time 53816874 ps
CPU time 1.27 seconds
Started Aug 15 06:33:26 PM PDT 24
Finished Aug 15 06:33:28 PM PDT 24
Peak memory 218980 kb
Host smart-65ce359c-fca1-4c9f-9310-eca31bf2f5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789478271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.2789478271
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.1373032359
Short name T190
Test name
Test status
Simulation time 79376822 ps
CPU time 1.13 seconds
Started Aug 15 06:33:30 PM PDT 24
Finished Aug 15 06:33:31 PM PDT 24
Peak memory 220972 kb
Host smart-c92571f3-ab3f-4311-9625-a3fd2e10cac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373032359 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.1373032359
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.1081246950
Short name T107
Test name
Test status
Simulation time 36305986 ps
CPU time 1.08 seconds
Started Aug 15 06:33:26 PM PDT 24
Finished Aug 15 06:33:28 PM PDT 24
Peak memory 220636 kb
Host smart-e96756b5-1ecf-44b3-a8e5-45b0da731292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081246950 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1081246950
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.591347346
Short name T368
Test name
Test status
Simulation time 55090121 ps
CPU time 1.35 seconds
Started Aug 15 06:33:25 PM PDT 24
Finished Aug 15 06:33:27 PM PDT 24
Peak memory 218644 kb
Host smart-f798ff98-21f2-4572-a661-e75ff52a0604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591347346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.591347346
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.1717934826
Short name T584
Test name
Test status
Simulation time 31446378 ps
CPU time 1.25 seconds
Started Aug 15 06:33:26 PM PDT 24
Finished Aug 15 06:33:27 PM PDT 24
Peak memory 220396 kb
Host smart-40d4aaa7-e9d1-4ca7-9224-2fff4c2f961c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717934826 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.1717934826
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.824636001
Short name T114
Test name
Test status
Simulation time 25091715 ps
CPU time 1.19 seconds
Started Aug 15 06:33:19 PM PDT 24
Finished Aug 15 06:33:21 PM PDT 24
Peak memory 219592 kb
Host smart-2e362be5-843b-424f-b312-85e376932382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824636001 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.824636001
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.1672856399
Short name T734
Test name
Test status
Simulation time 40699654 ps
CPU time 1.13 seconds
Started Aug 15 06:33:27 PM PDT 24
Finished Aug 15 06:33:28 PM PDT 24
Peak memory 218740 kb
Host smart-73f38d8c-732f-420d-97f9-a5fbf44dee56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672856399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1672856399
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.2229277274
Short name T516
Test name
Test status
Simulation time 88189263 ps
CPU time 1.25 seconds
Started Aug 15 06:32:13 PM PDT 24
Finished Aug 15 06:32:15 PM PDT 24
Peak memory 219804 kb
Host smart-f9796bc2-9977-437c-b937-6e61e5869f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229277274 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.2229277274
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.3817937451
Short name T497
Test name
Test status
Simulation time 48828362 ps
CPU time 0.9 seconds
Started Aug 15 06:32:08 PM PDT 24
Finished Aug 15 06:32:09 PM PDT 24
Peak memory 206788 kb
Host smart-c0981b10-cc93-4eac-8c4d-d8a6f44e75ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817937451 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3817937451
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.3514841523
Short name T187
Test name
Test status
Simulation time 20357871 ps
CPU time 0.96 seconds
Started Aug 15 06:32:08 PM PDT 24
Finished Aug 15 06:32:09 PM PDT 24
Peak memory 215464 kb
Host smart-176faf6e-ae64-452c-a2bf-2f9aca5b71fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514841523 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3514841523
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.306626327
Short name T125
Test name
Test status
Simulation time 199776600 ps
CPU time 1.05 seconds
Started Aug 15 06:32:07 PM PDT 24
Finished Aug 15 06:32:08 PM PDT 24
Peak memory 217000 kb
Host smart-ae6e61c4-0eff-4a4a-8322-8c8a31560eaf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306626327 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_dis
able_auto_req_mode.306626327
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.1986481986
Short name T131
Test name
Test status
Simulation time 59593038 ps
CPU time 1.04 seconds
Started Aug 15 06:32:10 PM PDT 24
Finished Aug 15 06:32:11 PM PDT 24
Peak memory 220756 kb
Host smart-2a8dc2cd-14dc-4e46-b8b4-025004c4f223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986481986 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.1986481986
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1232769019
Short name T480
Test name
Test status
Simulation time 49034888 ps
CPU time 1.89 seconds
Started Aug 15 06:32:07 PM PDT 24
Finished Aug 15 06:32:10 PM PDT 24
Peak memory 219660 kb
Host smart-85387aa3-9727-474f-a320-0d68bd92bd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232769019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1232769019
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.575117450
Short name T757
Test name
Test status
Simulation time 21074004 ps
CPU time 1.21 seconds
Started Aug 15 06:32:13 PM PDT 24
Finished Aug 15 06:32:15 PM PDT 24
Peak memory 224464 kb
Host smart-c97b7397-46d5-47a6-9291-58e2b0aab7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575117450 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.575117450
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.3679597234
Short name T237
Test name
Test status
Simulation time 29567452 ps
CPU time 0.93 seconds
Started Aug 15 06:32:10 PM PDT 24
Finished Aug 15 06:32:11 PM PDT 24
Peak memory 207152 kb
Host smart-152794d5-d025-4289-b91f-232e85cde377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679597234 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3679597234
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.1561805441
Short name T727
Test name
Test status
Simulation time 18283396 ps
CPU time 1.02 seconds
Started Aug 15 06:32:05 PM PDT 24
Finished Aug 15 06:32:06 PM PDT 24
Peak memory 215328 kb
Host smart-ce69ea5a-ed75-45f3-93b9-a6f87c4441a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561805441 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1561805441
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.3768963033
Short name T939
Test name
Test status
Simulation time 716952599 ps
CPU time 2.62 seconds
Started Aug 15 06:32:07 PM PDT 24
Finished Aug 15 06:32:10 PM PDT 24
Peak memory 217460 kb
Host smart-afbb056a-018e-45e7-8c7d-ef110eb3cf7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768963033 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.3768963033
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.3426221305
Short name T800
Test name
Test status
Simulation time 4786521438 ps
CPU time 124.55 seconds
Started Aug 15 06:32:08 PM PDT 24
Finished Aug 15 06:34:13 PM PDT 24
Peak memory 218932 kb
Host smart-67e4104e-d4ec-44e5-909f-5d5e96ac02d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426221305 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.3426221305
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.2502548128
Short name T535
Test name
Test status
Simulation time 25910086 ps
CPU time 1.2 seconds
Started Aug 15 06:33:21 PM PDT 24
Finished Aug 15 06:33:22 PM PDT 24
Peak memory 220716 kb
Host smart-b9439e93-e665-446b-ab21-cdb13650c553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502548128 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.2502548128
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.1979195011
Short name T115
Test name
Test status
Simulation time 43002445 ps
CPU time 1.1 seconds
Started Aug 15 06:33:24 PM PDT 24
Finished Aug 15 06:33:25 PM PDT 24
Peak memory 220744 kb
Host smart-1a42b251-97f1-4864-bd1e-14847fed6da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979195011 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.1979195011
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.3436465066
Short name T267
Test name
Test status
Simulation time 159648296 ps
CPU time 1.39 seconds
Started Aug 15 06:33:26 PM PDT 24
Finished Aug 15 06:33:28 PM PDT 24
Peak memory 217544 kb
Host smart-6810c138-ab16-4098-9aab-1b3604cf0f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436465066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3436465066
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.2387569716
Short name T664
Test name
Test status
Simulation time 24426653 ps
CPU time 1.2 seconds
Started Aug 15 06:33:27 PM PDT 24
Finished Aug 15 06:33:29 PM PDT 24
Peak memory 219864 kb
Host smart-dadb013e-3a05-4ab3-9d03-95d3d3342bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387569716 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.2387569716
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.392888332
Short name T123
Test name
Test status
Simulation time 27646308 ps
CPU time 1.42 seconds
Started Aug 15 06:33:27 PM PDT 24
Finished Aug 15 06:33:29 PM PDT 24
Peak memory 228808 kb
Host smart-d102467b-68ae-4683-a2d9-9a5c47367294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392888332 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.392888332
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.3889143243
Short name T629
Test name
Test status
Simulation time 59424146 ps
CPU time 2.24 seconds
Started Aug 15 06:33:21 PM PDT 24
Finished Aug 15 06:33:24 PM PDT 24
Peak memory 217572 kb
Host smart-352381be-c0fd-4645-87b9-7323a233d940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889143243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.3889143243
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.3457632763
Short name T945
Test name
Test status
Simulation time 25373152 ps
CPU time 1.21 seconds
Started Aug 15 06:33:35 PM PDT 24
Finished Aug 15 06:33:36 PM PDT 24
Peak memory 218752 kb
Host smart-fb0b2444-8842-4f19-bd80-600c3b97693b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457632763 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.3457632763
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.1505797342
Short name T753
Test name
Test status
Simulation time 34863231 ps
CPU time 0.86 seconds
Started Aug 15 06:33:20 PM PDT 24
Finished Aug 15 06:33:21 PM PDT 24
Peak memory 218356 kb
Host smart-bb8aa641-84d0-4625-aa9e-c5e3d303ab40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505797342 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.1505797342
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.3875644617
Short name T621
Test name
Test status
Simulation time 38751133 ps
CPU time 1.38 seconds
Started Aug 15 06:33:26 PM PDT 24
Finished Aug 15 06:33:27 PM PDT 24
Peak memory 218700 kb
Host smart-0cc41550-57fd-4ab7-b45b-1872ac5dc755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875644617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.3875644617
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.1630068602
Short name T931
Test name
Test status
Simulation time 58065219 ps
CPU time 1.17 seconds
Started Aug 15 06:33:25 PM PDT 24
Finished Aug 15 06:33:27 PM PDT 24
Peak memory 220860 kb
Host smart-be2a4ef3-5c84-40e3-b3cf-97d1b8494c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630068602 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.1630068602
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.1234425286
Short name T213
Test name
Test status
Simulation time 47851665 ps
CPU time 1.16 seconds
Started Aug 15 06:33:21 PM PDT 24
Finished Aug 15 06:33:22 PM PDT 24
Peak memory 219744 kb
Host smart-66ce25d1-e1cc-4f7a-968e-3d1d4f4fbe61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234425286 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1234425286
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.2061216
Short name T661
Test name
Test status
Simulation time 147269009 ps
CPU time 1.29 seconds
Started Aug 15 06:33:26 PM PDT 24
Finished Aug 15 06:33:27 PM PDT 24
Peak memory 219020 kb
Host smart-e931afec-159d-4f3b-8352-3337929459ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.2061216
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.3683550757
Short name T146
Test name
Test status
Simulation time 28390754 ps
CPU time 1.3 seconds
Started Aug 15 06:33:28 PM PDT 24
Finished Aug 15 06:33:30 PM PDT 24
Peak memory 218720 kb
Host smart-bd1c85ae-9f4f-4ab6-9ce5-747ba62f2930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683550757 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.3683550757
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.3330081950
Short name T385
Test name
Test status
Simulation time 33501138 ps
CPU time 0.92 seconds
Started Aug 15 06:33:19 PM PDT 24
Finished Aug 15 06:33:20 PM PDT 24
Peak memory 219928 kb
Host smart-6a6d5de6-ab84-43ac-8fe6-4135d5af46f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330081950 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3330081950
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.4111895007
Short name T313
Test name
Test status
Simulation time 71438051 ps
CPU time 1.36 seconds
Started Aug 15 06:33:27 PM PDT 24
Finished Aug 15 06:33:29 PM PDT 24
Peak memory 218740 kb
Host smart-3968706b-b5af-4da2-9b62-f2dba43b993c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111895007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.4111895007
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.751450510
Short name T31
Test name
Test status
Simulation time 62762115 ps
CPU time 1.08 seconds
Started Aug 15 06:33:28 PM PDT 24
Finished Aug 15 06:33:29 PM PDT 24
Peak memory 218748 kb
Host smart-502f8e84-e68c-413f-9e5e-e88c8b8944d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751450510 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.751450510
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.796302797
Short name T889
Test name
Test status
Simulation time 18157145 ps
CPU time 1.08 seconds
Started Aug 15 06:33:28 PM PDT 24
Finished Aug 15 06:33:30 PM PDT 24
Peak memory 215492 kb
Host smart-8b0544cc-ba09-40f2-a6ef-1ab5082ebaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796302797 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.796302797
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.2885672303
Short name T838
Test name
Test status
Simulation time 85205721 ps
CPU time 1.13 seconds
Started Aug 15 06:33:28 PM PDT 24
Finished Aug 15 06:33:29 PM PDT 24
Peak memory 217400 kb
Host smart-5a66aab6-bb32-4d71-b916-a4ab06f9bb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885672303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.2885672303
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.903819934
Short name T658
Test name
Test status
Simulation time 29862202 ps
CPU time 1.32 seconds
Started Aug 15 06:33:25 PM PDT 24
Finished Aug 15 06:33:27 PM PDT 24
Peak memory 219852 kb
Host smart-8c69fc42-05f4-4155-8430-b980006c40e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903819934 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.903819934
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.164457866
Short name T686
Test name
Test status
Simulation time 22556915 ps
CPU time 1.19 seconds
Started Aug 15 06:33:44 PM PDT 24
Finished Aug 15 06:33:45 PM PDT 24
Peak memory 218640 kb
Host smart-be1cc3f6-d975-4da7-83d5-9a225a3d3a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164457866 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.164457866
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.333771971
Short name T904
Test name
Test status
Simulation time 36764943 ps
CPU time 1.1 seconds
Started Aug 15 06:33:26 PM PDT 24
Finished Aug 15 06:33:27 PM PDT 24
Peak memory 217392 kb
Host smart-cf22ee53-0dca-49de-b2c4-af1d32142730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333771971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.333771971
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.3251313528
Short name T356
Test name
Test status
Simulation time 322084305 ps
CPU time 1.07 seconds
Started Aug 15 06:33:27 PM PDT 24
Finished Aug 15 06:33:28 PM PDT 24
Peak memory 218432 kb
Host smart-16c9cd87-6273-43d6-a999-3f8c252ff2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251313528 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.3251313528
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.2603481575
Short name T447
Test name
Test status
Simulation time 40580455 ps
CPU time 1.1 seconds
Started Aug 15 06:33:25 PM PDT 24
Finished Aug 15 06:33:27 PM PDT 24
Peak memory 219748 kb
Host smart-a5c30898-f03a-41ef-a3fd-a4afdfc00073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603481575 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2603481575
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.1604124227
Short name T576
Test name
Test status
Simulation time 93034690 ps
CPU time 1.35 seconds
Started Aug 15 06:33:23 PM PDT 24
Finished Aug 15 06:33:24 PM PDT 24
Peak memory 218784 kb
Host smart-b376e7ad-5ebf-4597-bbc9-2388dfdc04f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604124227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.1604124227
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.2901659280
Short name T189
Test name
Test status
Simulation time 73976589 ps
CPU time 1.13 seconds
Started Aug 15 06:33:19 PM PDT 24
Finished Aug 15 06:33:20 PM PDT 24
Peak memory 219716 kb
Host smart-84b57996-c039-4b10-87ee-d3c480f8257a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901659280 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.2901659280
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.3563902545
Short name T214
Test name
Test status
Simulation time 19236737 ps
CPU time 1.05 seconds
Started Aug 15 06:33:27 PM PDT 24
Finished Aug 15 06:33:28 PM PDT 24
Peak memory 215456 kb
Host smart-0ed84e53-29de-4e25-bdad-0b3a5f6d066c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563902545 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.3563902545
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.2123789262
Short name T505
Test name
Test status
Simulation time 73608239 ps
CPU time 1.38 seconds
Started Aug 15 06:33:29 PM PDT 24
Finished Aug 15 06:33:31 PM PDT 24
Peak memory 218564 kb
Host smart-00af2606-d8c7-4867-8b12-d2a8c7fa36c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123789262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2123789262
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.2092467612
Short name T29
Test name
Test status
Simulation time 35498143 ps
CPU time 1.07 seconds
Started Aug 15 06:33:27 PM PDT 24
Finished Aug 15 06:33:28 PM PDT 24
Peak memory 219548 kb
Host smart-c556bf1a-3105-4770-8751-6b009f8edf24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092467612 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.2092467612
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.336351967
Short name T832
Test name
Test status
Simulation time 45847776 ps
CPU time 1.16 seconds
Started Aug 15 06:33:28 PM PDT 24
Finished Aug 15 06:33:29 PM PDT 24
Peak memory 219672 kb
Host smart-a731b574-2ef0-47f8-ad71-b0b29ef09ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336351967 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.336351967
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.3976754432
Short name T770
Test name
Test status
Simulation time 67223815 ps
CPU time 1.21 seconds
Started Aug 15 06:33:26 PM PDT 24
Finished Aug 15 06:33:28 PM PDT 24
Peak memory 215392 kb
Host smart-b06b3092-dbdc-466c-9c36-91b1ade27aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976754432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3976754432
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.4003963243
Short name T218
Test name
Test status
Simulation time 48693709 ps
CPU time 1.17 seconds
Started Aug 15 06:32:13 PM PDT 24
Finished Aug 15 06:32:15 PM PDT 24
Peak memory 220036 kb
Host smart-207c2fb2-7a36-4cc0-b9d1-069786a14a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003963243 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.4003963243
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.1228835924
Short name T396
Test name
Test status
Simulation time 27485738 ps
CPU time 0.92 seconds
Started Aug 15 06:32:22 PM PDT 24
Finished Aug 15 06:32:23 PM PDT 24
Peak memory 206788 kb
Host smart-53f0a273-c97f-49cd-b458-258af4531d9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228835924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.1228835924
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.3015740702
Short name T916
Test name
Test status
Simulation time 11982457 ps
CPU time 0.89 seconds
Started Aug 15 06:32:24 PM PDT 24
Finished Aug 15 06:32:25 PM PDT 24
Peak memory 215436 kb
Host smart-6904b37e-5461-4fed-aba9-ac0618b28ed5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015740702 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3015740702
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.3199374539
Short name T932
Test name
Test status
Simulation time 52817261 ps
CPU time 1.01 seconds
Started Aug 15 06:32:19 PM PDT 24
Finished Aug 15 06:32:20 PM PDT 24
Peak memory 215352 kb
Host smart-2faf5c61-d22d-40be-b871-9d56d2ed676d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199374539 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.3199374539
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3744362124
Short name T806
Test name
Test status
Simulation time 71304877 ps
CPU time 1.11 seconds
Started Aug 15 06:32:11 PM PDT 24
Finished Aug 15 06:32:13 PM PDT 24
Peak memory 219588 kb
Host smart-a19df8b4-28ff-4b29-bc98-7ac15fcd9866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744362124 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3744362124
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.647128841
Short name T678
Test name
Test status
Simulation time 72622652 ps
CPU time 1.07 seconds
Started Aug 15 06:32:06 PM PDT 24
Finished Aug 15 06:32:07 PM PDT 24
Peak memory 217296 kb
Host smart-68ea454b-8fc2-4bfe-874e-95f6404b4620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647128841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.647128841
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.4102417628
Short name T578
Test name
Test status
Simulation time 24634041 ps
CPU time 0.95 seconds
Started Aug 15 06:32:11 PM PDT 24
Finished Aug 15 06:32:12 PM PDT 24
Peak memory 215444 kb
Host smart-d80b8789-aa7d-4521-af43-4e12190438f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102417628 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.4102417628
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.3792730778
Short name T746
Test name
Test status
Simulation time 40645264 ps
CPU time 0.87 seconds
Started Aug 15 06:32:10 PM PDT 24
Finished Aug 15 06:32:11 PM PDT 24
Peak memory 207208 kb
Host smart-7cafee09-2159-48f6-a450-4041f777be10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792730778 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3792730778
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.1368928538
Short name T440
Test name
Test status
Simulation time 19570734 ps
CPU time 1.06 seconds
Started Aug 15 06:32:10 PM PDT 24
Finished Aug 15 06:32:11 PM PDT 24
Peak memory 215376 kb
Host smart-fcdc5f15-2d1e-4bc5-a74a-e2e5ca47aa7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368928538 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1368928538
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.1310248443
Short name T425
Test name
Test status
Simulation time 232878212 ps
CPU time 4.65 seconds
Started Aug 15 06:32:09 PM PDT 24
Finished Aug 15 06:32:14 PM PDT 24
Peak memory 218424 kb
Host smart-48b4553d-8109-40a2-9759-af1e87318d01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310248443 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.1310248443
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/80.edn_alert.1594480400
Short name T245
Test name
Test status
Simulation time 29309935 ps
CPU time 1.27 seconds
Started Aug 15 06:33:27 PM PDT 24
Finished Aug 15 06:33:29 PM PDT 24
Peak memory 220696 kb
Host smart-d904c3d6-f0e7-46d5-a411-cd80c16e50c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594480400 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.1594480400
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.82977115
Short name T846
Test name
Test status
Simulation time 24918379 ps
CPU time 1.17 seconds
Started Aug 15 06:33:28 PM PDT 24
Finished Aug 15 06:33:30 PM PDT 24
Peak memory 218584 kb
Host smart-c1a6b3de-ebe9-4962-8808-772c8bc3b96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82977115 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.82977115
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.2314582765
Short name T690
Test name
Test status
Simulation time 71436844 ps
CPU time 1.28 seconds
Started Aug 15 06:33:29 PM PDT 24
Finished Aug 15 06:33:31 PM PDT 24
Peak memory 218968 kb
Host smart-eb2bfbe5-9aab-4c9a-882e-8caed6e8fdd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314582765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2314582765
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.2947557649
Short name T730
Test name
Test status
Simulation time 361146607 ps
CPU time 1.4 seconds
Started Aug 15 06:33:35 PM PDT 24
Finished Aug 15 06:33:37 PM PDT 24
Peak memory 215756 kb
Host smart-1914c1dd-3bd9-4927-a9c0-7a49ea5139f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947557649 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.2947557649
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.1396432136
Short name T137
Test name
Test status
Simulation time 31071293 ps
CPU time 1.05 seconds
Started Aug 15 06:33:29 PM PDT 24
Finished Aug 15 06:33:30 PM PDT 24
Peak memory 224080 kb
Host smart-b036eade-bec8-42b4-ba2d-8ea4bdb0e082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396432136 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.1396432136
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.4055530647
Short name T929
Test name
Test status
Simulation time 35537792 ps
CPU time 1.48 seconds
Started Aug 15 06:33:25 PM PDT 24
Finished Aug 15 06:33:27 PM PDT 24
Peak memory 219508 kb
Host smart-08c059af-7ea7-4dc1-b576-acea5677be1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055530647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.4055530647
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.987614470
Short name T531
Test name
Test status
Simulation time 48598959 ps
CPU time 1.27 seconds
Started Aug 15 06:33:25 PM PDT 24
Finished Aug 15 06:33:27 PM PDT 24
Peak memory 219084 kb
Host smart-a774d750-7142-48b1-b4b0-7fe5904c2d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987614470 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.987614470
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.1063681067
Short name T543
Test name
Test status
Simulation time 28538326 ps
CPU time 1.35 seconds
Started Aug 15 06:33:28 PM PDT 24
Finished Aug 15 06:33:30 PM PDT 24
Peak memory 225052 kb
Host smart-829d12e8-4348-4608-8f7a-8625c3e7c2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063681067 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1063681067
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.64190803
Short name T350
Test name
Test status
Simulation time 35977968 ps
CPU time 1.17 seconds
Started Aug 15 06:33:38 PM PDT 24
Finished Aug 15 06:33:39 PM PDT 24
Peak memory 217516 kb
Host smart-f236ce6c-e702-4cfd-8331-e04ea1d39e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64190803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.64190803
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.228803763
Short name T222
Test name
Test status
Simulation time 45519285 ps
CPU time 1.1 seconds
Started Aug 15 06:33:26 PM PDT 24
Finished Aug 15 06:33:27 PM PDT 24
Peak memory 220364 kb
Host smart-d6f6d9f5-6050-4dcb-870d-f7bd4d2a3dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228803763 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.228803763
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.1341736547
Short name T171
Test name
Test status
Simulation time 23803309 ps
CPU time 1.06 seconds
Started Aug 15 06:33:30 PM PDT 24
Finished Aug 15 06:33:31 PM PDT 24
Peak memory 224120 kb
Host smart-babbdbb7-7da3-486d-8042-09db3f38d094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341736547 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.1341736547
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.1759496863
Short name T366
Test name
Test status
Simulation time 53812136 ps
CPU time 1.3 seconds
Started Aug 15 06:33:26 PM PDT 24
Finished Aug 15 06:33:28 PM PDT 24
Peak memory 218992 kb
Host smart-58f70a8c-fec2-407d-a906-9731c20f00d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759496863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.1759496863
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.1505128309
Short name T783
Test name
Test status
Simulation time 24427713 ps
CPU time 1.28 seconds
Started Aug 15 06:33:27 PM PDT 24
Finished Aug 15 06:33:28 PM PDT 24
Peak memory 219344 kb
Host smart-5cdee062-bc2f-4925-ad30-a02f6f81becb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505128309 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.1505128309
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.1358164108
Short name T65
Test name
Test status
Simulation time 22786128 ps
CPU time 0.94 seconds
Started Aug 15 06:33:27 PM PDT 24
Finished Aug 15 06:33:29 PM PDT 24
Peak memory 218268 kb
Host smart-23e674c0-bd0d-4666-9092-d811de25773a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358164108 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1358164108
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.3284442382
Short name T856
Test name
Test status
Simulation time 51152152 ps
CPU time 1.34 seconds
Started Aug 15 06:33:31 PM PDT 24
Finished Aug 15 06:33:32 PM PDT 24
Peak memory 218820 kb
Host smart-6f13882f-9eed-4620-b8f7-42c0d929d236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284442382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3284442382
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.2263384757
Short name T863
Test name
Test status
Simulation time 30190661 ps
CPU time 1.19 seconds
Started Aug 15 06:33:29 PM PDT 24
Finished Aug 15 06:33:31 PM PDT 24
Peak memory 220028 kb
Host smart-890126d5-2442-4652-a286-af5c34a1bc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263384757 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.2263384757
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.3935546089
Short name T683
Test name
Test status
Simulation time 32319640 ps
CPU time 1.13 seconds
Started Aug 15 06:33:26 PM PDT 24
Finished Aug 15 06:33:28 PM PDT 24
Peak memory 224084 kb
Host smart-97ca1d3a-8678-4d94-aeb6-46c5c96f6720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935546089 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3935546089
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.3657626326
Short name T640
Test name
Test status
Simulation time 40319103 ps
CPU time 1.43 seconds
Started Aug 15 06:33:28 PM PDT 24
Finished Aug 15 06:33:30 PM PDT 24
Peak memory 218548 kb
Host smart-180e309e-f045-4322-8916-d4e8a5e36707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657626326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3657626326
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.3896645514
Short name T552
Test name
Test status
Simulation time 54482405 ps
CPU time 1.19 seconds
Started Aug 15 06:33:36 PM PDT 24
Finished Aug 15 06:33:37 PM PDT 24
Peak memory 218688 kb
Host smart-2b12f9d4-5bfd-499b-b0ee-f8b4c36dd727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896645514 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.3896645514
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_genbits.4208424878
Short name T644
Test name
Test status
Simulation time 73758170 ps
CPU time 1.11 seconds
Started Aug 15 06:33:27 PM PDT 24
Finished Aug 15 06:33:28 PM PDT 24
Peak memory 217400 kb
Host smart-e237d6e0-5720-437f-b218-01be89f798f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208424878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.4208424878
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.3454776198
Short name T858
Test name
Test status
Simulation time 284077740 ps
CPU time 1.2 seconds
Started Aug 15 06:33:37 PM PDT 24
Finished Aug 15 06:33:38 PM PDT 24
Peak memory 220124 kb
Host smart-31281732-4e07-4a3a-921d-c4e218e71047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454776198 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.3454776198
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.4063801029
Short name T397
Test name
Test status
Simulation time 19143540 ps
CPU time 1.07 seconds
Started Aug 15 06:33:26 PM PDT 24
Finished Aug 15 06:33:27 PM PDT 24
Peak memory 218612 kb
Host smart-2a491dd6-4964-4956-9b21-769e2c798c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063801029 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.4063801029
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.416033363
Short name T797
Test name
Test status
Simulation time 210555647 ps
CPU time 1.38 seconds
Started Aug 15 06:33:29 PM PDT 24
Finished Aug 15 06:33:30 PM PDT 24
Peak memory 217452 kb
Host smart-8d2c2639-ab43-4c73-a046-0b02a360d942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416033363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.416033363
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.1097236238
Short name T129
Test name
Test status
Simulation time 26619698 ps
CPU time 1.21 seconds
Started Aug 15 06:33:27 PM PDT 24
Finished Aug 15 06:33:29 PM PDT 24
Peak memory 218676 kb
Host smart-fe01665f-5086-4b30-bac5-4fa9b921b55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097236238 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.1097236238
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.3102659497
Short name T156
Test name
Test status
Simulation time 23841678 ps
CPU time 0.92 seconds
Started Aug 15 06:33:30 PM PDT 24
Finished Aug 15 06:33:31 PM PDT 24
Peak memory 218652 kb
Host smart-20a9a06b-379d-4fb6-896c-ecbed44514c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102659497 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.3102659497
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1358477033
Short name T434
Test name
Test status
Simulation time 47250970 ps
CPU time 1.19 seconds
Started Aug 15 06:33:28 PM PDT 24
Finished Aug 15 06:33:30 PM PDT 24
Peak memory 218448 kb
Host smart-20ff2a72-9c84-4244-892d-8732ec0150cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358477033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1358477033
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.1891014503
Short name T109
Test name
Test status
Simulation time 177135368 ps
CPU time 1.26 seconds
Started Aug 15 06:33:43 PM PDT 24
Finished Aug 15 06:33:44 PM PDT 24
Peak memory 220540 kb
Host smart-3a81f80d-b4f9-4e32-8492-87ef374a2d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891014503 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.1891014503
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.3080358128
Short name T905
Test name
Test status
Simulation time 47890368 ps
CPU time 0.84 seconds
Started Aug 15 06:33:37 PM PDT 24
Finished Aug 15 06:33:38 PM PDT 24
Peak memory 218000 kb
Host smart-903b351d-aac3-4d60-ba20-164377a9898f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080358128 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.3080358128
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.2453984368
Short name T691
Test name
Test status
Simulation time 67127858 ps
CPU time 1.51 seconds
Started Aug 15 06:33:27 PM PDT 24
Finished Aug 15 06:33:29 PM PDT 24
Peak memory 218744 kb
Host smart-c2f3af45-3cad-43a4-9c9c-7a0d17c7814f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453984368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.2453984368
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert_test.2066223668
Short name T762
Test name
Test status
Simulation time 23602087 ps
CPU time 0.86 seconds
Started Aug 15 06:32:12 PM PDT 24
Finished Aug 15 06:32:13 PM PDT 24
Peak memory 206764 kb
Host smart-d567ebb4-61fb-44dc-91a6-6634ea0c5714
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066223668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.2066223668
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.2082452384
Short name T550
Test name
Test status
Simulation time 15746946 ps
CPU time 0.86 seconds
Started Aug 15 06:32:19 PM PDT 24
Finished Aug 15 06:32:20 PM PDT 24
Peak memory 215216 kb
Host smart-575910da-dff6-4aec-884e-31354c2d5efc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082452384 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2082452384
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.576969478
Short name T20
Test name
Test status
Simulation time 32208944 ps
CPU time 1.01 seconds
Started Aug 15 06:32:14 PM PDT 24
Finished Aug 15 06:32:15 PM PDT 24
Peak memory 217036 kb
Host smart-c516a0f9-a247-4e14-ab28-d6c46431afa0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576969478 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_dis
able_auto_req_mode.576969478
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.836378334
Short name T450
Test name
Test status
Simulation time 26831782 ps
CPU time 1.22 seconds
Started Aug 15 06:32:17 PM PDT 24
Finished Aug 15 06:32:18 PM PDT 24
Peak memory 218776 kb
Host smart-7f86872b-1378-41c7-80d7-5fb71c2b3f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836378334 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.836378334
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.2836635007
Short name T493
Test name
Test status
Simulation time 74997266 ps
CPU time 1.29 seconds
Started Aug 15 06:32:13 PM PDT 24
Finished Aug 15 06:32:15 PM PDT 24
Peak memory 218416 kb
Host smart-98988604-0a2e-4501-b5bc-63f5b5e342dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836635007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2836635007
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2629265019
Short name T620
Test name
Test status
Simulation time 25171025 ps
CPU time 1.07 seconds
Started Aug 15 06:32:16 PM PDT 24
Finished Aug 15 06:32:17 PM PDT 24
Peak memory 224244 kb
Host smart-71a31b9d-a04b-4e1b-bbf0-98736149d82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629265019 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2629265019
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.1961866305
Short name T571
Test name
Test status
Simulation time 67515764 ps
CPU time 0.93 seconds
Started Aug 15 06:32:19 PM PDT 24
Finished Aug 15 06:32:20 PM PDT 24
Peak memory 207132 kb
Host smart-acfa87b2-5311-4c4f-a78a-bf263633b6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961866305 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1961866305
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.1112724445
Short name T876
Test name
Test status
Simulation time 19733993 ps
CPU time 1.02 seconds
Started Aug 15 06:32:13 PM PDT 24
Finished Aug 15 06:32:15 PM PDT 24
Peak memory 215316 kb
Host smart-bdc2c2e2-71b5-4456-a3fc-e3be38e7bde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112724445 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.1112724445
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1559024740
Short name T375
Test name
Test status
Simulation time 908889008 ps
CPU time 1.71 seconds
Started Aug 15 06:32:12 PM PDT 24
Finished Aug 15 06:32:14 PM PDT 24
Peak memory 215196 kb
Host smart-8d8f3ab8-adee-41df-8cee-946317c921ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559024740 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1559024740
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.1185948538
Short name T424
Test name
Test status
Simulation time 1325353335 ps
CPU time 33.09 seconds
Started Aug 15 06:32:11 PM PDT 24
Finished Aug 15 06:32:44 PM PDT 24
Peak memory 217680 kb
Host smart-53aac76e-a552-4ce1-b570-7182e28dceff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185948538 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.1185948538
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.1303237358
Short name T568
Test name
Test status
Simulation time 47778027 ps
CPU time 1.17 seconds
Started Aug 15 06:33:26 PM PDT 24
Finished Aug 15 06:33:27 PM PDT 24
Peak memory 220816 kb
Host smart-7bea32d5-8f78-4791-a42c-263d84e69fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303237358 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.1303237358
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.2057744466
Short name T205
Test name
Test status
Simulation time 36679498 ps
CPU time 0.94 seconds
Started Aug 15 06:33:28 PM PDT 24
Finished Aug 15 06:33:29 PM PDT 24
Peak memory 219488 kb
Host smart-e66249e9-e275-4ffc-82c0-dd3b02d38567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057744466 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.2057744466
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.293100953
Short name T566
Test name
Test status
Simulation time 137861451 ps
CPU time 2.64 seconds
Started Aug 15 06:33:25 PM PDT 24
Finished Aug 15 06:33:28 PM PDT 24
Peak memory 218664 kb
Host smart-b1addb4f-9207-47a7-a3f9-89d4e44557dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293100953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.293100953
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.726188620
Short name T840
Test name
Test status
Simulation time 67522685 ps
CPU time 1.26 seconds
Started Aug 15 06:33:31 PM PDT 24
Finished Aug 15 06:33:32 PM PDT 24
Peak memory 219384 kb
Host smart-e921ba04-f79c-4aac-bb5e-a2c8d0d7f31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726188620 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.726188620
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.2170148992
Short name T680
Test name
Test status
Simulation time 19506300 ps
CPU time 1.12 seconds
Started Aug 15 06:33:39 PM PDT 24
Finished Aug 15 06:33:41 PM PDT 24
Peak memory 215544 kb
Host smart-7dbea71f-8da7-4ac4-b840-a3e2cbfd15ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170148992 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.2170148992
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.2919235766
Short name T283
Test name
Test status
Simulation time 49384738 ps
CPU time 1.81 seconds
Started Aug 15 06:33:26 PM PDT 24
Finished Aug 15 06:33:28 PM PDT 24
Peak memory 218516 kb
Host smart-ac4a1fc6-ab5a-4755-bde0-3a8d4276ffeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919235766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.2919235766
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.2593309522
Short name T950
Test name
Test status
Simulation time 163070147 ps
CPU time 1.19 seconds
Started Aug 15 06:33:33 PM PDT 24
Finished Aug 15 06:33:34 PM PDT 24
Peak memory 218808 kb
Host smart-e3fe363e-bae9-43a6-8562-f3cb8f0a0542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593309522 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.2593309522
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.4187264000
Short name T157
Test name
Test status
Simulation time 40406177 ps
CPU time 0.86 seconds
Started Aug 15 06:33:28 PM PDT 24
Finished Aug 15 06:33:29 PM PDT 24
Peak memory 218208 kb
Host smart-abf49d8c-cf1a-4d6a-b800-acd26da3d999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187264000 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.4187264000
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3660294101
Short name T750
Test name
Test status
Simulation time 57532679 ps
CPU time 0.98 seconds
Started Aug 15 06:33:27 PM PDT 24
Finished Aug 15 06:33:29 PM PDT 24
Peak memory 217416 kb
Host smart-4b3722c5-aabd-4beb-aa6b-6a3d061a5b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660294101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3660294101
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.2779928893
Short name T243
Test name
Test status
Simulation time 71293991 ps
CPU time 1.29 seconds
Started Aug 15 06:33:37 PM PDT 24
Finished Aug 15 06:33:39 PM PDT 24
Peak memory 219672 kb
Host smart-4482af8c-d5be-4150-b8a1-746f8456d790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779928893 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.2779928893
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.4111646113
Short name T203
Test name
Test status
Simulation time 29613535 ps
CPU time 1.36 seconds
Started Aug 15 06:33:37 PM PDT 24
Finished Aug 15 06:33:38 PM PDT 24
Peak memory 225744 kb
Host smart-406afd4b-9cd8-4dc7-ad90-67927abf9fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111646113 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.4111646113
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.1418862085
Short name T755
Test name
Test status
Simulation time 62550437 ps
CPU time 1.1 seconds
Started Aug 15 06:33:34 PM PDT 24
Finished Aug 15 06:33:35 PM PDT 24
Peak memory 217500 kb
Host smart-f1e87537-7b15-4473-b560-f10dd21bc44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418862085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.1418862085
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.1432058300
Short name T387
Test name
Test status
Simulation time 89779979 ps
CPU time 1.11 seconds
Started Aug 15 06:33:31 PM PDT 24
Finished Aug 15 06:33:32 PM PDT 24
Peak memory 218856 kb
Host smart-4d4873f3-48a7-4c45-a478-f8ccfea12f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432058300 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.1432058300
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.3970001478
Short name T594
Test name
Test status
Simulation time 32524991 ps
CPU time 0.87 seconds
Started Aug 15 06:33:30 PM PDT 24
Finished Aug 15 06:33:31 PM PDT 24
Peak memory 218164 kb
Host smart-b3c9a03e-b0bd-491f-a8f7-86f52e910340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970001478 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3970001478
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.2003726720
Short name T302
Test name
Test status
Simulation time 62341777 ps
CPU time 1.3 seconds
Started Aug 15 06:33:33 PM PDT 24
Finished Aug 15 06:33:35 PM PDT 24
Peak memory 218552 kb
Host smart-b014f924-3043-4460-b46f-79214166e2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003726720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2003726720
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.851028623
Short name T963
Test name
Test status
Simulation time 184702509 ps
CPU time 1.29 seconds
Started Aug 15 06:33:41 PM PDT 24
Finished Aug 15 06:33:42 PM PDT 24
Peak memory 219684 kb
Host smart-ae48f795-adb2-4a3d-bfa0-34d036c044e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851028623 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.851028623
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.4291083340
Short name T431
Test name
Test status
Simulation time 18292063 ps
CPU time 1.05 seconds
Started Aug 15 06:33:40 PM PDT 24
Finished Aug 15 06:33:41 PM PDT 24
Peak memory 218488 kb
Host smart-ca17670d-c636-4586-8de3-610d276c0cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291083340 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.4291083340
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.2502879194
Short name T409
Test name
Test status
Simulation time 55058197 ps
CPU time 1.32 seconds
Started Aug 15 06:33:37 PM PDT 24
Finished Aug 15 06:33:39 PM PDT 24
Peak memory 218492 kb
Host smart-950b4526-0228-4db9-8f95-1a7bc117dd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502879194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2502879194
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.3777768727
Short name T625
Test name
Test status
Simulation time 54117393 ps
CPU time 1.24 seconds
Started Aug 15 06:33:36 PM PDT 24
Finished Aug 15 06:33:38 PM PDT 24
Peak memory 218676 kb
Host smart-e8ac7da8-cf66-4c28-92d1-b4325df261c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777768727 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.3777768727
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.370294385
Short name T124
Test name
Test status
Simulation time 21282707 ps
CPU time 1.27 seconds
Started Aug 15 06:33:47 PM PDT 24
Finished Aug 15 06:33:48 PM PDT 24
Peak memory 229848 kb
Host smart-8894cf03-120b-428e-976d-f168abe05509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370294385 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.370294385
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.1231425017
Short name T538
Test name
Test status
Simulation time 323761263 ps
CPU time 1.96 seconds
Started Aug 15 06:33:40 PM PDT 24
Finished Aug 15 06:33:42 PM PDT 24
Peak memory 218932 kb
Host smart-cfe9d3e0-2ac8-4792-8b07-01a1549d499e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231425017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.1231425017
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.3751211970
Short name T420
Test name
Test status
Simulation time 44473295 ps
CPU time 1.1 seconds
Started Aug 15 06:33:38 PM PDT 24
Finished Aug 15 06:33:39 PM PDT 24
Peak memory 218664 kb
Host smart-216ae7ec-93f6-4c61-a7c1-e645b0ebcd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751211970 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.3751211970
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.2061551557
Short name T647
Test name
Test status
Simulation time 32760563 ps
CPU time 0.82 seconds
Started Aug 15 06:33:48 PM PDT 24
Finished Aug 15 06:33:49 PM PDT 24
Peak memory 219120 kb
Host smart-4d024073-60e6-4298-9c70-14441886838b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061551557 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2061551557
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.258457894
Short name T374
Test name
Test status
Simulation time 209659637 ps
CPU time 2.68 seconds
Started Aug 15 06:33:49 PM PDT 24
Finished Aug 15 06:33:52 PM PDT 24
Peak memory 219972 kb
Host smart-8d07057c-a159-45cd-af58-96f27c3ab763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258457894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.258457894
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.2508388108
Short name T62
Test name
Test status
Simulation time 91476865 ps
CPU time 1.38 seconds
Started Aug 15 06:33:49 PM PDT 24
Finished Aug 15 06:33:50 PM PDT 24
Peak memory 220308 kb
Host smart-cfbf0388-f9dd-4322-a16f-bd2879be3042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508388108 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.2508388108
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.2583995422
Short name T130
Test name
Test status
Simulation time 63006666 ps
CPU time 0.92 seconds
Started Aug 15 06:33:38 PM PDT 24
Finished Aug 15 06:33:39 PM PDT 24
Peak memory 219292 kb
Host smart-037a6eed-4153-4398-becd-ac01ebe098dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583995422 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.2583995422
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.939681335
Short name T643
Test name
Test status
Simulation time 275723060 ps
CPU time 3.76 seconds
Started Aug 15 06:33:43 PM PDT 24
Finished Aug 15 06:33:47 PM PDT 24
Peak memory 220640 kb
Host smart-632a7446-b892-4c78-96c4-724b39b995c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939681335 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.939681335
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.1141925557
Short name T127
Test name
Test status
Simulation time 45243570 ps
CPU time 1.27 seconds
Started Aug 15 06:33:46 PM PDT 24
Finished Aug 15 06:33:47 PM PDT 24
Peak memory 218804 kb
Host smart-83600e71-7c9e-4c26-b225-dabda4bd802b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141925557 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.1141925557
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.998357494
Short name T149
Test name
Test status
Simulation time 34342633 ps
CPU time 1.08 seconds
Started Aug 15 06:33:40 PM PDT 24
Finished Aug 15 06:33:41 PM PDT 24
Peak memory 220812 kb
Host smart-829fe3ee-ce5d-4c20-8dc5-f0bc23775f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998357494 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.998357494
Directory /workspace/99.edn_err/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%