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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.83 98.25 93.97 97.02 92.44 96.37 99.77 92.99


Total test records in report: 1108
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T1014 /workspace/coverage/cover_reg_top/13.edn_csr_rw.1291916519 Aug 18 05:57:10 PM PDT 24 Aug 18 05:57:11 PM PDT 24 11190171 ps
T1015 /workspace/coverage/cover_reg_top/30.edn_intr_test.304324491 Aug 18 05:57:21 PM PDT 24 Aug 18 05:57:22 PM PDT 24 69967725 ps
T1016 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3191051502 Aug 18 05:57:06 PM PDT 24 Aug 18 05:57:07 PM PDT 24 18059554 ps
T324 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.983218273 Aug 18 05:56:31 PM PDT 24 Aug 18 05:56:35 PM PDT 24 162356037 ps
T1017 /workspace/coverage/cover_reg_top/9.edn_intr_test.623256256 Aug 18 05:57:00 PM PDT 24 Aug 18 05:57:01 PM PDT 24 26082482 ps
T1018 /workspace/coverage/cover_reg_top/49.edn_intr_test.4220223348 Aug 18 05:57:23 PM PDT 24 Aug 18 05:57:24 PM PDT 24 21660913 ps
T1019 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2060646980 Aug 18 05:57:15 PM PDT 24 Aug 18 05:57:16 PM PDT 24 35091735 ps
T1020 /workspace/coverage/cover_reg_top/32.edn_intr_test.2926465159 Aug 18 05:57:19 PM PDT 24 Aug 18 05:57:20 PM PDT 24 23338687 ps
T328 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2524171803 Aug 18 05:56:50 PM PDT 24 Aug 18 05:57:06 PM PDT 24 1037805588 ps
T1021 /workspace/coverage/cover_reg_top/48.edn_intr_test.4271362008 Aug 18 05:57:20 PM PDT 24 Aug 18 05:57:21 PM PDT 24 14630155 ps
T1022 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3583896341 Aug 18 05:56:56 PM PDT 24 Aug 18 05:56:57 PM PDT 24 42211056 ps
T1023 /workspace/coverage/cover_reg_top/35.edn_intr_test.2329005710 Aug 18 05:57:21 PM PDT 24 Aug 18 05:57:22 PM PDT 24 14896928 ps
T1024 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.743194431 Aug 18 05:56:41 PM PDT 24 Aug 18 05:56:43 PM PDT 24 79289267 ps
T325 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.287331664 Aug 18 05:57:06 PM PDT 24 Aug 18 05:57:07 PM PDT 24 260527695 ps
T1025 /workspace/coverage/cover_reg_top/6.edn_tl_errors.782439623 Aug 18 05:56:51 PM PDT 24 Aug 18 05:56:53 PM PDT 24 63885250 ps
T1026 /workspace/coverage/cover_reg_top/8.edn_tl_errors.663061598 Aug 18 05:56:58 PM PDT 24 Aug 18 05:57:00 PM PDT 24 88227805 ps
T1027 /workspace/coverage/cover_reg_top/17.edn_tl_errors.2659776117 Aug 18 05:57:16 PM PDT 24 Aug 18 05:57:18 PM PDT 24 28585737 ps
T1028 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.28227783 Aug 18 05:56:49 PM PDT 24 Aug 18 05:56:50 PM PDT 24 223577593 ps
T1029 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.433627644 Aug 18 05:56:58 PM PDT 24 Aug 18 05:56:59 PM PDT 24 156359773 ps
T1030 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1968534068 Aug 18 05:57:00 PM PDT 24 Aug 18 05:57:02 PM PDT 24 25582230 ps
T1031 /workspace/coverage/cover_reg_top/9.edn_tl_errors.1124387914 Aug 18 05:56:58 PM PDT 24 Aug 18 05:57:00 PM PDT 24 90427619 ps
T295 /workspace/coverage/cover_reg_top/9.edn_csr_rw.454222098 Aug 18 05:57:01 PM PDT 24 Aug 18 05:57:02 PM PDT 24 16823331 ps
T296 /workspace/coverage/cover_reg_top/19.edn_csr_rw.2345433010 Aug 18 05:57:13 PM PDT 24 Aug 18 05:57:14 PM PDT 24 19406558 ps
T1032 /workspace/coverage/cover_reg_top/24.edn_intr_test.873183100 Aug 18 05:57:20 PM PDT 24 Aug 18 05:57:21 PM PDT 24 16246639 ps
T1033 /workspace/coverage/cover_reg_top/6.edn_csr_rw.237905220 Aug 18 05:56:55 PM PDT 24 Aug 18 05:56:56 PM PDT 24 26787895 ps
T1034 /workspace/coverage/cover_reg_top/0.edn_tl_errors.3879022135 Aug 18 05:56:35 PM PDT 24 Aug 18 05:56:38 PM PDT 24 412754166 ps
T1035 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.140125118 Aug 18 05:56:31 PM PDT 24 Aug 18 05:56:33 PM PDT 24 31500743 ps
T1036 /workspace/coverage/cover_reg_top/42.edn_intr_test.3403323448 Aug 18 05:57:25 PM PDT 24 Aug 18 05:57:26 PM PDT 24 16448479 ps
T1037 /workspace/coverage/cover_reg_top/1.edn_tl_errors.3432605501 Aug 18 05:56:30 PM PDT 24 Aug 18 05:56:32 PM PDT 24 90478943 ps
T1038 /workspace/coverage/cover_reg_top/47.edn_intr_test.957807441 Aug 18 05:57:22 PM PDT 24 Aug 18 05:57:23 PM PDT 24 71277982 ps
T1039 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.504470153 Aug 18 05:56:52 PM PDT 24 Aug 18 05:56:53 PM PDT 24 18862035 ps
T1040 /workspace/coverage/cover_reg_top/4.edn_tl_errors.3252545725 Aug 18 05:56:41 PM PDT 24 Aug 18 05:56:44 PM PDT 24 74965166 ps
T1041 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1208571959 Aug 18 05:56:57 PM PDT 24 Aug 18 05:57:00 PM PDT 24 80835814 ps
T1042 /workspace/coverage/cover_reg_top/5.edn_intr_test.1417550303 Aug 18 05:56:50 PM PDT 24 Aug 18 05:56:51 PM PDT 24 20840431 ps
T1043 /workspace/coverage/cover_reg_top/14.edn_tl_errors.555978644 Aug 18 05:57:07 PM PDT 24 Aug 18 05:57:09 PM PDT 24 27245550 ps
T1044 /workspace/coverage/cover_reg_top/4.edn_csr_rw.2716000029 Aug 18 05:56:51 PM PDT 24 Aug 18 05:56:52 PM PDT 24 40897156 ps
T326 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3764635452 Aug 18 05:57:21 PM PDT 24 Aug 18 05:57:24 PM PDT 24 93241110 ps
T1045 /workspace/coverage/cover_reg_top/10.edn_tl_errors.2679095445 Aug 18 05:57:00 PM PDT 24 Aug 18 05:57:04 PM PDT 24 241291845 ps
T1046 /workspace/coverage/cover_reg_top/2.edn_intr_test.4222414389 Aug 18 05:56:41 PM PDT 24 Aug 18 05:56:42 PM PDT 24 33055341 ps
T1047 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.539032184 Aug 18 05:57:08 PM PDT 24 Aug 18 05:57:09 PM PDT 24 24061391 ps
T1048 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2352898607 Aug 18 05:57:15 PM PDT 24 Aug 18 05:57:16 PM PDT 24 30458638 ps
T1049 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.558046109 Aug 18 05:57:14 PM PDT 24 Aug 18 05:57:15 PM PDT 24 193298353 ps
T1050 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2920493725 Aug 18 05:57:08 PM PDT 24 Aug 18 05:57:09 PM PDT 24 18924569 ps
T1051 /workspace/coverage/cover_reg_top/12.edn_tl_errors.851429044 Aug 18 05:57:09 PM PDT 24 Aug 18 05:57:13 PM PDT 24 80483177 ps
T1052 /workspace/coverage/cover_reg_top/3.edn_intr_test.1594738410 Aug 18 05:56:43 PM PDT 24 Aug 18 05:56:44 PM PDT 24 13988077 ps
T1053 /workspace/coverage/cover_reg_top/4.edn_intr_test.860916341 Aug 18 05:56:44 PM PDT 24 Aug 18 05:56:45 PM PDT 24 13466367 ps
T1054 /workspace/coverage/cover_reg_top/16.edn_tl_errors.612112784 Aug 18 05:57:08 PM PDT 24 Aug 18 05:57:12 PM PDT 24 934858565 ps
T1055 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1472950497 Aug 18 05:56:58 PM PDT 24 Aug 18 05:57:00 PM PDT 24 67648130 ps
T1056 /workspace/coverage/cover_reg_top/14.edn_intr_test.675922383 Aug 18 05:57:09 PM PDT 24 Aug 18 05:57:10 PM PDT 24 83547558 ps
T1057 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2812771052 Aug 18 05:56:57 PM PDT 24 Aug 18 05:56:59 PM PDT 24 77558907 ps
T1058 /workspace/coverage/cover_reg_top/3.edn_csr_rw.3131495261 Aug 18 05:56:41 PM PDT 24 Aug 18 05:56:42 PM PDT 24 45615320 ps
T1059 /workspace/coverage/cover_reg_top/18.edn_tl_errors.164247849 Aug 18 05:57:15 PM PDT 24 Aug 18 05:57:18 PM PDT 24 136854703 ps
T1060 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1138906659 Aug 18 05:56:58 PM PDT 24 Aug 18 05:57:00 PM PDT 24 103621349 ps
T1061 /workspace/coverage/cover_reg_top/13.edn_tl_errors.1046157870 Aug 18 05:57:10 PM PDT 24 Aug 18 05:57:14 PM PDT 24 478159886 ps
T1062 /workspace/coverage/cover_reg_top/26.edn_intr_test.3600390569 Aug 18 05:57:22 PM PDT 24 Aug 18 05:57:23 PM PDT 24 13631654 ps
T1063 /workspace/coverage/cover_reg_top/0.edn_csr_rw.2325347287 Aug 18 05:56:29 PM PDT 24 Aug 18 05:56:30 PM PDT 24 13527367 ps
T1064 /workspace/coverage/cover_reg_top/38.edn_intr_test.452523820 Aug 18 05:57:21 PM PDT 24 Aug 18 05:57:22 PM PDT 24 37476261 ps
T1065 /workspace/coverage/cover_reg_top/17.edn_intr_test.2549699357 Aug 18 05:57:13 PM PDT 24 Aug 18 05:57:14 PM PDT 24 13588228 ps
T1066 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1961376094 Aug 18 05:57:06 PM PDT 24 Aug 18 05:57:07 PM PDT 24 38731377 ps
T1067 /workspace/coverage/cover_reg_top/34.edn_intr_test.682361278 Aug 18 05:57:21 PM PDT 24 Aug 18 05:57:22 PM PDT 24 17036672 ps
T1068 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3085431592 Aug 18 05:56:40 PM PDT 24 Aug 18 05:56:41 PM PDT 24 60335670 ps
T297 /workspace/coverage/cover_reg_top/12.edn_csr_rw.2861064288 Aug 18 05:57:07 PM PDT 24 Aug 18 05:57:08 PM PDT 24 73172326 ps
T1069 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.372772245 Aug 18 05:56:51 PM PDT 24 Aug 18 05:56:52 PM PDT 24 292844931 ps
T1070 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3575896282 Aug 18 05:57:00 PM PDT 24 Aug 18 05:57:02 PM PDT 24 278901393 ps
T1071 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.682876719 Aug 18 05:56:44 PM PDT 24 Aug 18 05:56:45 PM PDT 24 35905575 ps
T1072 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3224972640 Aug 18 05:56:52 PM PDT 24 Aug 18 05:56:53 PM PDT 24 44409312 ps
T1073 /workspace/coverage/cover_reg_top/29.edn_intr_test.844473156 Aug 18 05:57:20 PM PDT 24 Aug 18 05:57:21 PM PDT 24 41693865 ps
T1074 /workspace/coverage/cover_reg_top/40.edn_intr_test.1313022391 Aug 18 05:57:27 PM PDT 24 Aug 18 05:57:28 PM PDT 24 26869180 ps
T1075 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2447564294 Aug 18 05:57:08 PM PDT 24 Aug 18 05:57:10 PM PDT 24 31728135 ps
T1076 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1127647582 Aug 18 05:56:30 PM PDT 24 Aug 18 05:56:31 PM PDT 24 21374147 ps
T1077 /workspace/coverage/cover_reg_top/8.edn_csr_rw.1941304382 Aug 18 05:56:58 PM PDT 24 Aug 18 05:56:59 PM PDT 24 70654254 ps
T298 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3084019033 Aug 18 05:56:31 PM PDT 24 Aug 18 05:56:32 PM PDT 24 16590419 ps
T1078 /workspace/coverage/cover_reg_top/23.edn_intr_test.1574627175 Aug 18 05:57:15 PM PDT 24 Aug 18 05:57:16 PM PDT 24 22861295 ps
T1079 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.205892356 Aug 18 05:56:42 PM PDT 24 Aug 18 05:56:43 PM PDT 24 194904708 ps
T1080 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3105799630 Aug 18 05:56:42 PM PDT 24 Aug 18 05:56:46 PM PDT 24 141836256 ps
T1081 /workspace/coverage/cover_reg_top/20.edn_intr_test.2268716717 Aug 18 05:57:13 PM PDT 24 Aug 18 05:57:14 PM PDT 24 40601615 ps
T1082 /workspace/coverage/cover_reg_top/45.edn_intr_test.3657207584 Aug 18 05:57:23 PM PDT 24 Aug 18 05:57:24 PM PDT 24 29439405 ps
T1083 /workspace/coverage/cover_reg_top/22.edn_intr_test.84914083 Aug 18 05:57:14 PM PDT 24 Aug 18 05:57:15 PM PDT 24 21374221 ps
T1084 /workspace/coverage/cover_reg_top/37.edn_intr_test.3267291558 Aug 18 05:57:21 PM PDT 24 Aug 18 05:57:22 PM PDT 24 16765768 ps
T1085 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2384731922 Aug 18 05:56:41 PM PDT 24 Aug 18 05:56:47 PM PDT 24 680735114 ps
T1086 /workspace/coverage/cover_reg_top/11.edn_tl_errors.2737679166 Aug 18 05:56:58 PM PDT 24 Aug 18 05:56:59 PM PDT 24 42111077 ps
T1087 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2580154179 Aug 18 05:56:41 PM PDT 24 Aug 18 05:56:46 PM PDT 24 702406371 ps
T1088 /workspace/coverage/cover_reg_top/1.edn_csr_rw.3013864818 Aug 18 05:56:30 PM PDT 24 Aug 18 05:56:31 PM PDT 24 72150335 ps
T1089 /workspace/coverage/cover_reg_top/19.edn_tl_errors.1166244785 Aug 18 05:57:22 PM PDT 24 Aug 18 05:57:25 PM PDT 24 170410336 ps
T1090 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3080281492 Aug 18 05:57:12 PM PDT 24 Aug 18 05:57:14 PM PDT 24 81521159 ps
T1091 /workspace/coverage/cover_reg_top/46.edn_intr_test.2712679905 Aug 18 05:57:21 PM PDT 24 Aug 18 05:57:22 PM PDT 24 44019148 ps
T299 /workspace/coverage/cover_reg_top/11.edn_csr_rw.2569611469 Aug 18 05:56:58 PM PDT 24 Aug 18 05:57:00 PM PDT 24 28343671 ps
T1092 /workspace/coverage/cover_reg_top/25.edn_intr_test.3761333154 Aug 18 05:57:19 PM PDT 24 Aug 18 05:57:20 PM PDT 24 45282181 ps
T1093 /workspace/coverage/cover_reg_top/8.edn_intr_test.2524059190 Aug 18 05:56:57 PM PDT 24 Aug 18 05:56:58 PM PDT 24 68948596 ps
T1094 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1600322227 Aug 18 05:56:44 PM PDT 24 Aug 18 05:56:45 PM PDT 24 21624825 ps
T300 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.960954867 Aug 18 05:56:31 PM PDT 24 Aug 18 05:56:32 PM PDT 24 15425528 ps
T301 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2693928905 Aug 18 05:56:41 PM PDT 24 Aug 18 05:56:42 PM PDT 24 25416609 ps
T1095 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1487469509 Aug 18 05:56:58 PM PDT 24 Aug 18 05:56:59 PM PDT 24 154083803 ps
T1096 /workspace/coverage/cover_reg_top/44.edn_intr_test.41678535 Aug 18 05:57:22 PM PDT 24 Aug 18 05:57:23 PM PDT 24 49968499 ps
T1097 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.4029237437 Aug 18 05:56:54 PM PDT 24 Aug 18 05:56:57 PM PDT 24 314004849 ps
T1098 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1689730807 Aug 18 05:57:08 PM PDT 24 Aug 18 05:57:10 PM PDT 24 21985155 ps
T1099 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1109087129 Aug 18 05:56:54 PM PDT 24 Aug 18 05:56:55 PM PDT 24 21713530 ps
T302 /workspace/coverage/cover_reg_top/14.edn_csr_rw.2755629844 Aug 18 05:57:06 PM PDT 24 Aug 18 05:57:07 PM PDT 24 36551776 ps
T1100 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2871475379 Aug 18 05:56:43 PM PDT 24 Aug 18 05:56:44 PM PDT 24 82142210 ps
T1101 /workspace/coverage/cover_reg_top/15.edn_intr_test.3381452876 Aug 18 05:57:06 PM PDT 24 Aug 18 05:57:07 PM PDT 24 57802253 ps
T303 /workspace/coverage/cover_reg_top/5.edn_csr_rw.3889273807 Aug 18 05:56:50 PM PDT 24 Aug 18 05:56:51 PM PDT 24 19367454 ps
T1102 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2826502855 Aug 18 05:56:41 PM PDT 24 Aug 18 05:56:42 PM PDT 24 22714686 ps
T1103 /workspace/coverage/cover_reg_top/18.edn_intr_test.4258642848 Aug 18 05:57:21 PM PDT 24 Aug 18 05:57:22 PM PDT 24 75634821 ps
T1104 /workspace/coverage/cover_reg_top/27.edn_intr_test.3200886370 Aug 18 05:57:21 PM PDT 24 Aug 18 05:57:22 PM PDT 24 27165391 ps
T1105 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.311425927 Aug 18 05:56:46 PM PDT 24 Aug 18 05:56:49 PM PDT 24 141219600 ps
T1106 /workspace/coverage/cover_reg_top/2.edn_csr_rw.2095622939 Aug 18 05:56:41 PM PDT 24 Aug 18 05:56:41 PM PDT 24 136994905 ps
T1107 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1231697890 Aug 18 05:57:06 PM PDT 24 Aug 18 05:57:08 PM PDT 24 86415593 ps
T1108 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2522397362 Aug 18 05:56:57 PM PDT 24 Aug 18 05:56:58 PM PDT 24 13391012 ps

Test location /workspace/coverage/default/30.edn_stress_all.1531860991
Short name T5
Test name
Test status
Simulation time 367358696 ps
CPU time 2.57 seconds
Started Aug 18 06:11:04 PM PDT 24
Finished Aug 18 06:11:07 PM PDT 24
Peak memory 215348 kb
Host smart-f5614d83-02f7-4a07-ae52-e81d10872330
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531860991 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1531860991
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/82.edn_genbits.3868412323
Short name T10
Test name
Test status
Simulation time 36475101 ps
CPU time 1.64 seconds
Started Aug 18 06:12:02 PM PDT 24
Finished Aug 18 06:12:03 PM PDT 24
Peak memory 220540 kb
Host smart-bbff444d-f770-4545-9a66-3c331e8809b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868412323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3868412323
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_err.2718276069
Short name T13
Test name
Test status
Simulation time 40472557 ps
CPU time 0.92 seconds
Started Aug 18 06:10:39 PM PDT 24
Finished Aug 18 06:10:40 PM PDT 24
Peak memory 223940 kb
Host smart-2fb519a9-b896-43fc-bba6-b5fd21e23b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718276069 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2718276069
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/107.edn_alert.2244501837
Short name T35
Test name
Test status
Simulation time 56709450 ps
CPU time 1.2 seconds
Started Aug 18 06:12:04 PM PDT 24
Finished Aug 18 06:12:06 PM PDT 24
Peak memory 220060 kb
Host smart-97922614-98b2-4166-b273-9c7948dfeb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244501837 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.2244501837
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/1.edn_sec_cm.1036899699
Short name T16
Test name
Test status
Simulation time 1880055269 ps
CPU time 9.56 seconds
Started Aug 18 06:09:59 PM PDT 24
Finished Aug 18 06:10:09 PM PDT 24
Peak memory 241640 kb
Host smart-b494ff44-f443-4101-ad9e-7bfa2310461b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036899699 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1036899699
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.2451131410
Short name T247
Test name
Test status
Simulation time 48920112690 ps
CPU time 101.38 seconds
Started Aug 18 06:11:33 PM PDT 24
Finished Aug 18 06:13:15 PM PDT 24
Peak memory 218624 kb
Host smart-55fa5458-1b5b-4a4f-92a2-d686c378db28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451131410 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.2451131410
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/166.edn_genbits.88273520
Short name T79
Test name
Test status
Simulation time 67167022 ps
CPU time 1.17 seconds
Started Aug 18 06:12:23 PM PDT 24
Finished Aug 18 06:12:24 PM PDT 24
Peak memory 215432 kb
Host smart-f533e181-af78-482b-918b-514995b45796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88273520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.88273520
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.411301546
Short name T20
Test name
Test status
Simulation time 118371583 ps
CPU time 1.03 seconds
Started Aug 18 06:10:25 PM PDT 24
Finished Aug 18 06:10:26 PM PDT 24
Peak memory 218328 kb
Host smart-178cbce4-8645-4fb0-80cb-1a2416b339e3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411301546 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_dis
able_auto_req_mode.411301546
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/181.edn_alert.1832102546
Short name T95
Test name
Test status
Simulation time 203678792 ps
CPU time 1.21 seconds
Started Aug 18 06:12:19 PM PDT 24
Finished Aug 18 06:12:21 PM PDT 24
Peak memory 218692 kb
Host smart-9e00502e-09fa-4c6f-aec6-c44ba0b9ff04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832102546 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.1832102546
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert.3133482800
Short name T23
Test name
Test status
Simulation time 23040837 ps
CPU time 1.21 seconds
Started Aug 18 06:10:43 PM PDT 24
Finished Aug 18 06:10:45 PM PDT 24
Peak memory 218888 kb
Host smart-d7fe03f3-b1fc-4e50-967f-4ae0a9cfca0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133482800 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3133482800
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/16.edn_stress_all.1032494137
Short name T111
Test name
Test status
Simulation time 795470455 ps
CPU time 4.22 seconds
Started Aug 18 06:10:39 PM PDT 24
Finished Aug 18 06:10:44 PM PDT 24
Peak memory 217280 kb
Host smart-c9246755-a03d-415d-9195-8cbb851e11c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032494137 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.1032494137
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.454560
Short name T19
Test name
Test status
Simulation time 67244537 ps
CPU time 1.08 seconds
Started Aug 18 06:10:17 PM PDT 24
Finished Aug 18 06:10:18 PM PDT 24
Peak memory 216920 kb
Host smart-d36b6f08-7fcf-4423-9397-44676f8145ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454560 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disabl
e_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disabl
e_auto_req_mode.454560
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_alert.1362862268
Short name T81
Test name
Test status
Simulation time 27780576 ps
CPU time 1.31 seconds
Started Aug 18 06:11:18 PM PDT 24
Finished Aug 18 06:11:19 PM PDT 24
Peak memory 215764 kb
Host smart-a3ee2382-c5e8-49a8-915e-6ca579169936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362862268 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.1362862268
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.4212212222
Short name T31
Test name
Test status
Simulation time 4463520861 ps
CPU time 57.71 seconds
Started Aug 18 06:11:26 PM PDT 24
Finished Aug 18 06:12:23 PM PDT 24
Peak memory 221436 kb
Host smart-b2d8b62f-97e5-404f-ab13-e5023f196718
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212212222 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.4212212222
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.edn_intr.3534340696
Short name T24
Test name
Test status
Simulation time 20200049 ps
CPU time 1.02 seconds
Started Aug 18 06:10:53 PM PDT 24
Finished Aug 18 06:10:54 PM PDT 24
Peak memory 216028 kb
Host smart-5b62904d-27eb-4eee-a236-36cbead03cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534340696 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3534340696
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.983218273
Short name T324
Test name
Test status
Simulation time 162356037 ps
CPU time 3.68 seconds
Started Aug 18 05:56:31 PM PDT 24
Finished Aug 18 05:56:35 PM PDT 24
Peak memory 207136 kb
Host smart-0a5ce202-6aff-4627-8ea5-2a8fad6c18a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983218273 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.983218273
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.4246547386
Short name T289
Test name
Test status
Simulation time 49220675 ps
CPU time 0.88 seconds
Started Aug 18 05:57:22 PM PDT 24
Finished Aug 18 05:57:23 PM PDT 24
Peak memory 207060 kb
Host smart-3069eccc-52a5-42c1-bb80-f709238fd327
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246547386 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.4246547386
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/default/164.edn_alert.3741568744
Short name T173
Test name
Test status
Simulation time 51719437 ps
CPU time 1.4 seconds
Started Aug 18 06:12:34 PM PDT 24
Finished Aug 18 06:12:35 PM PDT 24
Peak memory 219708 kb
Host smart-09f21cdd-b8bb-48cf-ab8f-66910b858faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741568744 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.3741568744
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/1.edn_disable.1058044916
Short name T205
Test name
Test status
Simulation time 13431071 ps
CPU time 0.92 seconds
Started Aug 18 06:10:02 PM PDT 24
Finished Aug 18 06:10:03 PM PDT 24
Peak memory 215572 kb
Host smart-0821e6fd-2473-4a00-8a7e-794ea525ac1f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058044916 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1058044916
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable.580551493
Short name T227
Test name
Test status
Simulation time 12213467 ps
CPU time 0.9 seconds
Started Aug 18 06:10:20 PM PDT 24
Finished Aug 18 06:10:21 PM PDT 24
Peak memory 215736 kb
Host smart-b9388b41-a1b8-449d-b1ee-0798c864416d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580551493 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.580551493
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/48.edn_genbits.4203952212
Short name T12
Test name
Test status
Simulation time 111146847 ps
CPU time 1.39 seconds
Started Aug 18 06:11:32 PM PDT 24
Finished Aug 18 06:11:34 PM PDT 24
Peak memory 220180 kb
Host smart-bdc06e0b-1c11-44d9-b57e-746d02b84298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203952212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.4203952212
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_disable.1793632736
Short name T232
Test name
Test status
Simulation time 18148554 ps
CPU time 1 seconds
Started Aug 18 06:10:01 PM PDT 24
Finished Aug 18 06:10:02 PM PDT 24
Peak memory 215444 kb
Host smart-81d08c47-d9a0-4828-bc16-1084b528090e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793632736 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.1793632736
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.2746277458
Short name T142
Test name
Test status
Simulation time 133100132 ps
CPU time 1.1 seconds
Started Aug 18 06:11:03 PM PDT 24
Finished Aug 18 06:11:04 PM PDT 24
Peak memory 216856 kb
Host smart-a309dc6d-80e0-471f-8612-721a1de0254a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746277458 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.2746277458
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/144.edn_genbits.1768750654
Short name T3
Test name
Test status
Simulation time 87598899 ps
CPU time 1.51 seconds
Started Aug 18 06:12:17 PM PDT 24
Finished Aug 18 06:12:19 PM PDT 24
Peak memory 218724 kb
Host smart-40e218e6-4db1-4018-8a7f-da5824e439fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768750654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1768750654
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_alert.1165081113
Short name T187
Test name
Test status
Simulation time 28002831 ps
CPU time 1.25 seconds
Started Aug 18 06:11:12 PM PDT 24
Finished Aug 18 06:11:13 PM PDT 24
Peak memory 220796 kb
Host smart-b7e56b10-ac48-4fe3-818d-495f602e3c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165081113 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.1165081113
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/187.edn_alert.654761907
Short name T163
Test name
Test status
Simulation time 43531768 ps
CPU time 1.13 seconds
Started Aug 18 06:12:50 PM PDT 24
Finished Aug 18 06:12:51 PM PDT 24
Peak memory 218840 kb
Host smart-305d4081-507a-4724-90d5-36d6568e2e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654761907 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.654761907
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/42.edn_intr.1835218414
Short name T26
Test name
Test status
Simulation time 25209315 ps
CPU time 1.04 seconds
Started Aug 18 06:11:26 PM PDT 24
Finished Aug 18 06:11:27 PM PDT 24
Peak memory 215900 kb
Host smart-fff29a5b-8fef-4e9b-a1cf-c50e62e29b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835218414 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.1835218414
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/52.edn_err.1275406846
Short name T8
Test name
Test status
Simulation time 23217840 ps
CPU time 1.17 seconds
Started Aug 18 06:11:39 PM PDT 24
Finished Aug 18 06:11:40 PM PDT 24
Peak memory 219832 kb
Host smart-9103bb15-a7dc-4948-9801-8a80ce87f412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275406846 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.1275406846
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/154.edn_genbits.38091364
Short name T321
Test name
Test status
Simulation time 108866964 ps
CPU time 1.29 seconds
Started Aug 18 06:12:13 PM PDT 24
Finished Aug 18 06:12:15 PM PDT 24
Peak memory 219412 kb
Host smart-c08b4b9e-4904-40eb-887a-c3aed1d43055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38091364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.38091364
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.3718745207
Short name T168
Test name
Test status
Simulation time 33188980 ps
CPU time 1.3 seconds
Started Aug 18 06:12:14 PM PDT 24
Finished Aug 18 06:12:16 PM PDT 24
Peak memory 218688 kb
Host smart-467f75bd-aa95-4907-ae1a-b6a6e8180aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718745207 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.3718745207
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/155.edn_alert.56874260
Short name T336
Test name
Test status
Simulation time 43701245 ps
CPU time 1.2 seconds
Started Aug 18 06:12:14 PM PDT 24
Finished Aug 18 06:12:15 PM PDT 24
Peak memory 220940 kb
Host smart-e32b1497-1d06-437d-8cd5-b836082d0f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56874260 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.56874260
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/14.edn_disable.2893714802
Short name T204
Test name
Test status
Simulation time 14798007 ps
CPU time 0.92 seconds
Started Aug 18 06:10:40 PM PDT 24
Finished Aug 18 06:10:41 PM PDT 24
Peak memory 215576 kb
Host smart-61b9f8d7-22ee-463d-820c-eb8642c47a4e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893714802 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.2893714802
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/183.edn_alert.4177070188
Short name T151
Test name
Test status
Simulation time 33025514 ps
CPU time 1.29 seconds
Started Aug 18 06:12:26 PM PDT 24
Finished Aug 18 06:12:28 PM PDT 24
Peak memory 218724 kb
Host smart-aba5564d-3d9d-4603-bd32-0232a30d0dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177070188 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.4177070188
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert.4273972731
Short name T15
Test name
Test status
Simulation time 78786644 ps
CPU time 1.2 seconds
Started Aug 18 06:10:48 PM PDT 24
Finished Aug 18 06:10:50 PM PDT 24
Peak memory 219692 kb
Host smart-3fdf2b55-d319-4ede-9384-c23dc196187e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273972731 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.4273972731
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert.1028361125
Short name T206
Test name
Test status
Simulation time 66386054 ps
CPU time 1.13 seconds
Started Aug 18 06:09:58 PM PDT 24
Finished Aug 18 06:09:59 PM PDT 24
Peak memory 219692 kb
Host smart-7af974db-8209-4597-9c78-43240ea9a8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028361125 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.1028361125
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/11.edn_disable.2944705188
Short name T546
Test name
Test status
Simulation time 11410553 ps
CPU time 0.89 seconds
Started Aug 18 06:10:33 PM PDT 24
Finished Aug 18 06:10:34 PM PDT 24
Peak memory 215404 kb
Host smart-e3c01df7-bd89-484b-b8b1-2d62ff8ac94c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944705188 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2944705188
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/118.edn_alert.4140813225
Short name T201
Test name
Test status
Simulation time 21824110 ps
CPU time 1.16 seconds
Started Aug 18 06:12:04 PM PDT 24
Finished Aug 18 06:12:05 PM PDT 24
Peak memory 218976 kb
Host smart-5425dd9f-69cc-4222-bc7b-8bea5e2546ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140813225 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.4140813225
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3120228825
Short name T538
Test name
Test status
Simulation time 85696894 ps
CPU time 1.08 seconds
Started Aug 18 06:10:38 PM PDT 24
Finished Aug 18 06:10:39 PM PDT 24
Peak memory 218580 kb
Host smart-61eafafc-6c46-456f-b75a-d6e1a1ff2b56
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120228825 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3120228825
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/126.edn_alert.296857825
Short name T848
Test name
Test status
Simulation time 63136836 ps
CPU time 1.08 seconds
Started Aug 18 06:12:03 PM PDT 24
Finished Aug 18 06:12:04 PM PDT 24
Peak memory 219720 kb
Host smart-0daaeb6b-93e8-4269-acce-c9dce87225d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296857825 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.296857825
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/134.edn_alert.346410610
Short name T164
Test name
Test status
Simulation time 63733695 ps
CPU time 1.08 seconds
Started Aug 18 06:12:15 PM PDT 24
Finished Aug 18 06:12:16 PM PDT 24
Peak memory 218740 kb
Host smart-f5722b45-4e2c-4404-8191-acb4710b99f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346410610 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.346410610
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.2586660557
Short name T220
Test name
Test status
Simulation time 32145480 ps
CPU time 1.18 seconds
Started Aug 18 06:10:41 PM PDT 24
Finished Aug 18 06:10:42 PM PDT 24
Peak memory 219960 kb
Host smart-ff991616-8a41-4766-86fc-f2eb19661008
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586660557 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.2586660557
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_disable.4273550188
Short name T481
Test name
Test status
Simulation time 41771186 ps
CPU time 0.9 seconds
Started Aug 18 06:10:48 PM PDT 24
Finished Aug 18 06:10:49 PM PDT 24
Peak memory 215460 kb
Host smart-3e729d5e-b31a-4095-8100-941f4538fd18
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273550188 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.4273550188
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/175.edn_alert.2249210910
Short name T156
Test name
Test status
Simulation time 356543989 ps
CPU time 1.45 seconds
Started Aug 18 06:12:20 PM PDT 24
Finished Aug 18 06:12:21 PM PDT 24
Peak memory 215776 kb
Host smart-687e66fa-e609-4f14-a919-cd60af20194b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249210910 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.2249210910
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.278631781
Short name T172
Test name
Test status
Simulation time 28338246 ps
CPU time 1.18 seconds
Started Aug 18 06:10:49 PM PDT 24
Finished Aug 18 06:10:51 PM PDT 24
Peak memory 217040 kb
Host smart-92f2052d-2ef4-4d29-9f24-29c6aad5303c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278631781 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_di
sable_auto_req_mode.278631781
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.3973090312
Short name T52
Test name
Test status
Simulation time 23187760 ps
CPU time 1.06 seconds
Started Aug 18 06:10:51 PM PDT 24
Finished Aug 18 06:10:52 PM PDT 24
Peak memory 224088 kb
Host smart-50d8c5c8-1983-4365-bed9-4012f15612d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973090312 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.3973090312
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.566517679
Short name T150
Test name
Test status
Simulation time 78795612 ps
CPU time 1.09 seconds
Started Aug 18 06:11:01 PM PDT 24
Finished Aug 18 06:11:02 PM PDT 24
Peak memory 217072 kb
Host smart-04a9a546-feb9-49b3-9795-c15452363dad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566517679 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_di
sable_auto_req_mode.566517679
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_disable.2852123702
Short name T214
Test name
Test status
Simulation time 46377519 ps
CPU time 0.88 seconds
Started Aug 18 06:11:07 PM PDT 24
Finished Aug 18 06:11:08 PM PDT 24
Peak memory 207104 kb
Host smart-4bb294bf-4f8c-40f4-bf52-fb286e4c5478
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852123702 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2852123702
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/65.edn_err.3680118174
Short name T211
Test name
Test status
Simulation time 24933918 ps
CPU time 1.2 seconds
Started Aug 18 06:11:58 PM PDT 24
Finished Aug 18 06:11:59 PM PDT 24
Peak memory 229552 kb
Host smart-c9694d6e-cf56-458c-9f7e-7d15d4e8eccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680118174 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.3680118174
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/187.edn_genbits.1052798620
Short name T339
Test name
Test status
Simulation time 81881886 ps
CPU time 1.35 seconds
Started Aug 18 06:12:33 PM PDT 24
Finished Aug 18 06:12:35 PM PDT 24
Peak memory 218704 kb
Host smart-b7d018fe-24fa-4aaf-9757-b271a5855cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052798620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.1052798620
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.1592974100
Short name T44
Test name
Test status
Simulation time 102926550 ps
CPU time 1.39 seconds
Started Aug 18 06:12:42 PM PDT 24
Finished Aug 18 06:12:44 PM PDT 24
Peak memory 219612 kb
Host smart-e4f91823-a6d9-4071-a188-7fe591bc9637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592974100 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1592974100
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_alert_test.2292122659
Short name T69
Test name
Test status
Simulation time 26188317 ps
CPU time 0.92 seconds
Started Aug 18 06:10:29 PM PDT 24
Finished Aug 18 06:10:30 PM PDT 24
Peak memory 215012 kb
Host smart-1e0bf30f-40ac-4b97-b06a-9871c450b07a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292122659 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2292122659
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/102.edn_alert.3316266532
Short name T516
Test name
Test status
Simulation time 22962950 ps
CPU time 1.15 seconds
Started Aug 18 06:12:01 PM PDT 24
Finished Aug 18 06:12:03 PM PDT 24
Peak memory 218852 kb
Host smart-608708e8-856c-48a5-8a94-ed26ef6694c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316266532 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.3316266532
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/11.edn_genbits.1673910769
Short name T355
Test name
Test status
Simulation time 220370235 ps
CPU time 0.96 seconds
Started Aug 18 06:10:31 PM PDT 24
Finished Aug 18 06:10:32 PM PDT 24
Peak memory 217544 kb
Host smart-4a948c3e-61bb-4f38-a54c-891f75f9c4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673910769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1673910769
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.2161874026
Short name T338
Test name
Test status
Simulation time 138002629 ps
CPU time 1.39 seconds
Started Aug 18 06:12:04 PM PDT 24
Finished Aug 18 06:12:06 PM PDT 24
Peak memory 219036 kb
Host smart-542b5445-983d-4d40-a11e-67f7db556e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161874026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.2161874026
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_genbits.3272647042
Short name T366
Test name
Test status
Simulation time 35473409 ps
CPU time 1.35 seconds
Started Aug 18 06:11:59 PM PDT 24
Finished Aug 18 06:12:00 PM PDT 24
Peak memory 217176 kb
Host smart-8a8c0923-7fd5-4baa-9cd4-8ea217850205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272647042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.3272647042
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.268594567
Short name T6
Test name
Test status
Simulation time 44124914 ps
CPU time 1.03 seconds
Started Aug 18 06:11:50 PM PDT 24
Finished Aug 18 06:11:51 PM PDT 24
Peak memory 219652 kb
Host smart-db9c3483-0050-48a2-b284-5536f5207d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268594567 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.268594567
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/17.edn_intr.1095435768
Short name T28
Test name
Test status
Simulation time 21687590 ps
CPU time 1.13 seconds
Started Aug 18 06:10:52 PM PDT 24
Finished Aug 18 06:10:53 PM PDT 24
Peak memory 215672 kb
Host smart-9ec89f0e-6ac7-46e6-89fa-90e36d36cf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095435768 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1095435768
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/10.edn_intr.3638170034
Short name T103
Test name
Test status
Simulation time 23801557 ps
CPU time 0.92 seconds
Started Aug 18 06:10:33 PM PDT 24
Finished Aug 18 06:10:34 PM PDT 24
Peak memory 215996 kb
Host smart-0f9ca0e2-3f42-49df-b3b9-feb9f843fc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638170034 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3638170034
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1231697890
Short name T1107
Test name
Test status
Simulation time 86415593 ps
CPU time 2.34 seconds
Started Aug 18 05:57:06 PM PDT 24
Finished Aug 18 05:57:08 PM PDT 24
Peak memory 215324 kb
Host smart-17dbb4ac-5ee0-4790-8753-1712f3e2e301
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231697890 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1231697890
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/default/102.edn_genbits.3220875411
Short name T333
Test name
Test status
Simulation time 170285335 ps
CPU time 1.64 seconds
Started Aug 18 06:12:05 PM PDT 24
Finished Aug 18 06:12:06 PM PDT 24
Peak memory 219272 kb
Host smart-b22ca534-afd4-4f7d-bd1f-8cd449977ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220875411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3220875411
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.580409987
Short name T348
Test name
Test status
Simulation time 71823533 ps
CPU time 1.38 seconds
Started Aug 18 06:12:03 PM PDT 24
Finished Aug 18 06:12:05 PM PDT 24
Peak memory 218564 kb
Host smart-9739eb65-578d-4aca-8f9a-636ae8db6281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580409987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.580409987
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.796500247
Short name T680
Test name
Test status
Simulation time 54603980 ps
CPU time 1.21 seconds
Started Aug 18 06:12:04 PM PDT 24
Finished Aug 18 06:12:05 PM PDT 24
Peak memory 220792 kb
Host smart-e3f67b96-7892-47ef-b1f5-452e8bc8c75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796500247 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.796500247
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.4290381061
Short name T903
Test name
Test status
Simulation time 94110790 ps
CPU time 1.32 seconds
Started Aug 18 06:12:05 PM PDT 24
Finished Aug 18 06:12:07 PM PDT 24
Peak memory 218756 kb
Host smart-1372b3c6-dc9e-48b3-a60c-7b6cee8fb4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290381061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.4290381061
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/130.edn_genbits.4089066561
Short name T905
Test name
Test status
Simulation time 49540093 ps
CPU time 1.76 seconds
Started Aug 18 06:12:16 PM PDT 24
Finished Aug 18 06:12:18 PM PDT 24
Peak memory 218608 kb
Host smart-f5e69145-0918-4ef6-bb6e-13ef447332ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089066561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.4089066561
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.2355698682
Short name T342
Test name
Test status
Simulation time 58281249 ps
CPU time 1.28 seconds
Started Aug 18 06:12:16 PM PDT 24
Finished Aug 18 06:12:18 PM PDT 24
Peak memory 218628 kb
Host smart-0251111b-889e-4a77-a69b-b25d9033147c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355698682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2355698682
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_stress_all.2333673770
Short name T630
Test name
Test status
Simulation time 233161028 ps
CPU time 1.74 seconds
Started Aug 18 06:10:46 PM PDT 24
Finished Aug 18 06:10:48 PM PDT 24
Peak memory 215356 kb
Host smart-56f68673-49e4-49f7-9211-727f9449e585
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333673770 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.2333673770
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/177.edn_genbits.2794230322
Short name T353
Test name
Test status
Simulation time 66247925 ps
CPU time 1.91 seconds
Started Aug 18 06:12:20 PM PDT 24
Finished Aug 18 06:12:22 PM PDT 24
Peak memory 219092 kb
Host smart-df40655d-9f83-4f73-971a-b4f774878e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794230322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2794230322
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.781016575
Short name T359
Test name
Test status
Simulation time 61136341 ps
CPU time 1.32 seconds
Started Aug 18 06:12:30 PM PDT 24
Finished Aug 18 06:12:32 PM PDT 24
Peak memory 215436 kb
Host smart-d9c7569a-cb24-494e-bb3e-c367038061d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781016575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.781016575
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.427646846
Short name T597
Test name
Test status
Simulation time 61760226 ps
CPU time 1.35 seconds
Started Aug 18 06:12:36 PM PDT 24
Finished Aug 18 06:12:38 PM PDT 24
Peak memory 218412 kb
Host smart-b3186ad9-b682-4a4a-b476-688370f4f5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427646846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.427646846
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.3817869638
Short name T715
Test name
Test status
Simulation time 141294797 ps
CPU time 1.44 seconds
Started Aug 18 06:12:38 PM PDT 24
Finished Aug 18 06:12:39 PM PDT 24
Peak memory 218992 kb
Host smart-05706b60-a861-4495-aecf-ed53d0ef8bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817869638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.3817869638
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.3106726343
Short name T346
Test name
Test status
Simulation time 63108572 ps
CPU time 2.11 seconds
Started Aug 18 06:12:56 PM PDT 24
Finished Aug 18 06:12:59 PM PDT 24
Peak memory 219204 kb
Host smart-d8fede4e-6979-4ee3-a605-e820cc999c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106726343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3106726343
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.3343086638
Short name T114
Test name
Test status
Simulation time 378572828 ps
CPU time 1.44 seconds
Started Aug 18 06:12:20 PM PDT 24
Finished Aug 18 06:12:22 PM PDT 24
Peak memory 220300 kb
Host smart-ef094ca9-d15b-447b-b506-eec5f0c2dae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343086638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.3343086638
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.4170707008
Short name T1005
Test name
Test status
Simulation time 45962595 ps
CPU time 1.66 seconds
Started Aug 18 05:56:29 PM PDT 24
Finished Aug 18 05:56:31 PM PDT 24
Peak memory 207016 kb
Host smart-206861f2-8cba-4f3b-8d92-1f858a08e4d8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170707008 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.4170707008
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3686224058
Short name T996
Test name
Test status
Simulation time 179088099 ps
CPU time 5.21 seconds
Started Aug 18 05:56:30 PM PDT 24
Finished Aug 18 05:56:36 PM PDT 24
Peak memory 207028 kb
Host smart-e29c8676-6843-41cd-9da3-6ed48533ce73
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686224058 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3686224058
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.960954867
Short name T300
Test name
Test status
Simulation time 15425528 ps
CPU time 0.94 seconds
Started Aug 18 05:56:31 PM PDT 24
Finished Aug 18 05:56:32 PM PDT 24
Peak memory 207028 kb
Host smart-cd4005ed-b8be-4cc2-a8d8-cb0f7386c65e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960954867 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.960954867
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.140125118
Short name T1035
Test name
Test status
Simulation time 31500743 ps
CPU time 1.86 seconds
Started Aug 18 05:56:31 PM PDT 24
Finished Aug 18 05:56:33 PM PDT 24
Peak memory 215460 kb
Host smart-c6f8e6fd-05e1-46e4-bd6f-e8b34394674e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140125118 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.140125118
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2325347287
Short name T1063
Test name
Test status
Simulation time 13527367 ps
CPU time 0.92 seconds
Started Aug 18 05:56:29 PM PDT 24
Finished Aug 18 05:56:30 PM PDT 24
Peak memory 207036 kb
Host smart-7457b59b-7152-4a62-a0ef-e9807218fd2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325347287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2325347287
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1773689862
Short name T1011
Test name
Test status
Simulation time 46636800 ps
CPU time 0.88 seconds
Started Aug 18 05:56:30 PM PDT 24
Finished Aug 18 05:56:31 PM PDT 24
Peak memory 206904 kb
Host smart-9abacdbe-0150-4308-954a-9bd2b4414e5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773689862 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1773689862
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1127647582
Short name T1076
Test name
Test status
Simulation time 21374147 ps
CPU time 1.26 seconds
Started Aug 18 05:56:30 PM PDT 24
Finished Aug 18 05:56:31 PM PDT 24
Peak memory 207204 kb
Host smart-496fb641-f3ea-4271-9ab7-101175866b6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127647582 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.1127647582
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3879022135
Short name T1034
Test name
Test status
Simulation time 412754166 ps
CPU time 3.61 seconds
Started Aug 18 05:56:35 PM PDT 24
Finished Aug 18 05:56:38 PM PDT 24
Peak memory 215280 kb
Host smart-1ea522e5-4259-467b-9d3d-a49dedb0c65c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879022135 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3879022135
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2059599989
Short name T292
Test name
Test status
Simulation time 18365217 ps
CPU time 1.21 seconds
Started Aug 18 05:56:41 PM PDT 24
Finished Aug 18 05:56:43 PM PDT 24
Peak memory 207092 kb
Host smart-fb83d2af-38e4-4579-945e-e84a33eff620
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059599989 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2059599989
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3105799630
Short name T1080
Test name
Test status
Simulation time 141836256 ps
CPU time 3.71 seconds
Started Aug 18 05:56:42 PM PDT 24
Finished Aug 18 05:56:46 PM PDT 24
Peak memory 207128 kb
Host smart-a88a2146-dc44-411d-8a4f-f4f308e292b6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105799630 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3105799630
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3084019033
Short name T298
Test name
Test status
Simulation time 16590419 ps
CPU time 0.98 seconds
Started Aug 18 05:56:31 PM PDT 24
Finished Aug 18 05:56:32 PM PDT 24
Peak memory 207064 kb
Host smart-69cab263-26cd-436b-9cab-658847895315
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084019033 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3084019033
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.411405138
Short name T995
Test name
Test status
Simulation time 77405576 ps
CPU time 1.16 seconds
Started Aug 18 05:56:42 PM PDT 24
Finished Aug 18 05:56:44 PM PDT 24
Peak memory 216960 kb
Host smart-4a4a315a-5d7e-4abb-b3f1-9d8d485f4d7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411405138 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.411405138
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.3013864818
Short name T1088
Test name
Test status
Simulation time 72150335 ps
CPU time 0.89 seconds
Started Aug 18 05:56:30 PM PDT 24
Finished Aug 18 05:56:31 PM PDT 24
Peak memory 206824 kb
Host smart-922f3a29-9eb7-40d5-a6f5-e72ea15bd624
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013864818 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3013864818
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.1359622637
Short name T989
Test name
Test status
Simulation time 25898536 ps
CPU time 0.89 seconds
Started Aug 18 05:56:30 PM PDT 24
Finished Aug 18 05:56:31 PM PDT 24
Peak memory 206972 kb
Host smart-b1da0e63-9f4e-4728-955f-39fc12556da3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359622637 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.1359622637
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1600322227
Short name T1094
Test name
Test status
Simulation time 21624825 ps
CPU time 1.11 seconds
Started Aug 18 05:56:44 PM PDT 24
Finished Aug 18 05:56:45 PM PDT 24
Peak memory 207348 kb
Host smart-3d3b2072-e63a-44b0-8a7f-2dea0db8fad8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600322227 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.1600322227
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.3432605501
Short name T1037
Test name
Test status
Simulation time 90478943 ps
CPU time 2.03 seconds
Started Aug 18 05:56:30 PM PDT 24
Finished Aug 18 05:56:32 PM PDT 24
Peak memory 215280 kb
Host smart-523c73e0-d1b0-47dd-bdc3-3619e8c02fbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432605501 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3432605501
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2400321013
Short name T1002
Test name
Test status
Simulation time 335058751 ps
CPU time 2.32 seconds
Started Aug 18 05:56:30 PM PDT 24
Finished Aug 18 05:56:32 PM PDT 24
Peak memory 207196 kb
Host smart-ec9919c9-e430-4da9-a740-b8b402c36a1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400321013 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2400321013
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3575896282
Short name T1070
Test name
Test status
Simulation time 278901393 ps
CPU time 1.32 seconds
Started Aug 18 05:57:00 PM PDT 24
Finished Aug 18 05:57:02 PM PDT 24
Peak memory 215376 kb
Host smart-6be476d8-5f6b-409a-ae9d-8b9a3a32d709
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575896282 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3575896282
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.310736303
Short name T293
Test name
Test status
Simulation time 42756498 ps
CPU time 0.84 seconds
Started Aug 18 05:57:00 PM PDT 24
Finished Aug 18 05:57:01 PM PDT 24
Peak memory 206876 kb
Host smart-db97cdeb-a7d2-44e3-97d2-9be319a9712b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310736303 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.310736303
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.3145723916
Short name T987
Test name
Test status
Simulation time 47200836 ps
CPU time 0.89 seconds
Started Aug 18 05:56:56 PM PDT 24
Finished Aug 18 05:56:57 PM PDT 24
Peak memory 206976 kb
Host smart-f7de7e0b-e1a9-49d4-a14a-8be7dd1b6007
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145723916 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.3145723916
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2522397362
Short name T1108
Test name
Test status
Simulation time 13391012 ps
CPU time 1.01 seconds
Started Aug 18 05:56:57 PM PDT 24
Finished Aug 18 05:56:58 PM PDT 24
Peak memory 207036 kb
Host smart-eef98f09-512a-48ee-a6c9-5f1d4752ccb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522397362 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2522397362
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2679095445
Short name T1045
Test name
Test status
Simulation time 241291845 ps
CPU time 4.16 seconds
Started Aug 18 05:57:00 PM PDT 24
Finished Aug 18 05:57:04 PM PDT 24
Peak memory 215316 kb
Host smart-2f7eb194-7125-4e6c-8af1-8868ff16f843
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679095445 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2679095445
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1130227363
Short name T1004
Test name
Test status
Simulation time 90359173 ps
CPU time 2.39 seconds
Started Aug 18 05:56:57 PM PDT 24
Finished Aug 18 05:57:00 PM PDT 24
Peak memory 207160 kb
Host smart-c09930a3-e11c-4b9d-81da-6bfbea709e12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130227363 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1130227363
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1487469509
Short name T1095
Test name
Test status
Simulation time 154083803 ps
CPU time 1.02 seconds
Started Aug 18 05:56:58 PM PDT 24
Finished Aug 18 05:56:59 PM PDT 24
Peak memory 207068 kb
Host smart-79816f3e-2540-48a2-86ed-8844a1302c84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487469509 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.1487469509
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.2569611469
Short name T299
Test name
Test status
Simulation time 28343671 ps
CPU time 0.82 seconds
Started Aug 18 05:56:58 PM PDT 24
Finished Aug 18 05:57:00 PM PDT 24
Peak memory 206884 kb
Host smart-c05e48e4-53ca-4c0f-8584-d0a9f3d961cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569611469 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.2569611469
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.3506504935
Short name T983
Test name
Test status
Simulation time 14670050 ps
CPU time 0.9 seconds
Started Aug 18 05:56:56 PM PDT 24
Finished Aug 18 05:56:57 PM PDT 24
Peak memory 206972 kb
Host smart-2e76caa6-7163-4d06-9242-43058d6cb2f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506504935 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.3506504935
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3583896341
Short name T1022
Test name
Test status
Simulation time 42211056 ps
CPU time 1.25 seconds
Started Aug 18 05:56:56 PM PDT 24
Finished Aug 18 05:56:57 PM PDT 24
Peak memory 207132 kb
Host smart-4a713ed7-4eae-48f7-84dc-eda4014c33ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583896341 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3583896341
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.2737679166
Short name T1086
Test name
Test status
Simulation time 42111077 ps
CPU time 1.8 seconds
Started Aug 18 05:56:58 PM PDT 24
Finished Aug 18 05:56:59 PM PDT 24
Peak memory 215336 kb
Host smart-62000235-4127-4c91-b467-efa425ad43f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737679166 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2737679166
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1472950497
Short name T1055
Test name
Test status
Simulation time 67648130 ps
CPU time 1.38 seconds
Started Aug 18 05:56:58 PM PDT 24
Finished Aug 18 05:57:00 PM PDT 24
Peak memory 207100 kb
Host smart-b5033c60-bd94-4f96-b3cd-b35299e818ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472950497 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1472950497
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2447564294
Short name T1075
Test name
Test status
Simulation time 31728135 ps
CPU time 1.42 seconds
Started Aug 18 05:57:08 PM PDT 24
Finished Aug 18 05:57:10 PM PDT 24
Peak memory 215460 kb
Host smart-f6aa48b6-bf95-4814-849d-3a08dd1f9fef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447564294 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.2447564294
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2861064288
Short name T297
Test name
Test status
Simulation time 73172326 ps
CPU time 0.82 seconds
Started Aug 18 05:57:07 PM PDT 24
Finished Aug 18 05:57:08 PM PDT 24
Peak memory 206856 kb
Host smart-9e12bac2-fb59-4edc-bf6d-987c94a945b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861064288 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2861064288
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.923665602
Short name T1010
Test name
Test status
Simulation time 13258165 ps
CPU time 0.9 seconds
Started Aug 18 05:57:05 PM PDT 24
Finished Aug 18 05:57:06 PM PDT 24
Peak memory 206948 kb
Host smart-6d6aa134-c7bc-4869-a277-9f42c2b8dcaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923665602 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.923665602
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1961376094
Short name T1066
Test name
Test status
Simulation time 38731377 ps
CPU time 0.95 seconds
Started Aug 18 05:57:06 PM PDT 24
Finished Aug 18 05:57:07 PM PDT 24
Peak memory 207136 kb
Host smart-4dd9c888-464f-4437-899b-ae1034339f9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961376094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1961376094
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.851429044
Short name T1051
Test name
Test status
Simulation time 80483177 ps
CPU time 2.96 seconds
Started Aug 18 05:57:09 PM PDT 24
Finished Aug 18 05:57:13 PM PDT 24
Peak memory 215300 kb
Host smart-9bba09a8-402f-43a1-bc63-38e62a33ced6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851429044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.851429044
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.426331414
Short name T284
Test name
Test status
Simulation time 1011434622 ps
CPU time 2.64 seconds
Started Aug 18 05:57:06 PM PDT 24
Finished Aug 18 05:57:09 PM PDT 24
Peak memory 207196 kb
Host smart-3c3edca2-45f3-4a63-8933-6752b8de4373
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426331414 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.426331414
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.539032184
Short name T1047
Test name
Test status
Simulation time 24061391 ps
CPU time 1.22 seconds
Started Aug 18 05:57:08 PM PDT 24
Finished Aug 18 05:57:09 PM PDT 24
Peak memory 215408 kb
Host smart-f7784e97-1c50-4ade-83d3-da10b26e2ff4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539032184 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.539032184
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.1291916519
Short name T1014
Test name
Test status
Simulation time 11190171 ps
CPU time 0.82 seconds
Started Aug 18 05:57:10 PM PDT 24
Finished Aug 18 05:57:11 PM PDT 24
Peak memory 206952 kb
Host smart-b4ea450e-02d4-4d1e-a30a-b69783b8fc8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291916519 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1291916519
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.376244667
Short name T1003
Test name
Test status
Simulation time 16674637 ps
CPU time 0.96 seconds
Started Aug 18 05:57:07 PM PDT 24
Finished Aug 18 05:57:08 PM PDT 24
Peak memory 206988 kb
Host smart-020d0b6e-727b-4f90-b2ae-c857a49cf2a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376244667 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.376244667
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1930393268
Short name T310
Test name
Test status
Simulation time 29517593 ps
CPU time 1.06 seconds
Started Aug 18 05:57:09 PM PDT 24
Finished Aug 18 05:57:10 PM PDT 24
Peak memory 207164 kb
Host smart-2a5e95ff-1505-4ce4-8e32-469830ebf7a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930393268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.1930393268
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.1046157870
Short name T1061
Test name
Test status
Simulation time 478159886 ps
CPU time 4.04 seconds
Started Aug 18 05:57:10 PM PDT 24
Finished Aug 18 05:57:14 PM PDT 24
Peak memory 215232 kb
Host smart-0dee4e28-6014-42a4-a929-fbb68ebaea8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046157870 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1046157870
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1337714591
Short name T991
Test name
Test status
Simulation time 79655560 ps
CPU time 2.38 seconds
Started Aug 18 05:57:10 PM PDT 24
Finished Aug 18 05:57:13 PM PDT 24
Peak memory 207556 kb
Host smart-8b80b215-d9de-4d40-8bd8-c527a0fcf061
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337714591 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1337714591
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1689730807
Short name T1098
Test name
Test status
Simulation time 21985155 ps
CPU time 1.41 seconds
Started Aug 18 05:57:08 PM PDT 24
Finished Aug 18 05:57:10 PM PDT 24
Peak memory 215400 kb
Host smart-4fc08f9e-3a5e-456b-acbc-f8d9d7d57799
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689730807 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1689730807
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.2755629844
Short name T302
Test name
Test status
Simulation time 36551776 ps
CPU time 0.85 seconds
Started Aug 18 05:57:06 PM PDT 24
Finished Aug 18 05:57:07 PM PDT 24
Peak memory 206964 kb
Host smart-8270de22-6ff3-42f3-ad10-6c10c9a69d45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755629844 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2755629844
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.675922383
Short name T1056
Test name
Test status
Simulation time 83547558 ps
CPU time 0.88 seconds
Started Aug 18 05:57:09 PM PDT 24
Finished Aug 18 05:57:10 PM PDT 24
Peak memory 206788 kb
Host smart-10b8f495-7ffb-44d0-8a82-f0670b75cc83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675922383 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.675922383
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.284778925
Short name T308
Test name
Test status
Simulation time 22726228 ps
CPU time 1.16 seconds
Started Aug 18 05:57:08 PM PDT 24
Finished Aug 18 05:57:10 PM PDT 24
Peak memory 207136 kb
Host smart-eac7da7f-5183-4805-889c-9e535fed74f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284778925 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_ou
tstanding.284778925
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.555978644
Short name T1043
Test name
Test status
Simulation time 27245550 ps
CPU time 1.85 seconds
Started Aug 18 05:57:07 PM PDT 24
Finished Aug 18 05:57:09 PM PDT 24
Peak memory 223404 kb
Host smart-bdbde6d0-44ef-4dda-826a-1db1cc77de60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555978644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.555978644
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2030860813
Short name T264
Test name
Test status
Simulation time 37443803 ps
CPU time 1.25 seconds
Started Aug 18 05:57:06 PM PDT 24
Finished Aug 18 05:57:08 PM PDT 24
Peak memory 215328 kb
Host smart-5fe22fcf-0ef6-4c25-9a1e-7fa96c6d472b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030860813 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2030860813
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.3787995300
Short name T307
Test name
Test status
Simulation time 23116004 ps
CPU time 0.86 seconds
Started Aug 18 05:57:06 PM PDT 24
Finished Aug 18 05:57:07 PM PDT 24
Peak memory 207052 kb
Host smart-426b22e5-eb07-47b6-bade-2574aa3e4ca2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787995300 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.3787995300
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3381452876
Short name T1101
Test name
Test status
Simulation time 57802253 ps
CPU time 0.87 seconds
Started Aug 18 05:57:06 PM PDT 24
Finished Aug 18 05:57:07 PM PDT 24
Peak memory 206988 kb
Host smart-71d85dee-c43b-46a0-85b5-8cb54806b22f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381452876 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3381452876
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2920493725
Short name T1050
Test name
Test status
Simulation time 18924569 ps
CPU time 1.22 seconds
Started Aug 18 05:57:08 PM PDT 24
Finished Aug 18 05:57:09 PM PDT 24
Peak memory 207152 kb
Host smart-ee76cf4f-a5d7-483b-b845-3844ecd47685
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920493725 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.2920493725
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.2234247804
Short name T984
Test name
Test status
Simulation time 81412486 ps
CPU time 1.87 seconds
Started Aug 18 05:57:08 PM PDT 24
Finished Aug 18 05:57:10 PM PDT 24
Peak memory 215328 kb
Host smart-83936cde-e8b2-4f14-9a48-4a9c3148666e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234247804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2234247804
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.287331664
Short name T325
Test name
Test status
Simulation time 260527695 ps
CPU time 1.4 seconds
Started Aug 18 05:57:06 PM PDT 24
Finished Aug 18 05:57:07 PM PDT 24
Peak memory 207180 kb
Host smart-bd5c0c1e-aa00-44d2-a5cb-2d7b689fdb0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287331664 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.287331664
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2352898607
Short name T1048
Test name
Test status
Simulation time 30458638 ps
CPU time 1.05 seconds
Started Aug 18 05:57:15 PM PDT 24
Finished Aug 18 05:57:16 PM PDT 24
Peak memory 215364 kb
Host smart-04d98680-d7dc-4c6c-855a-9065e39a8da3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352898607 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2352898607
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.853474234
Short name T999
Test name
Test status
Simulation time 13571465 ps
CPU time 0.89 seconds
Started Aug 18 05:57:06 PM PDT 24
Finished Aug 18 05:57:07 PM PDT 24
Peak memory 206968 kb
Host smart-a5f3fe19-160e-4c3a-9bcf-bae6ae81607f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853474234 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.853474234
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3249812028
Short name T979
Test name
Test status
Simulation time 32946298 ps
CPU time 0.82 seconds
Started Aug 18 05:57:08 PM PDT 24
Finished Aug 18 05:57:09 PM PDT 24
Peak memory 206760 kb
Host smart-09db9157-7b97-4d6e-b719-5b065338f051
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249812028 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3249812028
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3191051502
Short name T1016
Test name
Test status
Simulation time 18059554 ps
CPU time 1.07 seconds
Started Aug 18 05:57:06 PM PDT 24
Finished Aug 18 05:57:07 PM PDT 24
Peak memory 207176 kb
Host smart-200a9624-eb3f-4c4b-83dd-88bb2eab6edd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191051502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3191051502
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.612112784
Short name T1054
Test name
Test status
Simulation time 934858565 ps
CPU time 3.56 seconds
Started Aug 18 05:57:08 PM PDT 24
Finished Aug 18 05:57:12 PM PDT 24
Peak memory 215312 kb
Host smart-b05177c8-7ab1-4f87-baec-1492f173134c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612112784 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.612112784
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.4152742945
Short name T327
Test name
Test status
Simulation time 273278624 ps
CPU time 1.39 seconds
Started Aug 18 05:57:10 PM PDT 24
Finished Aug 18 05:57:11 PM PDT 24
Peak memory 207084 kb
Host smart-3d6ab11b-584e-490b-be9a-608c58f07d41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152742945 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.4152742945
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2060646980
Short name T1019
Test name
Test status
Simulation time 35091735 ps
CPU time 1.09 seconds
Started Aug 18 05:57:15 PM PDT 24
Finished Aug 18 05:57:16 PM PDT 24
Peak memory 217048 kb
Host smart-402d46a6-959a-40b6-91df-30845e1e3adb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060646980 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2060646980
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.2549699357
Short name T1065
Test name
Test status
Simulation time 13588228 ps
CPU time 0.86 seconds
Started Aug 18 05:57:13 PM PDT 24
Finished Aug 18 05:57:14 PM PDT 24
Peak memory 206956 kb
Host smart-e8190280-132b-43a3-b493-d086f0764a02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549699357 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.2549699357
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1891655958
Short name T1012
Test name
Test status
Simulation time 38167215 ps
CPU time 1.07 seconds
Started Aug 18 05:57:15 PM PDT 24
Finished Aug 18 05:57:16 PM PDT 24
Peak memory 207076 kb
Host smart-f99f2d95-1257-46c1-801f-5704fec0cb04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891655958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.1891655958
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.2659776117
Short name T1027
Test name
Test status
Simulation time 28585737 ps
CPU time 1.68 seconds
Started Aug 18 05:57:16 PM PDT 24
Finished Aug 18 05:57:18 PM PDT 24
Peak memory 215516 kb
Host smart-d2f20520-7d86-43db-adae-e3fcb640a80a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659776117 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2659776117
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3764635452
Short name T326
Test name
Test status
Simulation time 93241110 ps
CPU time 2.52 seconds
Started Aug 18 05:57:21 PM PDT 24
Finished Aug 18 05:57:24 PM PDT 24
Peak memory 207188 kb
Host smart-64e48210-f3b4-4f79-84d0-294a2f340d3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764635452 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3764635452
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.76464578
Short name T1001
Test name
Test status
Simulation time 19705567 ps
CPU time 1.2 seconds
Started Aug 18 05:57:21 PM PDT 24
Finished Aug 18 05:57:23 PM PDT 24
Peak memory 215388 kb
Host smart-5e374385-9508-46c5-bad1-c2d525846982
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76464578 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.76464578
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1588684529
Short name T294
Test name
Test status
Simulation time 22724100 ps
CPU time 0.87 seconds
Started Aug 18 05:57:14 PM PDT 24
Finished Aug 18 05:57:15 PM PDT 24
Peak memory 207028 kb
Host smart-40cd7042-d6da-4fae-82ef-84e827a45b4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588684529 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1588684529
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.4258642848
Short name T1103
Test name
Test status
Simulation time 75634821 ps
CPU time 0.8 seconds
Started Aug 18 05:57:21 PM PDT 24
Finished Aug 18 05:57:22 PM PDT 24
Peak memory 206836 kb
Host smart-30787284-86ac-46e2-9fe4-ab71cedf3da7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258642848 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.4258642848
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2474874217
Short name T304
Test name
Test status
Simulation time 69928439 ps
CPU time 1.07 seconds
Started Aug 18 05:57:27 PM PDT 24
Finished Aug 18 05:57:28 PM PDT 24
Peak memory 207204 kb
Host smart-bdb4df2b-bd07-4450-a84f-9adaa733b80f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474874217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.2474874217
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.164247849
Short name T1059
Test name
Test status
Simulation time 136854703 ps
CPU time 2.61 seconds
Started Aug 18 05:57:15 PM PDT 24
Finished Aug 18 05:57:18 PM PDT 24
Peak memory 215324 kb
Host smart-91da34cd-61f0-4d70-b285-87ddbe91576a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164247849 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.164247849
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.558046109
Short name T1049
Test name
Test status
Simulation time 193298353 ps
CPU time 1.57 seconds
Started Aug 18 05:57:14 PM PDT 24
Finished Aug 18 05:57:15 PM PDT 24
Peak memory 215328 kb
Host smart-73913962-6791-4654-a677-893e90091212
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558046109 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.558046109
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.42550121
Short name T977
Test name
Test status
Simulation time 44610388 ps
CPU time 1.18 seconds
Started Aug 18 05:57:12 PM PDT 24
Finished Aug 18 05:57:13 PM PDT 24
Peak memory 215288 kb
Host smart-2922db88-edf9-4166-a8c7-ed39589a60c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42550121 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.42550121
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2345433010
Short name T296
Test name
Test status
Simulation time 19406558 ps
CPU time 0.96 seconds
Started Aug 18 05:57:13 PM PDT 24
Finished Aug 18 05:57:14 PM PDT 24
Peak memory 207064 kb
Host smart-0bff242a-ecdb-4b46-a410-066c08ea351e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345433010 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2345433010
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.1953307669
Short name T992
Test name
Test status
Simulation time 47695930 ps
CPU time 0.88 seconds
Started Aug 18 05:57:13 PM PDT 24
Finished Aug 18 05:57:14 PM PDT 24
Peak memory 206948 kb
Host smart-f3a8ab87-7222-488b-a127-2a3f4cb36069
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953307669 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.1953307669
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3080281492
Short name T1090
Test name
Test status
Simulation time 81521159 ps
CPU time 1.12 seconds
Started Aug 18 05:57:12 PM PDT 24
Finished Aug 18 05:57:14 PM PDT 24
Peak memory 207124 kb
Host smart-0082238c-92e7-473a-9d41-28e565c6c8c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080281492 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.3080281492
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1166244785
Short name T1089
Test name
Test status
Simulation time 170410336 ps
CPU time 2.96 seconds
Started Aug 18 05:57:22 PM PDT 24
Finished Aug 18 05:57:25 PM PDT 24
Peak memory 215328 kb
Host smart-2390dcc7-f832-4248-8bf9-2a012ed80b1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166244785 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1166244785
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1612725636
Short name T316
Test name
Test status
Simulation time 145045012 ps
CPU time 2.23 seconds
Started Aug 18 05:57:15 PM PDT 24
Finished Aug 18 05:57:17 PM PDT 24
Peak memory 207152 kb
Host smart-961764a2-62f3-4e30-b6cc-bb5a5bda1d2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612725636 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1612725636
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2693928905
Short name T301
Test name
Test status
Simulation time 25416609 ps
CPU time 1.04 seconds
Started Aug 18 05:56:41 PM PDT 24
Finished Aug 18 05:56:42 PM PDT 24
Peak memory 207136 kb
Host smart-22db3981-92a7-4523-9098-5c61561c89ab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693928905 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.2693928905
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2580154179
Short name T1087
Test name
Test status
Simulation time 702406371 ps
CPU time 4.85 seconds
Started Aug 18 05:56:41 PM PDT 24
Finished Aug 18 05:56:46 PM PDT 24
Peak memory 207020 kb
Host smart-447767ac-7cb7-43ba-9aa8-6ec3acdf8ad6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580154179 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2580154179
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2826502855
Short name T1102
Test name
Test status
Simulation time 22714686 ps
CPU time 0.9 seconds
Started Aug 18 05:56:41 PM PDT 24
Finished Aug 18 05:56:42 PM PDT 24
Peak memory 207052 kb
Host smart-4dd21155-56b2-439d-a5b1-ef965f619303
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826502855 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2826502855
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3085431592
Short name T1068
Test name
Test status
Simulation time 60335670 ps
CPU time 1.05 seconds
Started Aug 18 05:56:40 PM PDT 24
Finished Aug 18 05:56:41 PM PDT 24
Peak memory 207208 kb
Host smart-76818b8f-0e86-4045-9f2c-e884e61181ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085431592 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3085431592
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2095622939
Short name T1106
Test name
Test status
Simulation time 136994905 ps
CPU time 0.88 seconds
Started Aug 18 05:56:41 PM PDT 24
Finished Aug 18 05:56:41 PM PDT 24
Peak memory 206784 kb
Host smart-ccc945f1-27fa-48d3-8d6f-e8c604494b9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095622939 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2095622939
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.4222414389
Short name T1046
Test name
Test status
Simulation time 33055341 ps
CPU time 0.78 seconds
Started Aug 18 05:56:41 PM PDT 24
Finished Aug 18 05:56:42 PM PDT 24
Peak memory 206828 kb
Host smart-5aa0ccc2-f092-4972-a7d1-4cade1b7bef6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222414389 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.4222414389
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2636605707
Short name T309
Test name
Test status
Simulation time 38690120 ps
CPU time 1.5 seconds
Started Aug 18 05:56:40 PM PDT 24
Finished Aug 18 05:56:41 PM PDT 24
Peak memory 207132 kb
Host smart-5affabd3-59bb-475c-a402-1f39850ea9fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636605707 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2636605707
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.696695745
Short name T982
Test name
Test status
Simulation time 257121111 ps
CPU time 2.64 seconds
Started Aug 18 05:56:41 PM PDT 24
Finished Aug 18 05:56:44 PM PDT 24
Peak memory 215228 kb
Host smart-ad9342c8-4457-455f-aea5-22539a7fd99b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696695745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.696695745
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.205892356
Short name T1079
Test name
Test status
Simulation time 194904708 ps
CPU time 1.6 seconds
Started Aug 18 05:56:42 PM PDT 24
Finished Aug 18 05:56:43 PM PDT 24
Peak memory 207072 kb
Host smart-18c175c6-7c42-4115-b63c-0c16ad47a707
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205892356 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.205892356
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.2268716717
Short name T1081
Test name
Test status
Simulation time 40601615 ps
CPU time 0.89 seconds
Started Aug 18 05:57:13 PM PDT 24
Finished Aug 18 05:57:14 PM PDT 24
Peak memory 206964 kb
Host smart-93becd91-46a9-4e1c-baeb-3ba3e85577ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268716717 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.2268716717
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.2980566343
Short name T997
Test name
Test status
Simulation time 16253878 ps
CPU time 0.78 seconds
Started Aug 18 05:57:14 PM PDT 24
Finished Aug 18 05:57:15 PM PDT 24
Peak memory 206816 kb
Host smart-b561676c-711b-4c36-9ad8-f800001d8447
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980566343 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.2980566343
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.84914083
Short name T1083
Test name
Test status
Simulation time 21374221 ps
CPU time 0.81 seconds
Started Aug 18 05:57:14 PM PDT 24
Finished Aug 18 05:57:15 PM PDT 24
Peak memory 206928 kb
Host smart-cd6f0264-e26e-4d89-a72a-4dad8fa5f32f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84914083 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.84914083
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.1574627175
Short name T1078
Test name
Test status
Simulation time 22861295 ps
CPU time 0.87 seconds
Started Aug 18 05:57:15 PM PDT 24
Finished Aug 18 05:57:16 PM PDT 24
Peak memory 206960 kb
Host smart-28ce7989-37c3-4408-9bea-60ddeb51a4c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574627175 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.1574627175
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.873183100
Short name T1032
Test name
Test status
Simulation time 16246639 ps
CPU time 0.88 seconds
Started Aug 18 05:57:20 PM PDT 24
Finished Aug 18 05:57:21 PM PDT 24
Peak memory 206972 kb
Host smart-14efa7cf-605a-4316-bb94-f194dbf0d544
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873183100 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.873183100
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3761333154
Short name T1092
Test name
Test status
Simulation time 45282181 ps
CPU time 0.88 seconds
Started Aug 18 05:57:19 PM PDT 24
Finished Aug 18 05:57:20 PM PDT 24
Peak memory 206956 kb
Host smart-7bc07705-6c6f-4aba-b4c9-d43136889769
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761333154 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3761333154
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.3600390569
Short name T1062
Test name
Test status
Simulation time 13631654 ps
CPU time 0.89 seconds
Started Aug 18 05:57:22 PM PDT 24
Finished Aug 18 05:57:23 PM PDT 24
Peak memory 206960 kb
Host smart-81a7400f-7a95-4a4b-8bf0-d8854450ef2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600390569 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3600390569
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3200886370
Short name T1104
Test name
Test status
Simulation time 27165391 ps
CPU time 0.8 seconds
Started Aug 18 05:57:21 PM PDT 24
Finished Aug 18 05:57:22 PM PDT 24
Peak memory 206764 kb
Host smart-442215f8-a891-434a-a50a-3cf1d26a8163
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200886370 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3200886370
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.1742991844
Short name T978
Test name
Test status
Simulation time 30730559 ps
CPU time 0.77 seconds
Started Aug 18 05:57:19 PM PDT 24
Finished Aug 18 05:57:20 PM PDT 24
Peak memory 206808 kb
Host smart-ca6b9473-46ef-4855-9c92-0905836e4229
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742991844 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.1742991844
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.844473156
Short name T1073
Test name
Test status
Simulation time 41693865 ps
CPU time 0.83 seconds
Started Aug 18 05:57:20 PM PDT 24
Finished Aug 18 05:57:21 PM PDT 24
Peak memory 206988 kb
Host smart-76326aff-2519-4003-8a38-86f1f49a2b18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844473156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.844473156
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2871475379
Short name T1100
Test name
Test status
Simulation time 82142210 ps
CPU time 1.65 seconds
Started Aug 18 05:56:43 PM PDT 24
Finished Aug 18 05:56:44 PM PDT 24
Peak memory 206996 kb
Host smart-f623e07d-2a56-47b3-8414-ba61870a055e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871475379 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.2871475379
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2384731922
Short name T1085
Test name
Test status
Simulation time 680735114 ps
CPU time 5.76 seconds
Started Aug 18 05:56:41 PM PDT 24
Finished Aug 18 05:56:47 PM PDT 24
Peak memory 207012 kb
Host smart-d9d998b9-2912-4175-8b2a-1d2f97c126b7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384731922 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.2384731922
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.682876719
Short name T1071
Test name
Test status
Simulation time 35905575 ps
CPU time 0.84 seconds
Started Aug 18 05:56:44 PM PDT 24
Finished Aug 18 05:56:45 PM PDT 24
Peak memory 206860 kb
Host smart-e3e48c5f-0776-4418-b86f-9064ede54ca1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682876719 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.682876719
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3544640229
Short name T988
Test name
Test status
Simulation time 78062038 ps
CPU time 1.11 seconds
Started Aug 18 05:56:40 PM PDT 24
Finished Aug 18 05:56:41 PM PDT 24
Peak memory 215364 kb
Host smart-c542cbe4-6df3-479b-9b39-94ec4d0f3bc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544640229 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3544640229
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.3131495261
Short name T1058
Test name
Test status
Simulation time 45615320 ps
CPU time 0.87 seconds
Started Aug 18 05:56:41 PM PDT 24
Finished Aug 18 05:56:42 PM PDT 24
Peak memory 207060 kb
Host smart-bbac0b9d-2781-45a6-89fd-12c35a502709
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131495261 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3131495261
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1594738410
Short name T1052
Test name
Test status
Simulation time 13988077 ps
CPU time 0.89 seconds
Started Aug 18 05:56:43 PM PDT 24
Finished Aug 18 05:56:44 PM PDT 24
Peak memory 206972 kb
Host smart-e02f2872-27ab-4879-97cf-65568de6c8ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594738410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1594738410
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.93001270
Short name T305
Test name
Test status
Simulation time 37625491 ps
CPU time 1.42 seconds
Started Aug 18 05:56:42 PM PDT 24
Finished Aug 18 05:56:44 PM PDT 24
Peak memory 207136 kb
Host smart-1ed0c0d2-6574-40e2-ae7d-adbf16ec8eab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93001270 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_outs
tanding.93001270
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.321997669
Short name T985
Test name
Test status
Simulation time 72939778 ps
CPU time 2.85 seconds
Started Aug 18 05:56:43 PM PDT 24
Finished Aug 18 05:56:46 PM PDT 24
Peak memory 215364 kb
Host smart-7a841433-9600-4066-b650-fb1a5423a5cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321997669 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.321997669
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.743194431
Short name T1024
Test name
Test status
Simulation time 79289267 ps
CPU time 2.19 seconds
Started Aug 18 05:56:41 PM PDT 24
Finished Aug 18 05:56:43 PM PDT 24
Peak memory 207164 kb
Host smart-5ab24adb-abf5-47e0-9151-5110589fe375
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743194431 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.743194431
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.304324491
Short name T1015
Test name
Test status
Simulation time 69967725 ps
CPU time 0.79 seconds
Started Aug 18 05:57:21 PM PDT 24
Finished Aug 18 05:57:22 PM PDT 24
Peak memory 206808 kb
Host smart-2e59f979-80b6-4ac6-a5d1-2f451b234a94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304324491 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.304324491
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.3118117535
Short name T1000
Test name
Test status
Simulation time 15763413 ps
CPU time 0.93 seconds
Started Aug 18 05:57:21 PM PDT 24
Finished Aug 18 05:57:22 PM PDT 24
Peak memory 206952 kb
Host smart-50aa3b1f-6c85-4e1f-9281-80c88229fc0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118117535 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3118117535
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2926465159
Short name T1020
Test name
Test status
Simulation time 23338687 ps
CPU time 0.89 seconds
Started Aug 18 05:57:19 PM PDT 24
Finished Aug 18 05:57:20 PM PDT 24
Peak memory 206884 kb
Host smart-7036fade-0ea4-42ef-914f-8c34f2f99b2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926465159 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2926465159
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.3424718485
Short name T1013
Test name
Test status
Simulation time 17732085 ps
CPU time 0.9 seconds
Started Aug 18 05:57:21 PM PDT 24
Finished Aug 18 05:57:22 PM PDT 24
Peak memory 206952 kb
Host smart-01575ed9-b4bc-41fb-bd30-d5f472c437ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424718485 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3424718485
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.682361278
Short name T1067
Test name
Test status
Simulation time 17036672 ps
CPU time 0.89 seconds
Started Aug 18 05:57:21 PM PDT 24
Finished Aug 18 05:57:22 PM PDT 24
Peak memory 206964 kb
Host smart-7c16cb2a-ef07-439d-a81c-b3e18ece81db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682361278 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.682361278
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.2329005710
Short name T1023
Test name
Test status
Simulation time 14896928 ps
CPU time 0.89 seconds
Started Aug 18 05:57:21 PM PDT 24
Finished Aug 18 05:57:22 PM PDT 24
Peak memory 206996 kb
Host smart-14d4c613-c2b2-4cc8-b23f-f7084d2ee136
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329005710 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2329005710
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.2932098377
Short name T990
Test name
Test status
Simulation time 30616464 ps
CPU time 0.81 seconds
Started Aug 18 05:57:19 PM PDT 24
Finished Aug 18 05:57:20 PM PDT 24
Peak memory 206828 kb
Host smart-e90faa9c-79a4-4fd7-b787-fad9e9b5a075
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932098377 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.2932098377
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.3267291558
Short name T1084
Test name
Test status
Simulation time 16765768 ps
CPU time 0.89 seconds
Started Aug 18 05:57:21 PM PDT 24
Finished Aug 18 05:57:22 PM PDT 24
Peak memory 206932 kb
Host smart-1e4be202-339c-4ff8-8f8f-7b2d9e98d6fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267291558 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.3267291558
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.452523820
Short name T1064
Test name
Test status
Simulation time 37476261 ps
CPU time 0.85 seconds
Started Aug 18 05:57:21 PM PDT 24
Finished Aug 18 05:57:22 PM PDT 24
Peak memory 206940 kb
Host smart-d681d427-6bd7-4a86-bd90-edc180b49110
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452523820 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.452523820
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3327457185
Short name T993
Test name
Test status
Simulation time 11419435 ps
CPU time 0.89 seconds
Started Aug 18 05:57:21 PM PDT 24
Finished Aug 18 05:57:22 PM PDT 24
Peak memory 206988 kb
Host smart-8c92899c-2ea0-4119-956a-79a68c779186
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327457185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3327457185
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3495016130
Short name T290
Test name
Test status
Simulation time 38102721 ps
CPU time 1.56 seconds
Started Aug 18 05:56:51 PM PDT 24
Finished Aug 18 05:56:52 PM PDT 24
Peak memory 207028 kb
Host smart-868973a7-e6eb-44be-8738-32206bd3cb58
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495016130 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.3495016130
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.85137840
Short name T981
Test name
Test status
Simulation time 263772278 ps
CPU time 6.38 seconds
Started Aug 18 05:56:52 PM PDT 24
Finished Aug 18 05:56:58 PM PDT 24
Peak memory 207080 kb
Host smart-0a9c609f-7d73-4bf0-a945-b6c2b863f0e7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85137840 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.85137840
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.504470153
Short name T1039
Test name
Test status
Simulation time 18862035 ps
CPU time 0.98 seconds
Started Aug 18 05:56:52 PM PDT 24
Finished Aug 18 05:56:53 PM PDT 24
Peak memory 207016 kb
Host smart-fc1ad440-8b3d-4c84-bef4-83ad825916af
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504470153 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.504470153
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.28227783
Short name T1028
Test name
Test status
Simulation time 223577593 ps
CPU time 1.2 seconds
Started Aug 18 05:56:49 PM PDT 24
Finished Aug 18 05:56:50 PM PDT 24
Peak memory 215480 kb
Host smart-65d98bd0-2f9d-4f54-bbd2-b694625371c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28227783 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.28227783
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2716000029
Short name T1044
Test name
Test status
Simulation time 40897156 ps
CPU time 0.83 seconds
Started Aug 18 05:56:51 PM PDT 24
Finished Aug 18 05:56:52 PM PDT 24
Peak memory 206856 kb
Host smart-509dd1fb-e324-4606-8281-a79b3ab6c4e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716000029 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2716000029
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.860916341
Short name T1053
Test name
Test status
Simulation time 13466367 ps
CPU time 0.86 seconds
Started Aug 18 05:56:44 PM PDT 24
Finished Aug 18 05:56:45 PM PDT 24
Peak memory 206960 kb
Host smart-fc1bf0ac-c7be-419a-937c-31a12420cc31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860916341 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.860916341
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3876580717
Short name T306
Test name
Test status
Simulation time 16268164 ps
CPU time 0.92 seconds
Started Aug 18 05:56:51 PM PDT 24
Finished Aug 18 05:56:52 PM PDT 24
Peak memory 207188 kb
Host smart-7ff2220e-9d66-429e-aea6-5b9859f8b409
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876580717 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.3876580717
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.3252545725
Short name T1040
Test name
Test status
Simulation time 74965166 ps
CPU time 2.92 seconds
Started Aug 18 05:56:41 PM PDT 24
Finished Aug 18 05:56:44 PM PDT 24
Peak memory 215328 kb
Host smart-db9ce042-527a-43a9-94f9-fdcdb0c7fb9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252545725 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.3252545725
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.311425927
Short name T1105
Test name
Test status
Simulation time 141219600 ps
CPU time 3.42 seconds
Started Aug 18 05:56:46 PM PDT 24
Finished Aug 18 05:56:49 PM PDT 24
Peak memory 207136 kb
Host smart-80fc66e3-3ed3-4f06-af90-576061a47368
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311425927 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.311425927
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1313022391
Short name T1074
Test name
Test status
Simulation time 26869180 ps
CPU time 0.89 seconds
Started Aug 18 05:57:27 PM PDT 24
Finished Aug 18 05:57:28 PM PDT 24
Peak memory 207000 kb
Host smart-dd401e5f-c42a-4342-bc02-8d56478c993b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313022391 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1313022391
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1321814429
Short name T1009
Test name
Test status
Simulation time 42510029 ps
CPU time 0.75 seconds
Started Aug 18 05:57:22 PM PDT 24
Finished Aug 18 05:57:23 PM PDT 24
Peak memory 206756 kb
Host smart-e8e2dc08-23ca-41f7-8587-f15436152ae9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321814429 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1321814429
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3403323448
Short name T1036
Test name
Test status
Simulation time 16448479 ps
CPU time 0.91 seconds
Started Aug 18 05:57:25 PM PDT 24
Finished Aug 18 05:57:26 PM PDT 24
Peak memory 207140 kb
Host smart-1b60c6d1-75f7-40d1-90ba-34fb2b80dce7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403323448 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3403323448
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.552997192
Short name T994
Test name
Test status
Simulation time 12710729 ps
CPU time 0.88 seconds
Started Aug 18 05:57:22 PM PDT 24
Finished Aug 18 05:57:23 PM PDT 24
Peak memory 206996 kb
Host smart-263974df-bfe0-49f5-a801-c5fa1499aabd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552997192 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.552997192
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.41678535
Short name T1096
Test name
Test status
Simulation time 49968499 ps
CPU time 0.88 seconds
Started Aug 18 05:57:22 PM PDT 24
Finished Aug 18 05:57:23 PM PDT 24
Peak memory 206900 kb
Host smart-5733f287-9041-43ba-9440-c61b3e9020ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41678535 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.41678535
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.3657207584
Short name T1082
Test name
Test status
Simulation time 29439405 ps
CPU time 0.78 seconds
Started Aug 18 05:57:23 PM PDT 24
Finished Aug 18 05:57:24 PM PDT 24
Peak memory 206704 kb
Host smart-80634aab-f195-4ee4-a1b4-7e5358776786
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657207584 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.3657207584
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.2712679905
Short name T1091
Test name
Test status
Simulation time 44019148 ps
CPU time 0.85 seconds
Started Aug 18 05:57:21 PM PDT 24
Finished Aug 18 05:57:22 PM PDT 24
Peak memory 206824 kb
Host smart-d3da9357-f3c4-40f2-ad74-b1d23beeb5ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712679905 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.2712679905
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.957807441
Short name T1038
Test name
Test status
Simulation time 71277982 ps
CPU time 0.79 seconds
Started Aug 18 05:57:22 PM PDT 24
Finished Aug 18 05:57:23 PM PDT 24
Peak memory 206740 kb
Host smart-97d8ef6e-cdbf-4484-8aad-49027b69c6e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957807441 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.957807441
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.4271362008
Short name T1021
Test name
Test status
Simulation time 14630155 ps
CPU time 0.89 seconds
Started Aug 18 05:57:20 PM PDT 24
Finished Aug 18 05:57:21 PM PDT 24
Peak memory 206960 kb
Host smart-a5764827-06c5-4edb-a52a-0e7e6b3a4707
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271362008 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.4271362008
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.4220223348
Short name T1018
Test name
Test status
Simulation time 21660913 ps
CPU time 0.88 seconds
Started Aug 18 05:57:23 PM PDT 24
Finished Aug 18 05:57:24 PM PDT 24
Peak memory 206996 kb
Host smart-5b6702cc-b1f6-409a-84d1-968b1972eaa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220223348 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.4220223348
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1587134010
Short name T265
Test name
Test status
Simulation time 146166010 ps
CPU time 1.07 seconds
Started Aug 18 05:56:52 PM PDT 24
Finished Aug 18 05:56:53 PM PDT 24
Peak memory 215292 kb
Host smart-5b8b96d7-45f8-4ec3-82ca-3ec6507b5b71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587134010 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1587134010
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.3889273807
Short name T303
Test name
Test status
Simulation time 19367454 ps
CPU time 0.92 seconds
Started Aug 18 05:56:50 PM PDT 24
Finished Aug 18 05:56:51 PM PDT 24
Peak memory 207024 kb
Host smart-9e158562-1205-4f80-bd8d-cc4660579307
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889273807 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.3889273807
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1417550303
Short name T1042
Test name
Test status
Simulation time 20840431 ps
CPU time 0.81 seconds
Started Aug 18 05:56:50 PM PDT 24
Finished Aug 18 05:56:51 PM PDT 24
Peak memory 206820 kb
Host smart-9928b9cb-7513-43ea-95e5-fa8cd18e15e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417550303 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1417550303
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3224972640
Short name T1072
Test name
Test status
Simulation time 44409312 ps
CPU time 1.41 seconds
Started Aug 18 05:56:52 PM PDT 24
Finished Aug 18 05:56:53 PM PDT 24
Peak memory 207136 kb
Host smart-2f2833b5-7fad-412c-9822-1d4ee57848b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224972640 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.3224972640
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.4094297788
Short name T1007
Test name
Test status
Simulation time 58357043 ps
CPU time 2.07 seconds
Started Aug 18 05:56:50 PM PDT 24
Finished Aug 18 05:56:52 PM PDT 24
Peak memory 215372 kb
Host smart-cf03ea0c-7d3f-416f-bbde-f7009f88f2a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094297788 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.4094297788
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2524171803
Short name T328
Test name
Test status
Simulation time 1037805588 ps
CPU time 16.23 seconds
Started Aug 18 05:56:50 PM PDT 24
Finished Aug 18 05:57:06 PM PDT 24
Peak memory 207120 kb
Host smart-baf9ee26-0181-4e4d-8b9c-8b807371d675
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524171803 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2524171803
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1403277562
Short name T980
Test name
Test status
Simulation time 14127906 ps
CPU time 1.03 seconds
Started Aug 18 05:56:53 PM PDT 24
Finished Aug 18 05:56:54 PM PDT 24
Peak memory 216912 kb
Host smart-452d3b6d-ac50-4059-90b8-812d2861acde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403277562 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1403277562
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.237905220
Short name T1033
Test name
Test status
Simulation time 26787895 ps
CPU time 0.88 seconds
Started Aug 18 05:56:55 PM PDT 24
Finished Aug 18 05:56:56 PM PDT 24
Peak memory 206944 kb
Host smart-b873fd57-ca03-4994-b2c2-590cd30a8f24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237905220 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.237905220
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.549094197
Short name T998
Test name
Test status
Simulation time 15842618 ps
CPU time 0.92 seconds
Started Aug 18 05:56:51 PM PDT 24
Finished Aug 18 05:56:53 PM PDT 24
Peak memory 206876 kb
Host smart-49ebedf8-eec8-4cb7-b540-6a9aecafd6fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549094197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.549094197
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.372772245
Short name T1069
Test name
Test status
Simulation time 292844931 ps
CPU time 1.34 seconds
Started Aug 18 05:56:51 PM PDT 24
Finished Aug 18 05:56:52 PM PDT 24
Peak memory 207120 kb
Host smart-bfaac728-fd54-4bdc-a8ed-97df217fbe60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372772245 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out
standing.372772245
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.782439623
Short name T1025
Test name
Test status
Simulation time 63885250 ps
CPU time 1.9 seconds
Started Aug 18 05:56:51 PM PDT 24
Finished Aug 18 05:56:53 PM PDT 24
Peak memory 215256 kb
Host smart-01620bfe-8ce2-4b6b-9fe9-d3a6f5ec0504
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782439623 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.782439623
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.4029237437
Short name T1097
Test name
Test status
Simulation time 314004849 ps
CPU time 2.35 seconds
Started Aug 18 05:56:54 PM PDT 24
Finished Aug 18 05:56:57 PM PDT 24
Peak memory 207140 kb
Host smart-dae9634f-a604-41c0-9ad7-16115b4d66cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029237437 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.4029237437
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1335438452
Short name T1008
Test name
Test status
Simulation time 51087179 ps
CPU time 1.71 seconds
Started Aug 18 05:56:51 PM PDT 24
Finished Aug 18 05:56:53 PM PDT 24
Peak memory 215360 kb
Host smart-9cc62f33-2ec1-476d-990e-a25feba1dfb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335438452 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1335438452
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.3028987696
Short name T291
Test name
Test status
Simulation time 31353398 ps
CPU time 0.81 seconds
Started Aug 18 05:56:51 PM PDT 24
Finished Aug 18 05:56:52 PM PDT 24
Peak memory 206852 kb
Host smart-83bc35e6-4a98-4be3-a171-1bf0d657e772
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028987696 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.3028987696
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.891184810
Short name T986
Test name
Test status
Simulation time 16262954 ps
CPU time 0.92 seconds
Started Aug 18 05:56:55 PM PDT 24
Finished Aug 18 05:56:56 PM PDT 24
Peak memory 206936 kb
Host smart-c9783bf8-8c5e-43b5-a78e-42c14348144a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891184810 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.891184810
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1109087129
Short name T1099
Test name
Test status
Simulation time 21713530 ps
CPU time 0.92 seconds
Started Aug 18 05:56:54 PM PDT 24
Finished Aug 18 05:56:55 PM PDT 24
Peak memory 207084 kb
Host smart-c96a7f00-8963-4a7f-93d2-c7f6c4c4997a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109087129 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1109087129
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2034739952
Short name T1006
Test name
Test status
Simulation time 124589410 ps
CPU time 2.53 seconds
Started Aug 18 05:56:51 PM PDT 24
Finished Aug 18 05:56:54 PM PDT 24
Peak memory 215356 kb
Host smart-a763eadd-a7e5-4e0b-b7cf-6a203496d8ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034739952 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2034739952
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3666666443
Short name T315
Test name
Test status
Simulation time 70996167 ps
CPU time 2.15 seconds
Started Aug 18 05:56:51 PM PDT 24
Finished Aug 18 05:56:53 PM PDT 24
Peak memory 207112 kb
Host smart-4ae6252a-53e8-4215-a595-e2f4abf99e67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666666443 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.3666666443
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1968534068
Short name T1030
Test name
Test status
Simulation time 25582230 ps
CPU time 1.65 seconds
Started Aug 18 05:57:00 PM PDT 24
Finished Aug 18 05:57:02 PM PDT 24
Peak memory 219848 kb
Host smart-03d1c047-e99d-4347-aa61-09429e25fd56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968534068 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1968534068
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1941304382
Short name T1077
Test name
Test status
Simulation time 70654254 ps
CPU time 0.89 seconds
Started Aug 18 05:56:58 PM PDT 24
Finished Aug 18 05:56:59 PM PDT 24
Peak memory 207012 kb
Host smart-cdcc99c6-111e-42f9-b397-517a53c9b53f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941304382 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1941304382
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.2524059190
Short name T1093
Test name
Test status
Simulation time 68948596 ps
CPU time 0.84 seconds
Started Aug 18 05:56:57 PM PDT 24
Finished Aug 18 05:56:58 PM PDT 24
Peak memory 206992 kb
Host smart-6025ba57-a2e0-41db-bb99-57d4b8c187b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524059190 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2524059190
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.433627644
Short name T1029
Test name
Test status
Simulation time 156359773 ps
CPU time 1.42 seconds
Started Aug 18 05:56:58 PM PDT 24
Finished Aug 18 05:56:59 PM PDT 24
Peak memory 207124 kb
Host smart-901e75cf-5776-4d92-94ae-108fce3326ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433627644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_out
standing.433627644
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.663061598
Short name T1026
Test name
Test status
Simulation time 88227805 ps
CPU time 2.42 seconds
Started Aug 18 05:56:58 PM PDT 24
Finished Aug 18 05:57:00 PM PDT 24
Peak memory 215356 kb
Host smart-3000648d-8ae6-484e-864a-8c76c372c215
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663061598 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.663061598
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1208571959
Short name T1041
Test name
Test status
Simulation time 80835814 ps
CPU time 2.03 seconds
Started Aug 18 05:56:57 PM PDT 24
Finished Aug 18 05:57:00 PM PDT 24
Peak memory 215336 kb
Host smart-90ba98fe-3870-4310-a6a6-5b89e2415fea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208571959 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1208571959
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1138906659
Short name T1060
Test name
Test status
Simulation time 103621349 ps
CPU time 1.34 seconds
Started Aug 18 05:56:58 PM PDT 24
Finished Aug 18 05:57:00 PM PDT 24
Peak memory 218484 kb
Host smart-94028bbc-5a8b-48c1-9b27-ced2bb948d56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138906659 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.1138906659
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.454222098
Short name T295
Test name
Test status
Simulation time 16823331 ps
CPU time 0.9 seconds
Started Aug 18 05:57:01 PM PDT 24
Finished Aug 18 05:57:02 PM PDT 24
Peak memory 207024 kb
Host smart-9aacf0a2-cacf-45d6-80dd-92002f8c4ca8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454222098 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.454222098
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.623256256
Short name T1017
Test name
Test status
Simulation time 26082482 ps
CPU time 0.85 seconds
Started Aug 18 05:57:00 PM PDT 24
Finished Aug 18 05:57:01 PM PDT 24
Peak memory 206960 kb
Host smart-35990b03-61d1-408c-81fc-ab6e40167754
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623256256 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.623256256
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2812771052
Short name T1057
Test name
Test status
Simulation time 77558907 ps
CPU time 1.06 seconds
Started Aug 18 05:56:57 PM PDT 24
Finished Aug 18 05:56:59 PM PDT 24
Peak memory 207144 kb
Host smart-dda16bc9-7403-4073-9c11-f5f379323e7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812771052 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.2812771052
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.1124387914
Short name T1031
Test name
Test status
Simulation time 90427619 ps
CPU time 1.76 seconds
Started Aug 18 05:56:58 PM PDT 24
Finished Aug 18 05:57:00 PM PDT 24
Peak memory 215188 kb
Host smart-d715cbc1-bbb4-4657-ae5d-f0978a684ca1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124387914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1124387914
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1142470985
Short name T323
Test name
Test status
Simulation time 485069825 ps
CPU time 2.34 seconds
Started Aug 18 05:56:58 PM PDT 24
Finished Aug 18 05:57:00 PM PDT 24
Peak memory 207340 kb
Host smart-49d5cbdd-9fcd-437b-9175-f2c2dc5657c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142470985 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.1142470985
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert_test.4234871163
Short name T746
Test name
Test status
Simulation time 27121291 ps
CPU time 0.89 seconds
Started Aug 18 06:10:00 PM PDT 24
Finished Aug 18 06:10:01 PM PDT 24
Peak memory 215016 kb
Host smart-af9b7cb6-daf1-4d39-8a26-b651b33cb178
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234871163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.4234871163
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.2243482899
Short name T143
Test name
Test status
Simulation time 84368221 ps
CPU time 1.07 seconds
Started Aug 18 06:10:03 PM PDT 24
Finished Aug 18 06:10:04 PM PDT 24
Peak memory 216848 kb
Host smart-32c834a7-f8be-47f3-8c15-bc549a35bdbe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243482899 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.2243482899
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.2687382470
Short name T398
Test name
Test status
Simulation time 20674820 ps
CPU time 1.16 seconds
Started Aug 18 06:10:01 PM PDT 24
Finished Aug 18 06:10:02 PM PDT 24
Peak memory 219872 kb
Host smart-732270b0-a49b-48d5-a2ca-2687fecdde64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687382470 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2687382470
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.250499854
Short name T98
Test name
Test status
Simulation time 38644453 ps
CPU time 1.42 seconds
Started Aug 18 06:09:55 PM PDT 24
Finished Aug 18 06:09:57 PM PDT 24
Peak memory 217568 kb
Host smart-e3ae2e67-867d-4749-b727-ea7789394bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250499854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.250499854
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.195811013
Short name T651
Test name
Test status
Simulation time 36184689 ps
CPU time 1.01 seconds
Started Aug 18 06:10:03 PM PDT 24
Finished Aug 18 06:10:04 PM PDT 24
Peak memory 224268 kb
Host smart-6aa8a989-2d8e-4829-98af-b501a0cda50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195811013 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.195811013
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.3972242625
Short name T632
Test name
Test status
Simulation time 17926147 ps
CPU time 0.98 seconds
Started Aug 18 06:09:54 PM PDT 24
Finished Aug 18 06:09:56 PM PDT 24
Peak memory 207192 kb
Host smart-e4c24c7c-e051-4399-8367-f7c480d9d7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972242625 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.3972242625
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.2228620671
Short name T18
Test name
Test status
Simulation time 1174075498 ps
CPU time 5.67 seconds
Started Aug 18 06:10:02 PM PDT 24
Finished Aug 18 06:10:08 PM PDT 24
Peak memory 239820 kb
Host smart-a1aa8d59-96b3-4fab-b640-575ca11e26c0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228620671 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.2228620671
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.996627468
Short name T833
Test name
Test status
Simulation time 16260373 ps
CPU time 0.95 seconds
Started Aug 18 06:09:54 PM PDT 24
Finished Aug 18 06:09:55 PM PDT 24
Peak memory 207168 kb
Host smart-6c88e8b7-41ab-4324-a400-d3d756c66268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996627468 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.996627468
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.2643438710
Short name T611
Test name
Test status
Simulation time 447990519 ps
CPU time 4.17 seconds
Started Aug 18 06:09:59 PM PDT 24
Finished Aug 18 06:10:03 PM PDT 24
Peak memory 215376 kb
Host smart-6d188a87-83db-4d61-b636-e45aa2ad1a19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643438710 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2643438710
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2612986304
Short name T658
Test name
Test status
Simulation time 6953022938 ps
CPU time 44.98 seconds
Started Aug 18 06:09:58 PM PDT 24
Finished Aug 18 06:10:43 PM PDT 24
Peak memory 218052 kb
Host smart-af3c8561-a7ae-425b-98ba-d0f86b4a0ce9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612986304 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2612986304
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.3249510325
Short name T133
Test name
Test status
Simulation time 54930801 ps
CPU time 1.26 seconds
Started Aug 18 06:10:00 PM PDT 24
Finished Aug 18 06:10:02 PM PDT 24
Peak memory 215740 kb
Host smart-6872a608-c9da-4d2c-b017-24f4f9e1ec53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249510325 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.3249510325
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.1711289532
Short name T536
Test name
Test status
Simulation time 23386683 ps
CPU time 0.87 seconds
Started Aug 18 06:09:59 PM PDT 24
Finished Aug 18 06:10:00 PM PDT 24
Peak memory 215016 kb
Host smart-fe8883af-42af-4e5e-bbfe-243e7710a5a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711289532 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1711289532
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.863678509
Short name T608
Test name
Test status
Simulation time 56590676 ps
CPU time 1.21 seconds
Started Aug 18 06:10:00 PM PDT 24
Finished Aug 18 06:10:02 PM PDT 24
Peak memory 216800 kb
Host smart-34481547-10e9-495d-b3c6-2fd2e122edbd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863678509 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_dis
able_auto_req_mode.863678509
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.177452445
Short name T458
Test name
Test status
Simulation time 29861817 ps
CPU time 1.36 seconds
Started Aug 18 06:09:59 PM PDT 24
Finished Aug 18 06:10:00 PM PDT 24
Peak memory 225856 kb
Host smart-5d414f85-9c37-41a1-b6ea-bf9ea4e26487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177452445 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.177452445
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.1120484517
Short name T34
Test name
Test status
Simulation time 29360323 ps
CPU time 1.34 seconds
Started Aug 18 06:10:01 PM PDT 24
Finished Aug 18 06:10:02 PM PDT 24
Peak memory 217396 kb
Host smart-b770de49-d9a4-4d33-8853-346a78dfa93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120484517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.1120484517
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.3750864231
Short name T61
Test name
Test status
Simulation time 28430906 ps
CPU time 1.12 seconds
Started Aug 18 06:10:01 PM PDT 24
Finished Aug 18 06:10:02 PM PDT 24
Peak memory 224244 kb
Host smart-c8a3e626-5d2d-40c9-8814-4f746cb130ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750864231 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.3750864231
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.4128706209
Short name T790
Test name
Test status
Simulation time 27809794 ps
CPU time 0.96 seconds
Started Aug 18 06:10:01 PM PDT 24
Finished Aug 18 06:10:02 PM PDT 24
Peak memory 207164 kb
Host smart-5d2358e7-ecb2-402e-ab34-0e8b2281d63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128706209 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.4128706209
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_smoke.209786643
Short name T117
Test name
Test status
Simulation time 17100205 ps
CPU time 0.97 seconds
Started Aug 18 06:10:00 PM PDT 24
Finished Aug 18 06:10:01 PM PDT 24
Peak memory 215380 kb
Host smart-16f5e115-8505-4fc6-90cc-7d5e0d3566b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209786643 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.209786643
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.690160317
Short name T484
Test name
Test status
Simulation time 284252467 ps
CPU time 3.59 seconds
Started Aug 18 06:10:02 PM PDT 24
Finished Aug 18 06:10:05 PM PDT 24
Peak memory 217404 kb
Host smart-863249f7-502d-44c8-a118-9328cd875228
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690160317 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.690160317
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_alert.3858067870
Short name T373
Test name
Test status
Simulation time 28096119 ps
CPU time 1.32 seconds
Started Aug 18 06:10:31 PM PDT 24
Finished Aug 18 06:10:33 PM PDT 24
Peak memory 220496 kb
Host smart-1a1f1a7f-f4e9-46c5-af3f-54d8a02f6c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858067870 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.3858067870
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_disable.1946226108
Short name T702
Test name
Test status
Simulation time 13399093 ps
CPU time 0.95 seconds
Started Aug 18 06:10:31 PM PDT 24
Finished Aug 18 06:10:32 PM PDT 24
Peak memory 215384 kb
Host smart-d93e7662-1467-4f08-8406-dfe92e0c417c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946226108 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1946226108
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.4129646233
Short name T277
Test name
Test status
Simulation time 155803046 ps
CPU time 1.09 seconds
Started Aug 18 06:10:40 PM PDT 24
Finished Aug 18 06:10:41 PM PDT 24
Peak memory 216780 kb
Host smart-dd2e7d41-b6d4-4852-8048-6e3463080320
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129646233 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.4129646233
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.107976175
Short name T275
Test name
Test status
Simulation time 32191843 ps
CPU time 0.91 seconds
Started Aug 18 06:10:31 PM PDT 24
Finished Aug 18 06:10:32 PM PDT 24
Peak memory 218280 kb
Host smart-0cc667ac-df44-4e9f-b04f-58afa7050f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107976175 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.107976175
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.1629520396
Short name T774
Test name
Test status
Simulation time 63509318 ps
CPU time 0.98 seconds
Started Aug 18 06:10:31 PM PDT 24
Finished Aug 18 06:10:32 PM PDT 24
Peak memory 218660 kb
Host smart-35ae18dd-ef78-4770-8e3a-7929f0b784ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629520396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.1629520396
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_smoke.1387397538
Short name T821
Test name
Test status
Simulation time 21610248 ps
CPU time 0.94 seconds
Started Aug 18 06:10:30 PM PDT 24
Finished Aug 18 06:10:31 PM PDT 24
Peak memory 215360 kb
Host smart-8e30ec8c-4e1a-4196-85af-6e7f689c0f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387397538 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1387397538
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.3321091552
Short name T570
Test name
Test status
Simulation time 74611745 ps
CPU time 2.07 seconds
Started Aug 18 06:10:32 PM PDT 24
Finished Aug 18 06:10:34 PM PDT 24
Peak memory 215504 kb
Host smart-1df4c3fc-7b62-47f6-9da8-d819fcdab0d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321091552 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3321091552
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/100.edn_alert.1152720404
Short name T125
Test name
Test status
Simulation time 66570256 ps
CPU time 1.17 seconds
Started Aug 18 06:12:03 PM PDT 24
Finished Aug 18 06:12:04 PM PDT 24
Peak memory 219976 kb
Host smart-2b8f7c29-eaf9-4a91-90c2-b3c4670d4309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152720404 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.1152720404
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.1555424180
Short name T513
Test name
Test status
Simulation time 49885627 ps
CPU time 1.84 seconds
Started Aug 18 06:12:01 PM PDT 24
Finished Aug 18 06:12:03 PM PDT 24
Peak memory 218452 kb
Host smart-2d52424e-9895-4910-9f86-9b52fed635e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555424180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.1555424180
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.1036509026
Short name T429
Test name
Test status
Simulation time 52545304 ps
CPU time 1.36 seconds
Started Aug 18 06:12:01 PM PDT 24
Finished Aug 18 06:12:03 PM PDT 24
Peak memory 219920 kb
Host smart-02d64731-3b74-4c95-8356-a6038e276218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036509026 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.1036509026
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/101.edn_genbits.2840495708
Short name T888
Test name
Test status
Simulation time 57094557 ps
CPU time 1.37 seconds
Started Aug 18 06:12:00 PM PDT 24
Finished Aug 18 06:12:02 PM PDT 24
Peak memory 217348 kb
Host smart-1d16cc76-abd7-470d-87a8-6b0caf5d2376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840495708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.2840495708
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.1860613087
Short name T766
Test name
Test status
Simulation time 26545994 ps
CPU time 1.25 seconds
Started Aug 18 06:12:03 PM PDT 24
Finished Aug 18 06:12:04 PM PDT 24
Peak memory 219628 kb
Host smart-e028418c-bdea-45de-b009-bd87fb33bb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860613087 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.1860613087
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/104.edn_alert.3461643027
Short name T313
Test name
Test status
Simulation time 55486295 ps
CPU time 1.24 seconds
Started Aug 18 06:12:04 PM PDT 24
Finished Aug 18 06:12:05 PM PDT 24
Peak memory 220424 kb
Host smart-258a07ad-c0d2-4507-ad19-ddfb8d68c342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461643027 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.3461643027
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.2095635850
Short name T370
Test name
Test status
Simulation time 69790420 ps
CPU time 1.1 seconds
Started Aug 18 06:12:06 PM PDT 24
Finished Aug 18 06:12:07 PM PDT 24
Peak memory 217336 kb
Host smart-113250bc-55e6-46c5-bdd8-7d72bbf7c03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095635850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2095635850
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.2538798616
Short name T427
Test name
Test status
Simulation time 99871197 ps
CPU time 1.23 seconds
Started Aug 18 06:12:08 PM PDT 24
Finished Aug 18 06:12:09 PM PDT 24
Peak memory 215780 kb
Host smart-fe43bf92-f4b1-4373-ab64-f9a6af20e6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538798616 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.2538798616
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.3905748309
Short name T555
Test name
Test status
Simulation time 22832904 ps
CPU time 1.24 seconds
Started Aug 18 06:12:02 PM PDT 24
Finished Aug 18 06:12:03 PM PDT 24
Peak memory 219756 kb
Host smart-b023ee43-bb86-453b-a3e5-c870d13177c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905748309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.3905748309
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.1529623039
Short name T254
Test name
Test status
Simulation time 118834256 ps
CPU time 1.2 seconds
Started Aug 18 06:12:06 PM PDT 24
Finished Aug 18 06:12:07 PM PDT 24
Peak memory 220868 kb
Host smart-476f0520-5352-435a-a250-5c403f059950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529623039 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.1529623039
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.2529737895
Short name T344
Test name
Test status
Simulation time 51976725 ps
CPU time 1.21 seconds
Started Aug 18 06:12:07 PM PDT 24
Finished Aug 18 06:12:08 PM PDT 24
Peak memory 218576 kb
Host smart-feaadbfc-41fa-4062-ba03-bc9826f52144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529737895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.2529737895
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.3356909621
Short name T461
Test name
Test status
Simulation time 41666111 ps
CPU time 1.67 seconds
Started Aug 18 06:12:08 PM PDT 24
Finished Aug 18 06:12:10 PM PDT 24
Peak memory 217240 kb
Host smart-69fb2885-4689-4b34-a2d2-d75dccfa25de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356909621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3356909621
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.628161873
Short name T534
Test name
Test status
Simulation time 41973422 ps
CPU time 1.13 seconds
Started Aug 18 06:12:11 PM PDT 24
Finished Aug 18 06:12:12 PM PDT 24
Peak memory 218640 kb
Host smart-114e0e5c-6429-4187-9c86-393ea973aab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628161873 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.628161873
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.1728835705
Short name T811
Test name
Test status
Simulation time 41305383 ps
CPU time 1.68 seconds
Started Aug 18 06:12:05 PM PDT 24
Finished Aug 18 06:12:07 PM PDT 24
Peak memory 217544 kb
Host smart-dd5aff8c-b983-46ab-b6f0-fc5ea6f15d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728835705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1728835705
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.1276856975
Short name T199
Test name
Test status
Simulation time 21766270 ps
CPU time 1.22 seconds
Started Aug 18 06:12:04 PM PDT 24
Finished Aug 18 06:12:05 PM PDT 24
Peak memory 220868 kb
Host smart-e2f031a4-b27e-45e3-9ced-feba0673d379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276856975 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.1276856975
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.3419791377
Short name T383
Test name
Test status
Simulation time 55799251 ps
CPU time 1.9 seconds
Started Aug 18 06:12:05 PM PDT 24
Finished Aug 18 06:12:07 PM PDT 24
Peak memory 218752 kb
Host smart-79add359-dca8-4c63-89e3-ae1f121e2685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419791377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3419791377
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.2162577254
Short name T697
Test name
Test status
Simulation time 54994552 ps
CPU time 1.22 seconds
Started Aug 18 06:10:32 PM PDT 24
Finished Aug 18 06:10:33 PM PDT 24
Peak memory 218520 kb
Host smart-d04ca749-944f-40ac-8001-05ba2115fc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162577254 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2162577254
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.1950321668
Short name T525
Test name
Test status
Simulation time 107016274 ps
CPU time 1.19 seconds
Started Aug 18 06:10:40 PM PDT 24
Finished Aug 18 06:10:42 PM PDT 24
Peak memory 207056 kb
Host smart-6960869b-0871-4248-9c5c-71181a94b686
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950321668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1950321668
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.495953647
Short name T45
Test name
Test status
Simulation time 89343698 ps
CPU time 1.13 seconds
Started Aug 18 06:10:39 PM PDT 24
Finished Aug 18 06:10:40 PM PDT 24
Peak memory 216764 kb
Host smart-1be3f424-59f9-4b8b-a604-6ff81f57fec7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495953647 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_di
sable_auto_req_mode.495953647
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.2453253987
Short name T77
Test name
Test status
Simulation time 74267046 ps
CPU time 1.06 seconds
Started Aug 18 06:10:33 PM PDT 24
Finished Aug 18 06:10:34 PM PDT 24
Peak memory 219616 kb
Host smart-9108a78e-d308-45eb-a178-1de67eae55ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453253987 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.2453253987
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_intr.2164192670
Short name T101
Test name
Test status
Simulation time 50649758 ps
CPU time 0.85 seconds
Started Aug 18 06:10:30 PM PDT 24
Finished Aug 18 06:10:31 PM PDT 24
Peak memory 215696 kb
Host smart-18c4fcf8-19b9-444d-95c9-fec860634995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164192670 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.2164192670
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.2603347562
Short name T480
Test name
Test status
Simulation time 24497375 ps
CPU time 0.92 seconds
Started Aug 18 06:10:31 PM PDT 24
Finished Aug 18 06:10:32 PM PDT 24
Peak memory 215324 kb
Host smart-e4cd55b9-219e-4b1e-8dd5-d05774e96bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603347562 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.2603347562
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1549357642
Short name T559
Test name
Test status
Simulation time 29617262 ps
CPU time 1.12 seconds
Started Aug 18 06:10:31 PM PDT 24
Finished Aug 18 06:10:32 PM PDT 24
Peak memory 206964 kb
Host smart-8d984b9c-2551-4aa5-ad95-db3bce87b19a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549357642 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1549357642
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/110.edn_alert.208897607
Short name T764
Test name
Test status
Simulation time 187272202 ps
CPU time 1.12 seconds
Started Aug 18 06:12:06 PM PDT 24
Finished Aug 18 06:12:07 PM PDT 24
Peak memory 219872 kb
Host smart-97ea026c-1b2c-4519-bdec-97cfb761feac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208897607 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.208897607
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.2860520293
Short name T521
Test name
Test status
Simulation time 36374400 ps
CPU time 1.59 seconds
Started Aug 18 06:12:04 PM PDT 24
Finished Aug 18 06:12:06 PM PDT 24
Peak memory 220600 kb
Host smart-649ba15d-2b3a-441d-bd8e-80af2dabbcc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860520293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2860520293
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.614511746
Short name T374
Test name
Test status
Simulation time 23946925 ps
CPU time 1.19 seconds
Started Aug 18 06:12:12 PM PDT 24
Finished Aug 18 06:12:13 PM PDT 24
Peak memory 218780 kb
Host smart-2af36064-5294-4e11-86ca-75fe3fd93836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614511746 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.614511746
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.1540330128
Short name T420
Test name
Test status
Simulation time 54832748 ps
CPU time 1.4 seconds
Started Aug 18 06:12:05 PM PDT 24
Finished Aug 18 06:12:07 PM PDT 24
Peak memory 218792 kb
Host smart-bac03170-63e4-443b-9530-6c314d59f549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540330128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1540330128
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.3878541634
Short name T810
Test name
Test status
Simulation time 33411235 ps
CPU time 1.38 seconds
Started Aug 18 06:12:08 PM PDT 24
Finished Aug 18 06:12:09 PM PDT 24
Peak memory 215744 kb
Host smart-a56fbb50-9e8b-4e08-a87c-edcb3f90c999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878541634 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.3878541634
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.583897257
Short name T436
Test name
Test status
Simulation time 38107923 ps
CPU time 1.55 seconds
Started Aug 18 06:12:03 PM PDT 24
Finished Aug 18 06:12:04 PM PDT 24
Peak memory 220396 kb
Host smart-081895f0-f7ed-4858-abf1-e8801b094623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583897257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.583897257
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.2710528534
Short name T130
Test name
Test status
Simulation time 32756723 ps
CPU time 1.35 seconds
Started Aug 18 06:12:01 PM PDT 24
Finished Aug 18 06:12:02 PM PDT 24
Peak memory 220024 kb
Host smart-5b1cd81b-df87-47e7-b378-1f178275f3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710528534 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.2710528534
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.3413509015
Short name T22
Test name
Test status
Simulation time 40461068 ps
CPU time 1.56 seconds
Started Aug 18 06:12:06 PM PDT 24
Finished Aug 18 06:12:07 PM PDT 24
Peak memory 218660 kb
Host smart-cfb4e9f1-e003-4c60-b576-f1832bf2af20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413509015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3413509015
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.1046535801
Short name T629
Test name
Test status
Simulation time 25930234 ps
CPU time 1.27 seconds
Started Aug 18 06:12:09 PM PDT 24
Finished Aug 18 06:12:10 PM PDT 24
Peak memory 219936 kb
Host smart-f55e0550-d766-4e40-9f52-a3f235dab1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046535801 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.1046535801
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.2877747832
Short name T609
Test name
Test status
Simulation time 40981894 ps
CPU time 1.59 seconds
Started Aug 18 06:12:05 PM PDT 24
Finished Aug 18 06:12:07 PM PDT 24
Peak memory 218516 kb
Host smart-2e5f6792-0cee-4108-a86b-866c7b7030fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877747832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.2877747832
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.2711099919
Short name T757
Test name
Test status
Simulation time 57245686 ps
CPU time 1.11 seconds
Started Aug 18 06:12:07 PM PDT 24
Finished Aug 18 06:12:08 PM PDT 24
Peak memory 220704 kb
Host smart-8aeedde8-1246-44d5-ae63-86693abac95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711099919 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.2711099919
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.270940542
Short name T721
Test name
Test status
Simulation time 33038098 ps
CPU time 1.32 seconds
Started Aug 18 06:12:06 PM PDT 24
Finished Aug 18 06:12:07 PM PDT 24
Peak memory 219696 kb
Host smart-ffd3b420-ea2a-48e9-a327-8715bc810798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270940542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.270940542
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.3979369376
Short name T867
Test name
Test status
Simulation time 43533562 ps
CPU time 1.22 seconds
Started Aug 18 06:12:07 PM PDT 24
Finished Aug 18 06:12:08 PM PDT 24
Peak memory 219960 kb
Host smart-bc34f77b-7b4c-470d-be9d-75d238beadcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979369376 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.3979369376
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.2372669793
Short name T644
Test name
Test status
Simulation time 33438211 ps
CPU time 1.31 seconds
Started Aug 18 06:12:04 PM PDT 24
Finished Aug 18 06:12:05 PM PDT 24
Peak memory 219548 kb
Host smart-e6140350-0088-4dd8-98ee-2b0ee5258dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372669793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.2372669793
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.1771415174
Short name T94
Test name
Test status
Simulation time 31725772 ps
CPU time 1.2 seconds
Started Aug 18 06:12:03 PM PDT 24
Finished Aug 18 06:12:04 PM PDT 24
Peak memory 219568 kb
Host smart-48fce1a7-b983-4454-a9df-ab0a76e35ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771415174 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.1771415174
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.1311988157
Short name T779
Test name
Test status
Simulation time 64934652 ps
CPU time 1.27 seconds
Started Aug 18 06:12:06 PM PDT 24
Finished Aug 18 06:12:07 PM PDT 24
Peak memory 218596 kb
Host smart-ca8b3823-ce91-4794-9f61-215a053d6d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311988157 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1311988157
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.2654431053
Short name T837
Test name
Test status
Simulation time 26583888 ps
CPU time 1.1 seconds
Started Aug 18 06:12:02 PM PDT 24
Finished Aug 18 06:12:03 PM PDT 24
Peak memory 219820 kb
Host smart-1d01b55e-f0a6-45e0-bff6-97e3eb518261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654431053 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.2654431053
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.3903934554
Short name T722
Test name
Test status
Simulation time 43729168 ps
CPU time 1.2 seconds
Started Aug 18 06:12:05 PM PDT 24
Finished Aug 18 06:12:07 PM PDT 24
Peak memory 220284 kb
Host smart-dcd227f4-643e-4b2b-9471-7f33a2b22ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903934554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3903934554
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.3480413827
Short name T238
Test name
Test status
Simulation time 77798468 ps
CPU time 1.16 seconds
Started Aug 18 06:10:41 PM PDT 24
Finished Aug 18 06:10:42 PM PDT 24
Peak memory 219952 kb
Host smart-70a73b86-e285-40c4-9712-96aad056b8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480413827 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.3480413827
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.3920809177
Short name T820
Test name
Test status
Simulation time 13043745 ps
CPU time 0.84 seconds
Started Aug 18 06:10:39 PM PDT 24
Finished Aug 18 06:10:40 PM PDT 24
Peak memory 206728 kb
Host smart-2f9bc940-9d6b-4944-bd76-de421358d5eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920809177 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3920809177
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.4227357708
Short name T225
Test name
Test status
Simulation time 12152229 ps
CPU time 0.97 seconds
Started Aug 18 06:10:46 PM PDT 24
Finished Aug 18 06:10:47 PM PDT 24
Peak memory 215528 kb
Host smart-1d872532-edbe-47da-9a2b-140a80673f3e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227357708 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.4227357708
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_err.840569199
Short name T196
Test name
Test status
Simulation time 23586077 ps
CPU time 0.94 seconds
Started Aug 18 06:10:42 PM PDT 24
Finished Aug 18 06:10:43 PM PDT 24
Peak memory 218328 kb
Host smart-30aa7892-e4f4-4eee-8c01-fe1ad7c60f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840569199 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.840569199
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.3793734995
Short name T895
Test name
Test status
Simulation time 64318814 ps
CPU time 1.25 seconds
Started Aug 18 06:10:45 PM PDT 24
Finished Aug 18 06:10:46 PM PDT 24
Peak memory 218348 kb
Host smart-81f73eb5-0ede-4205-87e9-186d323db7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793734995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.3793734995
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.1411725181
Short name T39
Test name
Test status
Simulation time 24548301 ps
CPU time 0.97 seconds
Started Aug 18 06:10:41 PM PDT 24
Finished Aug 18 06:10:42 PM PDT 24
Peak memory 215476 kb
Host smart-5f0e8189-ecd9-4ec3-8ef3-1a954a9f89fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411725181 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1411725181
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.3536614883
Short name T826
Test name
Test status
Simulation time 78926055 ps
CPU time 1.09 seconds
Started Aug 18 06:10:39 PM PDT 24
Finished Aug 18 06:10:41 PM PDT 24
Peak memory 215364 kb
Host smart-de293af2-1975-4254-94a1-6319ee46cdc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536614883 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.3536614883
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.2575574781
Short name T737
Test name
Test status
Simulation time 341862833 ps
CPU time 3.7 seconds
Started Aug 18 06:10:40 PM PDT 24
Finished Aug 18 06:10:44 PM PDT 24
Peak memory 215444 kb
Host smart-d70487a9-8489-4f37-86ea-9b66ed4b4df2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575574781 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2575574781
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.1628185300
Short name T248
Test name
Test status
Simulation time 4485271612 ps
CPU time 59.29 seconds
Started Aug 18 06:10:40 PM PDT 24
Finished Aug 18 06:11:39 PM PDT 24
Peak memory 218228 kb
Host smart-53dbdada-7c5c-4281-827b-552efdae61f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628185300 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.1628185300
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.1351097596
Short name T634
Test name
Test status
Simulation time 220089364 ps
CPU time 1.26 seconds
Started Aug 18 06:12:08 PM PDT 24
Finished Aug 18 06:12:10 PM PDT 24
Peak memory 220620 kb
Host smart-a5fe850e-e10a-4558-a5e4-71cd2185a997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351097596 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.1351097596
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.914308868
Short name T129
Test name
Test status
Simulation time 50107418 ps
CPU time 1.12 seconds
Started Aug 18 06:12:06 PM PDT 24
Finished Aug 18 06:12:07 PM PDT 24
Peak memory 220196 kb
Host smart-3eced29c-7300-49be-b353-5aa2a4e08bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914308868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.914308868
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.1678657026
Short name T822
Test name
Test status
Simulation time 22829074 ps
CPU time 1.27 seconds
Started Aug 18 06:12:04 PM PDT 24
Finished Aug 18 06:12:05 PM PDT 24
Peak memory 218720 kb
Host smart-76cf8c5f-79dc-4791-8c99-e5543e13f1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678657026 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.1678657026
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.3924771770
Short name T752
Test name
Test status
Simulation time 58485223 ps
CPU time 1.71 seconds
Started Aug 18 06:12:11 PM PDT 24
Finished Aug 18 06:12:13 PM PDT 24
Peak memory 220216 kb
Host smart-684d8f11-fbc8-4753-b444-4eb15c1021c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924771770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.3924771770
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.3434893569
Short name T761
Test name
Test status
Simulation time 71215203 ps
CPU time 1.09 seconds
Started Aug 18 06:12:06 PM PDT 24
Finished Aug 18 06:12:08 PM PDT 24
Peak memory 217436 kb
Host smart-69c019a8-daa1-4600-a18f-93b02c83cbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434893569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3434893569
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.4231708594
Short name T854
Test name
Test status
Simulation time 53175573 ps
CPU time 1.21 seconds
Started Aug 18 06:12:11 PM PDT 24
Finished Aug 18 06:12:13 PM PDT 24
Peak memory 218668 kb
Host smart-2a9180a6-5dca-48d7-af52-d63bc25a5b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231708594 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.4231708594
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.805346267
Short name T801
Test name
Test status
Simulation time 76350499 ps
CPU time 1.27 seconds
Started Aug 18 06:12:06 PM PDT 24
Finished Aug 18 06:12:08 PM PDT 24
Peak memory 219876 kb
Host smart-fbcf099d-5dd1-4af4-9219-0e5e867fe4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805346267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.805346267
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.3752343207
Short name T743
Test name
Test status
Simulation time 58097122 ps
CPU time 1.3 seconds
Started Aug 18 06:12:07 PM PDT 24
Finished Aug 18 06:12:08 PM PDT 24
Peak memory 215676 kb
Host smart-6607eeac-39cb-4be7-bad4-fe44c2ff64f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752343207 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.3752343207
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.3063388938
Short name T686
Test name
Test status
Simulation time 42457607 ps
CPU time 1.16 seconds
Started Aug 18 06:12:11 PM PDT 24
Finished Aug 18 06:12:12 PM PDT 24
Peak memory 218760 kb
Host smart-dbef3280-5cd6-4d8c-9568-b7d2f32666d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063388938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3063388938
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.2421724422
Short name T488
Test name
Test status
Simulation time 154517175 ps
CPU time 1.19 seconds
Started Aug 18 06:12:04 PM PDT 24
Finished Aug 18 06:12:05 PM PDT 24
Peak memory 219244 kb
Host smart-68425bfd-77a3-4a3b-8978-caf4db52f9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421724422 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.2421724422
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.574122205
Short name T613
Test name
Test status
Simulation time 99108128 ps
CPU time 1.65 seconds
Started Aug 18 06:12:05 PM PDT 24
Finished Aug 18 06:12:06 PM PDT 24
Peak memory 218980 kb
Host smart-4681e747-b218-4e33-8ec2-71d8e7433467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574122205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.574122205
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.918829661
Short name T376
Test name
Test status
Simulation time 74047224 ps
CPU time 1.46 seconds
Started Aug 18 06:12:06 PM PDT 24
Finished Aug 18 06:12:07 PM PDT 24
Peak memory 218620 kb
Host smart-58f8bb43-930c-4cc1-af06-2d6f4a07dbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918829661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.918829661
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.702389141
Short name T120
Test name
Test status
Simulation time 40287980 ps
CPU time 1.16 seconds
Started Aug 18 06:12:06 PM PDT 24
Finished Aug 18 06:12:07 PM PDT 24
Peak memory 220076 kb
Host smart-7ec1304b-9e28-4c50-b473-bbb61fa87c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702389141 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.702389141
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.3824653831
Short name T932
Test name
Test status
Simulation time 38861903 ps
CPU time 1.53 seconds
Started Aug 18 06:12:06 PM PDT 24
Finished Aug 18 06:12:08 PM PDT 24
Peak memory 218772 kb
Host smart-fa7e11df-3e2c-4f8c-b032-29a89c1033ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824653831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.3824653831
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.1132691503
Short name T320
Test name
Test status
Simulation time 29107807 ps
CPU time 1.32 seconds
Started Aug 18 06:12:06 PM PDT 24
Finished Aug 18 06:12:08 PM PDT 24
Peak memory 220304 kb
Host smart-ea8702d2-aad0-4849-b309-cf13efae4eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132691503 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.1132691503
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/129.edn_alert.3628032121
Short name T738
Test name
Test status
Simulation time 52722814 ps
CPU time 1.18 seconds
Started Aug 18 06:12:18 PM PDT 24
Finished Aug 18 06:12:19 PM PDT 24
Peak memory 218684 kb
Host smart-a17e3f6c-0e31-4971-866a-2fb9fda854a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628032121 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.3628032121
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.4209401869
Short name T754
Test name
Test status
Simulation time 78093748 ps
CPU time 1.19 seconds
Started Aug 18 06:12:06 PM PDT 24
Finished Aug 18 06:12:07 PM PDT 24
Peak memory 215288 kb
Host smart-fa9c1a37-5050-43af-a666-26dcc790f85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209401869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.4209401869
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert_test.2203356694
Short name T635
Test name
Test status
Simulation time 17611257 ps
CPU time 0.98 seconds
Started Aug 18 06:10:41 PM PDT 24
Finished Aug 18 06:10:42 PM PDT 24
Peak memory 206836 kb
Host smart-9ccd7e69-cb6d-40eb-8c5a-2f9f7564135f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203356694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2203356694
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.3783604399
Short name T708
Test name
Test status
Simulation time 16537396 ps
CPU time 0.94 seconds
Started Aug 18 06:10:38 PM PDT 24
Finished Aug 18 06:10:39 PM PDT 24
Peak memory 215600 kb
Host smart-e182adf5-40a7-4eed-8ea5-c1ab45ed2b80
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783604399 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.3783604399
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.2654110353
Short name T510
Test name
Test status
Simulation time 96803881 ps
CPU time 1.12 seconds
Started Aug 18 06:10:40 PM PDT 24
Finished Aug 18 06:10:41 PM PDT 24
Peak memory 216892 kb
Host smart-3499dd96-a28c-44f2-ae79-07ae720c7170
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654110353 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.2654110353
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_genbits.4222505729
Short name T99
Test name
Test status
Simulation time 72666439 ps
CPU time 1.41 seconds
Started Aug 18 06:10:46 PM PDT 24
Finished Aug 18 06:10:48 PM PDT 24
Peak memory 218828 kb
Host smart-acf46e0a-89f3-44d1-a050-28777180a4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222505729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.4222505729
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.2475265354
Short name T914
Test name
Test status
Simulation time 21989041 ps
CPU time 0.93 seconds
Started Aug 18 06:10:42 PM PDT 24
Finished Aug 18 06:10:43 PM PDT 24
Peak memory 215800 kb
Host smart-c1ef2f71-1848-4257-9fd7-c00d004a70e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475265354 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.2475265354
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.1815532370
Short name T964
Test name
Test status
Simulation time 19146433 ps
CPU time 0.92 seconds
Started Aug 18 06:10:40 PM PDT 24
Finished Aug 18 06:10:41 PM PDT 24
Peak memory 215400 kb
Host smart-b25be352-9b58-4dd9-8ecb-bee283c90302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815532370 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1815532370
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.1599361697
Short name T419
Test name
Test status
Simulation time 325799455 ps
CPU time 5.2 seconds
Started Aug 18 06:10:42 PM PDT 24
Finished Aug 18 06:10:47 PM PDT 24
Peak memory 217188 kb
Host smart-88a834df-14b2-4018-b984-1235c05fdf1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599361697 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1599361697
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.1329980309
Short name T582
Test name
Test status
Simulation time 18648342129 ps
CPU time 137.57 seconds
Started Aug 18 06:10:42 PM PDT 24
Finished Aug 18 06:12:59 PM PDT 24
Peak memory 219388 kb
Host smart-357f4f27-2a32-467c-83df-7205efbf281e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329980309 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.1329980309
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.2428579339
Short name T957
Test name
Test status
Simulation time 82104199 ps
CPU time 1.1 seconds
Started Aug 18 06:12:12 PM PDT 24
Finished Aug 18 06:12:13 PM PDT 24
Peak memory 220216 kb
Host smart-d0ab1fd2-e486-49fe-b70d-68db3d82c818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428579339 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.2428579339
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/131.edn_alert.3404197159
Short name T913
Test name
Test status
Simulation time 36113685 ps
CPU time 1.14 seconds
Started Aug 18 06:12:12 PM PDT 24
Finished Aug 18 06:12:14 PM PDT 24
Peak memory 219912 kb
Host smart-ab292b15-b6e0-4c1f-98b6-8e511c975e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404197159 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.3404197159
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.1146453580
Short name T42
Test name
Test status
Simulation time 89591833 ps
CPU time 3.16 seconds
Started Aug 18 06:12:13 PM PDT 24
Finished Aug 18 06:12:16 PM PDT 24
Peak memory 220660 kb
Host smart-5a04ef0c-6397-4abb-ba7a-f1fc1864e49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146453580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.1146453580
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.3992569394
Short name T145
Test name
Test status
Simulation time 32217982 ps
CPU time 1.37 seconds
Started Aug 18 06:12:15 PM PDT 24
Finished Aug 18 06:12:16 PM PDT 24
Peak memory 215780 kb
Host smart-624a5fcd-1749-4b0a-ba76-e27a8e9c57a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992569394 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.3992569394
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.1084444593
Short name T657
Test name
Test status
Simulation time 172073138 ps
CPU time 2.48 seconds
Started Aug 18 06:12:15 PM PDT 24
Finished Aug 18 06:12:18 PM PDT 24
Peak memory 219592 kb
Host smart-279c7ab1-d33c-464a-8132-7e03f5613776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084444593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1084444593
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.2985271247
Short name T832
Test name
Test status
Simulation time 52696258 ps
CPU time 1.15 seconds
Started Aug 18 06:12:12 PM PDT 24
Finished Aug 18 06:12:14 PM PDT 24
Peak memory 220448 kb
Host smart-ecd5afed-0290-473c-ae40-7fad55931a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985271247 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.2985271247
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.3994439584
Short name T271
Test name
Test status
Simulation time 152939526 ps
CPU time 1.12 seconds
Started Aug 18 06:12:13 PM PDT 24
Finished Aug 18 06:12:14 PM PDT 24
Peak memory 217596 kb
Host smart-efe848ab-4e5b-4445-b088-d3fc60d31e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994439584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3994439584
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.2030885159
Short name T444
Test name
Test status
Simulation time 52032570 ps
CPU time 1.61 seconds
Started Aug 18 06:12:14 PM PDT 24
Finished Aug 18 06:12:15 PM PDT 24
Peak memory 217500 kb
Host smart-6fd09395-6ad0-4a04-a10d-11160fb41e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030885159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2030885159
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.2860685127
Short name T311
Test name
Test status
Simulation time 29255495 ps
CPU time 1.26 seconds
Started Aug 18 06:12:14 PM PDT 24
Finished Aug 18 06:12:16 PM PDT 24
Peak memory 220804 kb
Host smart-c9d4ee6c-9b8f-4bb2-b85f-bcbed65dd2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860685127 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.2860685127
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.208980953
Short name T466
Test name
Test status
Simulation time 65616504 ps
CPU time 1 seconds
Started Aug 18 06:12:19 PM PDT 24
Finished Aug 18 06:12:20 PM PDT 24
Peak memory 217456 kb
Host smart-bbed7435-3ed2-4ffe-9a10-e4a87b021a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208980953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.208980953
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.3143300605
Short name T874
Test name
Test status
Simulation time 28976974 ps
CPU time 1.27 seconds
Started Aug 18 06:12:14 PM PDT 24
Finished Aug 18 06:12:16 PM PDT 24
Peak memory 218860 kb
Host smart-9cc817bc-9263-4b6b-b5e1-39e5668feeea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143300605 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.3143300605
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.3058607852
Short name T523
Test name
Test status
Simulation time 69698880 ps
CPU time 1.12 seconds
Started Aug 18 06:12:21 PM PDT 24
Finished Aug 18 06:12:22 PM PDT 24
Peak memory 217480 kb
Host smart-abbd9805-ced9-44c0-9c0e-282ae8801541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058607852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3058607852
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.1157137905
Short name T127
Test name
Test status
Simulation time 42823341 ps
CPU time 1.26 seconds
Started Aug 18 06:12:16 PM PDT 24
Finished Aug 18 06:12:18 PM PDT 24
Peak memory 218840 kb
Host smart-239f554d-c7dc-45c3-ae58-032555d5ed5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157137905 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.1157137905
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.1212771570
Short name T614
Test name
Test status
Simulation time 174326333 ps
CPU time 1.26 seconds
Started Aug 18 06:12:12 PM PDT 24
Finished Aug 18 06:12:14 PM PDT 24
Peak memory 218936 kb
Host smart-aaacbcbf-9023-4252-a073-9b65fa8c6b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212771570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1212771570
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.3152693685
Short name T388
Test name
Test status
Simulation time 34447610 ps
CPU time 1.44 seconds
Started Aug 18 06:12:16 PM PDT 24
Finished Aug 18 06:12:18 PM PDT 24
Peak memory 218552 kb
Host smart-5667e967-99c7-422d-9435-2c697a1a1754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152693685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.3152693685
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.500237350
Short name T946
Test name
Test status
Simulation time 24832726 ps
CPU time 1.16 seconds
Started Aug 18 06:12:12 PM PDT 24
Finished Aug 18 06:12:13 PM PDT 24
Peak memory 218756 kb
Host smart-7f1343cf-97f4-49ea-a222-222fbff06f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500237350 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.500237350
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.3960936483
Short name T800
Test name
Test status
Simulation time 72036259 ps
CPU time 1.15 seconds
Started Aug 18 06:12:19 PM PDT 24
Finished Aug 18 06:12:20 PM PDT 24
Peak memory 217556 kb
Host smart-5745bdd6-3df6-4901-a186-e603f5399460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960936483 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3960936483
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.549522063
Short name T524
Test name
Test status
Simulation time 47121427 ps
CPU time 1.09 seconds
Started Aug 18 06:10:41 PM PDT 24
Finished Aug 18 06:10:42 PM PDT 24
Peak memory 219688 kb
Host smart-5e01a883-3b13-4284-a8c1-cd739cfc5d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549522063 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.549522063
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.444001517
Short name T414
Test name
Test status
Simulation time 16896916 ps
CPU time 0.98 seconds
Started Aug 18 06:10:42 PM PDT 24
Finished Aug 18 06:10:43 PM PDT 24
Peak memory 206768 kb
Host smart-323f137d-5df7-48df-931c-b57ffa330c2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444001517 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.444001517
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_err.177906292
Short name T788
Test name
Test status
Simulation time 22626179 ps
CPU time 1.24 seconds
Started Aug 18 06:10:39 PM PDT 24
Finished Aug 18 06:10:41 PM PDT 24
Peak memory 224128 kb
Host smart-a4599406-fb7b-4bb9-a8b1-c779c43e8d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177906292 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.177906292
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.2173199546
Short name T473
Test name
Test status
Simulation time 240224749 ps
CPU time 1.39 seconds
Started Aug 18 06:10:42 PM PDT 24
Finished Aug 18 06:10:44 PM PDT 24
Peak memory 219048 kb
Host smart-84bcb0eb-4137-41da-aa2d-312864bfcffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173199546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2173199546
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.4173186642
Short name T673
Test name
Test status
Simulation time 21534359 ps
CPU time 1.08 seconds
Started Aug 18 06:10:45 PM PDT 24
Finished Aug 18 06:10:46 PM PDT 24
Peak memory 215744 kb
Host smart-20067128-74b3-4cc3-a26a-37154a38b808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173186642 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.4173186642
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.4285589947
Short name T879
Test name
Test status
Simulation time 159116038 ps
CPU time 1.01 seconds
Started Aug 18 06:10:41 PM PDT 24
Finished Aug 18 06:10:42 PM PDT 24
Peak memory 215336 kb
Host smart-c79479c9-95e3-4dc7-8fef-f21f1a6d7810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285589947 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.4285589947
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1586212890
Short name T906
Test name
Test status
Simulation time 52234476 ps
CPU time 1.71 seconds
Started Aug 18 06:10:40 PM PDT 24
Finished Aug 18 06:10:42 PM PDT 24
Peak memory 215456 kb
Host smart-e9035afb-9c45-4799-8356-ce68253bea3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586212890 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1586212890
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/140.edn_alert.547283422
Short name T870
Test name
Test status
Simulation time 25215656 ps
CPU time 1.16 seconds
Started Aug 18 06:12:14 PM PDT 24
Finished Aug 18 06:12:15 PM PDT 24
Peak memory 220636 kb
Host smart-2ab5f66e-e98e-49ca-982a-8713807ec451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547283422 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.547283422
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.3312602227
Short name T775
Test name
Test status
Simulation time 254562598 ps
CPU time 3.82 seconds
Started Aug 18 06:12:14 PM PDT 24
Finished Aug 18 06:12:18 PM PDT 24
Peak memory 217564 kb
Host smart-0cd2b575-637c-430d-acc1-f4952a261815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312602227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.3312602227
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.2853245306
Short name T789
Test name
Test status
Simulation time 29146746 ps
CPU time 1.27 seconds
Started Aug 18 06:12:13 PM PDT 24
Finished Aug 18 06:12:15 PM PDT 24
Peak memory 220576 kb
Host smart-c6dc3d76-4d11-43b7-83d5-948e6383c266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853245306 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.2853245306
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.516915026
Short name T939
Test name
Test status
Simulation time 286798857 ps
CPU time 1.42 seconds
Started Aug 18 06:12:14 PM PDT 24
Finished Aug 18 06:12:16 PM PDT 24
Peak memory 218820 kb
Host smart-f8b149f4-ba68-40de-839c-30a43c0b5103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516915026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.516915026
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.1713633043
Short name T672
Test name
Test status
Simulation time 40394381 ps
CPU time 1.16 seconds
Started Aug 18 06:12:14 PM PDT 24
Finished Aug 18 06:12:15 PM PDT 24
Peak memory 218856 kb
Host smart-a083c8c0-2d01-4e53-8171-1a15c4aef5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713633043 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.1713633043
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.2326764174
Short name T849
Test name
Test status
Simulation time 86448763 ps
CPU time 2.54 seconds
Started Aug 18 06:12:14 PM PDT 24
Finished Aug 18 06:12:17 PM PDT 24
Peak memory 218984 kb
Host smart-0e2793cf-1044-4abb-86d1-43ca23366343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326764174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2326764174
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.850562096
Short name T198
Test name
Test status
Simulation time 33887185 ps
CPU time 1.28 seconds
Started Aug 18 06:12:15 PM PDT 24
Finished Aug 18 06:12:16 PM PDT 24
Peak memory 221200 kb
Host smart-d40dde7e-c32f-45a0-8668-cb590009c029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850562096 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.850562096
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.1051704716
Short name T520
Test name
Test status
Simulation time 56845915 ps
CPU time 1.34 seconds
Started Aug 18 06:12:11 PM PDT 24
Finished Aug 18 06:12:12 PM PDT 24
Peak memory 219628 kb
Host smart-03ab0718-005f-4ebf-bb9a-afd49c90922e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051704716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.1051704716
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.1010943053
Short name T828
Test name
Test status
Simulation time 26933365 ps
CPU time 1.2 seconds
Started Aug 18 06:12:15 PM PDT 24
Finished Aug 18 06:12:16 PM PDT 24
Peak memory 215872 kb
Host smart-d4f0b35c-2fe9-4f75-89eb-711155f675cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010943053 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.1010943053
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/145.edn_alert.3054454271
Short name T566
Test name
Test status
Simulation time 86390193 ps
CPU time 1.15 seconds
Started Aug 18 06:12:14 PM PDT 24
Finished Aug 18 06:12:15 PM PDT 24
Peak memory 215768 kb
Host smart-b6450fee-72ad-4ede-91a1-19ca836a41aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054454271 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.3054454271
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.2917421143
Short name T579
Test name
Test status
Simulation time 43686227 ps
CPU time 1.48 seconds
Started Aug 18 06:12:15 PM PDT 24
Finished Aug 18 06:12:16 PM PDT 24
Peak memory 220372 kb
Host smart-ee6e817e-5037-4870-bf2d-e9813131779f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917421143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2917421143
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.3713937723
Short name T139
Test name
Test status
Simulation time 24851144 ps
CPU time 1.18 seconds
Started Aug 18 06:12:12 PM PDT 24
Finished Aug 18 06:12:13 PM PDT 24
Peak memory 218676 kb
Host smart-5baadb60-8772-4280-a42b-6cb4dff99384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713937723 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.3713937723
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.1929560250
Short name T855
Test name
Test status
Simulation time 52129262 ps
CPU time 1.83 seconds
Started Aug 18 06:12:16 PM PDT 24
Finished Aug 18 06:12:18 PM PDT 24
Peak memory 218544 kb
Host smart-160e6ec7-3149-4793-bb48-e0cf72627bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929560250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1929560250
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.58898253
Short name T242
Test name
Test status
Simulation time 134360541 ps
CPU time 1.23 seconds
Started Aug 18 06:12:14 PM PDT 24
Finished Aug 18 06:12:15 PM PDT 24
Peak memory 220376 kb
Host smart-53f7e818-2972-44d1-8a0a-dfbdebf0ae70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58898253 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.58898253
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.3044346019
Short name T84
Test name
Test status
Simulation time 62967486 ps
CPU time 1.04 seconds
Started Aug 18 06:12:13 PM PDT 24
Finished Aug 18 06:12:15 PM PDT 24
Peak memory 218780 kb
Host smart-45263c9f-ca1c-4c32-8e8f-f0125d24d69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044346019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3044346019
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.558070778
Short name T417
Test name
Test status
Simulation time 82574720 ps
CPU time 1.27 seconds
Started Aug 18 06:12:13 PM PDT 24
Finished Aug 18 06:12:14 PM PDT 24
Peak memory 218664 kb
Host smart-bf82e32b-ea03-4cd6-92b4-b48d7baebac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558070778 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.558070778
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/149.edn_alert.1627051874
Short name T135
Test name
Test status
Simulation time 74889846 ps
CPU time 1.22 seconds
Started Aug 18 06:12:14 PM PDT 24
Finished Aug 18 06:12:16 PM PDT 24
Peak memory 219044 kb
Host smart-d36c2f03-27fe-4108-812e-5d3f5ea51ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627051874 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.1627051874
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.3755284132
Short name T701
Test name
Test status
Simulation time 72568243 ps
CPU time 1.08 seconds
Started Aug 18 06:12:14 PM PDT 24
Finished Aug 18 06:12:15 PM PDT 24
Peak memory 215368 kb
Host smart-b5e39623-a7cd-41a8-8124-ff6354f0d22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755284132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.3755284132
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3840873231
Short name T966
Test name
Test status
Simulation time 75334542 ps
CPU time 1.16 seconds
Started Aug 18 06:10:45 PM PDT 24
Finished Aug 18 06:10:46 PM PDT 24
Peak memory 220312 kb
Host smart-701c7c7e-f698-4278-aa9c-adb9b9f0a01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840873231 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3840873231
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.2423153163
Short name T962
Test name
Test status
Simulation time 14895633 ps
CPU time 0.93 seconds
Started Aug 18 06:10:41 PM PDT 24
Finished Aug 18 06:10:42 PM PDT 24
Peak memory 214948 kb
Host smart-d9e7a008-e95e-455e-8024-fd094d79de65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423153163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2423153163
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.3900236690
Short name T463
Test name
Test status
Simulation time 21920074 ps
CPU time 0.84 seconds
Started Aug 18 06:10:52 PM PDT 24
Finished Aug 18 06:10:53 PM PDT 24
Peak memory 206888 kb
Host smart-51b5ad37-649b-45bf-97f7-65a4c598d6a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900236690 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3900236690
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2175590093
Short name T720
Test name
Test status
Simulation time 32968994 ps
CPU time 1.19 seconds
Started Aug 18 06:10:43 PM PDT 24
Finished Aug 18 06:10:44 PM PDT 24
Peak memory 218660 kb
Host smart-ffb53060-b73a-4756-bcef-61a5bdb01aa8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175590093 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2175590093
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.1092829921
Short name T583
Test name
Test status
Simulation time 28388185 ps
CPU time 1.29 seconds
Started Aug 18 06:10:40 PM PDT 24
Finished Aug 18 06:10:41 PM PDT 24
Peak memory 225656 kb
Host smart-efaf72ba-15ff-4762-a9eb-9d5dd3a00330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092829921 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1092829921
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.3759864451
Short name T317
Test name
Test status
Simulation time 116778941 ps
CPU time 1.45 seconds
Started Aug 18 06:10:37 PM PDT 24
Finished Aug 18 06:10:39 PM PDT 24
Peak memory 218784 kb
Host smart-493242d7-1d25-48f8-87db-2de080c9e400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759864451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.3759864451
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.3409599790
Short name T781
Test name
Test status
Simulation time 26201897 ps
CPU time 0.95 seconds
Started Aug 18 06:10:41 PM PDT 24
Finished Aug 18 06:10:42 PM PDT 24
Peak memory 215564 kb
Host smart-ee1fc4ae-d41d-4a16-b3f8-f6875a0f0c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409599790 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.3409599790
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.2189135772
Short name T422
Test name
Test status
Simulation time 52940847 ps
CPU time 0.97 seconds
Started Aug 18 06:10:46 PM PDT 24
Finished Aug 18 06:10:47 PM PDT 24
Peak memory 215276 kb
Host smart-f4ca6ecc-c0d8-4afb-b17e-70f875ed6449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189135772 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2189135772
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.717860113
Short name T816
Test name
Test status
Simulation time 583193574 ps
CPU time 3.46 seconds
Started Aug 18 06:10:40 PM PDT 24
Finished Aug 18 06:10:43 PM PDT 24
Peak memory 217152 kb
Host smart-4cb10cc7-332a-47d7-93f5-535cad917b51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717860113 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.717860113
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.1834456587
Short name T261
Test name
Test status
Simulation time 13210266974 ps
CPU time 162.53 seconds
Started Aug 18 06:10:40 PM PDT 24
Finished Aug 18 06:13:23 PM PDT 24
Peak memory 222336 kb
Host smart-b5cf7f7d-dbf7-4111-8ef8-8d63c80d7269
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834456587 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.1834456587
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.2434910115
Short name T492
Test name
Test status
Simulation time 255974788 ps
CPU time 1.38 seconds
Started Aug 18 06:12:15 PM PDT 24
Finished Aug 18 06:12:16 PM PDT 24
Peak memory 219580 kb
Host smart-f290325f-1b2e-470f-811c-fb1c4515e686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434910115 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.2434910115
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.3854171554
Short name T886
Test name
Test status
Simulation time 290638820 ps
CPU time 3.76 seconds
Started Aug 18 06:12:13 PM PDT 24
Finished Aug 18 06:12:17 PM PDT 24
Peak memory 220352 kb
Host smart-caefc89b-d67e-4fcd-a3c3-14be22ae1c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854171554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3854171554
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.2389695722
Short name T431
Test name
Test status
Simulation time 23988360 ps
CPU time 1.2 seconds
Started Aug 18 06:12:13 PM PDT 24
Finished Aug 18 06:12:15 PM PDT 24
Peak memory 219824 kb
Host smart-2353e35e-4179-4609-aa43-6fd292bdb2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389695722 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.2389695722
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.2611678001
Short name T486
Test name
Test status
Simulation time 91773677 ps
CPU time 1.99 seconds
Started Aug 18 06:12:13 PM PDT 24
Finished Aug 18 06:12:15 PM PDT 24
Peak memory 219072 kb
Host smart-c2593992-9933-4995-8668-694f9dcd2a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611678001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.2611678001
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.140459519
Short name T237
Test name
Test status
Simulation time 59848047 ps
CPU time 1.22 seconds
Started Aug 18 06:12:15 PM PDT 24
Finished Aug 18 06:12:16 PM PDT 24
Peak memory 221180 kb
Host smart-d601d691-c6db-435a-9bb4-71378305411b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140459519 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.140459519
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.2658449825
Short name T437
Test name
Test status
Simulation time 70140657 ps
CPU time 2.71 seconds
Started Aug 18 06:12:19 PM PDT 24
Finished Aug 18 06:12:22 PM PDT 24
Peak memory 220668 kb
Host smart-9ce66b01-6500-4a8b-8f5a-1dd6a948e15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658449825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.2658449825
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.2499423979
Short name T539
Test name
Test status
Simulation time 43376013 ps
CPU time 1.15 seconds
Started Aug 18 06:12:15 PM PDT 24
Finished Aug 18 06:12:16 PM PDT 24
Peak memory 219780 kb
Host smart-8f7d5dbe-c298-4b9e-ac13-1365a97d17a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499423979 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.2499423979
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.4157309562
Short name T567
Test name
Test status
Simulation time 50205129 ps
CPU time 1.26 seconds
Started Aug 18 06:12:14 PM PDT 24
Finished Aug 18 06:12:16 PM PDT 24
Peak memory 218732 kb
Host smart-f1e4ffe2-4d37-4366-8304-1ebdb0a240f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157309562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.4157309562
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.1419364954
Short name T780
Test name
Test status
Simulation time 26787572 ps
CPU time 1.14 seconds
Started Aug 18 06:12:17 PM PDT 24
Finished Aug 18 06:12:18 PM PDT 24
Peak memory 219736 kb
Host smart-c50084dc-9c22-49ed-a0ce-6a99beb0a072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419364954 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.1419364954
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.1135034181
Short name T430
Test name
Test status
Simulation time 54136647 ps
CPU time 1.03 seconds
Started Aug 18 06:12:15 PM PDT 24
Finished Aug 18 06:12:17 PM PDT 24
Peak memory 217148 kb
Host smart-9073bf12-e532-4843-ae96-b731d9645292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135034181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1135034181
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.1899353797
Short name T195
Test name
Test status
Simulation time 34158098 ps
CPU time 1.19 seconds
Started Aug 18 06:12:13 PM PDT 24
Finished Aug 18 06:12:15 PM PDT 24
Peak memory 220724 kb
Host smart-7b09291c-baad-4791-90e4-bb1ae558f299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899353797 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.1899353797
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.3003613003
Short name T961
Test name
Test status
Simulation time 65274147 ps
CPU time 1.16 seconds
Started Aug 18 06:12:14 PM PDT 24
Finished Aug 18 06:12:16 PM PDT 24
Peak memory 219060 kb
Host smart-c7fd2172-75f3-4837-820a-d117c8dd676d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003613003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3003613003
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.1679091341
Short name T968
Test name
Test status
Simulation time 25654253 ps
CPU time 1.25 seconds
Started Aug 18 06:12:14 PM PDT 24
Finished Aug 18 06:12:16 PM PDT 24
Peak memory 218620 kb
Host smart-07e0e83e-e6ac-4b3c-a94d-dee4870abb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679091341 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.1679091341
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.4070144317
Short name T571
Test name
Test status
Simulation time 26742703 ps
CPU time 1.19 seconds
Started Aug 18 06:12:19 PM PDT 24
Finished Aug 18 06:12:20 PM PDT 24
Peak memory 217396 kb
Host smart-5e861aee-a715-4d90-b410-007f24afd02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070144317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.4070144317
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.4172956553
Short name T945
Test name
Test status
Simulation time 45734960 ps
CPU time 1.15 seconds
Started Aug 18 06:12:21 PM PDT 24
Finished Aug 18 06:12:22 PM PDT 24
Peak memory 220676 kb
Host smart-4fbd65d3-93d9-4cd5-970d-e3cc3bd3bc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172956553 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.4172956553
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.3852534210
Short name T935
Test name
Test status
Simulation time 64136988 ps
CPU time 1.17 seconds
Started Aug 18 06:12:14 PM PDT 24
Finished Aug 18 06:12:15 PM PDT 24
Peak memory 218696 kb
Host smart-a74e7d75-9ab9-460e-894f-4298c136690a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852534210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.3852534210
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.1858794146
Short name T21
Test name
Test status
Simulation time 78420479 ps
CPU time 1.12 seconds
Started Aug 18 06:12:25 PM PDT 24
Finished Aug 18 06:12:26 PM PDT 24
Peak memory 218856 kb
Host smart-5fe18a8b-b042-48cb-9e69-5af391574186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858794146 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.1858794146
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.2979846392
Short name T667
Test name
Test status
Simulation time 80931023 ps
CPU time 2.87 seconds
Started Aug 18 06:12:14 PM PDT 24
Finished Aug 18 06:12:17 PM PDT 24
Peak memory 218956 kb
Host smart-50a66e04-0662-48b3-ae89-d4fcb0d78a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979846392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.2979846392
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.2189730159
Short name T496
Test name
Test status
Simulation time 45296493 ps
CPU time 1.23 seconds
Started Aug 18 06:10:40 PM PDT 24
Finished Aug 18 06:10:42 PM PDT 24
Peak memory 220668 kb
Host smart-7af7bcba-273c-44a2-837e-98e7393053fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189730159 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2189730159
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.1212766755
Short name T767
Test name
Test status
Simulation time 15834757 ps
CPU time 0.96 seconds
Started Aug 18 06:10:48 PM PDT 24
Finished Aug 18 06:10:49 PM PDT 24
Peak memory 206752 kb
Host smart-4427a612-9e24-40a0-934b-8105b4872eb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212766755 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1212766755
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.4270661249
Short name T880
Test name
Test status
Simulation time 12232776 ps
CPU time 0.9 seconds
Started Aug 18 06:10:47 PM PDT 24
Finished Aug 18 06:10:48 PM PDT 24
Peak memory 215592 kb
Host smart-6e92e96f-85dd-4670-bdeb-fde54a666a8b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270661249 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.4270661249
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1667046371
Short name T760
Test name
Test status
Simulation time 152311816 ps
CPU time 1.03 seconds
Started Aug 18 06:10:47 PM PDT 24
Finished Aug 18 06:10:48 PM PDT 24
Peak memory 216904 kb
Host smart-74487224-240f-4dc8-aa3c-51b82d2ba69b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667046371 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1667046371
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.3917993980
Short name T881
Test name
Test status
Simulation time 32299228 ps
CPU time 0.87 seconds
Started Aug 18 06:10:49 PM PDT 24
Finished Aug 18 06:10:50 PM PDT 24
Peak memory 218148 kb
Host smart-2124355b-d098-40ef-9226-e99ed6c8e997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917993980 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.3917993980
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.2933342103
Short name T799
Test name
Test status
Simulation time 39561459 ps
CPU time 1.49 seconds
Started Aug 18 06:10:40 PM PDT 24
Finished Aug 18 06:10:42 PM PDT 24
Peak memory 217556 kb
Host smart-81842503-1f8e-49b2-a907-1e529f9e2b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933342103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2933342103
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.785930112
Short name T105
Test name
Test status
Simulation time 26232058 ps
CPU time 0.93 seconds
Started Aug 18 06:10:40 PM PDT 24
Finished Aug 18 06:10:41 PM PDT 24
Peak memory 215840 kb
Host smart-30243671-0dd1-44e2-89d7-f4c62d77dc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785930112 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.785930112
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.493389965
Short name T75
Test name
Test status
Simulation time 47616393 ps
CPU time 0.86 seconds
Started Aug 18 06:10:50 PM PDT 24
Finished Aug 18 06:10:51 PM PDT 24
Peak memory 215280 kb
Host smart-2431887d-b8fa-4482-bf6c-9c5fa0c0d0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493389965 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.493389965
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/160.edn_alert.3875204485
Short name T314
Test name
Test status
Simulation time 33666294 ps
CPU time 1.38 seconds
Started Aug 18 06:12:35 PM PDT 24
Finished Aug 18 06:12:37 PM PDT 24
Peak memory 215780 kb
Host smart-46735e58-52d8-4eb6-8f7b-8db581b81613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875204485 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.3875204485
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.1941599864
Short name T890
Test name
Test status
Simulation time 60793199 ps
CPU time 1.09 seconds
Started Aug 18 06:12:20 PM PDT 24
Finished Aug 18 06:12:22 PM PDT 24
Peak memory 217516 kb
Host smart-7c8cd39f-f373-4804-8a13-d8c0217471b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941599864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1941599864
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.789787534
Short name T952
Test name
Test status
Simulation time 27593171 ps
CPU time 1.24 seconds
Started Aug 18 06:12:18 PM PDT 24
Finished Aug 18 06:12:20 PM PDT 24
Peak memory 218588 kb
Host smart-64a964dd-1b87-4249-b0ab-33e1286067ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789787534 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.789787534
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.360267487
Short name T552
Test name
Test status
Simulation time 159147168 ps
CPU time 1.16 seconds
Started Aug 18 06:12:18 PM PDT 24
Finished Aug 18 06:12:19 PM PDT 24
Peak memory 217620 kb
Host smart-1decc92c-b3cf-4200-80a9-7e9288b61b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360267487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.360267487
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.1772085014
Short name T877
Test name
Test status
Simulation time 180955239 ps
CPU time 1.26 seconds
Started Aug 18 06:12:24 PM PDT 24
Finished Aug 18 06:12:25 PM PDT 24
Peak memory 220820 kb
Host smart-3a1e58d8-06f7-4e82-bb3c-04f0ad201b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772085014 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.1772085014
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.2635527292
Short name T936
Test name
Test status
Simulation time 32272534 ps
CPU time 1.31 seconds
Started Aug 18 06:12:18 PM PDT 24
Finished Aug 18 06:12:20 PM PDT 24
Peak memory 220228 kb
Host smart-cf6f6d4a-94b9-4273-a0d0-1f702a887a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635527292 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.2635527292
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.1219063036
Short name T194
Test name
Test status
Simulation time 80934532 ps
CPU time 1.14 seconds
Started Aug 18 06:12:29 PM PDT 24
Finished Aug 18 06:12:30 PM PDT 24
Peak memory 218688 kb
Host smart-8959861f-d336-434a-9b83-410ad508e8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219063036 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.1219063036
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.671296263
Short name T683
Test name
Test status
Simulation time 32387431 ps
CPU time 1.49 seconds
Started Aug 18 06:12:19 PM PDT 24
Finished Aug 18 06:12:21 PM PDT 24
Peak memory 217340 kb
Host smart-26826cb1-3093-4f6b-b1c6-8ebf4e9c32c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671296263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.671296263
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.307312082
Short name T889
Test name
Test status
Simulation time 25089535 ps
CPU time 1.15 seconds
Started Aug 18 06:12:18 PM PDT 24
Finished Aug 18 06:12:20 PM PDT 24
Peak memory 217492 kb
Host smart-ba7dff65-31d9-4d84-9879-5a2f30c5519f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307312082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.307312082
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.3724614787
Short name T282
Test name
Test status
Simulation time 24727820 ps
CPU time 1.25 seconds
Started Aug 18 06:12:33 PM PDT 24
Finished Aug 18 06:12:34 PM PDT 24
Peak memory 219392 kb
Host smart-c4502268-eaa6-468f-8439-99fabd7edb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724614787 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.3724614787
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.1208633360
Short name T472
Test name
Test status
Simulation time 68756698 ps
CPU time 1.38 seconds
Started Aug 18 06:12:19 PM PDT 24
Finished Aug 18 06:12:20 PM PDT 24
Peak memory 217448 kb
Host smart-49d1f01e-70fb-40b9-a7d6-f080c10d57c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208633360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1208633360
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.2520011253
Short name T235
Test name
Test status
Simulation time 44098604 ps
CPU time 1.22 seconds
Started Aug 18 06:12:21 PM PDT 24
Finished Aug 18 06:12:22 PM PDT 24
Peak memory 220484 kb
Host smart-9233ee80-bd7c-4055-a831-536766344262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520011253 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.2520011253
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/167.edn_alert.4092891419
Short name T659
Test name
Test status
Simulation time 225061900 ps
CPU time 1.12 seconds
Started Aug 18 06:12:28 PM PDT 24
Finished Aug 18 06:12:29 PM PDT 24
Peak memory 219156 kb
Host smart-7cd885a6-0f4a-42e0-8dc0-7c2a01875f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092891419 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.4092891419
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.894545230
Short name T354
Test name
Test status
Simulation time 89302156 ps
CPU time 1.14 seconds
Started Aug 18 06:12:20 PM PDT 24
Finished Aug 18 06:12:21 PM PDT 24
Peak memory 217400 kb
Host smart-1c720229-907e-47ba-912e-1666710d7b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894545230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.894545230
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.4242452636
Short name T331
Test name
Test status
Simulation time 51549276 ps
CPU time 1.22 seconds
Started Aug 18 06:12:19 PM PDT 24
Finished Aug 18 06:12:20 PM PDT 24
Peak memory 215784 kb
Host smart-5a05419f-e12f-4618-9f31-6c8e416beda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242452636 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.4242452636
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.749122205
Short name T531
Test name
Test status
Simulation time 26277004 ps
CPU time 1.36 seconds
Started Aug 18 06:12:20 PM PDT 24
Finished Aug 18 06:12:22 PM PDT 24
Peak memory 217796 kb
Host smart-50dc459d-a299-46d5-ad7f-af4f789678db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749122205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.749122205
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.4045940146
Short name T274
Test name
Test status
Simulation time 47381376 ps
CPU time 1.19 seconds
Started Aug 18 06:12:22 PM PDT 24
Finished Aug 18 06:12:23 PM PDT 24
Peak memory 220220 kb
Host smart-fd6bc6ac-810e-4829-8034-642a4073870e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045940146 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.4045940146
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.559234584
Short name T468
Test name
Test status
Simulation time 43202292 ps
CPU time 1.4 seconds
Started Aug 18 06:12:30 PM PDT 24
Finished Aug 18 06:12:31 PM PDT 24
Peak memory 218880 kb
Host smart-59cb9edf-5534-4f20-b886-8f78fae5bee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559234584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.559234584
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.3134621401
Short name T550
Test name
Test status
Simulation time 26151701 ps
CPU time 1.28 seconds
Started Aug 18 06:10:46 PM PDT 24
Finished Aug 18 06:10:48 PM PDT 24
Peak memory 219692 kb
Host smart-d9bbae3e-91e7-400a-939d-6d2591fb115e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134621401 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.3134621401
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.33267033
Short name T864
Test name
Test status
Simulation time 129766888 ps
CPU time 0.84 seconds
Started Aug 18 06:10:46 PM PDT 24
Finished Aug 18 06:10:47 PM PDT 24
Peak memory 206632 kb
Host smart-87f05786-8610-4aa7-b92b-07fc90b33e84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33267033 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.33267033
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.276354777
Short name T633
Test name
Test status
Simulation time 33078782 ps
CPU time 1.21 seconds
Started Aug 18 06:10:48 PM PDT 24
Finished Aug 18 06:10:49 PM PDT 24
Peak memory 216832 kb
Host smart-eebb27d8-0154-48cc-9626-5987a3a39e56
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276354777 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_di
sable_auto_req_mode.276354777
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.984909502
Short name T182
Test name
Test status
Simulation time 30757431 ps
CPU time 0.84 seconds
Started Aug 18 06:10:46 PM PDT 24
Finished Aug 18 06:10:47 PM PDT 24
Peak memory 218256 kb
Host smart-fa2f2e7f-9181-41e6-b67f-3cd89745084a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984909502 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.984909502
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.4120670082
Short name T89
Test name
Test status
Simulation time 73785780 ps
CPU time 1.07 seconds
Started Aug 18 06:10:51 PM PDT 24
Finished Aug 18 06:10:53 PM PDT 24
Peak memory 217332 kb
Host smart-ee813a20-b57b-418a-ba76-cb0931429c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120670082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.4120670082
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_smoke.1540111835
Short name T470
Test name
Test status
Simulation time 19278510 ps
CPU time 1.03 seconds
Started Aug 18 06:10:47 PM PDT 24
Finished Aug 18 06:10:48 PM PDT 24
Peak memory 215340 kb
Host smart-0baf53a1-9464-43d1-9a34-da01acd4aa1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540111835 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.1540111835
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.2052752930
Short name T263
Test name
Test status
Simulation time 7546541262 ps
CPU time 85.88 seconds
Started Aug 18 06:10:47 PM PDT 24
Finished Aug 18 06:12:13 PM PDT 24
Peak memory 219084 kb
Host smart-f8c72df4-2574-4449-8e9c-15d2d4834f3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052752930 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.2052752930
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.3073788136
Short name T594
Test name
Test status
Simulation time 98450601 ps
CPU time 1.36 seconds
Started Aug 18 06:12:24 PM PDT 24
Finished Aug 18 06:12:25 PM PDT 24
Peak memory 219832 kb
Host smart-df284b46-f9a6-4c36-a006-ed0886b71d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073788136 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.3073788136
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.1125453905
Short name T512
Test name
Test status
Simulation time 52993325 ps
CPU time 1.19 seconds
Started Aug 18 06:12:17 PM PDT 24
Finished Aug 18 06:12:19 PM PDT 24
Peak memory 217416 kb
Host smart-3e8492c1-ff75-4a15-9f3d-7b06a35ea18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125453905 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1125453905
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.1567292810
Short name T186
Test name
Test status
Simulation time 69490235 ps
CPU time 1.06 seconds
Started Aug 18 06:12:33 PM PDT 24
Finished Aug 18 06:12:34 PM PDT 24
Peak memory 220104 kb
Host smart-273ddad2-53e7-4511-9a43-f931fdf9571d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567292810 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.1567292810
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.481791993
Short name T873
Test name
Test status
Simulation time 171085832 ps
CPU time 1.41 seconds
Started Aug 18 06:12:17 PM PDT 24
Finished Aug 18 06:12:19 PM PDT 24
Peak memory 217288 kb
Host smart-aa817ed6-b655-4e10-8f66-f9d8a193dc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481791993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.481791993
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.1186239966
Short name T287
Test name
Test status
Simulation time 116836001 ps
CPU time 1.3 seconds
Started Aug 18 06:12:27 PM PDT 24
Finished Aug 18 06:12:28 PM PDT 24
Peak memory 219892 kb
Host smart-9294dd9e-d161-43d0-906a-83832fbcf933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186239966 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.1186239966
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.3891475519
Short name T562
Test name
Test status
Simulation time 56276323 ps
CPU time 0.97 seconds
Started Aug 18 06:12:22 PM PDT 24
Finished Aug 18 06:12:23 PM PDT 24
Peak memory 217464 kb
Host smart-ae30ba44-d309-4dbb-b639-7256c6643f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891475519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3891475519
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.3599002168
Short name T475
Test name
Test status
Simulation time 27938067 ps
CPU time 1.2 seconds
Started Aug 18 06:12:36 PM PDT 24
Finished Aug 18 06:12:37 PM PDT 24
Peak memory 220752 kb
Host smart-66b59f5e-2088-4117-987f-126a9d377933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599002168 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.3599002168
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.1612083438
Short name T959
Test name
Test status
Simulation time 169542700 ps
CPU time 1.21 seconds
Started Aug 18 06:12:29 PM PDT 24
Finished Aug 18 06:12:31 PM PDT 24
Peak memory 217428 kb
Host smart-f89c2459-7eab-4469-9dcc-e1b45bae6a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612083438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1612083438
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.1461367262
Short name T921
Test name
Test status
Simulation time 86585833 ps
CPU time 1.22 seconds
Started Aug 18 06:12:21 PM PDT 24
Finished Aug 18 06:12:22 PM PDT 24
Peak memory 218644 kb
Host smart-f421c9d1-6935-4fa1-81c9-f18c128c80ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461367262 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.1461367262
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.2570721258
Short name T762
Test name
Test status
Simulation time 39906844 ps
CPU time 1.43 seconds
Started Aug 18 06:12:31 PM PDT 24
Finished Aug 18 06:12:33 PM PDT 24
Peak memory 217468 kb
Host smart-c5d064c0-d34f-4e16-9544-f3c8b903f0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570721258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2570721258
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.688621301
Short name T66
Test name
Test status
Simulation time 73129527 ps
CPU time 1.13 seconds
Started Aug 18 06:12:20 PM PDT 24
Finished Aug 18 06:12:21 PM PDT 24
Peak memory 218912 kb
Host smart-63234ea0-2c57-4285-a0cd-a03651368f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688621301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.688621301
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.3224285535
Short name T656
Test name
Test status
Simulation time 25697026 ps
CPU time 1.23 seconds
Started Aug 18 06:12:33 PM PDT 24
Finished Aug 18 06:12:34 PM PDT 24
Peak memory 218844 kb
Host smart-453ac072-3519-425e-b540-95edfe824105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224285535 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.3224285535
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/177.edn_alert.4063596620
Short name T443
Test name
Test status
Simulation time 26344349 ps
CPU time 1.2 seconds
Started Aug 18 06:12:24 PM PDT 24
Finished Aug 18 06:12:26 PM PDT 24
Peak memory 219848 kb
Host smart-caca0f66-c1c2-41ee-8342-dc8134c20a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063596620 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.4063596620
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/178.edn_alert.2553089808
Short name T887
Test name
Test status
Simulation time 35639103 ps
CPU time 1.11 seconds
Started Aug 18 06:12:37 PM PDT 24
Finished Aug 18 06:12:38 PM PDT 24
Peak memory 219996 kb
Host smart-f9edc572-3164-494a-a305-32e66dd97cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553089808 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.2553089808
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.168654735
Short name T949
Test name
Test status
Simulation time 70600515 ps
CPU time 1.14 seconds
Started Aug 18 06:12:32 PM PDT 24
Finished Aug 18 06:12:34 PM PDT 24
Peak memory 217492 kb
Host smart-79dc9666-01e6-4341-a3fa-2305c031c480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168654735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.168654735
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.4184124217
Short name T80
Test name
Test status
Simulation time 26602867 ps
CPU time 1.25 seconds
Started Aug 18 06:12:27 PM PDT 24
Finished Aug 18 06:12:28 PM PDT 24
Peak memory 220456 kb
Host smart-4d43f6f1-dc4a-4d97-bc05-e8d0d4b5e3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184124217 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.4184124217
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.1427728083
Short name T842
Test name
Test status
Simulation time 51065476 ps
CPU time 1.25 seconds
Started Aug 18 06:12:25 PM PDT 24
Finished Aug 18 06:12:26 PM PDT 24
Peak memory 217592 kb
Host smart-1846237b-26c1-443d-a95e-004ac94c97af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427728083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.1427728083
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.4135104629
Short name T901
Test name
Test status
Simulation time 44543741 ps
CPU time 1.13 seconds
Started Aug 18 06:10:47 PM PDT 24
Finished Aug 18 06:10:48 PM PDT 24
Peak memory 218832 kb
Host smart-42f67300-ffcf-402b-a702-a65e20b48e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135104629 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.4135104629
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.4084605865
Short name T626
Test name
Test status
Simulation time 23103147 ps
CPU time 1.06 seconds
Started Aug 18 06:10:51 PM PDT 24
Finished Aug 18 06:10:52 PM PDT 24
Peak memory 206868 kb
Host smart-2259a903-e44d-4e7b-bd95-e2dbb558f499
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084605865 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.4084605865
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.788077586
Short name T438
Test name
Test status
Simulation time 31263119 ps
CPU time 0.85 seconds
Started Aug 18 06:10:46 PM PDT 24
Finished Aug 18 06:10:47 PM PDT 24
Peak memory 207016 kb
Host smart-0c70f623-6305-4dd0-89e7-75987bb31936
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788077586 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.788077586
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2179412780
Short name T479
Test name
Test status
Simulation time 27917440 ps
CPU time 1.18 seconds
Started Aug 18 06:10:49 PM PDT 24
Finished Aug 18 06:10:50 PM PDT 24
Peak memory 216720 kb
Host smart-c03b54d8-9961-4f9c-b8b7-ac81ade15f79
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179412780 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2179412780
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.252781902
Short name T158
Test name
Test status
Simulation time 30320545 ps
CPU time 1.01 seconds
Started Aug 18 06:10:48 PM PDT 24
Finished Aug 18 06:10:49 PM PDT 24
Peak memory 219656 kb
Host smart-05c92562-3a58-4d6a-9ad9-d860e79e0e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252781902 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.252781902
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.3907923670
Short name T838
Test name
Test status
Simulation time 65294854 ps
CPU time 1.07 seconds
Started Aug 18 06:10:55 PM PDT 24
Finished Aug 18 06:10:57 PM PDT 24
Peak memory 217304 kb
Host smart-1de3b0ae-93a1-413c-82aa-1f88fe7bedfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907923670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.3907923670
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1421938981
Short name T137
Test name
Test status
Simulation time 30503155 ps
CPU time 0.86 seconds
Started Aug 18 06:10:46 PM PDT 24
Finished Aug 18 06:10:47 PM PDT 24
Peak memory 215920 kb
Host smart-79d668e6-e47c-4559-b112-e8971f2ef90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421938981 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1421938981
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.440904770
Short name T426
Test name
Test status
Simulation time 52535382 ps
CPU time 0.94 seconds
Started Aug 18 06:10:46 PM PDT 24
Finished Aug 18 06:10:47 PM PDT 24
Peak memory 215304 kb
Host smart-78dd1262-7f7a-49f9-b667-1e66c901c6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440904770 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.440904770
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.2726621353
Short name T528
Test name
Test status
Simulation time 1211163639 ps
CPU time 5.04 seconds
Started Aug 18 06:10:49 PM PDT 24
Finished Aug 18 06:10:54 PM PDT 24
Peak memory 217452 kb
Host smart-25d5883e-e01f-4023-b77b-2604f7ef4fe2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726621353 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.2726621353
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2919687121
Short name T260
Test name
Test status
Simulation time 4495505310 ps
CPU time 101.55 seconds
Started Aug 18 06:10:52 PM PDT 24
Finished Aug 18 06:12:34 PM PDT 24
Peak memory 218172 kb
Host smart-d6d0cb8e-a6e2-4acf-bcfe-c1aa841eb40f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919687121 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2919687121
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.2654992456
Short name T763
Test name
Test status
Simulation time 27680743 ps
CPU time 1.29 seconds
Started Aug 18 06:12:22 PM PDT 24
Finished Aug 18 06:12:24 PM PDT 24
Peak memory 218836 kb
Host smart-b6a68cbd-4854-4920-a401-ec70b452e55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654992456 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.2654992456
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.3647545768
Short name T402
Test name
Test status
Simulation time 111650841 ps
CPU time 1.19 seconds
Started Aug 18 06:12:24 PM PDT 24
Finished Aug 18 06:12:26 PM PDT 24
Peak memory 219032 kb
Host smart-5543df43-0a36-4d51-a0f6-19f8e4de099b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647545768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3647545768
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.2450179617
Short name T385
Test name
Test status
Simulation time 31106367 ps
CPU time 1.45 seconds
Started Aug 18 06:12:20 PM PDT 24
Finished Aug 18 06:12:22 PM PDT 24
Peak memory 217500 kb
Host smart-1ba3ace4-4e36-4f7d-bd91-2056c64bfd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450179617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.2450179617
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.68181092
Short name T687
Test name
Test status
Simulation time 37967539 ps
CPU time 1.16 seconds
Started Aug 18 06:12:47 PM PDT 24
Finished Aug 18 06:12:49 PM PDT 24
Peak memory 219820 kb
Host smart-0cdf7288-0f95-437b-b054-a5123a13325d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68181092 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.68181092
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.3067144521
Short name T841
Test name
Test status
Simulation time 149196348 ps
CPU time 1.36 seconds
Started Aug 18 06:12:20 PM PDT 24
Finished Aug 18 06:12:22 PM PDT 24
Peak memory 217492 kb
Host smart-c4adec41-9ec3-468f-9889-d8ebce61ea0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067144521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.3067144521
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.2886751878
Short name T963
Test name
Test status
Simulation time 51414143 ps
CPU time 1.7 seconds
Started Aug 18 06:12:20 PM PDT 24
Finished Aug 18 06:12:22 PM PDT 24
Peak memory 218776 kb
Host smart-4656be90-373d-41e2-9bd1-7f99181476fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886751878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.2886751878
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.954588071
Short name T749
Test name
Test status
Simulation time 36636640 ps
CPU time 1.24 seconds
Started Aug 18 06:12:24 PM PDT 24
Finished Aug 18 06:12:26 PM PDT 24
Peak memory 219112 kb
Host smart-f15f34d1-033d-4cae-9dd2-92c4572d57d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954588071 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.954588071
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/185.edn_alert.2955147430
Short name T951
Test name
Test status
Simulation time 39938642 ps
CPU time 1.1 seconds
Started Aug 18 06:12:36 PM PDT 24
Finished Aug 18 06:12:37 PM PDT 24
Peak memory 218460 kb
Host smart-b0e17892-de25-4557-bc1f-82b9d6136c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955147430 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.2955147430
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.415534160
Short name T778
Test name
Test status
Simulation time 126136537 ps
CPU time 2.87 seconds
Started Aug 18 06:12:22 PM PDT 24
Finished Aug 18 06:12:25 PM PDT 24
Peak memory 218764 kb
Host smart-7a0ac6d2-5a94-455c-9429-c077631b897f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415534160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.415534160
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.229582263
Short name T691
Test name
Test status
Simulation time 27075722 ps
CPU time 1.22 seconds
Started Aug 18 06:12:32 PM PDT 24
Finished Aug 18 06:12:33 PM PDT 24
Peak memory 218840 kb
Host smart-956795b3-8302-4486-8b32-00a7a3205835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229582263 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.229582263
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.3845786816
Short name T527
Test name
Test status
Simulation time 45577929 ps
CPU time 1.42 seconds
Started Aug 18 06:12:35 PM PDT 24
Finished Aug 18 06:12:37 PM PDT 24
Peak memory 218548 kb
Host smart-a368dd15-c9de-48e7-9dab-5fa9fc021b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845786816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3845786816
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.3003341119
Short name T958
Test name
Test status
Simulation time 64015009 ps
CPU time 1.14 seconds
Started Aug 18 06:12:44 PM PDT 24
Finished Aug 18 06:12:46 PM PDT 24
Peak memory 219772 kb
Host smart-603a39b7-8930-46b9-9c28-3dfd137e5d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003341119 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.3003341119
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.3756382500
Short name T446
Test name
Test status
Simulation time 52701503 ps
CPU time 1.2 seconds
Started Aug 18 06:12:35 PM PDT 24
Finished Aug 18 06:12:36 PM PDT 24
Peak memory 218584 kb
Host smart-82001b1e-cbc4-48db-8d7c-b6c55740727e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756382500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3756382500
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.2287088262
Short name T627
Test name
Test status
Simulation time 69686445 ps
CPU time 1.18 seconds
Started Aug 18 06:12:35 PM PDT 24
Finished Aug 18 06:12:36 PM PDT 24
Peak memory 219716 kb
Host smart-c1ae82ce-6cf8-40ee-842c-d140dcf4ad31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287088262 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.2287088262
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.376815563
Short name T515
Test name
Test status
Simulation time 92863491 ps
CPU time 1.16 seconds
Started Aug 18 06:12:41 PM PDT 24
Finished Aug 18 06:12:42 PM PDT 24
Peak memory 217448 kb
Host smart-e02c7f2d-185e-4e15-9fc6-990012867575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376815563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.376815563
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert_test.98226150
Short name T68
Test name
Test status
Simulation time 16123625 ps
CPU time 0.9 seconds
Started Aug 18 06:10:45 PM PDT 24
Finished Aug 18 06:10:46 PM PDT 24
Peak memory 214984 kb
Host smart-7c333f20-7c95-4037-a984-21af653e9ab7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98226150 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.98226150
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.2996897798
Short name T714
Test name
Test status
Simulation time 13893158 ps
CPU time 0.92 seconds
Started Aug 18 06:10:48 PM PDT 24
Finished Aug 18 06:10:49 PM PDT 24
Peak memory 215628 kb
Host smart-ade58c16-d8e9-4f35-a498-a1227b49794f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996897798 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2996897798
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_err.2415451154
Short name T203
Test name
Test status
Simulation time 25319728 ps
CPU time 1 seconds
Started Aug 18 06:10:47 PM PDT 24
Finished Aug 18 06:10:48 PM PDT 24
Peak memory 223952 kb
Host smart-8ecf07ce-ebf8-4415-94ca-49eb70cc7596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415451154 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.2415451154
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.713235496
Short name T809
Test name
Test status
Simulation time 59689061 ps
CPU time 1.21 seconds
Started Aug 18 06:10:49 PM PDT 24
Finished Aug 18 06:10:51 PM PDT 24
Peak memory 219276 kb
Host smart-ebdc369e-d7a1-4fb8-9bde-25674893daf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713235496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.713235496
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.4116069329
Short name T808
Test name
Test status
Simulation time 21885043 ps
CPU time 1.08 seconds
Started Aug 18 06:10:57 PM PDT 24
Finished Aug 18 06:10:58 PM PDT 24
Peak memory 215508 kb
Host smart-6cdd417f-1f32-42c3-b241-bdeaa63483a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116069329 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.4116069329
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.3442667319
Short name T834
Test name
Test status
Simulation time 30725408 ps
CPU time 0.93 seconds
Started Aug 18 06:10:48 PM PDT 24
Finished Aug 18 06:10:49 PM PDT 24
Peak memory 215384 kb
Host smart-2276ab8d-6bb7-44fd-8c7d-0b095a7b4d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442667319 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.3442667319
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.804702659
Short name T489
Test name
Test status
Simulation time 220202223 ps
CPU time 1.59 seconds
Started Aug 18 06:10:47 PM PDT 24
Finished Aug 18 06:10:48 PM PDT 24
Peak memory 217312 kb
Host smart-fc7dd9a4-9565-4487-982c-d5178d9dcf53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804702659 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.804702659
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.3011680256
Short name T840
Test name
Test status
Simulation time 8972724648 ps
CPU time 62.42 seconds
Started Aug 18 06:10:47 PM PDT 24
Finished Aug 18 06:11:50 PM PDT 24
Peak memory 217480 kb
Host smart-592b231d-62b2-441b-a317-787a87f4ea79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011680256 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.3011680256
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.2956642972
Short name T603
Test name
Test status
Simulation time 96976618 ps
CPU time 1.19 seconds
Started Aug 18 06:12:33 PM PDT 24
Finished Aug 18 06:12:34 PM PDT 24
Peak memory 218732 kb
Host smart-f300ca48-688c-4f2e-92c1-47dd51e83e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956642972 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.2956642972
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.196138690
Short name T507
Test name
Test status
Simulation time 186055222 ps
CPU time 1.08 seconds
Started Aug 18 06:12:21 PM PDT 24
Finished Aug 18 06:12:22 PM PDT 24
Peak memory 217540 kb
Host smart-e77252e2-b4b9-44e0-b3cd-601ccabbfb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196138690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.196138690
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.3655866371
Short name T703
Test name
Test status
Simulation time 71710509 ps
CPU time 1.16 seconds
Started Aug 18 06:12:22 PM PDT 24
Finished Aug 18 06:12:23 PM PDT 24
Peak memory 220612 kb
Host smart-1e08ccfb-1fcd-4b00-b59e-04ad5a244cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655866371 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.3655866371
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.2959320493
Short name T624
Test name
Test status
Simulation time 61071540 ps
CPU time 1.2 seconds
Started Aug 18 06:12:33 PM PDT 24
Finished Aug 18 06:12:34 PM PDT 24
Peak memory 218576 kb
Host smart-e82eb84b-20d8-485f-bd4e-cb27aac0cdb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959320493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2959320493
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.4110730599
Short name T927
Test name
Test status
Simulation time 22752223 ps
CPU time 1.12 seconds
Started Aug 18 06:12:28 PM PDT 24
Finished Aug 18 06:12:29 PM PDT 24
Peak memory 220888 kb
Host smart-03d6b701-8a4b-4f52-a677-652cf919e5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110730599 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.4110730599
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.2097361497
Short name T476
Test name
Test status
Simulation time 70257868 ps
CPU time 1.29 seconds
Started Aug 18 06:12:36 PM PDT 24
Finished Aug 18 06:12:37 PM PDT 24
Peak memory 218904 kb
Host smart-dee49122-0260-445f-ad88-945c3a294634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097361497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2097361497
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.1858655907
Short name T619
Test name
Test status
Simulation time 31597473 ps
CPU time 1.08 seconds
Started Aug 18 06:12:22 PM PDT 24
Finished Aug 18 06:12:23 PM PDT 24
Peak memory 218928 kb
Host smart-3d622744-19b0-4cf4-9262-31d48bc7670a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858655907 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.1858655907
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.694984714
Short name T825
Test name
Test status
Simulation time 44456313 ps
CPU time 1.54 seconds
Started Aug 18 06:12:29 PM PDT 24
Finished Aug 18 06:12:31 PM PDT 24
Peak memory 218472 kb
Host smart-c3c788dc-cd8f-4b4a-9ce0-6b8dc885caf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694984714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.694984714
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.2091046715
Short name T283
Test name
Test status
Simulation time 65516145 ps
CPU time 1.35 seconds
Started Aug 18 06:12:26 PM PDT 24
Finished Aug 18 06:12:28 PM PDT 24
Peak memory 220184 kb
Host smart-e7218a61-7ac0-44f8-9265-1d405fae5af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091046715 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.2091046715
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.248945477
Short name T428
Test name
Test status
Simulation time 90502453 ps
CPU time 1.15 seconds
Started Aug 18 06:12:36 PM PDT 24
Finished Aug 18 06:12:37 PM PDT 24
Peak memory 217400 kb
Host smart-34576e2c-c4fb-4135-b92c-040042bfc1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248945477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.248945477
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.831340875
Short name T83
Test name
Test status
Simulation time 190734192 ps
CPU time 1.25 seconds
Started Aug 18 06:12:33 PM PDT 24
Finished Aug 18 06:12:34 PM PDT 24
Peak memory 220140 kb
Host smart-6f3db2c5-6a49-479a-b8d3-b934d1582668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831340875 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.831340875
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.360312988
Short name T776
Test name
Test status
Simulation time 77015872 ps
CPU time 2.14 seconds
Started Aug 18 06:12:28 PM PDT 24
Finished Aug 18 06:12:30 PM PDT 24
Peak memory 219652 kb
Host smart-70f4da32-9ee0-478d-9403-f7c3ca47365a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360312988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.360312988
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.1767330737
Short name T910
Test name
Test status
Simulation time 39638334 ps
CPU time 1.14 seconds
Started Aug 18 06:12:33 PM PDT 24
Finished Aug 18 06:12:34 PM PDT 24
Peak memory 218784 kb
Host smart-4220dacf-3052-4aa3-bb60-5ea2417f1ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767330737 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.1767330737
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.648957389
Short name T639
Test name
Test status
Simulation time 64235595 ps
CPU time 1.05 seconds
Started Aug 18 06:12:31 PM PDT 24
Finished Aug 18 06:12:32 PM PDT 24
Peak memory 217244 kb
Host smart-f9da6c60-877f-4ba3-8aa1-72ab20be54eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648957389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.648957389
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.678857798
Short name T404
Test name
Test status
Simulation time 23545969 ps
CPU time 1.15 seconds
Started Aug 18 06:12:33 PM PDT 24
Finished Aug 18 06:12:34 PM PDT 24
Peak memory 218752 kb
Host smart-fee85287-fdc9-4da0-baee-08905c6ae930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678857798 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.678857798
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.3657396360
Short name T682
Test name
Test status
Simulation time 134943061 ps
CPU time 1.39 seconds
Started Aug 18 06:12:41 PM PDT 24
Finished Aug 18 06:12:42 PM PDT 24
Peak memory 218956 kb
Host smart-dd9e0850-c426-4b74-b8de-10e513458695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657396360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3657396360
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.3094473423
Short name T732
Test name
Test status
Simulation time 23136754 ps
CPU time 1.2 seconds
Started Aug 18 06:12:38 PM PDT 24
Finished Aug 18 06:12:40 PM PDT 24
Peak memory 218988 kb
Host smart-9506bf96-47e5-4dcb-9bac-f16296c60ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094473423 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.3094473423
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.727759702
Short name T432
Test name
Test status
Simulation time 128464585 ps
CPU time 1.55 seconds
Started Aug 18 06:12:37 PM PDT 24
Finished Aug 18 06:12:38 PM PDT 24
Peak memory 217592 kb
Host smart-5e60db64-5ca4-4879-b6fd-759397c2013d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727759702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.727759702
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.3757540500
Short name T85
Test name
Test status
Simulation time 39418393 ps
CPU time 1.28 seconds
Started Aug 18 06:12:40 PM PDT 24
Finished Aug 18 06:12:41 PM PDT 24
Peak memory 218528 kb
Host smart-e6d6701b-5efe-49dc-952f-0e3106a85b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757540500 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.3757540500
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.2511188850
Short name T727
Test name
Test status
Simulation time 439988508 ps
CPU time 3.65 seconds
Started Aug 18 06:12:42 PM PDT 24
Finished Aug 18 06:12:46 PM PDT 24
Peak memory 218948 kb
Host smart-ac15e7d4-ef39-400c-a8ce-acdf7750ad71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511188850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2511188850
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.125511246
Short name T916
Test name
Test status
Simulation time 39718345 ps
CPU time 1.12 seconds
Started Aug 18 06:10:10 PM PDT 24
Finished Aug 18 06:10:11 PM PDT 24
Peak memory 218676 kb
Host smart-7961870a-c888-4e07-b83f-8c80fe0277a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125511246 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.125511246
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.1207580323
Short name T711
Test name
Test status
Simulation time 23697859 ps
CPU time 0.91 seconds
Started Aug 18 06:10:11 PM PDT 24
Finished Aug 18 06:10:12 PM PDT 24
Peak memory 206716 kb
Host smart-e476dade-e92d-4afe-bbc9-3c6c7e762afc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207580323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.1207580323
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.1658984046
Short name T96
Test name
Test status
Simulation time 36035592 ps
CPU time 0.83 seconds
Started Aug 18 06:10:10 PM PDT 24
Finished Aug 18 06:10:11 PM PDT 24
Peak memory 215484 kb
Host smart-cb8dffcd-d43a-416a-872a-afc1ac7e63c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658984046 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1658984046
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.3495218865
Short name T730
Test name
Test status
Simulation time 27362221 ps
CPU time 1.14 seconds
Started Aug 18 06:10:10 PM PDT 24
Finished Aug 18 06:10:11 PM PDT 24
Peak memory 219696 kb
Host smart-7d2ede31-9ec5-4a30-a681-3a1e7bbcc296
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495218865 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.3495218865
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.3368632780
Short name T218
Test name
Test status
Simulation time 36680804 ps
CPU time 0.83 seconds
Started Aug 18 06:10:12 PM PDT 24
Finished Aug 18 06:10:13 PM PDT 24
Peak memory 218244 kb
Host smart-698b2a00-f501-4b41-bc53-5dcc118accfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368632780 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.3368632780
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.3404566287
Short name T491
Test name
Test status
Simulation time 37484573 ps
CPU time 1.37 seconds
Started Aug 18 06:10:09 PM PDT 24
Finished Aug 18 06:10:10 PM PDT 24
Peak memory 220320 kb
Host smart-ca5e1dc9-895b-4132-9e27-66fed1a049ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404566287 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3404566287
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.2570749985
Short name T108
Test name
Test status
Simulation time 27580243 ps
CPU time 0.92 seconds
Started Aug 18 06:10:09 PM PDT 24
Finished Aug 18 06:10:10 PM PDT 24
Peak memory 215924 kb
Host smart-a6ea3d28-f623-498d-980c-7430c542a6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570749985 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2570749985
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.347155254
Short name T755
Test name
Test status
Simulation time 15197880 ps
CPU time 0.92 seconds
Started Aug 18 06:10:10 PM PDT 24
Finished Aug 18 06:10:11 PM PDT 24
Peak memory 207192 kb
Host smart-66f97c5a-0d37-4859-8eaf-b17206b15175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347155254 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.347155254
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.1721611933
Short name T17
Test name
Test status
Simulation time 1098618497 ps
CPU time 9.17 seconds
Started Aug 18 06:10:10 PM PDT 24
Finished Aug 18 06:10:20 PM PDT 24
Peak memory 240604 kb
Host smart-48dcab25-44bc-4b7d-8808-8f14a2d586f9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721611933 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1721611933
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.3681896080
Short name T928
Test name
Test status
Simulation time 31263937 ps
CPU time 0.99 seconds
Started Aug 18 06:10:03 PM PDT 24
Finished Aug 18 06:10:04 PM PDT 24
Peak memory 215304 kb
Host smart-e573b337-78d5-4523-aa71-ccce2ffa63b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681896080 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.3681896080
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.2484806043
Short name T113
Test name
Test status
Simulation time 516564497 ps
CPU time 6.23 seconds
Started Aug 18 06:10:08 PM PDT 24
Finished Aug 18 06:10:14 PM PDT 24
Peak memory 220060 kb
Host smart-4cf09103-9a6b-4f33-a574-8824554e32da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484806043 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2484806043
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.3199664487
Short name T258
Test name
Test status
Simulation time 10255789118 ps
CPU time 44.79 seconds
Started Aug 18 06:10:10 PM PDT 24
Finished Aug 18 06:10:55 PM PDT 24
Peak memory 218056 kb
Host smart-396201e4-9931-45ab-9677-5ed132ba8524
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199664487 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.3199664487
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.3571066969
Short name T169
Test name
Test status
Simulation time 50682307 ps
CPU time 1.25 seconds
Started Aug 18 06:10:49 PM PDT 24
Finished Aug 18 06:10:50 PM PDT 24
Peak memory 219508 kb
Host smart-40ba6258-1035-4f48-9c0e-fe7d0a2da20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571066969 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.3571066969
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.1951585181
Short name T954
Test name
Test status
Simulation time 24925117 ps
CPU time 0.88 seconds
Started Aug 18 06:10:49 PM PDT 24
Finished Aug 18 06:10:50 PM PDT 24
Peak memory 206780 kb
Host smart-609e5f2b-355f-4f24-956c-912ff1549686
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951585181 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.1951585181
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.1939479370
Short name T652
Test name
Test status
Simulation time 16831032 ps
CPU time 0.84 seconds
Started Aug 18 06:10:47 PM PDT 24
Finished Aug 18 06:10:48 PM PDT 24
Peak memory 215216 kb
Host smart-d38a0302-b366-4a4e-9b90-68b9337e70d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939479370 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1939479370
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.2111409511
Short name T285
Test name
Test status
Simulation time 222837061 ps
CPU time 1.16 seconds
Started Aug 18 06:10:49 PM PDT 24
Finished Aug 18 06:10:51 PM PDT 24
Peak memory 217028 kb
Host smart-40975ba4-91fc-47f3-a6e8-bcfa870b804d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111409511 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.2111409511
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_genbits.2132840334
Short name T454
Test name
Test status
Simulation time 52678758 ps
CPU time 1.08 seconds
Started Aug 18 06:10:49 PM PDT 24
Finished Aug 18 06:10:50 PM PDT 24
Peak memory 217764 kb
Host smart-90acfe0b-7330-4e76-b5de-9d1dc0c6524b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132840334 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.2132840334
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.101298506
Short name T106
Test name
Test status
Simulation time 23609401 ps
CPU time 1 seconds
Started Aug 18 06:10:47 PM PDT 24
Finished Aug 18 06:10:48 PM PDT 24
Peak memory 215996 kb
Host smart-8fb87ea2-696b-4448-bef5-69def3b7c828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101298506 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.101298506
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.1514802721
Short name T442
Test name
Test status
Simulation time 36268072 ps
CPU time 0.92 seconds
Started Aug 18 06:10:52 PM PDT 24
Finished Aug 18 06:10:53 PM PDT 24
Peak memory 215384 kb
Host smart-2015a57a-57de-4313-aed3-23e5433cb608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514802721 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.1514802721
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.24356110
Short name T280
Test name
Test status
Simulation time 463666241 ps
CPU time 2.4 seconds
Started Aug 18 06:10:49 PM PDT 24
Finished Aug 18 06:10:52 PM PDT 24
Peak memory 215404 kb
Host smart-de43780c-1541-4ff4-a076-279c10881499
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24356110 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.24356110
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/200.edn_genbits.292832058
Short name T495
Test name
Test status
Simulation time 58293702 ps
CPU time 1.24 seconds
Started Aug 18 06:12:28 PM PDT 24
Finished Aug 18 06:12:29 PM PDT 24
Peak memory 219524 kb
Host smart-18feb964-919d-4b16-aa9b-0cbab580a8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292832058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.292832058
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.1273215602
Short name T395
Test name
Test status
Simulation time 75063703 ps
CPU time 1.17 seconds
Started Aug 18 06:12:37 PM PDT 24
Finished Aug 18 06:12:38 PM PDT 24
Peak memory 220388 kb
Host smart-1f32d549-ef8a-4d5e-a79a-1429dbe40e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273215602 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.1273215602
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.1375940867
Short name T322
Test name
Test status
Simulation time 121588770 ps
CPU time 1.23 seconds
Started Aug 18 06:12:39 PM PDT 24
Finished Aug 18 06:12:40 PM PDT 24
Peak memory 220340 kb
Host smart-cc04393c-cab2-4321-97f0-c976a597d240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375940867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.1375940867
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2363907303
Short name T674
Test name
Test status
Simulation time 35616601 ps
CPU time 1.42 seconds
Started Aug 18 06:12:33 PM PDT 24
Finished Aug 18 06:12:35 PM PDT 24
Peak memory 217424 kb
Host smart-78cf7e9e-932f-436e-bb2f-b2c978158cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363907303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2363907303
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.3660838944
Short name T122
Test name
Test status
Simulation time 41083678 ps
CPU time 1.68 seconds
Started Aug 18 06:12:51 PM PDT 24
Finished Aug 18 06:12:53 PM PDT 24
Peak memory 218880 kb
Host smart-31f4a124-d43b-47a1-885b-500f94ff4c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660838944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3660838944
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.3990192727
Short name T37
Test name
Test status
Simulation time 35054268 ps
CPU time 1.08 seconds
Started Aug 18 06:12:37 PM PDT 24
Finished Aug 18 06:12:39 PM PDT 24
Peak memory 218840 kb
Host smart-0fe9dd1d-6014-41f5-8dfa-a07abd6bed09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990192727 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.3990192727
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.740899497
Short name T706
Test name
Test status
Simulation time 73986844 ps
CPU time 1.2 seconds
Started Aug 18 06:12:43 PM PDT 24
Finished Aug 18 06:12:44 PM PDT 24
Peak memory 218780 kb
Host smart-959b8498-1264-474b-a86e-948ff5419f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740899497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.740899497
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.90263384
Short name T971
Test name
Test status
Simulation time 72306401 ps
CPU time 1.1 seconds
Started Aug 18 06:12:39 PM PDT 24
Finished Aug 18 06:12:40 PM PDT 24
Peak memory 217356 kb
Host smart-72733934-344a-45d8-b065-2a48fd92feaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90263384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.90263384
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.2772080832
Short name T174
Test name
Test status
Simulation time 124000105 ps
CPU time 1.35 seconds
Started Aug 18 06:10:49 PM PDT 24
Finished Aug 18 06:10:50 PM PDT 24
Peak memory 219876 kb
Host smart-eddc93eb-1263-4a1c-a1d5-6abe94c8d3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772080832 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.2772080832
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.3528162021
Short name T380
Test name
Test status
Simulation time 68504709 ps
CPU time 0.81 seconds
Started Aug 18 06:10:48 PM PDT 24
Finished Aug 18 06:10:49 PM PDT 24
Peak memory 206900 kb
Host smart-ee986db1-ddb0-4808-b84f-517256af90e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528162021 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3528162021
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.3092637811
Short name T575
Test name
Test status
Simulation time 28810704 ps
CPU time 0.86 seconds
Started Aug 18 06:10:48 PM PDT 24
Finished Aug 18 06:10:49 PM PDT 24
Peak memory 215444 kb
Host smart-4417df92-8c29-4638-ac49-985343c3d68f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092637811 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3092637811
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.1350697803
Short name T161
Test name
Test status
Simulation time 74115563 ps
CPU time 1.07 seconds
Started Aug 18 06:10:57 PM PDT 24
Finished Aug 18 06:10:58 PM PDT 24
Peak memory 216844 kb
Host smart-b527840a-f5b1-4783-9483-44aac74bb3ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350697803 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.1350697803
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.3115314506
Short name T616
Test name
Test status
Simulation time 34194782 ps
CPU time 0.92 seconds
Started Aug 18 06:10:48 PM PDT 24
Finished Aug 18 06:10:49 PM PDT 24
Peak memory 218352 kb
Host smart-3731bd90-cbfd-4b0a-91da-f4db2b6a2338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115314506 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3115314506
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.2496167954
Short name T90
Test name
Test status
Simulation time 111820711 ps
CPU time 1.74 seconds
Started Aug 18 06:10:50 PM PDT 24
Finished Aug 18 06:10:52 PM PDT 24
Peak memory 218980 kb
Host smart-7537ff56-a53f-4d2e-b912-bd6c276b423b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496167954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2496167954
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3898306946
Short name T43
Test name
Test status
Simulation time 74508830 ps
CPU time 0.85 seconds
Started Aug 18 06:10:57 PM PDT 24
Finished Aug 18 06:10:58 PM PDT 24
Peak memory 215336 kb
Host smart-b4262027-34a6-42c2-8e6c-224fc4663add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898306946 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3898306946
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.47848060
Short name T396
Test name
Test status
Simulation time 15224921 ps
CPU time 1 seconds
Started Aug 18 06:10:51 PM PDT 24
Finished Aug 18 06:10:53 PM PDT 24
Peak memory 207212 kb
Host smart-573cfd05-b3e3-44d8-86ee-7431d266b806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47848060 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.47848060
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.759982953
Short name T49
Test name
Test status
Simulation time 212653835 ps
CPU time 1.11 seconds
Started Aug 18 06:10:52 PM PDT 24
Finished Aug 18 06:10:53 PM PDT 24
Peak memory 206544 kb
Host smart-c05d9a3d-e632-46c1-b97e-1e2b775d277f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759982953 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.759982953
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.1630746827
Short name T553
Test name
Test status
Simulation time 1689914212 ps
CPU time 45.01 seconds
Started Aug 18 06:10:51 PM PDT 24
Finished Aug 18 06:11:37 PM PDT 24
Peak memory 220292 kb
Host smart-b3e856f8-df3d-4b52-9041-743fe3b34239
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630746827 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.1630746827
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.1479232169
Short name T485
Test name
Test status
Simulation time 67701790 ps
CPU time 1.08 seconds
Started Aug 18 06:12:49 PM PDT 24
Finished Aug 18 06:12:50 PM PDT 24
Peak memory 219268 kb
Host smart-fb399b96-60f3-4143-bfac-8105388ac517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479232169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.1479232169
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.2513529984
Short name T471
Test name
Test status
Simulation time 49045465 ps
CPU time 1.17 seconds
Started Aug 18 06:12:39 PM PDT 24
Finished Aug 18 06:12:40 PM PDT 24
Peak memory 220304 kb
Host smart-071eca82-af59-418c-98eb-50df08308f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513529984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2513529984
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.2727226295
Short name T508
Test name
Test status
Simulation time 30144673 ps
CPU time 1.37 seconds
Started Aug 18 06:12:45 PM PDT 24
Finished Aug 18 06:12:47 PM PDT 24
Peak memory 218648 kb
Host smart-37185dc2-a4b1-42c5-ab20-80d2583e8d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727226295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2727226295
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3495831303
Short name T453
Test name
Test status
Simulation time 40523836 ps
CPU time 1.4 seconds
Started Aug 18 06:12:33 PM PDT 24
Finished Aug 18 06:12:35 PM PDT 24
Peak memory 217536 kb
Host smart-7f7b8beb-5e29-4624-ba07-831b5560a3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495831303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3495831303
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.2181409269
Short name T393
Test name
Test status
Simulation time 39061494 ps
CPU time 1.67 seconds
Started Aug 18 06:12:40 PM PDT 24
Finished Aug 18 06:12:41 PM PDT 24
Peak memory 218596 kb
Host smart-ad2a91e3-e7e8-43d7-b148-5201227c9d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181409269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.2181409269
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.1494221137
Short name T599
Test name
Test status
Simulation time 106419573 ps
CPU time 1.62 seconds
Started Aug 18 06:12:42 PM PDT 24
Finished Aug 18 06:12:44 PM PDT 24
Peak memory 219088 kb
Host smart-bfc3965c-ad0f-4e4d-b5a4-1737ea3661a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494221137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.1494221137
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.2957017608
Short name T908
Test name
Test status
Simulation time 43532777 ps
CPU time 1.56 seconds
Started Aug 18 06:12:41 PM PDT 24
Finished Aug 18 06:12:42 PM PDT 24
Peak memory 220456 kb
Host smart-3604041e-e05b-4945-b5d6-9cc6dcf4a58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957017608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2957017608
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.4039526578
Short name T384
Test name
Test status
Simulation time 58883467 ps
CPU time 1.33 seconds
Started Aug 18 06:12:44 PM PDT 24
Finished Aug 18 06:12:45 PM PDT 24
Peak memory 217460 kb
Host smart-2a764ed9-cb2d-4323-9d97-616e4927f6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039526578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.4039526578
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2570879124
Short name T581
Test name
Test status
Simulation time 61019376 ps
CPU time 1.69 seconds
Started Aug 18 06:12:41 PM PDT 24
Finished Aug 18 06:12:42 PM PDT 24
Peak memory 218756 kb
Host smart-7a5baa7e-ee76-45a1-b4d1-c6c9790d9a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570879124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2570879124
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1528149467
Short name T514
Test name
Test status
Simulation time 47849076 ps
CPU time 1.38 seconds
Started Aug 18 06:12:45 PM PDT 24
Finished Aug 18 06:12:47 PM PDT 24
Peak memory 217580 kb
Host smart-36ec7fcc-1451-4162-a2bd-2e1374e7845b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528149467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1528149467
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.2966557636
Short name T134
Test name
Test status
Simulation time 39485794 ps
CPU time 1.17 seconds
Started Aug 18 06:11:01 PM PDT 24
Finished Aug 18 06:11:02 PM PDT 24
Peak memory 218708 kb
Host smart-ec698ced-89be-4e21-9a31-efaea3f55c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966557636 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2966557636
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.2718361295
Short name T733
Test name
Test status
Simulation time 28354943 ps
CPU time 0.96 seconds
Started Aug 18 06:11:03 PM PDT 24
Finished Aug 18 06:11:05 PM PDT 24
Peak memory 214988 kb
Host smart-b31c83f0-52c6-4915-8a70-a5cdeb5d9732
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718361295 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2718361295
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.1317979135
Short name T65
Test name
Test status
Simulation time 28223416 ps
CPU time 0.83 seconds
Started Aug 18 06:11:02 PM PDT 24
Finished Aug 18 06:11:03 PM PDT 24
Peak memory 215172 kb
Host smart-4f7101d4-2384-41ff-b771-8ecd9347f4d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317979135 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.1317979135
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.2981713354
Short name T907
Test name
Test status
Simulation time 56660460 ps
CPU time 1.14 seconds
Started Aug 18 06:10:54 PM PDT 24
Finished Aug 18 06:10:55 PM PDT 24
Peak memory 216844 kb
Host smart-b704b77b-0485-4a51-967f-f43fcce9d13e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981713354 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.2981713354
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.3414153143
Short name T505
Test name
Test status
Simulation time 23297598 ps
CPU time 1.09 seconds
Started Aug 18 06:10:58 PM PDT 24
Finished Aug 18 06:10:59 PM PDT 24
Peak memory 218612 kb
Host smart-9addb287-4955-429f-b3ff-011a13e38b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414153143 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3414153143
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.736293232
Short name T537
Test name
Test status
Simulation time 73539877 ps
CPU time 1.18 seconds
Started Aug 18 06:10:49 PM PDT 24
Finished Aug 18 06:10:50 PM PDT 24
Peak memory 217660 kb
Host smart-19e07b97-83f1-49f4-8662-f250dade298d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736293232 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.736293232
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.4181790618
Short name T794
Test name
Test status
Simulation time 35650321 ps
CPU time 1.01 seconds
Started Aug 18 06:10:48 PM PDT 24
Finished Aug 18 06:10:49 PM PDT 24
Peak memory 224276 kb
Host smart-a61e02a7-cd09-4031-b6b1-ec584ae22227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181790618 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.4181790618
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.2608898234
Short name T933
Test name
Test status
Simulation time 18219283 ps
CPU time 0.99 seconds
Started Aug 18 06:10:52 PM PDT 24
Finished Aug 18 06:10:53 PM PDT 24
Peak memory 215384 kb
Host smart-16b5b8dc-7869-4d3a-93ce-3701228f0297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608898234 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2608898234
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2933835958
Short name T678
Test name
Test status
Simulation time 278670749 ps
CPU time 3.36 seconds
Started Aug 18 06:10:52 PM PDT 24
Finished Aug 18 06:10:56 PM PDT 24
Peak memory 215404 kb
Host smart-f89848ed-a45a-4a7d-98e1-827bf97ba937
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933835958 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2933835958
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3066983253
Short name T259
Test name
Test status
Simulation time 1311366931 ps
CPU time 30.68 seconds
Started Aug 18 06:10:51 PM PDT 24
Finished Aug 18 06:11:22 PM PDT 24
Peak memory 223776 kb
Host smart-f1ac3601-a504-48e3-8cc6-ba17a2054526
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066983253 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3066983253
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.1861958417
Short name T595
Test name
Test status
Simulation time 92756768 ps
CPU time 1.15 seconds
Started Aug 18 06:12:33 PM PDT 24
Finished Aug 18 06:12:34 PM PDT 24
Peak memory 217408 kb
Host smart-c00d584e-e0ee-4ff0-8d05-a0fe8c44c0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861958417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.1861958417
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.781884961
Short name T356
Test name
Test status
Simulation time 36518823 ps
CPU time 1.28 seconds
Started Aug 18 06:12:47 PM PDT 24
Finished Aug 18 06:12:49 PM PDT 24
Peak memory 218616 kb
Host smart-ac75421f-933b-4090-86de-388dd6ada00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781884961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.781884961
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.2412434018
Short name T617
Test name
Test status
Simulation time 63248040 ps
CPU time 1.79 seconds
Started Aug 18 06:12:38 PM PDT 24
Finished Aug 18 06:12:40 PM PDT 24
Peak memory 220388 kb
Host smart-764b22bf-7d1e-4729-9634-c650528c015f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412434018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.2412434018
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.154638454
Short name T894
Test name
Test status
Simulation time 91208229 ps
CPU time 1.19 seconds
Started Aug 18 06:12:35 PM PDT 24
Finished Aug 18 06:12:36 PM PDT 24
Peak memory 218628 kb
Host smart-c878fc9d-2e23-4424-b8cf-f68395c6666c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154638454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.154638454
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.2581381162
Short name T255
Test name
Test status
Simulation time 67439095 ps
CPU time 1.64 seconds
Started Aug 18 06:12:28 PM PDT 24
Finished Aug 18 06:12:30 PM PDT 24
Peak memory 218928 kb
Host smart-3f76c747-134a-4329-8c9d-5ec330cec6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581381162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2581381162
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.3982529748
Short name T560
Test name
Test status
Simulation time 131904161 ps
CPU time 1.08 seconds
Started Aug 18 06:12:38 PM PDT 24
Finished Aug 18 06:12:39 PM PDT 24
Peak memory 217428 kb
Host smart-78d03206-0d24-4992-92c7-588b74446ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982529748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3982529748
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3793733191
Short name T572
Test name
Test status
Simulation time 41257404 ps
CPU time 1.27 seconds
Started Aug 18 06:12:42 PM PDT 24
Finished Aug 18 06:12:43 PM PDT 24
Peak memory 217292 kb
Host smart-7d4f6fa9-42d7-4671-9141-f53c3eb832cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793733191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3793733191
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.1319601940
Short name T253
Test name
Test status
Simulation time 48277965 ps
CPU time 1.38 seconds
Started Aug 18 06:12:39 PM PDT 24
Finished Aug 18 06:12:41 PM PDT 24
Peak memory 219336 kb
Host smart-343f2035-1799-4090-9337-b4f62724ec74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319601940 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1319601940
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.2813812187
Short name T868
Test name
Test status
Simulation time 113951980 ps
CPU time 1.14 seconds
Started Aug 18 06:12:41 PM PDT 24
Finished Aug 18 06:12:42 PM PDT 24
Peak memory 217488 kb
Host smart-1c9c40c1-ba74-4916-8013-8fdf34372c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813812187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2813812187
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.601809947
Short name T251
Test name
Test status
Simulation time 331053109 ps
CPU time 1.32 seconds
Started Aug 18 06:12:47 PM PDT 24
Finished Aug 18 06:12:49 PM PDT 24
Peak memory 217532 kb
Host smart-4f28f937-4a1c-496d-a114-e50ce37dbc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601809947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.601809947
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.1652074132
Short name T915
Test name
Test status
Simulation time 64316223 ps
CPU time 1.12 seconds
Started Aug 18 06:11:03 PM PDT 24
Finished Aug 18 06:11:05 PM PDT 24
Peak memory 218796 kb
Host smart-77eb50f4-f8d8-4621-93fc-d57e38eac8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652074132 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1652074132
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.2876977351
Short name T694
Test name
Test status
Simulation time 18923500 ps
CPU time 0.94 seconds
Started Aug 18 06:10:57 PM PDT 24
Finished Aug 18 06:10:58 PM PDT 24
Peak memory 206792 kb
Host smart-ca0dbae1-efa0-4f06-bace-9ea3435cf5ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876977351 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.2876977351
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.2433384708
Short name T190
Test name
Test status
Simulation time 34475856 ps
CPU time 0.81 seconds
Started Aug 18 06:11:03 PM PDT 24
Finished Aug 18 06:11:04 PM PDT 24
Peak memory 215452 kb
Host smart-506bd5f8-b282-4591-8eed-01a85b937492
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433384708 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2433384708
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_err.2775067668
Short name T176
Test name
Test status
Simulation time 18695754 ps
CPU time 1.02 seconds
Started Aug 18 06:10:53 PM PDT 24
Finished Aug 18 06:10:54 PM PDT 24
Peak memory 218592 kb
Host smart-50381492-86e9-4110-9744-b134d45813fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775067668 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.2775067668
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.2376670104
Short name T728
Test name
Test status
Simulation time 47383587 ps
CPU time 1.21 seconds
Started Aug 18 06:10:56 PM PDT 24
Finished Aug 18 06:10:57 PM PDT 24
Peak memory 217416 kb
Host smart-6d862da5-3cc9-4a5b-a24c-a0e0da4da7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376670104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2376670104
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.1448304539
Short name T252
Test name
Test status
Simulation time 28743975 ps
CPU time 0.9 seconds
Started Aug 18 06:10:54 PM PDT 24
Finished Aug 18 06:10:55 PM PDT 24
Peak memory 215600 kb
Host smart-b3779f4c-e841-49be-99b9-dcdf061fb962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448304539 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1448304539
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.1198954719
Short name T589
Test name
Test status
Simulation time 23353346 ps
CPU time 1.02 seconds
Started Aug 18 06:10:55 PM PDT 24
Finished Aug 18 06:10:56 PM PDT 24
Peak memory 215360 kb
Host smart-ec4a21dc-56ba-4862-aa90-a39da0b0a6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198954719 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.1198954719
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3605568164
Short name T115
Test name
Test status
Simulation time 48628004 ps
CPU time 1.45 seconds
Started Aug 18 06:10:55 PM PDT 24
Finished Aug 18 06:10:56 PM PDT 24
Peak memory 215536 kb
Host smart-3be38d58-4405-4921-877a-b59819775b04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605568164 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3605568164
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/230.edn_genbits.14884611
Short name T2
Test name
Test status
Simulation time 73268871 ps
CPU time 1.34 seconds
Started Aug 18 06:12:36 PM PDT 24
Finished Aug 18 06:12:37 PM PDT 24
Peak memory 220476 kb
Host smart-7fe319d1-5177-4ea4-99e8-b4e2bb50ee53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14884611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.14884611
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.165845599
Short name T941
Test name
Test status
Simulation time 74184019 ps
CPU time 1.11 seconds
Started Aug 18 06:12:39 PM PDT 24
Finished Aug 18 06:12:40 PM PDT 24
Peak memory 217428 kb
Host smart-c44600ce-9943-410c-aba5-4a1b674833fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165845599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.165845599
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.1685266336
Short name T662
Test name
Test status
Simulation time 75772642 ps
CPU time 1.16 seconds
Started Aug 18 06:12:49 PM PDT 24
Finished Aug 18 06:12:50 PM PDT 24
Peak memory 218720 kb
Host smart-51106cab-a74f-453a-aa74-3a1bec6b79da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685266336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.1685266336
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.1755703822
Short name T46
Test name
Test status
Simulation time 101042512 ps
CPU time 1.9 seconds
Started Aug 18 06:12:49 PM PDT 24
Finished Aug 18 06:12:51 PM PDT 24
Peak memory 219548 kb
Host smart-df6f5a0f-bf3b-4390-8954-2984c5ef8635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755703822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1755703822
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2925564882
Short name T668
Test name
Test status
Simulation time 57899663 ps
CPU time 1.74 seconds
Started Aug 18 06:12:31 PM PDT 24
Finished Aug 18 06:12:33 PM PDT 24
Peak memory 218744 kb
Host smart-d1563b50-8e13-4d51-9af7-0ff3cc594ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925564882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2925564882
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.3044164560
Short name T343
Test name
Test status
Simulation time 41632766 ps
CPU time 1.59 seconds
Started Aug 18 06:12:46 PM PDT 24
Finished Aug 18 06:12:48 PM PDT 24
Peak memory 217600 kb
Host smart-4312d4d6-f4ec-47d7-9638-b74b44766e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044164560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.3044164560
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.3151494319
Short name T503
Test name
Test status
Simulation time 74214259 ps
CPU time 1.48 seconds
Started Aug 18 06:12:45 PM PDT 24
Finished Aug 18 06:12:46 PM PDT 24
Peak memory 218828 kb
Host smart-6ae37025-95aa-439d-a2cc-0eae4359cdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151494319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3151494319
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.799509308
Short name T615
Test name
Test status
Simulation time 57045355 ps
CPU time 1.81 seconds
Started Aug 18 06:12:51 PM PDT 24
Finished Aug 18 06:12:53 PM PDT 24
Peak memory 217472 kb
Host smart-4ba68fba-cde9-4079-82fb-fcd4fcb26cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799509308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.799509308
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.1108128856
Short name T692
Test name
Test status
Simulation time 47964366 ps
CPU time 1.83 seconds
Started Aug 18 06:12:49 PM PDT 24
Finished Aug 18 06:12:51 PM PDT 24
Peak memory 217404 kb
Host smart-02346fbf-9a35-415e-a8eb-a99068e87906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108128856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.1108128856
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.2573902126
Short name T467
Test name
Test status
Simulation time 80669340 ps
CPU time 1.14 seconds
Started Aug 18 06:12:51 PM PDT 24
Finished Aug 18 06:12:53 PM PDT 24
Peak memory 217368 kb
Host smart-26d1a5cb-b21a-4bd2-8c61-ce29a5cc0dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573902126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2573902126
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.1275893115
Short name T330
Test name
Test status
Simulation time 37564213 ps
CPU time 1.24 seconds
Started Aug 18 06:10:54 PM PDT 24
Finished Aug 18 06:10:55 PM PDT 24
Peak memory 219972 kb
Host smart-f82597dd-b9f0-46ef-bebf-552a9719c511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275893115 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1275893115
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.2687741801
Short name T955
Test name
Test status
Simulation time 27283251 ps
CPU time 0.87 seconds
Started Aug 18 06:10:56 PM PDT 24
Finished Aug 18 06:10:57 PM PDT 24
Peak memory 214896 kb
Host smart-abeacb70-4c09-4062-81ec-f7b766a99826
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687741801 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2687741801
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.186983921
Short name T226
Test name
Test status
Simulation time 73998561 ps
CPU time 0.87 seconds
Started Aug 18 06:11:03 PM PDT 24
Finished Aug 18 06:11:04 PM PDT 24
Peak memory 215436 kb
Host smart-734a26d1-79a6-4658-a027-bcfb3aedc0bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186983921 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.186983921
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.1255892900
Short name T144
Test name
Test status
Simulation time 37108649 ps
CPU time 1.24 seconds
Started Aug 18 06:10:56 PM PDT 24
Finished Aug 18 06:10:57 PM PDT 24
Peak memory 216948 kb
Host smart-0776eade-2239-48a7-adee-76370c509f15
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255892900 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.1255892900
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.147028623
Short name T709
Test name
Test status
Simulation time 33350212 ps
CPU time 1.35 seconds
Started Aug 18 06:11:02 PM PDT 24
Finished Aug 18 06:11:04 PM PDT 24
Peak memory 219796 kb
Host smart-46e9c2e1-c1fd-4fcc-ae83-3ee3b3e09e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147028623 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.147028623
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.1347280092
Short name T126
Test name
Test status
Simulation time 47963916 ps
CPU time 1.18 seconds
Started Aug 18 06:10:55 PM PDT 24
Finished Aug 18 06:10:57 PM PDT 24
Peak memory 218752 kb
Host smart-304825e3-0f77-45fe-94ba-3cd5364533e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347280092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1347280092
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.2221190674
Short name T675
Test name
Test status
Simulation time 29002429 ps
CPU time 0.99 seconds
Started Aug 18 06:10:54 PM PDT 24
Finished Aug 18 06:10:55 PM PDT 24
Peak memory 215512 kb
Host smart-6576b9b5-4fb9-434f-9a8a-c8092d5356f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221190674 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2221190674
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.2143980507
Short name T636
Test name
Test status
Simulation time 16289310 ps
CPU time 0.98 seconds
Started Aug 18 06:10:55 PM PDT 24
Finished Aug 18 06:10:56 PM PDT 24
Peak memory 215376 kb
Host smart-870efe41-d659-499c-b1ca-d1c3f5f9a405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143980507 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.2143980507
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2210176079
Short name T131
Test name
Test status
Simulation time 266184576 ps
CPU time 5.3 seconds
Started Aug 18 06:10:54 PM PDT 24
Finished Aug 18 06:11:00 PM PDT 24
Peak memory 215476 kb
Host smart-2fca7711-32d9-491d-9eb7-0a7650e9bd21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210176079 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2210176079
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/240.edn_genbits.2865729148
Short name T281
Test name
Test status
Simulation time 45329135 ps
CPU time 1.25 seconds
Started Aug 18 06:12:50 PM PDT 24
Finished Aug 18 06:12:51 PM PDT 24
Peak memory 219636 kb
Host smart-f0e4a2dc-703a-4139-baba-8d5f1134a6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865729148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.2865729148
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1043032629
Short name T839
Test name
Test status
Simulation time 36240714 ps
CPU time 1.08 seconds
Started Aug 18 06:12:50 PM PDT 24
Finished Aug 18 06:12:51 PM PDT 24
Peak memory 217288 kb
Host smart-3c02edec-ce3e-45ba-a1e1-9ee8fdd610d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043032629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1043032629
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.2511033458
Short name T400
Test name
Test status
Simulation time 54077913 ps
CPU time 1.77 seconds
Started Aug 18 06:12:42 PM PDT 24
Finished Aug 18 06:12:44 PM PDT 24
Peak memory 218784 kb
Host smart-d42bf2e3-e1fc-400d-9c67-8d30adabfc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511033458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.2511033458
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.67356035
Short name T784
Test name
Test status
Simulation time 54544664 ps
CPU time 1.17 seconds
Started Aug 18 06:12:35 PM PDT 24
Finished Aug 18 06:12:36 PM PDT 24
Peak memory 217476 kb
Host smart-19361ba1-fa13-4672-bd4e-7d014991fa77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67356035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.67356035
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.1596824691
Short name T857
Test name
Test status
Simulation time 85612902 ps
CPU time 1.04 seconds
Started Aug 18 06:12:49 PM PDT 24
Finished Aug 18 06:12:51 PM PDT 24
Peak memory 217292 kb
Host smart-a402df55-491f-4d27-9d1f-84a89d233e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596824691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.1596824691
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.2091063050
Short name T696
Test name
Test status
Simulation time 42488095 ps
CPU time 1.33 seconds
Started Aug 18 06:12:48 PM PDT 24
Finished Aug 18 06:12:50 PM PDT 24
Peak memory 217308 kb
Host smart-11724bd3-f634-4f5d-acf3-076accfc4862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091063050 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.2091063050
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.208388387
Short name T477
Test name
Test status
Simulation time 67468066 ps
CPU time 1.29 seconds
Started Aug 18 06:12:53 PM PDT 24
Finished Aug 18 06:12:54 PM PDT 24
Peak memory 218580 kb
Host smart-1a999306-2db0-4727-bc8a-c7b99aa4a9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208388387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.208388387
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.1733014119
Short name T386
Test name
Test status
Simulation time 62690711 ps
CPU time 1.59 seconds
Started Aug 18 06:12:48 PM PDT 24
Finished Aug 18 06:12:49 PM PDT 24
Peak memory 218736 kb
Host smart-b5e950a0-c77f-440e-ad46-3286ebec6ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733014119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1733014119
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.457381219
Short name T497
Test name
Test status
Simulation time 247588032 ps
CPU time 1.68 seconds
Started Aug 18 06:12:54 PM PDT 24
Finished Aug 18 06:12:56 PM PDT 24
Peak memory 218828 kb
Host smart-064adaff-9fcf-4707-9387-e3ac6b78c2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457381219 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.457381219
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.3031147082
Short name T736
Test name
Test status
Simulation time 32074956 ps
CPU time 1.35 seconds
Started Aug 18 06:11:06 PM PDT 24
Finished Aug 18 06:11:07 PM PDT 24
Peak memory 219968 kb
Host smart-4f323271-7b0e-4a7d-be83-eb82d771996f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031147082 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3031147082
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.1076123021
Short name T858
Test name
Test status
Simulation time 28991918 ps
CPU time 0.84 seconds
Started Aug 18 06:10:55 PM PDT 24
Finished Aug 18 06:10:56 PM PDT 24
Peak memory 206072 kb
Host smart-7215c135-cb67-4a8c-adf7-aae242493ee5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076123021 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1076123021
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.961332532
Short name T947
Test name
Test status
Simulation time 25266086 ps
CPU time 0.84 seconds
Started Aug 18 06:10:55 PM PDT 24
Finished Aug 18 06:10:56 PM PDT 24
Peak memory 207016 kb
Host smart-e0eeba4c-2f78-4612-8b34-fe5ef85e3feb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961332532 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.961332532
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.4284420942
Short name T569
Test name
Test status
Simulation time 72866886 ps
CPU time 0.95 seconds
Started Aug 18 06:11:01 PM PDT 24
Finished Aug 18 06:11:03 PM PDT 24
Peak memory 218316 kb
Host smart-68aa0a85-da43-4640-ac63-8d5101734653
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284420942 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.4284420942
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.1052208102
Short name T638
Test name
Test status
Simulation time 19913620 ps
CPU time 1.13 seconds
Started Aug 18 06:10:56 PM PDT 24
Finished Aug 18 06:10:57 PM PDT 24
Peak memory 218552 kb
Host smart-613d03e6-7005-4720-87dd-462433824988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052208102 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.1052208102
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.1439901650
Short name T744
Test name
Test status
Simulation time 58084594 ps
CPU time 0.99 seconds
Started Aug 18 06:10:54 PM PDT 24
Finished Aug 18 06:10:55 PM PDT 24
Peak memory 217388 kb
Host smart-e221e41c-8551-40eb-a106-e1badec72880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439901650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1439901650
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.1463048578
Short name T511
Test name
Test status
Simulation time 19978584 ps
CPU time 1.11 seconds
Started Aug 18 06:10:55 PM PDT 24
Finished Aug 18 06:10:56 PM PDT 24
Peak memory 215832 kb
Host smart-d712dc7a-73a6-4a68-9302-e38369e8fdab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463048578 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.1463048578
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.1616072551
Short name T850
Test name
Test status
Simulation time 40795695 ps
CPU time 0.9 seconds
Started Aug 18 06:11:01 PM PDT 24
Finished Aug 18 06:11:02 PM PDT 24
Peak memory 215336 kb
Host smart-ce8eedb2-1571-4f8b-a95c-8056ef317cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616072551 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.1616072551
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2472463608
Short name T604
Test name
Test status
Simulation time 110337228 ps
CPU time 1.88 seconds
Started Aug 18 06:10:55 PM PDT 24
Finished Aug 18 06:10:58 PM PDT 24
Peak memory 217424 kb
Host smart-b29f16e0-1940-4b14-be05-eb4c3555b309
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472463608 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2472463608
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/250.edn_genbits.964350236
Short name T349
Test name
Test status
Simulation time 35525657 ps
CPU time 1.42 seconds
Started Aug 18 06:12:39 PM PDT 24
Finished Aug 18 06:12:41 PM PDT 24
Peak memory 217264 kb
Host smart-7db40e6c-f8e7-41bc-9760-b2d0eccda288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964350236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.964350236
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.556343843
Short name T392
Test name
Test status
Simulation time 54886834 ps
CPU time 1.1 seconds
Started Aug 18 06:12:51 PM PDT 24
Finished Aug 18 06:12:52 PM PDT 24
Peak memory 217352 kb
Host smart-cf80eb57-f30f-4c60-acea-a61ff0261fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556343843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.556343843
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.1718612022
Short name T713
Test name
Test status
Simulation time 64308663 ps
CPU time 1.05 seconds
Started Aug 18 06:12:51 PM PDT 24
Finished Aug 18 06:12:52 PM PDT 24
Peak memory 217416 kb
Host smart-cde5bd6c-5028-4991-8966-4bdfcbaec126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718612022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.1718612022
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.3702964101
Short name T351
Test name
Test status
Simulation time 57425537 ps
CPU time 1.15 seconds
Started Aug 18 06:12:40 PM PDT 24
Finished Aug 18 06:12:41 PM PDT 24
Peak memory 218712 kb
Host smart-806eddf5-61b4-45c2-8806-7760493be3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702964101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.3702964101
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.4250539587
Short name T836
Test name
Test status
Simulation time 38751755 ps
CPU time 1.45 seconds
Started Aug 18 06:12:39 PM PDT 24
Finished Aug 18 06:12:41 PM PDT 24
Peak memory 218528 kb
Host smart-d3f2b69c-3c69-4b61-8132-0cca2e6ae83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250539587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.4250539587
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.858008305
Short name T558
Test name
Test status
Simulation time 51748647 ps
CPU time 0.99 seconds
Started Aug 18 06:12:48 PM PDT 24
Finished Aug 18 06:12:50 PM PDT 24
Peak memory 215428 kb
Host smart-7546c860-60bc-4e59-9016-4be214971685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858008305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.858008305
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.4173254098
Short name T399
Test name
Test status
Simulation time 85966669 ps
CPU time 1.53 seconds
Started Aug 18 06:12:52 PM PDT 24
Finished Aug 18 06:12:54 PM PDT 24
Peak memory 219040 kb
Host smart-5a3e7814-cccf-42d9-b058-860fce7a929f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173254098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.4173254098
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.2766613308
Short name T257
Test name
Test status
Simulation time 55449038 ps
CPU time 1.08 seconds
Started Aug 18 06:12:50 PM PDT 24
Finished Aug 18 06:12:51 PM PDT 24
Peak memory 217268 kb
Host smart-0f120464-80da-45b3-afec-6f250be60d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766613308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.2766613308
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.3804752750
Short name T340
Test name
Test status
Simulation time 80350677 ps
CPU time 1.65 seconds
Started Aug 18 06:12:50 PM PDT 24
Finished Aug 18 06:12:51 PM PDT 24
Peak memory 218724 kb
Host smart-e22b4784-d831-4d32-8f9a-75054ea2f430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804752750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.3804752750
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.1906303229
Short name T334
Test name
Test status
Simulation time 208946472 ps
CPU time 1.27 seconds
Started Aug 18 06:11:02 PM PDT 24
Finished Aug 18 06:11:03 PM PDT 24
Peak memory 218456 kb
Host smart-3921eaec-6d22-42ca-9a43-8695689c279a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906303229 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.1906303229
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.2629940855
Short name T435
Test name
Test status
Simulation time 16036195 ps
CPU time 0.9 seconds
Started Aug 18 06:11:02 PM PDT 24
Finished Aug 18 06:11:03 PM PDT 24
Peak memory 214968 kb
Host smart-ad34728a-a809-4774-9362-b25aa2deca70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629940855 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2629940855
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.3886306872
Short name T63
Test name
Test status
Simulation time 10238303 ps
CPU time 0.86 seconds
Started Aug 18 06:11:08 PM PDT 24
Finished Aug 18 06:11:09 PM PDT 24
Peak memory 215400 kb
Host smart-784e03ca-d89e-4a24-8279-359e41dcfe9b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886306872 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.3886306872
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_err.1702003172
Short name T222
Test name
Test status
Simulation time 27072909 ps
CPU time 0.93 seconds
Started Aug 18 06:11:03 PM PDT 24
Finished Aug 18 06:11:05 PM PDT 24
Peak memory 218440 kb
Host smart-25e602cc-c3e4-48ba-a314-f76190b7c5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702003172 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1702003172
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.271369541
Short name T421
Test name
Test status
Simulation time 47986393 ps
CPU time 1.62 seconds
Started Aug 18 06:10:57 PM PDT 24
Finished Aug 18 06:10:58 PM PDT 24
Peak memory 218456 kb
Host smart-057b531b-e71b-46a8-977c-a6bfbf47a57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271369541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.271369541
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_smoke.1139784137
Short name T403
Test name
Test status
Simulation time 48780436 ps
CPU time 0.93 seconds
Started Aug 18 06:11:02 PM PDT 24
Finished Aug 18 06:11:03 PM PDT 24
Peak memory 215308 kb
Host smart-33deb4b8-a31a-423c-8ed0-aced4f30e342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139784137 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.1139784137
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.628106206
Short name T547
Test name
Test status
Simulation time 82521779 ps
CPU time 2.2 seconds
Started Aug 18 06:10:52 PM PDT 24
Finished Aug 18 06:10:55 PM PDT 24
Peak memory 215240 kb
Host smart-a9b057d9-6afb-4c6c-a727-2739150eed77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628106206 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.628106206
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/260.edn_genbits.443511441
Short name T835
Test name
Test status
Simulation time 52363446 ps
CPU time 1.57 seconds
Started Aug 18 06:12:47 PM PDT 24
Finished Aug 18 06:12:49 PM PDT 24
Peak memory 217404 kb
Host smart-e0f28c4c-38af-4f98-a988-8da8287e012b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443511441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.443511441
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.310440718
Short name T278
Test name
Test status
Simulation time 90767414 ps
CPU time 1.44 seconds
Started Aug 18 06:12:50 PM PDT 24
Finished Aug 18 06:12:52 PM PDT 24
Peak memory 218948 kb
Host smart-bb14f5a9-5ef0-484a-ad00-1bc27c26425d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310440718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.310440718
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.2583852436
Short name T410
Test name
Test status
Simulation time 243332481 ps
CPU time 2.85 seconds
Started Aug 18 06:12:48 PM PDT 24
Finished Aug 18 06:12:51 PM PDT 24
Peak memory 217704 kb
Host smart-4ad90853-8070-4f61-ab85-9cc69cede983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583852436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.2583852436
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1743445636
Short name T899
Test name
Test status
Simulation time 52915314 ps
CPU time 1.15 seconds
Started Aug 18 06:12:51 PM PDT 24
Finished Aug 18 06:12:52 PM PDT 24
Peak memory 218660 kb
Host smart-4870a7f2-497d-4a68-9aec-9d874abffa94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743445636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1743445636
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.2724637137
Short name T110
Test name
Test status
Simulation time 159612458 ps
CPU time 1.49 seconds
Started Aug 18 06:12:50 PM PDT 24
Finished Aug 18 06:12:52 PM PDT 24
Peak memory 218816 kb
Host smart-0c5106b6-e03c-4ec5-9b6a-578bd41fde21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724637137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.2724637137
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2837435744
Short name T684
Test name
Test status
Simulation time 107811146 ps
CPU time 1.26 seconds
Started Aug 18 06:12:49 PM PDT 24
Finished Aug 18 06:12:50 PM PDT 24
Peak memory 215384 kb
Host smart-b5440294-114d-482f-85f4-ac7b7294bfec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837435744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2837435744
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.2112839045
Short name T929
Test name
Test status
Simulation time 30936583 ps
CPU time 1.02 seconds
Started Aug 18 06:12:53 PM PDT 24
Finished Aug 18 06:12:55 PM PDT 24
Peak memory 217608 kb
Host smart-1f2e97a7-5bc0-45c2-8a14-273e823784fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112839045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2112839045
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.3865441740
Short name T519
Test name
Test status
Simulation time 103381658 ps
CPU time 1.09 seconds
Started Aug 18 06:12:54 PM PDT 24
Finished Aug 18 06:12:56 PM PDT 24
Peak memory 217348 kb
Host smart-efb91f2d-ac66-4cf9-a379-d7a783ebc0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865441740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.3865441740
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.256910506
Short name T676
Test name
Test status
Simulation time 290876059 ps
CPU time 1.03 seconds
Started Aug 18 06:12:50 PM PDT 24
Finished Aug 18 06:12:51 PM PDT 24
Peak memory 217560 kb
Host smart-3f3e2afc-4224-4353-8c44-4855ca8692c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256910506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.256910506
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.1518247126
Short name T814
Test name
Test status
Simulation time 36592976 ps
CPU time 1.45 seconds
Started Aug 18 06:12:51 PM PDT 24
Finished Aug 18 06:12:53 PM PDT 24
Peak memory 220364 kb
Host smart-b8e9d96f-ca85-4ba3-be46-11b23f726264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518247126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.1518247126
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.2137953709
Short name T146
Test name
Test status
Simulation time 259575291 ps
CPU time 1.31 seconds
Started Aug 18 06:11:05 PM PDT 24
Finished Aug 18 06:11:07 PM PDT 24
Peak memory 219844 kb
Host smart-fd49ca3d-2640-4a14-a845-2c339fbf3357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137953709 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.2137953709
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1913471827
Short name T689
Test name
Test status
Simulation time 15943953 ps
CPU time 0.97 seconds
Started Aug 18 06:11:03 PM PDT 24
Finished Aug 18 06:11:04 PM PDT 24
Peak memory 206804 kb
Host smart-cd5b5795-99d4-4b38-9531-b361ef71f3c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913471827 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1913471827
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.3326607027
Short name T100
Test name
Test status
Simulation time 13477398 ps
CPU time 0.95 seconds
Started Aug 18 06:11:08 PM PDT 24
Finished Aug 18 06:11:09 PM PDT 24
Peak memory 215344 kb
Host smart-d03e4654-e3ce-4d91-a073-f62782fa8105
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326607027 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3326607027
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.1686789951
Short name T72
Test name
Test status
Simulation time 27083202 ps
CPU time 1.13 seconds
Started Aug 18 06:11:04 PM PDT 24
Finished Aug 18 06:11:05 PM PDT 24
Peak memory 217008 kb
Host smart-8acd41ff-5a52-47d8-ae56-51771148fdb3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686789951 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.1686789951
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.3721030175
Short name T409
Test name
Test status
Simulation time 21093597 ps
CPU time 1.15 seconds
Started Aug 18 06:11:02 PM PDT 24
Finished Aug 18 06:11:03 PM PDT 24
Peak memory 218868 kb
Host smart-f7e62f6d-031c-4c6f-9fbb-0ae6e5fb2d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721030175 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.3721030175
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.1830119521
Short name T128
Test name
Test status
Simulation time 68149676 ps
CPU time 1.31 seconds
Started Aug 18 06:11:00 PM PDT 24
Finished Aug 18 06:11:02 PM PDT 24
Peak memory 219012 kb
Host smart-78b80abe-ff64-4402-b3e5-757e39ace7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830119521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.1830119521
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.1964381465
Short name T14
Test name
Test status
Simulation time 21325000 ps
CPU time 1.25 seconds
Started Aug 18 06:11:06 PM PDT 24
Finished Aug 18 06:11:08 PM PDT 24
Peak memory 224228 kb
Host smart-b02bfff6-3eb7-44ef-9399-bcd1835a292c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964381465 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1964381465
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.3754861075
Short name T922
Test name
Test status
Simulation time 41055263 ps
CPU time 0.94 seconds
Started Aug 18 06:11:05 PM PDT 24
Finished Aug 18 06:11:07 PM PDT 24
Peak memory 215360 kb
Host smart-4d697e49-426a-434e-bfbc-eec398bdf111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754861075 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.3754861075
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.3828791086
Short name T540
Test name
Test status
Simulation time 426650843 ps
CPU time 5.4 seconds
Started Aug 18 06:11:02 PM PDT 24
Finished Aug 18 06:11:08 PM PDT 24
Peak memory 220648 kb
Host smart-d34b1ef4-46c9-4ca8-86be-7e2bac2ab1ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828791086 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3828791086
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.3733748531
Short name T249
Test name
Test status
Simulation time 7689025077 ps
CPU time 43.22 seconds
Started Aug 18 06:11:09 PM PDT 24
Finished Aug 18 06:11:52 PM PDT 24
Peak memory 218684 kb
Host smart-273d920d-d97f-46fd-88e7-51d58f275d28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733748531 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.3733748531
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.3123445975
Short name T350
Test name
Test status
Simulation time 45335041 ps
CPU time 1.36 seconds
Started Aug 18 06:12:47 PM PDT 24
Finished Aug 18 06:12:48 PM PDT 24
Peak memory 218672 kb
Host smart-c83e2d35-7fa1-452e-acea-c3bbfc3b64c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123445975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.3123445975
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.2796879313
Short name T557
Test name
Test status
Simulation time 49878792 ps
CPU time 1.47 seconds
Started Aug 18 06:12:46 PM PDT 24
Finished Aug 18 06:12:48 PM PDT 24
Peak memory 215420 kb
Host smart-9b57bfb2-537e-4cb1-8a93-8287a4e9ad70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796879313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2796879313
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.914482263
Short name T318
Test name
Test status
Simulation time 25907747 ps
CPU time 1.36 seconds
Started Aug 18 06:12:44 PM PDT 24
Finished Aug 18 06:12:45 PM PDT 24
Peak memory 218796 kb
Host smart-889b3494-6e3c-475d-abcd-5dd2ffe3e186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914482263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.914482263
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.1754684993
Short name T407
Test name
Test status
Simulation time 56274648 ps
CPU time 1.39 seconds
Started Aug 18 06:12:56 PM PDT 24
Finished Aug 18 06:12:58 PM PDT 24
Peak memory 217572 kb
Host smart-37a3f018-7609-4ea1-aa5a-1c842bfef8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754684993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.1754684993
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3052155534
Short name T38
Test name
Test status
Simulation time 385492358 ps
CPU time 3.87 seconds
Started Aug 18 06:12:52 PM PDT 24
Finished Aug 18 06:12:56 PM PDT 24
Peak memory 217636 kb
Host smart-62ce8c30-794d-42c8-aee0-cf0332cf9184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052155534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3052155534
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.7936622
Short name T319
Test name
Test status
Simulation time 40455623 ps
CPU time 1.42 seconds
Started Aug 18 06:12:48 PM PDT 24
Finished Aug 18 06:12:49 PM PDT 24
Peak memory 215484 kb
Host smart-23fa9842-a2bc-4862-8460-07c178f3f737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7936622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.7936622
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.1449002558
Short name T830
Test name
Test status
Simulation time 42673526 ps
CPU time 1.21 seconds
Started Aug 18 06:12:47 PM PDT 24
Finished Aug 18 06:12:48 PM PDT 24
Peak memory 218816 kb
Host smart-d1258776-2dfa-41bb-8cd6-5a5c9b468e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449002558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1449002558
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.115247188
Short name T902
Test name
Test status
Simulation time 45515358 ps
CPU time 1.68 seconds
Started Aug 18 06:12:40 PM PDT 24
Finished Aug 18 06:12:42 PM PDT 24
Peak memory 217676 kb
Host smart-66a973dc-168c-435f-9c7a-177d14c6b57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115247188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.115247188
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.3727935576
Short name T770
Test name
Test status
Simulation time 84144216 ps
CPU time 1.31 seconds
Started Aug 18 06:12:44 PM PDT 24
Finished Aug 18 06:12:46 PM PDT 24
Peak memory 218776 kb
Host smart-ae8fb77f-a893-4786-a68c-7809d947bb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727935576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3727935576
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.884493831
Short name T621
Test name
Test status
Simulation time 106763011 ps
CPU time 1.11 seconds
Started Aug 18 06:12:54 PM PDT 24
Finished Aug 18 06:12:55 PM PDT 24
Peak memory 217576 kb
Host smart-bff2e592-d4d0-458b-9278-4958f4bc6917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884493831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.884493831
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.689662385
Short name T846
Test name
Test status
Simulation time 78154919 ps
CPU time 1.19 seconds
Started Aug 18 06:11:08 PM PDT 24
Finished Aug 18 06:11:09 PM PDT 24
Peak memory 218724 kb
Host smart-8e931ee8-f04f-4098-bbed-53e58111304c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689662385 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.689662385
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.2416478023
Short name T574
Test name
Test status
Simulation time 37550081 ps
CPU time 0.91 seconds
Started Aug 18 06:11:05 PM PDT 24
Finished Aug 18 06:11:06 PM PDT 24
Peak memory 214884 kb
Host smart-605a7a7d-5f5a-4668-8658-6aa0f94dc465
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416478023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2416478023
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.1524218972
Short name T530
Test name
Test status
Simulation time 22606539 ps
CPU time 0.94 seconds
Started Aug 18 06:11:07 PM PDT 24
Finished Aug 18 06:11:08 PM PDT 24
Peak memory 215060 kb
Host smart-975c1f80-551a-4668-9986-76de46acd845
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524218972 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1524218972
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.850540496
Short name T160
Test name
Test status
Simulation time 38539243 ps
CPU time 1 seconds
Started Aug 18 06:11:09 PM PDT 24
Finished Aug 18 06:11:10 PM PDT 24
Peak memory 218796 kb
Host smart-65f34237-d72c-4d05-b6c8-06c7fffe8c5e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850540496 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_di
sable_auto_req_mode.850540496
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.2306547046
Short name T526
Test name
Test status
Simulation time 21024127 ps
CPU time 1.09 seconds
Started Aug 18 06:11:01 PM PDT 24
Finished Aug 18 06:11:03 PM PDT 24
Peak memory 218656 kb
Host smart-892f3069-a4ca-4928-b993-463963e546b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306547046 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2306547046
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.3722803857
Short name T593
Test name
Test status
Simulation time 48229618 ps
CPU time 1.55 seconds
Started Aug 18 06:11:04 PM PDT 24
Finished Aug 18 06:11:06 PM PDT 24
Peak memory 218420 kb
Host smart-296c46bf-120d-45e4-8aef-e24f7576c46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722803857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3722803857
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.2362483668
Short name T622
Test name
Test status
Simulation time 40978070 ps
CPU time 0.89 seconds
Started Aug 18 06:11:02 PM PDT 24
Finished Aug 18 06:11:03 PM PDT 24
Peak memory 215628 kb
Host smart-a7f4466e-74f3-4647-b4c7-bea47c242d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362483668 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2362483668
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.49575568
Short name T457
Test name
Test status
Simulation time 18036357 ps
CPU time 1 seconds
Started Aug 18 06:11:08 PM PDT 24
Finished Aug 18 06:11:09 PM PDT 24
Peak memory 215328 kb
Host smart-c16482ee-f888-4060-a853-04cd07a0a34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49575568 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.49575568
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.3368745162
Short name T942
Test name
Test status
Simulation time 96332516 ps
CPU time 2 seconds
Started Aug 18 06:11:09 PM PDT 24
Finished Aug 18 06:11:11 PM PDT 24
Peak memory 215384 kb
Host smart-cf8dc2ff-37e0-433b-8fd2-49fb86b43e49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368745162 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3368745162
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.205554919
Short name T610
Test name
Test status
Simulation time 6058733095 ps
CPU time 124.4 seconds
Started Aug 18 06:11:01 PM PDT 24
Finished Aug 18 06:13:06 PM PDT 24
Peak memory 222016 kb
Host smart-d6aab451-2fd2-47c5-b264-2c8ec3dc5421
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205554919 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.205554919
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.2967325714
Short name T923
Test name
Test status
Simulation time 53679973 ps
CPU time 2.12 seconds
Started Aug 18 06:12:40 PM PDT 24
Finished Aug 18 06:12:42 PM PDT 24
Peak memory 219452 kb
Host smart-6b8b8d6f-bb5b-4460-8dba-78b7ce8a67c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967325714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.2967325714
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.513600126
Short name T819
Test name
Test status
Simulation time 98531818 ps
CPU time 2.25 seconds
Started Aug 18 06:12:50 PM PDT 24
Finished Aug 18 06:12:52 PM PDT 24
Peak memory 218728 kb
Host smart-b257b2ff-4cfc-4133-81c6-9fb15bfe92e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513600126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.513600126
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.1488022601
Short name T11
Test name
Test status
Simulation time 28285597 ps
CPU time 1.39 seconds
Started Aug 18 06:12:46 PM PDT 24
Finished Aug 18 06:12:48 PM PDT 24
Peak memory 220360 kb
Host smart-2bb9858a-e6eb-4fe7-93d5-786e9dc2d4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488022601 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.1488022601
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.3731088016
Short name T434
Test name
Test status
Simulation time 40149668 ps
CPU time 1.48 seconds
Started Aug 18 06:12:43 PM PDT 24
Finished Aug 18 06:12:45 PM PDT 24
Peak memory 218652 kb
Host smart-19c258e1-3406-41f2-b3c5-19af9bb6ea8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731088016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.3731088016
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.330449467
Short name T578
Test name
Test status
Simulation time 38771749 ps
CPU time 1.71 seconds
Started Aug 18 06:12:46 PM PDT 24
Finished Aug 18 06:12:48 PM PDT 24
Peak memory 218832 kb
Host smart-c096dcea-5996-47aa-86dd-7214946e57f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330449467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.330449467
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.2361001608
Short name T483
Test name
Test status
Simulation time 73647675 ps
CPU time 1.82 seconds
Started Aug 18 06:12:47 PM PDT 24
Finished Aug 18 06:12:49 PM PDT 24
Peak memory 220552 kb
Host smart-f14ecaba-d6dc-4d3c-90d3-67ccb885fddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361001608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2361001608
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.3517471905
Short name T506
Test name
Test status
Simulation time 47451325 ps
CPU time 1.28 seconds
Started Aug 18 06:12:58 PM PDT 24
Finished Aug 18 06:12:59 PM PDT 24
Peak memory 217280 kb
Host smart-a57a8ab0-f9e8-468e-ac0b-e789ba3b5359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517471905 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3517471905
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.3009896383
Short name T549
Test name
Test status
Simulation time 54120357 ps
CPU time 1.96 seconds
Started Aug 18 06:12:52 PM PDT 24
Finished Aug 18 06:12:54 PM PDT 24
Peak memory 218920 kb
Host smart-5efef3df-d0c0-4cf9-8bc4-a7aeba06d919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009896383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.3009896383
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.4196925010
Short name T465
Test name
Test status
Simulation time 39229551 ps
CPU time 1.42 seconds
Started Aug 18 06:12:53 PM PDT 24
Finished Aug 18 06:12:55 PM PDT 24
Peak memory 218672 kb
Host smart-2e70b14c-61bc-482b-8c1c-4a148751ffb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196925010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.4196925010
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.3776964200
Short name T405
Test name
Test status
Simulation time 68248104 ps
CPU time 1.02 seconds
Started Aug 18 06:12:54 PM PDT 24
Finished Aug 18 06:12:55 PM PDT 24
Peak memory 217724 kb
Host smart-24412e45-45ec-4254-a387-8a40cc809310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776964200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.3776964200
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.491512854
Short name T965
Test name
Test status
Simulation time 65859705 ps
CPU time 1.15 seconds
Started Aug 18 06:11:04 PM PDT 24
Finished Aug 18 06:11:06 PM PDT 24
Peak memory 219252 kb
Host smart-c7f12100-ea50-4242-ad73-424e8efb724b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491512854 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.491512854
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.2765568366
Short name T909
Test name
Test status
Simulation time 43419081 ps
CPU time 0.9 seconds
Started Aug 18 06:11:01 PM PDT 24
Finished Aug 18 06:11:02 PM PDT 24
Peak memory 206724 kb
Host smart-fd84d2c6-bc1b-4c41-b23c-1ca86417d8e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765568366 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.2765568366
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1658001505
Short name T171
Test name
Test status
Simulation time 41017715 ps
CPU time 1.45 seconds
Started Aug 18 06:11:04 PM PDT 24
Finished Aug 18 06:11:06 PM PDT 24
Peak memory 216820 kb
Host smart-720b690d-57e4-43a3-ada6-6613e4c5ed0f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658001505 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1658001505
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.1537904895
Short name T154
Test name
Test status
Simulation time 44493050 ps
CPU time 1.06 seconds
Started Aug 18 06:11:03 PM PDT 24
Finished Aug 18 06:11:04 PM PDT 24
Peak memory 220572 kb
Host smart-f25a8ecc-b37c-4480-9a53-e9394aec62f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537904895 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.1537904895
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.1149713764
Short name T930
Test name
Test status
Simulation time 278781382 ps
CPU time 1.57 seconds
Started Aug 18 06:11:03 PM PDT 24
Finished Aug 18 06:11:05 PM PDT 24
Peak memory 219032 kb
Host smart-02fe4a0f-6fb2-4111-810e-fac7358facbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149713764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.1149713764
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.4273017804
Short name T494
Test name
Test status
Simulation time 22296600 ps
CPU time 1.17 seconds
Started Aug 18 06:11:03 PM PDT 24
Finished Aug 18 06:11:05 PM PDT 24
Peak memory 224272 kb
Host smart-09aaf354-b155-4abb-9bee-b140dde31dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273017804 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.4273017804
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.1371666310
Short name T418
Test name
Test status
Simulation time 24814214 ps
CPU time 1.06 seconds
Started Aug 18 06:11:03 PM PDT 24
Finished Aug 18 06:11:04 PM PDT 24
Peak memory 215376 kb
Host smart-39e66e65-87ba-40b5-aa00-931943370626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371666310 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.1371666310
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.3490730608
Short name T48
Test name
Test status
Simulation time 292741084 ps
CPU time 4.83 seconds
Started Aug 18 06:11:09 PM PDT 24
Finished Aug 18 06:11:14 PM PDT 24
Peak memory 215604 kb
Host smart-c9a1fe2e-10ea-46b9-876b-413ff94c8bf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490730608 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3490730608
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2048450485
Short name T585
Test name
Test status
Simulation time 4335544629 ps
CPU time 62.15 seconds
Started Aug 18 06:11:05 PM PDT 24
Finished Aug 18 06:12:07 PM PDT 24
Peak memory 217408 kb
Host smart-80de8651-d044-49ce-8158-9005d7557493
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048450485 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2048450485
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.3358445845
Short name T362
Test name
Test status
Simulation time 45921824 ps
CPU time 1.68 seconds
Started Aug 18 06:12:56 PM PDT 24
Finished Aug 18 06:12:58 PM PDT 24
Peak memory 217608 kb
Host smart-523cc608-13e0-4e04-804d-b3c8f1c08b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358445845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.3358445845
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.549061788
Short name T267
Test name
Test status
Simulation time 51163387 ps
CPU time 1.68 seconds
Started Aug 18 06:12:40 PM PDT 24
Finished Aug 18 06:12:42 PM PDT 24
Peak memory 218568 kb
Host smart-f2400527-bc29-4a01-ace3-fd72efc5b8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549061788 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.549061788
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.3802043222
Short name T860
Test name
Test status
Simulation time 70001438 ps
CPU time 1.14 seconds
Started Aug 18 06:12:44 PM PDT 24
Finished Aug 18 06:12:46 PM PDT 24
Peak memory 218812 kb
Host smart-1da9e150-8c1c-42cb-b0c9-a3cdb5ea5d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802043222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3802043222
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2290026693
Short name T243
Test name
Test status
Simulation time 225581934 ps
CPU time 3.29 seconds
Started Aug 18 06:12:41 PM PDT 24
Finished Aug 18 06:12:44 PM PDT 24
Peak memory 220684 kb
Host smart-63204601-f55a-423c-b98d-139289542a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290026693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2290026693
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3181683796
Short name T561
Test name
Test status
Simulation time 94578360 ps
CPU time 1.2 seconds
Started Aug 18 06:12:46 PM PDT 24
Finished Aug 18 06:12:47 PM PDT 24
Peak memory 218584 kb
Host smart-7356d23f-e91e-4c8c-b2de-8cb329e25ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181683796 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3181683796
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.4018391393
Short name T576
Test name
Test status
Simulation time 162089155 ps
CPU time 1.33 seconds
Started Aug 18 06:12:45 PM PDT 24
Finished Aug 18 06:12:47 PM PDT 24
Peak memory 217524 kb
Host smart-b4fb9cb9-f6d8-43fb-b8e6-5e81c31c90b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018391393 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.4018391393
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3294018487
Short name T394
Test name
Test status
Simulation time 180487718 ps
CPU time 1.02 seconds
Started Aug 18 06:12:50 PM PDT 24
Finished Aug 18 06:12:51 PM PDT 24
Peak memory 217436 kb
Host smart-cb071968-863b-46f5-b64b-ba1f0803de9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294018487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3294018487
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.1022797061
Short name T504
Test name
Test status
Simulation time 39805010 ps
CPU time 1.37 seconds
Started Aug 18 06:12:54 PM PDT 24
Finished Aug 18 06:12:56 PM PDT 24
Peak memory 220436 kb
Host smart-744d1e98-175e-4f36-b5e7-a1bd751826d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022797061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1022797061
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.3388172369
Short name T717
Test name
Test status
Simulation time 40280257 ps
CPU time 1.49 seconds
Started Aug 18 06:12:49 PM PDT 24
Finished Aug 18 06:12:50 PM PDT 24
Peak memory 215380 kb
Host smart-f73a5fba-e2b1-4597-8a00-c4476ed32097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388172369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.3388172369
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.519111885
Short name T591
Test name
Test status
Simulation time 64040061 ps
CPU time 1.37 seconds
Started Aug 18 06:12:52 PM PDT 24
Finished Aug 18 06:12:53 PM PDT 24
Peak memory 219456 kb
Host smart-65a21bc6-304e-4235-83c2-894c905da420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519111885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.519111885
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.489985688
Short name T337
Test name
Test status
Simulation time 30339869 ps
CPU time 1.29 seconds
Started Aug 18 06:10:09 PM PDT 24
Finished Aug 18 06:10:11 PM PDT 24
Peak memory 220516 kb
Host smart-92300cbd-4f5b-4741-bb93-d8bca4ebfd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489985688 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.489985688
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.2385886134
Short name T724
Test name
Test status
Simulation time 15858465 ps
CPU time 1 seconds
Started Aug 18 06:10:11 PM PDT 24
Finished Aug 18 06:10:12 PM PDT 24
Peak memory 215008 kb
Host smart-63f82379-381a-48f5-a015-247351e17aaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385886134 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2385886134
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.1240835348
Short name T542
Test name
Test status
Simulation time 14139561 ps
CPU time 0.93 seconds
Started Aug 18 06:10:09 PM PDT 24
Finished Aug 18 06:10:10 PM PDT 24
Peak memory 215648 kb
Host smart-64b07b5c-6596-49dd-ab9e-432da8293c26
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240835348 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1240835348
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.421305412
Short name T896
Test name
Test status
Simulation time 33194507 ps
CPU time 1.22 seconds
Started Aug 18 06:10:11 PM PDT 24
Finished Aug 18 06:10:12 PM PDT 24
Peak memory 218552 kb
Host smart-8d2c28cf-6cb2-4fa8-823f-70307d44a5ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421305412 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis
able_auto_req_mode.421305412
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.97966030
Short name T140
Test name
Test status
Simulation time 72920121 ps
CPU time 0.91 seconds
Started Aug 18 06:10:08 PM PDT 24
Finished Aug 18 06:10:09 PM PDT 24
Peak memory 219660 kb
Host smart-21cccd89-8a8a-4535-a0cd-2b2cb6d5cd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97966030 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.97966030
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.1545265462
Short name T88
Test name
Test status
Simulation time 34452277 ps
CPU time 1.3 seconds
Started Aug 18 06:10:10 PM PDT 24
Finished Aug 18 06:10:11 PM PDT 24
Peak memory 218456 kb
Host smart-5eae5321-5cbc-4952-baaf-c496e08b38e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545265462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1545265462
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.1576149949
Short name T669
Test name
Test status
Simulation time 33082017 ps
CPU time 0.92 seconds
Started Aug 18 06:10:10 PM PDT 24
Finished Aug 18 06:10:11 PM PDT 24
Peak memory 215624 kb
Host smart-6ca5a280-9f0f-4e7b-bff5-ef262fc5253e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576149949 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.1576149949
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.4229328668
Short name T698
Test name
Test status
Simulation time 110264331 ps
CPU time 0.93 seconds
Started Aug 18 06:10:09 PM PDT 24
Finished Aug 18 06:10:10 PM PDT 24
Peak memory 207184 kb
Host smart-5099e746-0f21-4cf2-9c8b-b395eaba2049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229328668 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.4229328668
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.1266338582
Short name T58
Test name
Test status
Simulation time 1728514293 ps
CPU time 8.42 seconds
Started Aug 18 06:10:10 PM PDT 24
Finished Aug 18 06:10:19 PM PDT 24
Peak memory 244000 kb
Host smart-8320a547-30d0-479b-84da-0839084c99e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266338582 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.1266338582
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.2666224745
Short name T601
Test name
Test status
Simulation time 17322846 ps
CPU time 1.02 seconds
Started Aug 18 06:10:13 PM PDT 24
Finished Aug 18 06:10:14 PM PDT 24
Peak memory 215388 kb
Host smart-486d14c6-759f-4e98-838b-2b707375a97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666224745 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2666224745
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1755149366
Short name T216
Test name
Test status
Simulation time 220153494 ps
CPU time 4.49 seconds
Started Aug 18 06:10:10 PM PDT 24
Finished Aug 18 06:10:15 PM PDT 24
Peak memory 217184 kb
Host smart-2f504132-4ade-4119-be6a-5e7f90490da3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755149366 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1755149366
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_alert.4047970120
Short name T804
Test name
Test status
Simulation time 101222047 ps
CPU time 1.15 seconds
Started Aug 18 06:11:09 PM PDT 24
Finished Aug 18 06:11:10 PM PDT 24
Peak memory 218732 kb
Host smart-7dbb9ce6-3acf-4cfa-9b0e-a297f87454df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047970120 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.4047970120
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.975378537
Short name T882
Test name
Test status
Simulation time 39793343 ps
CPU time 0.86 seconds
Started Aug 18 06:11:10 PM PDT 24
Finished Aug 18 06:11:11 PM PDT 24
Peak memory 206772 kb
Host smart-f564adf4-3ca0-4f8e-88f9-879d677f2382
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975378537 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.975378537
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.3521845140
Short name T185
Test name
Test status
Simulation time 20781284 ps
CPU time 0.85 seconds
Started Aug 18 06:11:13 PM PDT 24
Finished Aug 18 06:11:14 PM PDT 24
Peak memory 215356 kb
Host smart-8a1d01d4-b32c-44ab-b230-1f0fa00d50a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521845140 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3521845140
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.3153552383
Short name T685
Test name
Test status
Simulation time 53590238 ps
CPU time 0.98 seconds
Started Aug 18 06:11:10 PM PDT 24
Finished Aug 18 06:11:11 PM PDT 24
Peak memory 219820 kb
Host smart-e550902b-39bb-4ae1-94b5-04f2f13b3134
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153552383 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.3153552383
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.1744197679
Short name T209
Test name
Test status
Simulation time 20537276 ps
CPU time 1.19 seconds
Started Aug 18 06:11:09 PM PDT 24
Finished Aug 18 06:11:10 PM PDT 24
Peak memory 218520 kb
Host smart-22ae851f-72e9-4854-ba8d-c7baa1a44ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744197679 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.1744197679
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3101551054
Short name T341
Test name
Test status
Simulation time 44209344 ps
CPU time 1.56 seconds
Started Aug 18 06:11:04 PM PDT 24
Finished Aug 18 06:11:06 PM PDT 24
Peak memory 217260 kb
Host smart-cae8cb3b-f465-4ae0-a8a2-1d0d9e4b9857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101551054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3101551054
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.541074013
Short name T107
Test name
Test status
Simulation time 73072940 ps
CPU time 0.86 seconds
Started Aug 18 06:11:11 PM PDT 24
Finished Aug 18 06:11:12 PM PDT 24
Peak memory 215524 kb
Host smart-3400082b-baac-4a34-9b34-47a00427a052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541074013 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.541074013
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.2886216702
Short name T740
Test name
Test status
Simulation time 153494521 ps
CPU time 0.99 seconds
Started Aug 18 06:11:09 PM PDT 24
Finished Aug 18 06:11:10 PM PDT 24
Peak memory 215396 kb
Host smart-25eb1acf-711a-4aef-8867-a261c9985f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886216702 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2886216702
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2827044934
Short name T262
Test name
Test status
Simulation time 7565754139 ps
CPU time 90.96 seconds
Started Aug 18 06:11:11 PM PDT 24
Finished Aug 18 06:12:42 PM PDT 24
Peak memory 220780 kb
Host smart-754795c6-444c-40b5-8a45-fe02874bfc3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827044934 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2827044934
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.2953946259
Short name T670
Test name
Test status
Simulation time 47498491 ps
CPU time 1.21 seconds
Started Aug 18 06:11:15 PM PDT 24
Finished Aug 18 06:11:16 PM PDT 24
Peak memory 220656 kb
Host smart-c2a4aea1-6a89-47c7-9d32-883b692be8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953946259 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.2953946259
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.2249344827
Short name T844
Test name
Test status
Simulation time 15446039 ps
CPU time 0.86 seconds
Started Aug 18 06:11:12 PM PDT 24
Finished Aug 18 06:11:13 PM PDT 24
Peak memory 206780 kb
Host smart-a27e80b0-4c31-4465-b954-1d42ffa5ade7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249344827 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2249344827
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.3785189659
Short name T920
Test name
Test status
Simulation time 10464182 ps
CPU time 0.92 seconds
Started Aug 18 06:11:12 PM PDT 24
Finished Aug 18 06:11:13 PM PDT 24
Peak memory 215216 kb
Host smart-56ff95e5-1ab5-4ab6-baaf-d3a91f30d86a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785189659 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3785189659
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.4199543794
Short name T332
Test name
Test status
Simulation time 69734786 ps
CPU time 0.99 seconds
Started Aug 18 06:11:12 PM PDT 24
Finished Aug 18 06:11:13 PM PDT 24
Peak memory 215364 kb
Host smart-eecfcb89-2b12-457a-9c7f-602ad2e54d3b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199543794 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.4199543794
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.3080501575
Short name T944
Test name
Test status
Simulation time 28619946 ps
CPU time 1.26 seconds
Started Aug 18 06:11:16 PM PDT 24
Finished Aug 18 06:11:18 PM PDT 24
Peak memory 219768 kb
Host smart-b864fa93-3b9f-4c7a-a2d0-853649f916f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080501575 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3080501575
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.489106313
Short name T490
Test name
Test status
Simulation time 46012106 ps
CPU time 1.86 seconds
Started Aug 18 06:11:09 PM PDT 24
Finished Aug 18 06:11:11 PM PDT 24
Peak memory 218476 kb
Host smart-b19648e1-0cc3-4f0b-8f1a-b2bd676ec0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489106313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.489106313
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.1325834282
Short name T768
Test name
Test status
Simulation time 23182322 ps
CPU time 1.15 seconds
Started Aug 18 06:11:15 PM PDT 24
Finished Aug 18 06:11:16 PM PDT 24
Peak memory 224248 kb
Host smart-df24243c-98af-4336-b39d-e5c0c5e5dcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325834282 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.1325834282
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.3608083849
Short name T411
Test name
Test status
Simulation time 30116286 ps
CPU time 0.94 seconds
Started Aug 18 06:11:11 PM PDT 24
Finished Aug 18 06:11:12 PM PDT 24
Peak memory 215404 kb
Host smart-18683ecc-c920-4b58-8895-33f85309e0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608083849 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.3608083849
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.1461719445
Short name T121
Test name
Test status
Simulation time 82377633 ps
CPU time 2.1 seconds
Started Aug 18 06:11:10 PM PDT 24
Finished Aug 18 06:11:13 PM PDT 24
Peak memory 218552 kb
Host smart-4e1da99a-ffc8-4259-a9a9-4298b956c98a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461719445 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1461719445
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_alert.141692059
Short name T478
Test name
Test status
Simulation time 28800656 ps
CPU time 1.3 seconds
Started Aug 18 06:11:08 PM PDT 24
Finished Aug 18 06:11:10 PM PDT 24
Peak memory 219432 kb
Host smart-f5061cf0-33f4-4ca0-8970-9a7950e295a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141692059 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.141692059
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.3025095128
Short name T831
Test name
Test status
Simulation time 22304203 ps
CPU time 0.87 seconds
Started Aug 18 06:11:12 PM PDT 24
Finished Aug 18 06:11:13 PM PDT 24
Peak memory 206628 kb
Host smart-42583b69-c389-4b84-95b5-211ceb556ced
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025095128 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3025095128
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.2999255175
Short name T745
Test name
Test status
Simulation time 53489465 ps
CPU time 0.9 seconds
Started Aug 18 06:11:13 PM PDT 24
Finished Aug 18 06:11:14 PM PDT 24
Peak memory 207212 kb
Host smart-0d4ea19d-d1a4-4f0e-8b28-08fc21141db5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999255175 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2999255175
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.2899055399
Short name T750
Test name
Test status
Simulation time 66313294 ps
CPU time 1 seconds
Started Aug 18 06:11:10 PM PDT 24
Finished Aug 18 06:11:11 PM PDT 24
Peak memory 218576 kb
Host smart-22806bfe-93ab-4711-8e7b-acf73692e96c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899055399 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.2899055399
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.2601010711
Short name T812
Test name
Test status
Simulation time 62439813 ps
CPU time 1.05 seconds
Started Aug 18 06:11:09 PM PDT 24
Finished Aug 18 06:11:10 PM PDT 24
Peak memory 218700 kb
Host smart-d9651558-8eba-4c30-8bae-a1c3cfd09cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601010711 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.2601010711
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.3071600238
Short name T646
Test name
Test status
Simulation time 56930471 ps
CPU time 1.2 seconds
Started Aug 18 06:11:08 PM PDT 24
Finished Aug 18 06:11:09 PM PDT 24
Peak memory 217372 kb
Host smart-5b062bce-bbeb-4a86-a479-115c20425d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071600238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3071600238
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.110623145
Short name T904
Test name
Test status
Simulation time 33253190 ps
CPU time 0.86 seconds
Started Aug 18 06:11:15 PM PDT 24
Finished Aug 18 06:11:16 PM PDT 24
Peak memory 215696 kb
Host smart-f3aa75a1-b27a-4266-aa3d-7b0436da0eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110623145 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.110623145
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.150197049
Short name T124
Test name
Test status
Simulation time 55123669 ps
CPU time 0.89 seconds
Started Aug 18 06:11:13 PM PDT 24
Finished Aug 18 06:11:14 PM PDT 24
Peak memory 215300 kb
Host smart-878b58d3-6095-4ed2-a6a8-f6865c6a9984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150197049 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.150197049
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.252006295
Short name T423
Test name
Test status
Simulation time 169290248 ps
CPU time 3.77 seconds
Started Aug 18 06:11:11 PM PDT 24
Finished Aug 18 06:11:14 PM PDT 24
Peak memory 217436 kb
Host smart-5067fceb-c75c-4f66-8969-0d6c603be14e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252006295 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.252006295
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.4172282830
Short name T32
Test name
Test status
Simulation time 5373123405 ps
CPU time 60.39 seconds
Started Aug 18 06:11:11 PM PDT 24
Finished Aug 18 06:12:12 PM PDT 24
Peak memory 221316 kb
Host smart-feadbc0f-e67c-47d6-b0df-191953b9f4ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172282830 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.4172282830
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert_test.157032658
Short name T425
Test name
Test status
Simulation time 52499538 ps
CPU time 0.88 seconds
Started Aug 18 06:11:19 PM PDT 24
Finished Aug 18 06:11:20 PM PDT 24
Peak memory 214920 kb
Host smart-a729c44a-ee9d-4295-b685-850b022ca33c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157032658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.157032658
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.1890997961
Short name T273
Test name
Test status
Simulation time 30063089 ps
CPU time 0.85 seconds
Started Aug 18 06:11:11 PM PDT 24
Finished Aug 18 06:11:12 PM PDT 24
Peak memory 206952 kb
Host smart-dfcae9d5-b682-4e00-999c-0543e77f04b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890997961 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1890997961
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.4067674186
Short name T136
Test name
Test status
Simulation time 42759874 ps
CPU time 1.33 seconds
Started Aug 18 06:11:10 PM PDT 24
Finished Aug 18 06:11:11 PM PDT 24
Peak memory 217048 kb
Host smart-4e94c2d8-1992-4a92-84f1-816aeda45496
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067674186 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.4067674186
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.356486369
Short name T455
Test name
Test status
Simulation time 36772743 ps
CPU time 0.96 seconds
Started Aug 18 06:11:11 PM PDT 24
Finished Aug 18 06:11:12 PM PDT 24
Peak memory 223956 kb
Host smart-549f6ee2-d0e9-4a26-a597-0a90f589dea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356486369 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.356486369
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.2452097044
Short name T518
Test name
Test status
Simulation time 43731946 ps
CPU time 1.51 seconds
Started Aug 18 06:11:10 PM PDT 24
Finished Aug 18 06:11:12 PM PDT 24
Peak memory 218452 kb
Host smart-2cf421e2-761b-4d97-b7d1-1f4fdd7910fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452097044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2452097044
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.1662416377
Short name T731
Test name
Test status
Simulation time 27566062 ps
CPU time 1.12 seconds
Started Aug 18 06:11:13 PM PDT 24
Finished Aug 18 06:11:14 PM PDT 24
Peak memory 224216 kb
Host smart-8a7a9c4d-4941-4966-8328-a5096eb160b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662416377 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.1662416377
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.2029384683
Short name T544
Test name
Test status
Simulation time 30198330 ps
CPU time 0.99 seconds
Started Aug 18 06:11:11 PM PDT 24
Finished Aug 18 06:11:13 PM PDT 24
Peak memory 215344 kb
Host smart-44870c18-6f27-465a-8343-e11015a72d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029384683 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.2029384683
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.145918462
Short name T215
Test name
Test status
Simulation time 17304480 ps
CPU time 0.94 seconds
Started Aug 18 06:11:19 PM PDT 24
Finished Aug 18 06:11:20 PM PDT 24
Peak memory 206488 kb
Host smart-24be0d36-3e9e-475d-a796-664a2359b72a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145918462 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.145918462
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_alert.4273265389
Short name T193
Test name
Test status
Simulation time 313434422 ps
CPU time 1.06 seconds
Started Aug 18 06:11:16 PM PDT 24
Finished Aug 18 06:11:18 PM PDT 24
Peak memory 219644 kb
Host smart-a50a116d-abd7-46f9-9295-a4a43a3a3a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273265389 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.4273265389
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.2664365574
Short name T735
Test name
Test status
Simulation time 35776602 ps
CPU time 0.85 seconds
Started Aug 18 06:11:18 PM PDT 24
Finished Aug 18 06:11:19 PM PDT 24
Peak memory 214760 kb
Host smart-7bd770ac-cdaa-49d6-b147-e119aba6faee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664365574 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.2664365574
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.3232268259
Short name T725
Test name
Test status
Simulation time 12797006 ps
CPU time 0.91 seconds
Started Aug 18 06:11:18 PM PDT 24
Finished Aug 18 06:11:19 PM PDT 24
Peak memory 215568 kb
Host smart-670e0424-dfa3-4c0b-b269-0958020f1f7e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232268259 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3232268259
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2352219262
Short name T148
Test name
Test status
Simulation time 92232968 ps
CPU time 1.3 seconds
Started Aug 18 06:11:20 PM PDT 24
Finished Aug 18 06:11:21 PM PDT 24
Peak memory 217028 kb
Host smart-4cfb73e3-89ea-4ac1-b3dc-69ce27e518ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352219262 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2352219262
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.295066890
Short name T152
Test name
Test status
Simulation time 88406677 ps
CPU time 1 seconds
Started Aug 18 06:11:15 PM PDT 24
Finished Aug 18 06:11:17 PM PDT 24
Peak memory 219428 kb
Host smart-1c390b9f-061d-4a1e-be31-a94f769c9436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295066890 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.295066890
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.1209155487
Short name T382
Test name
Test status
Simulation time 49595699 ps
CPU time 1.59 seconds
Started Aug 18 06:11:21 PM PDT 24
Finished Aug 18 06:11:23 PM PDT 24
Peak memory 219032 kb
Host smart-d99db602-dd92-47db-986e-572055756294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209155487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1209155487
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.2409765365
Short name T27
Test name
Test status
Simulation time 19797447 ps
CPU time 1.11 seconds
Started Aug 18 06:11:17 PM PDT 24
Finished Aug 18 06:11:18 PM PDT 24
Peak memory 215948 kb
Host smart-f4fa893c-9eeb-4064-b051-59ea8b649b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409765365 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.2409765365
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.2494782106
Short name T459
Test name
Test status
Simulation time 49816171 ps
CPU time 1.01 seconds
Started Aug 18 06:11:18 PM PDT 24
Finished Aug 18 06:11:19 PM PDT 24
Peak memory 215360 kb
Host smart-2efd613d-5d0a-4f0a-b0da-663eda163067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494782106 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2494782106
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.2093561436
Short name T123
Test name
Test status
Simulation time 650325704 ps
CPU time 3.87 seconds
Started Aug 18 06:11:18 PM PDT 24
Finished Aug 18 06:11:22 PM PDT 24
Peak memory 217276 kb
Host smart-ca89f846-5847-4b88-802b-ee06f5e2f5a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093561436 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.2093561436
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_alert.252579173
Short name T926
Test name
Test status
Simulation time 24968547 ps
CPU time 1.28 seconds
Started Aug 18 06:11:18 PM PDT 24
Finished Aug 18 06:11:19 PM PDT 24
Peak memory 219856 kb
Host smart-02db0a40-1987-4133-92e4-0eaa5b42101b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252579173 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.252579173
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.3522382248
Short name T73
Test name
Test status
Simulation time 61750080 ps
CPU time 0.95 seconds
Started Aug 18 06:11:17 PM PDT 24
Finished Aug 18 06:11:18 PM PDT 24
Peak memory 206776 kb
Host smart-61c06453-5947-488e-93c6-0688df5f7445
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522382248 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.3522382248
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.3722686222
Short name T240
Test name
Test status
Simulation time 14103938 ps
CPU time 0.92 seconds
Started Aug 18 06:11:16 PM PDT 24
Finished Aug 18 06:11:17 PM PDT 24
Peak memory 215612 kb
Host smart-96012d1e-c300-4116-91b0-73d8a614fee1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722686222 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.3722686222
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.3609906505
Short name T586
Test name
Test status
Simulation time 26115827 ps
CPU time 1.06 seconds
Started Aug 18 06:11:17 PM PDT 24
Finished Aug 18 06:11:19 PM PDT 24
Peak memory 216880 kb
Host smart-e6b8060e-9e4a-47e4-a928-7faa24618c01
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609906505 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.3609906505
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.62533656
Short name T487
Test name
Test status
Simulation time 28281526 ps
CPU time 1.27 seconds
Started Aug 18 06:11:19 PM PDT 24
Finished Aug 18 06:11:21 PM PDT 24
Peak memory 217336 kb
Host smart-567315e7-4b0f-4a40-b79c-1ad188b74386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62533656 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.62533656
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.2898143707
Short name T612
Test name
Test status
Simulation time 106633607 ps
CPU time 1.25 seconds
Started Aug 18 06:11:18 PM PDT 24
Finished Aug 18 06:11:20 PM PDT 24
Peak memory 217424 kb
Host smart-af9ef6b1-7e87-4802-8fe3-d2c72ecd49be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898143707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.2898143707
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.3674802742
Short name T109
Test name
Test status
Simulation time 23052944 ps
CPU time 0.96 seconds
Started Aug 18 06:11:19 PM PDT 24
Finished Aug 18 06:11:20 PM PDT 24
Peak memory 215840 kb
Host smart-539a5457-8c0f-4488-ac9a-4c782fd4ac31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674802742 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3674802742
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.3084091937
Short name T469
Test name
Test status
Simulation time 61741516 ps
CPU time 0.88 seconds
Started Aug 18 06:11:18 PM PDT 24
Finished Aug 18 06:11:19 PM PDT 24
Peak memory 207132 kb
Host smart-b6432411-c226-40f5-bde3-2ad57f54fadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084091937 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.3084091937
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.24627281
Short name T782
Test name
Test status
Simulation time 674110335 ps
CPU time 3.98 seconds
Started Aug 18 06:11:23 PM PDT 24
Finished Aug 18 06:11:27 PM PDT 24
Peak memory 220220 kb
Host smart-34a5848e-fcf2-4587-9eee-13c31c73eb21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24627281 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.24627281
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_alert_test.2076226496
Short name T372
Test name
Test status
Simulation time 49255895 ps
CPU time 0.89 seconds
Started Aug 18 06:11:19 PM PDT 24
Finished Aug 18 06:11:20 PM PDT 24
Peak memory 206740 kb
Host smart-8998468c-d88a-4f10-9933-13427bb35e1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076226496 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2076226496
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.3269300053
Short name T564
Test name
Test status
Simulation time 12635157 ps
CPU time 0.89 seconds
Started Aug 18 06:11:19 PM PDT 24
Finished Aug 18 06:11:20 PM PDT 24
Peak memory 207336 kb
Host smart-56af211f-c117-45db-83a8-dd44e9af3b37
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269300053 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3269300053
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.3530976540
Short name T231
Test name
Test status
Simulation time 101430050 ps
CPU time 1.21 seconds
Started Aug 18 06:11:18 PM PDT 24
Finished Aug 18 06:11:20 PM PDT 24
Peak memory 216976 kb
Host smart-310a9654-ecd7-47cc-a042-531db7f6e1c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530976540 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.3530976540
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.3810449145
Short name T773
Test name
Test status
Simulation time 20122166 ps
CPU time 0.98 seconds
Started Aug 18 06:11:17 PM PDT 24
Finished Aug 18 06:11:18 PM PDT 24
Peak memory 218516 kb
Host smart-36ae1b8d-3648-4bc8-a524-ae6321be2a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810449145 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.3810449145
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.3824048061
Short name T641
Test name
Test status
Simulation time 46268943 ps
CPU time 1.33 seconds
Started Aug 18 06:11:19 PM PDT 24
Finished Aug 18 06:11:21 PM PDT 24
Peak memory 217476 kb
Host smart-f4f1c0be-eaa2-4145-bedc-580080e53b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824048061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3824048061
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.3728897593
Short name T606
Test name
Test status
Simulation time 23144112 ps
CPU time 1.09 seconds
Started Aug 18 06:11:17 PM PDT 24
Finished Aug 18 06:11:19 PM PDT 24
Peak memory 215444 kb
Host smart-2de0c650-e7e8-4160-a49e-a6f213ee0b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728897593 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.3728897593
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.422082149
Short name T807
Test name
Test status
Simulation time 123695215 ps
CPU time 0.91 seconds
Started Aug 18 06:11:17 PM PDT 24
Finished Aug 18 06:11:19 PM PDT 24
Peak memory 215312 kb
Host smart-715f7ee2-387c-46c8-bc91-27a5b854f96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422082149 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.422082149
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.4072186188
Short name T637
Test name
Test status
Simulation time 135957800 ps
CPU time 3.24 seconds
Started Aug 18 06:11:17 PM PDT 24
Finished Aug 18 06:11:21 PM PDT 24
Peak memory 217284 kb
Host smart-2561171b-e73d-4476-878d-fcbe38b6512b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072186188 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.4072186188
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_alert.3044525792
Short name T943
Test name
Test status
Simulation time 93308164 ps
CPU time 1.23 seconds
Started Aug 18 06:11:18 PM PDT 24
Finished Aug 18 06:11:20 PM PDT 24
Peak memory 219784 kb
Host smart-a28f5e84-a54e-4711-a176-ecd700b01eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044525792 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3044525792
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2444189461
Short name T765
Test name
Test status
Simulation time 100062121 ps
CPU time 0.91 seconds
Started Aug 18 06:11:18 PM PDT 24
Finished Aug 18 06:11:19 PM PDT 24
Peak memory 206800 kb
Host smart-1c4f53e1-d765-4b3e-ab92-7f37097dbe95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444189461 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2444189461
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.3846118112
Short name T596
Test name
Test status
Simulation time 36961582 ps
CPU time 0.83 seconds
Started Aug 18 06:11:18 PM PDT 24
Finished Aug 18 06:11:20 PM PDT 24
Peak memory 215476 kb
Host smart-fdff7aaf-4b55-415a-8752-f542ef5042ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846118112 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.3846118112
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.4101062169
Short name T149
Test name
Test status
Simulation time 82440346 ps
CPU time 1 seconds
Started Aug 18 06:11:18 PM PDT 24
Finished Aug 18 06:11:19 PM PDT 24
Peak memory 217012 kb
Host smart-280e95a4-1527-4c0c-9497-ba38ee6ef13e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101062169 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.4101062169
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.1077514932
Short name T64
Test name
Test status
Simulation time 86124218 ps
CPU time 1.01 seconds
Started Aug 18 06:11:18 PM PDT 24
Finished Aug 18 06:11:19 PM PDT 24
Peak memory 220632 kb
Host smart-b60d1fc6-f385-4d9b-9927-4b434f9b7db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077514932 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.1077514932
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.1543671599
Short name T815
Test name
Test status
Simulation time 65727275 ps
CPU time 1.14 seconds
Started Aug 18 06:11:18 PM PDT 24
Finished Aug 18 06:11:19 PM PDT 24
Peak memory 218760 kb
Host smart-1b4c1e92-f4af-4b6e-81e2-3b37cd65b1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543671599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1543671599
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.889124805
Short name T712
Test name
Test status
Simulation time 34245711 ps
CPU time 0.85 seconds
Started Aug 18 06:11:17 PM PDT 24
Finished Aug 18 06:11:18 PM PDT 24
Peak memory 215304 kb
Host smart-ab2b754c-745a-474e-ac3f-ba8f5923158f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889124805 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.889124805
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.1488046920
Short name T769
Test name
Test status
Simulation time 28703865 ps
CPU time 0.96 seconds
Started Aug 18 06:11:20 PM PDT 24
Finished Aug 18 06:11:22 PM PDT 24
Peak memory 207192 kb
Host smart-c149f499-8761-4485-a6a9-4a4516b7a9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488046920 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.1488046920
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.4161386435
Short name T119
Test name
Test status
Simulation time 90560903 ps
CPU time 1.65 seconds
Started Aug 18 06:11:19 PM PDT 24
Finished Aug 18 06:11:20 PM PDT 24
Peak memory 217280 kb
Host smart-07928591-6789-472a-98cf-0f270f0264af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161386435 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.4161386435
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.2945815869
Short name T246
Test name
Test status
Simulation time 2088728342 ps
CPU time 49.28 seconds
Started Aug 18 06:11:17 PM PDT 24
Finished Aug 18 06:12:07 PM PDT 24
Peak memory 217936 kb
Host smart-e6da9fff-c593-434d-b8cd-770c3971ab54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945815869 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.2945815869
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.497120340
Short name T157
Test name
Test status
Simulation time 50645290 ps
CPU time 1.26 seconds
Started Aug 18 06:11:26 PM PDT 24
Finished Aug 18 06:11:28 PM PDT 24
Peak memory 219664 kb
Host smart-86c817d7-ae72-4658-bf90-0bf9f50f1bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497120340 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.497120340
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.1000741711
Short name T269
Test name
Test status
Simulation time 15804915 ps
CPU time 0.96 seconds
Started Aug 18 06:11:28 PM PDT 24
Finished Aug 18 06:11:29 PM PDT 24
Peak memory 214948 kb
Host smart-08e9b010-79f8-4533-aa22-d7bb846ff93c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000741711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1000741711
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.1016535280
Short name T861
Test name
Test status
Simulation time 29453069 ps
CPU time 0.79 seconds
Started Aug 18 06:11:27 PM PDT 24
Finished Aug 18 06:11:28 PM PDT 24
Peak memory 215468 kb
Host smart-87b3bd2d-3d28-4691-a1f2-1576d19b5a2d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016535280 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1016535280
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.2135771838
Short name T948
Test name
Test status
Simulation time 26760614 ps
CPU time 1.15 seconds
Started Aug 18 06:11:26 PM PDT 24
Finished Aug 18 06:11:28 PM PDT 24
Peak memory 218444 kb
Host smart-9bbeea69-0286-4eea-bf21-3a5b011d4789
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135771838 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.2135771838
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.1839479534
Short name T623
Test name
Test status
Simulation time 44460625 ps
CPU time 0.99 seconds
Started Aug 18 06:11:25 PM PDT 24
Finished Aug 18 06:11:26 PM PDT 24
Peak memory 218628 kb
Host smart-e0d4f69c-b633-4733-951f-95b8f7ef0229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839479534 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1839479534
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.3403592236
Short name T541
Test name
Test status
Simulation time 32216116 ps
CPU time 1.41 seconds
Started Aug 18 06:11:18 PM PDT 24
Finished Aug 18 06:11:19 PM PDT 24
Peak memory 217452 kb
Host smart-92fce9ba-e45e-4d4e-8b5e-8732049770a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403592236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.3403592236
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.2250645239
Short name T866
Test name
Test status
Simulation time 50311361 ps
CPU time 0.88 seconds
Started Aug 18 06:11:27 PM PDT 24
Finished Aug 18 06:11:28 PM PDT 24
Peak memory 215832 kb
Host smart-2d317889-ac0f-4efa-b181-c283f918fded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250645239 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.2250645239
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.38729931
Short name T447
Test name
Test status
Simulation time 21017796 ps
CPU time 0.93 seconds
Started Aug 18 06:11:18 PM PDT 24
Finished Aug 18 06:11:19 PM PDT 24
Peak memory 215340 kb
Host smart-0fe50be0-327e-44cd-a3a9-a116568ae13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38729931 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.38729931
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3907616942
Short name T367
Test name
Test status
Simulation time 142828953 ps
CPU time 1.97 seconds
Started Aug 18 06:11:19 PM PDT 24
Finished Aug 18 06:11:21 PM PDT 24
Peak memory 217100 kb
Host smart-f40e3aa5-31ba-490b-af0e-bc4dce205660
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907616942 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3907616942
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_alert.733530008
Short name T493
Test name
Test status
Simulation time 65546602 ps
CPU time 1.28 seconds
Started Aug 18 06:11:26 PM PDT 24
Finished Aug 18 06:11:27 PM PDT 24
Peak memory 219820 kb
Host smart-0d42cc32-1059-47c9-9f5d-f716f86db4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733530008 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.733530008
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.1878146442
Short name T786
Test name
Test status
Simulation time 17043356 ps
CPU time 0.96 seconds
Started Aug 18 06:11:30 PM PDT 24
Finished Aug 18 06:11:31 PM PDT 24
Peak memory 214916 kb
Host smart-2684549c-50b4-4616-afb4-094ffebfe0d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878146442 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1878146442
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.4189373163
Short name T230
Test name
Test status
Simulation time 12829850 ps
CPU time 0.87 seconds
Started Aug 18 06:11:25 PM PDT 24
Finished Aug 18 06:11:26 PM PDT 24
Peak memory 215432 kb
Host smart-df5a8f96-081f-4bb4-b576-d44e6e884211
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189373163 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.4189373163
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.4274705990
Short name T853
Test name
Test status
Simulation time 103180223 ps
CPU time 1.18 seconds
Started Aug 18 06:11:26 PM PDT 24
Finished Aug 18 06:11:27 PM PDT 24
Peak memory 215308 kb
Host smart-dcffdb64-3d3e-48cd-82a1-75046b210685
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274705990 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.4274705990
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.2172279816
Short name T556
Test name
Test status
Simulation time 19283695 ps
CPU time 1.12 seconds
Started Aug 18 06:11:28 PM PDT 24
Finished Aug 18 06:11:29 PM PDT 24
Peak memory 218476 kb
Host smart-0a59fd89-ee0b-47fb-922a-bb1587f6385f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172279816 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.2172279816
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.1494977338
Short name T975
Test name
Test status
Simulation time 35049240 ps
CPU time 1.42 seconds
Started Aug 18 06:11:25 PM PDT 24
Finished Aug 18 06:11:27 PM PDT 24
Peak memory 218704 kb
Host smart-caa70f9b-ba58-4816-a304-30020cea8f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494977338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1494977338
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.726239764
Short name T885
Test name
Test status
Simulation time 37336564 ps
CPU time 0.87 seconds
Started Aug 18 06:11:26 PM PDT 24
Finished Aug 18 06:11:27 PM PDT 24
Peak memory 215780 kb
Host smart-dbe33510-f33f-44b7-bdb8-f1578eaa354f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726239764 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.726239764
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.2702210546
Short name T389
Test name
Test status
Simulation time 17853272 ps
CPU time 0.93 seconds
Started Aug 18 06:11:28 PM PDT 24
Finished Aug 18 06:11:29 PM PDT 24
Peak memory 215372 kb
Host smart-2c67edd2-c7e9-4481-a2bb-21f56b0b8752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702210546 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.2702210546
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.1451569364
Short name T132
Test name
Test status
Simulation time 222092477 ps
CPU time 4.72 seconds
Started Aug 18 06:11:29 PM PDT 24
Finished Aug 18 06:11:34 PM PDT 24
Peak memory 217424 kb
Host smart-8a50a391-b08b-45d1-9446-0f5ad6b9d726
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451569364 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.1451569364
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.1924274019
Short name T829
Test name
Test status
Simulation time 31688522232 ps
CPU time 152.97 seconds
Started Aug 18 06:11:25 PM PDT 24
Finished Aug 18 06:13:58 PM PDT 24
Peak memory 218576 kb
Host smart-c7480b04-c180-41ae-9860-0e1dce992f11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924274019 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.1924274019
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.1350716646
Short name T288
Test name
Test status
Simulation time 30778836 ps
CPU time 1.3 seconds
Started Aug 18 06:10:10 PM PDT 24
Finished Aug 18 06:10:12 PM PDT 24
Peak memory 220600 kb
Host smart-efc04f6d-a2e4-4829-b0fc-530e9b95f46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350716646 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1350716646
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.501745283
Short name T406
Test name
Test status
Simulation time 16300235 ps
CPU time 0.89 seconds
Started Aug 18 06:10:09 PM PDT 24
Finished Aug 18 06:10:09 PM PDT 24
Peak memory 206824 kb
Host smart-33338d49-3f7f-442f-9ec5-5d7ae388c548
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501745283 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.501745283
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.3528041052
Short name T813
Test name
Test status
Simulation time 21398443 ps
CPU time 0.87 seconds
Started Aug 18 06:10:11 PM PDT 24
Finished Aug 18 06:10:12 PM PDT 24
Peak memory 215364 kb
Host smart-a0f08626-c2d3-4e2a-8a04-f9d8a78dfb2a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528041052 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.3528041052
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.992345842
Short name T688
Test name
Test status
Simulation time 95557594 ps
CPU time 1.02 seconds
Started Aug 18 06:10:09 PM PDT 24
Finished Aug 18 06:10:10 PM PDT 24
Peak memory 215384 kb
Host smart-3868efe4-67b2-4fee-a42e-2d8320e44ba9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992345842 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_dis
able_auto_req_mode.992345842
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.3595835347
Short name T217
Test name
Test status
Simulation time 53846295 ps
CPU time 1.01 seconds
Started Aug 18 06:10:10 PM PDT 24
Finished Aug 18 06:10:11 PM PDT 24
Peak memory 215500 kb
Host smart-495a13ec-4317-482a-8a5d-f5d4ed5637d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595835347 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.3595835347
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.358563630
Short name T852
Test name
Test status
Simulation time 70997432 ps
CPU time 1.36 seconds
Started Aug 18 06:10:08 PM PDT 24
Finished Aug 18 06:10:09 PM PDT 24
Peak memory 218656 kb
Host smart-b37bb577-9691-4126-9336-c83dbfd5e80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358563630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.358563630
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.2509817048
Short name T138
Test name
Test status
Simulation time 28280227 ps
CPU time 0.87 seconds
Started Aug 18 06:10:10 PM PDT 24
Finished Aug 18 06:10:11 PM PDT 24
Peak memory 215740 kb
Host smart-1f9bda8b-9e4d-4fa2-b062-11c37d306125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509817048 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2509817048
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.4148326553
Short name T805
Test name
Test status
Simulation time 16278513 ps
CPU time 1.06 seconds
Started Aug 18 06:10:12 PM PDT 24
Finished Aug 18 06:10:14 PM PDT 24
Peak memory 207204 kb
Host smart-eb5c8565-fee8-4ad0-aaf2-06f0eeb407fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148326553 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.4148326553
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.3497467557
Short name T57
Test name
Test status
Simulation time 5124208792 ps
CPU time 9.37 seconds
Started Aug 18 06:10:11 PM PDT 24
Finished Aug 18 06:10:20 PM PDT 24
Peak memory 242092 kb
Host smart-f1aba23d-5928-4349-8a2a-96207402cba8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497467557 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.3497467557
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.1789304039
Short name T580
Test name
Test status
Simulation time 27147605 ps
CPU time 0.96 seconds
Started Aug 18 06:10:10 PM PDT 24
Finished Aug 18 06:10:11 PM PDT 24
Peak memory 215472 kb
Host smart-84b3ecd6-4531-4bbe-85f2-1849b7ce8ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789304039 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.1789304039
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1298045763
Short name T256
Test name
Test status
Simulation time 27313470 ps
CPU time 0.9 seconds
Started Aug 18 06:10:10 PM PDT 24
Finished Aug 18 06:10:11 PM PDT 24
Peak memory 206552 kb
Host smart-3e55c050-19a0-46ce-9053-324af6017a4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298045763 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1298045763
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2010376081
Short name T796
Test name
Test status
Simulation time 2948885699 ps
CPU time 75.43 seconds
Started Aug 18 06:10:10 PM PDT 24
Finished Aug 18 06:11:26 PM PDT 24
Peak memory 221204 kb
Host smart-c2d5f50e-07ab-4a99-9dd4-a724a9e2e6b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010376081 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2010376081
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.4007391766
Short name T643
Test name
Test status
Simulation time 59225043 ps
CPU time 1.35 seconds
Started Aug 18 06:11:29 PM PDT 24
Finished Aug 18 06:11:30 PM PDT 24
Peak memory 215704 kb
Host smart-ad529fe4-39bd-4c5d-9afc-bb1deffeff17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007391766 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.4007391766
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.3251613897
Short name T565
Test name
Test status
Simulation time 12600313 ps
CPU time 0.85 seconds
Started Aug 18 06:11:32 PM PDT 24
Finished Aug 18 06:11:33 PM PDT 24
Peak memory 207016 kb
Host smart-a1f3356d-2b40-413b-8687-a88ac1ac1517
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251613897 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3251613897
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.2059285821
Short name T824
Test name
Test status
Simulation time 33847061 ps
CPU time 0.86 seconds
Started Aug 18 06:11:24 PM PDT 24
Finished Aug 18 06:11:25 PM PDT 24
Peak memory 215336 kb
Host smart-c3a1c3b0-47c9-42fa-bbfa-96c5dad6509f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059285821 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2059285821
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.1017715121
Short name T884
Test name
Test status
Simulation time 41320948 ps
CPU time 0.99 seconds
Started Aug 18 06:11:26 PM PDT 24
Finished Aug 18 06:11:27 PM PDT 24
Peak memory 218372 kb
Host smart-4bd38e2c-52cb-4bd1-8b5d-312fcf5e8da1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017715121 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.1017715121
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.3914434757
Short name T178
Test name
Test status
Simulation time 35251696 ps
CPU time 0.99 seconds
Started Aug 18 06:11:33 PM PDT 24
Finished Aug 18 06:11:34 PM PDT 24
Peak memory 223992 kb
Host smart-a6e357ac-552c-44ed-92b0-72cd34566116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914434757 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.3914434757
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.2009426491
Short name T843
Test name
Test status
Simulation time 286118881 ps
CPU time 4.07 seconds
Started Aug 18 06:11:30 PM PDT 24
Finished Aug 18 06:11:34 PM PDT 24
Peak memory 220304 kb
Host smart-fa42b3b5-5984-421c-8a46-a62c9f2ab29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009426491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.2009426491
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.2904417712
Short name T563
Test name
Test status
Simulation time 25256303 ps
CPU time 1.03 seconds
Started Aug 18 06:11:27 PM PDT 24
Finished Aug 18 06:11:28 PM PDT 24
Peak memory 215484 kb
Host smart-599b6608-e50d-43a7-a1b3-e74ad724e5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904417712 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.2904417712
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.392740877
Short name T759
Test name
Test status
Simulation time 14982672 ps
CPU time 0.97 seconds
Started Aug 18 06:11:27 PM PDT 24
Finished Aug 18 06:11:28 PM PDT 24
Peak memory 215344 kb
Host smart-f11d4a4b-78aa-456f-8e8e-43f80e61dd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392740877 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.392740877
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.3600836986
Short name T587
Test name
Test status
Simulation time 128211802 ps
CPU time 1.44 seconds
Started Aug 18 06:11:26 PM PDT 24
Finished Aug 18 06:11:27 PM PDT 24
Peak memory 217288 kb
Host smart-491f5ab1-40ea-4051-9130-ec581b3b0dbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600836986 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.3600836986
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_alert.3511813983
Short name T777
Test name
Test status
Simulation time 40433078 ps
CPU time 1.21 seconds
Started Aug 18 06:11:29 PM PDT 24
Finished Aug 18 06:11:30 PM PDT 24
Peak memory 219688 kb
Host smart-1ae3402e-adb3-4fde-97df-99623c8e16f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511813983 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.3511813983
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.2218975513
Short name T517
Test name
Test status
Simulation time 81113500 ps
CPU time 0.87 seconds
Started Aug 18 06:11:27 PM PDT 24
Finished Aug 18 06:11:28 PM PDT 24
Peak memory 206780 kb
Host smart-36a803be-a44a-4090-8920-c61f5468ea71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218975513 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2218975513
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.1280905647
Short name T710
Test name
Test status
Simulation time 46210062 ps
CPU time 0.86 seconds
Started Aug 18 06:11:29 PM PDT 24
Finished Aug 18 06:11:30 PM PDT 24
Peak memory 215476 kb
Host smart-ab9f4f44-46aa-49e6-b193-ce5b655244c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280905647 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.1280905647
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.2522214379
Short name T229
Test name
Test status
Simulation time 209717463 ps
CPU time 1.16 seconds
Started Aug 18 06:11:25 PM PDT 24
Finished Aug 18 06:11:26 PM PDT 24
Peak memory 217048 kb
Host smart-21925299-f347-4b6f-bf77-cf78210d40dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522214379 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.2522214379
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3199136285
Short name T197
Test name
Test status
Simulation time 21907621 ps
CPU time 1.04 seconds
Started Aug 18 06:11:27 PM PDT 24
Finished Aug 18 06:11:28 PM PDT 24
Peak memory 218412 kb
Host smart-8f3a4e80-d090-440e-b16f-99f07741e455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199136285 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3199136285
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.1652238520
Short name T847
Test name
Test status
Simulation time 52224700 ps
CPU time 1.19 seconds
Started Aug 18 06:11:29 PM PDT 24
Finished Aug 18 06:11:31 PM PDT 24
Peak memory 217528 kb
Host smart-66a64706-bd53-405b-b8cd-c423c16d0f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652238520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1652238520
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.579406235
Short name T976
Test name
Test status
Simulation time 35609958 ps
CPU time 1.04 seconds
Started Aug 18 06:11:25 PM PDT 24
Finished Aug 18 06:11:26 PM PDT 24
Peak memory 224240 kb
Host smart-f34664cb-d961-46a9-9a74-a0911dbdff89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579406235 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.579406235
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.2797346159
Short name T937
Test name
Test status
Simulation time 16097788 ps
CPU time 0.99 seconds
Started Aug 18 06:11:26 PM PDT 24
Finished Aug 18 06:11:27 PM PDT 24
Peak memory 215380 kb
Host smart-3732e473-49ec-41cb-8b9c-5d5d3da18c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797346159 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.2797346159
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.999424728
Short name T681
Test name
Test status
Simulation time 110130959 ps
CPU time 1.92 seconds
Started Aug 18 06:11:26 PM PDT 24
Finished Aug 18 06:11:28 PM PDT 24
Peak memory 217528 kb
Host smart-a710af32-52a2-4aad-9973-5036eb8fdd10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999424728 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.999424728
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_alert.1043590061
Short name T413
Test name
Test status
Simulation time 89424433 ps
CPU time 1.16 seconds
Started Aug 18 06:11:29 PM PDT 24
Finished Aug 18 06:11:31 PM PDT 24
Peak memory 219676 kb
Host smart-ce4181d1-2ece-4e6c-8307-1c64390fe257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043590061 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1043590061
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2094059431
Short name T371
Test name
Test status
Simulation time 17380822 ps
CPU time 0.79 seconds
Started Aug 18 06:11:25 PM PDT 24
Finished Aug 18 06:11:26 PM PDT 24
Peak memory 206384 kb
Host smart-3d303bff-7a2f-40ac-bedc-2f34ca80f1cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094059431 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2094059431
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.3139926807
Short name T499
Test name
Test status
Simulation time 81230092 ps
CPU time 0.8 seconds
Started Aug 18 06:11:28 PM PDT 24
Finished Aug 18 06:11:29 PM PDT 24
Peak memory 215444 kb
Host smart-356313b5-15dc-4f61-9a55-30bb77b7d42b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139926807 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3139926807
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3876210912
Short name T71
Test name
Test status
Simulation time 113236256 ps
CPU time 1.25 seconds
Started Aug 18 06:11:26 PM PDT 24
Finished Aug 18 06:11:27 PM PDT 24
Peak memory 216980 kb
Host smart-4d5dc460-381f-4fc1-b133-658e5840c07f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876210912 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3876210912
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.597261365
Short name T803
Test name
Test status
Simulation time 19694289 ps
CPU time 1.11 seconds
Started Aug 18 06:11:27 PM PDT 24
Finished Aug 18 06:11:28 PM PDT 24
Peak memory 219688 kb
Host smart-b1241723-c94e-4218-8832-13c6ac495e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597261365 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.597261365
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.2445593559
Short name T871
Test name
Test status
Simulation time 51525793 ps
CPU time 1.84 seconds
Started Aug 18 06:11:28 PM PDT 24
Finished Aug 18 06:11:30 PM PDT 24
Peak memory 220368 kb
Host smart-7d224213-6ba2-4ab5-ab8a-00ff6b45fd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445593559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.2445593559
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_smoke.627239268
Short name T543
Test name
Test status
Simulation time 48972457 ps
CPU time 0.91 seconds
Started Aug 18 06:11:27 PM PDT 24
Finished Aug 18 06:11:28 PM PDT 24
Peak memory 215368 kb
Host smart-a08a7f01-3e6b-47d4-8965-2ec6b5660f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627239268 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.627239268
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.1057709164
Short name T783
Test name
Test status
Simulation time 266948393 ps
CPU time 1.29 seconds
Started Aug 18 06:11:28 PM PDT 24
Finished Aug 18 06:11:30 PM PDT 24
Peak memory 217424 kb
Host smart-97075d9e-d2c1-4bb7-8ee7-31288a3ead7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057709164 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1057709164
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_alert.3913777087
Short name T647
Test name
Test status
Simulation time 27958468 ps
CPU time 1.31 seconds
Started Aug 18 06:11:29 PM PDT 24
Finished Aug 18 06:11:30 PM PDT 24
Peak memory 220392 kb
Host smart-8b453349-10aa-4766-8d11-af52825f588c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913777087 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.3913777087
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.1471760476
Short name T663
Test name
Test status
Simulation time 41799903 ps
CPU time 0.83 seconds
Started Aug 18 06:11:32 PM PDT 24
Finished Aug 18 06:11:33 PM PDT 24
Peak memory 206796 kb
Host smart-7c08a453-a6a2-4ef2-b828-e2192cb2e7db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471760476 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1471760476
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.3067018436
Short name T192
Test name
Test status
Simulation time 21912699 ps
CPU time 0.86 seconds
Started Aug 18 06:11:27 PM PDT 24
Finished Aug 18 06:11:28 PM PDT 24
Peak memory 215476 kb
Host smart-deb1f5fd-c329-45a0-b0ec-996debe87b0a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067018436 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.3067018436
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.3602667783
Short name T378
Test name
Test status
Simulation time 30275483 ps
CPU time 1.13 seconds
Started Aug 18 06:11:30 PM PDT 24
Finished Aug 18 06:11:31 PM PDT 24
Peak memory 218432 kb
Host smart-6c35d4af-f9ad-4dcc-9583-dd94d32fc2bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602667783 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.3602667783
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.4180737201
Short name T60
Test name
Test status
Simulation time 20626906 ps
CPU time 1.01 seconds
Started Aug 18 06:11:28 PM PDT 24
Finished Aug 18 06:11:29 PM PDT 24
Peak memory 218500 kb
Host smart-91691bdd-4687-48fd-8b02-e8e773507c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180737201 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.4180737201
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.1370830836
Short name T856
Test name
Test status
Simulation time 92562641 ps
CPU time 1.31 seconds
Started Aug 18 06:11:27 PM PDT 24
Finished Aug 18 06:11:29 PM PDT 24
Peak memory 217392 kb
Host smart-513441cc-2429-49b7-bee4-5ca0fb8627c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370830836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.1370830836
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.1519763982
Short name T29
Test name
Test status
Simulation time 28587443 ps
CPU time 0.9 seconds
Started Aug 18 06:11:28 PM PDT 24
Finished Aug 18 06:11:29 PM PDT 24
Peak memory 215916 kb
Host smart-ca17aa69-ec2b-4c67-96d7-fe1931338f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519763982 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.1519763982
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.3036309121
Short name T726
Test name
Test status
Simulation time 32386310 ps
CPU time 0.95 seconds
Started Aug 18 06:11:25 PM PDT 24
Finished Aug 18 06:11:26 PM PDT 24
Peak memory 207208 kb
Host smart-e447b9c7-edd6-451f-a8dd-63fa71eb7292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036309121 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.3036309121
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.427494291
Short name T548
Test name
Test status
Simulation time 1051768724 ps
CPU time 2.76 seconds
Started Aug 18 06:11:27 PM PDT 24
Finished Aug 18 06:11:30 PM PDT 24
Peak memory 217492 kb
Host smart-98fbbf73-f956-46ae-a76f-e8fba12d8fcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427494291 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.427494291
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_alert.453975096
Short name T86
Test name
Test status
Simulation time 38651818 ps
CPU time 1.21 seconds
Started Aug 18 06:11:27 PM PDT 24
Finished Aug 18 06:11:29 PM PDT 24
Peak memory 215768 kb
Host smart-7e23ce2c-28f1-4b54-978f-27f5b22170e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453975096 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.453975096
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.3694132046
Short name T649
Test name
Test status
Simulation time 16666823 ps
CPU time 0.89 seconds
Started Aug 18 06:11:38 PM PDT 24
Finished Aug 18 06:11:39 PM PDT 24
Peak memory 206812 kb
Host smart-f9879237-22b7-414d-b898-fd72df2f9e63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694132046 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3694132046
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.468056888
Short name T40
Test name
Test status
Simulation time 24131995 ps
CPU time 0.89 seconds
Started Aug 18 06:11:38 PM PDT 24
Finished Aug 18 06:11:39 PM PDT 24
Peak memory 215216 kb
Host smart-9d721c31-9967-4b4a-bb6e-51ab23c64ee5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468056888 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.468056888
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.1671367003
Short name T219
Test name
Test status
Simulation time 80814967 ps
CPU time 1.26 seconds
Started Aug 18 06:11:32 PM PDT 24
Finished Aug 18 06:11:33 PM PDT 24
Peak memory 219684 kb
Host smart-95f5478b-4dda-496f-b28a-bb64e99f6b17
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671367003 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.1671367003
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.4111099470
Short name T189
Test name
Test status
Simulation time 36905245 ps
CPU time 1.01 seconds
Started Aug 18 06:11:32 PM PDT 24
Finished Aug 18 06:11:33 PM PDT 24
Peak memory 223964 kb
Host smart-58f6ca97-934d-4ac9-81b0-9a7b90a0ab0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111099470 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.4111099470
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.956169761
Short name T818
Test name
Test status
Simulation time 82874557 ps
CPU time 1.18 seconds
Started Aug 18 06:11:30 PM PDT 24
Finished Aug 18 06:11:31 PM PDT 24
Peak memory 219456 kb
Host smart-f27d9a96-779f-439d-8fb8-1ec1c81b106f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956169761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.956169761
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.193380531
Short name T876
Test name
Test status
Simulation time 22467063 ps
CPU time 1.12 seconds
Started Aug 18 06:11:26 PM PDT 24
Finished Aug 18 06:11:27 PM PDT 24
Peak memory 215508 kb
Host smart-864d1633-76bb-4c67-a630-083414b47b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193380531 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.193380531
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.2707599659
Short name T82
Test name
Test status
Simulation time 41183807 ps
CPU time 1 seconds
Started Aug 18 06:11:29 PM PDT 24
Finished Aug 18 06:11:30 PM PDT 24
Peak memory 215396 kb
Host smart-151510cb-2e1c-46a7-b21a-02fdb50d6fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707599659 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.2707599659
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.2172098956
Short name T272
Test name
Test status
Simulation time 92156171 ps
CPU time 2.09 seconds
Started Aug 18 06:11:26 PM PDT 24
Finished Aug 18 06:11:28 PM PDT 24
Peak memory 215180 kb
Host smart-6a0bc3be-c99f-42bf-b66a-9eb6e1230363
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172098956 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2172098956
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_alert.3184299314
Short name T960
Test name
Test status
Simulation time 111294922 ps
CPU time 1.21 seconds
Started Aug 18 06:11:33 PM PDT 24
Finished Aug 18 06:11:34 PM PDT 24
Peak memory 218560 kb
Host smart-01dd6c6c-8b30-43a2-83b8-3a994ac1601c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184299314 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.3184299314
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.639632194
Short name T664
Test name
Test status
Simulation time 15175550 ps
CPU time 0.95 seconds
Started Aug 18 06:11:37 PM PDT 24
Finished Aug 18 06:11:38 PM PDT 24
Peak memory 206836 kb
Host smart-703ab465-9e1d-4a31-acb3-f39274e933e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639632194 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.639632194
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.3633827103
Short name T179
Test name
Test status
Simulation time 13002862 ps
CPU time 0.95 seconds
Started Aug 18 06:11:36 PM PDT 24
Finished Aug 18 06:11:37 PM PDT 24
Peak memory 215608 kb
Host smart-cbe93969-3a73-4d3c-9e81-906ecf199c11
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633827103 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3633827103
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.2862159213
Short name T167
Test name
Test status
Simulation time 99200379 ps
CPU time 1.14 seconds
Started Aug 18 06:11:31 PM PDT 24
Finished Aug 18 06:11:32 PM PDT 24
Peak memory 219756 kb
Host smart-4f7c6e24-29a6-49e4-bee1-df9e0981f8c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862159213 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.2862159213
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.1273992680
Short name T50
Test name
Test status
Simulation time 54808863 ps
CPU time 1.12 seconds
Started Aug 18 06:11:34 PM PDT 24
Finished Aug 18 06:11:35 PM PDT 24
Peak memory 224132 kb
Host smart-84228c41-0f00-44f6-aab3-8180d42e8666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273992680 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1273992680
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.3305071946
Short name T424
Test name
Test status
Simulation time 26985406 ps
CPU time 1.23 seconds
Started Aug 18 06:11:32 PM PDT 24
Finished Aug 18 06:11:34 PM PDT 24
Peak memory 220548 kb
Host smart-2c7c050d-fe2e-496e-a285-370559de7261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305071946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3305071946
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.2571669000
Short name T30
Test name
Test status
Simulation time 21793341 ps
CPU time 1.07 seconds
Started Aug 18 06:11:36 PM PDT 24
Finished Aug 18 06:11:38 PM PDT 24
Peak memory 215924 kb
Host smart-cf1acd54-b729-47ad-b687-d598c20d2bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571669000 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.2571669000
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.844400412
Short name T862
Test name
Test status
Simulation time 24172328 ps
CPU time 0.95 seconds
Started Aug 18 06:11:30 PM PDT 24
Finished Aug 18 06:11:31 PM PDT 24
Peak memory 207196 kb
Host smart-a832053d-b907-4ee0-b798-c1b674c6acdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844400412 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.844400412
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1521733757
Short name T677
Test name
Test status
Simulation time 222351100 ps
CPU time 1.49 seconds
Started Aug 18 06:11:42 PM PDT 24
Finished Aug 18 06:11:44 PM PDT 24
Peak memory 215424 kb
Host smart-ce279c85-7807-410a-94e3-7b1cc85364da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521733757 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1521733757
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.2221995783
Short name T245
Test name
Test status
Simulation time 6158253235 ps
CPU time 71.47 seconds
Started Aug 18 06:11:33 PM PDT 24
Finished Aug 18 06:12:45 PM PDT 24
Peak memory 218204 kb
Host smart-ae33d5a8-3b32-40de-bc13-fe7ea2d06e62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221995783 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.2221995783
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.3896400543
Short name T660
Test name
Test status
Simulation time 82265349 ps
CPU time 1.18 seconds
Started Aug 18 06:11:33 PM PDT 24
Finished Aug 18 06:11:34 PM PDT 24
Peak memory 218880 kb
Host smart-49a01d84-fe1c-421f-909e-c9ae6be7e33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896400543 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.3896400543
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.4209916466
Short name T70
Test name
Test status
Simulation time 34367806 ps
CPU time 0.83 seconds
Started Aug 18 06:11:32 PM PDT 24
Finished Aug 18 06:11:33 PM PDT 24
Peak memory 214784 kb
Host smart-e4dc11dd-1700-4cc6-97a8-2461cdec57ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209916466 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.4209916466
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.3703399671
Short name T718
Test name
Test status
Simulation time 23768547 ps
CPU time 0.88 seconds
Started Aug 18 06:11:34 PM PDT 24
Finished Aug 18 06:11:35 PM PDT 24
Peak memory 215468 kb
Host smart-252d32ca-4024-48aa-9240-244d12c89fe5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703399671 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3703399671
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.4040663393
Short name T973
Test name
Test status
Simulation time 55085061 ps
CPU time 1 seconds
Started Aug 18 06:11:38 PM PDT 24
Finished Aug 18 06:11:40 PM PDT 24
Peak memory 216852 kb
Host smart-f3f3dc7e-b8ee-4bec-8acb-33701ee33ddb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040663393 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.4040663393
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.2417320380
Short name T4
Test name
Test status
Simulation time 69586263 ps
CPU time 0.88 seconds
Started Aug 18 06:11:31 PM PDT 24
Finished Aug 18 06:11:32 PM PDT 24
Peak memory 218624 kb
Host smart-8465218a-1ac9-4c0c-a5ab-2de58075017d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417320380 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2417320380
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.4033228077
Short name T705
Test name
Test status
Simulation time 47385897 ps
CPU time 1.54 seconds
Started Aug 18 06:11:35 PM PDT 24
Finished Aug 18 06:11:37 PM PDT 24
Peak memory 218552 kb
Host smart-51754371-5d18-4106-b7b8-ffb57013bd13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033228077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.4033228077
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.1589600266
Short name T650
Test name
Test status
Simulation time 28589264 ps
CPU time 0.93 seconds
Started Aug 18 06:11:42 PM PDT 24
Finished Aug 18 06:11:43 PM PDT 24
Peak memory 215640 kb
Host smart-ae465a0e-594c-4b3b-afe1-6182954a34d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589600266 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1589600266
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.2376755089
Short name T661
Test name
Test status
Simulation time 52850586 ps
CPU time 0.94 seconds
Started Aug 18 06:11:31 PM PDT 24
Finished Aug 18 06:11:32 PM PDT 24
Peak memory 215364 kb
Host smart-e65f3de8-c456-4f0f-bc25-15e5b7df8af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376755089 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.2376755089
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.2404238409
Short name T379
Test name
Test status
Simulation time 258321668 ps
CPU time 2.87 seconds
Started Aug 18 06:11:29 PM PDT 24
Finished Aug 18 06:11:32 PM PDT 24
Peak memory 215360 kb
Host smart-c7ba75c8-3ddc-4158-8c43-4b3cb6bc4297
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404238409 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2404238409
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_alert.3928895236
Short name T239
Test name
Test status
Simulation time 63845433 ps
CPU time 1.02 seconds
Started Aug 18 06:11:31 PM PDT 24
Finished Aug 18 06:11:32 PM PDT 24
Peak memory 220160 kb
Host smart-a7941a6b-0121-42d1-b0b5-cf9482e0b207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928895236 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.3928895236
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.910124082
Short name T751
Test name
Test status
Simulation time 36869426 ps
CPU time 0.87 seconds
Started Aug 18 06:11:36 PM PDT 24
Finished Aug 18 06:11:37 PM PDT 24
Peak memory 206552 kb
Host smart-7cd8c3ea-e0a4-4e8c-b93d-3c94fc5c9117
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910124082 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.910124082
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.844306993
Short name T228
Test name
Test status
Simulation time 22718257 ps
CPU time 0.93 seconds
Started Aug 18 06:11:37 PM PDT 24
Finished Aug 18 06:11:38 PM PDT 24
Peak memory 215432 kb
Host smart-54882fa5-1006-4da2-b4b0-19818e406fae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844306993 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.844306993
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1398198436
Short name T482
Test name
Test status
Simulation time 103955091 ps
CPU time 1.01 seconds
Started Aug 18 06:11:36 PM PDT 24
Finished Aug 18 06:11:37 PM PDT 24
Peak memory 217020 kb
Host smart-4300c2a5-c0af-4e0e-967f-fdc95d541961
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398198436 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1398198436
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.4190882286
Short name T221
Test name
Test status
Simulation time 46417532 ps
CPU time 1.13 seconds
Started Aug 18 06:11:33 PM PDT 24
Finished Aug 18 06:11:34 PM PDT 24
Peak memory 219804 kb
Host smart-eba931b2-1754-4d11-bf4e-efdbfc38e637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190882286 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.4190882286
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.237152033
Short name T363
Test name
Test status
Simulation time 117938306 ps
CPU time 1.53 seconds
Started Aug 18 06:11:36 PM PDT 24
Finished Aug 18 06:11:38 PM PDT 24
Peak memory 220804 kb
Host smart-4c6abf40-0570-479a-87f5-d7e6491c02a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237152033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.237152033
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.3253285966
Short name T529
Test name
Test status
Simulation time 23086853 ps
CPU time 1.24 seconds
Started Aug 18 06:11:36 PM PDT 24
Finished Aug 18 06:11:37 PM PDT 24
Peak memory 224236 kb
Host smart-2d560cfd-e11b-4772-8f4c-ff4a118faf79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253285966 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.3253285966
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.2335219681
Short name T925
Test name
Test status
Simulation time 18209748 ps
CPU time 0.99 seconds
Started Aug 18 06:11:35 PM PDT 24
Finished Aug 18 06:11:36 PM PDT 24
Peak memory 215376 kb
Host smart-bcdb2192-0b14-40ea-b2fb-259f69f935cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335219681 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2335219681
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.446700202
Short name T827
Test name
Test status
Simulation time 558925349 ps
CPU time 3.28 seconds
Started Aug 18 06:11:38 PM PDT 24
Finished Aug 18 06:11:41 PM PDT 24
Peak memory 215484 kb
Host smart-bc9eb7da-a3d8-409e-a554-38d5259ffd07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446700202 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.446700202
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.4069773368
Short name T33
Test name
Test status
Simulation time 4750595447 ps
CPU time 78.48 seconds
Started Aug 18 06:11:36 PM PDT 24
Finished Aug 18 06:12:55 PM PDT 24
Peak memory 223764 kb
Host smart-e337093c-e870-4d00-87c5-fba21571e670
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069773368 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.4069773368
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.3306229128
Short name T753
Test name
Test status
Simulation time 31660189 ps
CPU time 1.33 seconds
Started Aug 18 06:11:34 PM PDT 24
Finished Aug 18 06:11:35 PM PDT 24
Peak memory 221092 kb
Host smart-7fe780fe-ed71-4541-8cf3-1c37ddca494f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306229128 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3306229128
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1098746599
Short name T865
Test name
Test status
Simulation time 27817861 ps
CPU time 0.99 seconds
Started Aug 18 06:11:34 PM PDT 24
Finished Aug 18 06:11:35 PM PDT 24
Peak memory 206740 kb
Host smart-6c8761a5-858b-419b-bf3e-a2b6fe4e3cb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098746599 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1098746599
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.1321888597
Short name T869
Test name
Test status
Simulation time 12729218 ps
CPU time 0.94 seconds
Started Aug 18 06:11:42 PM PDT 24
Finished Aug 18 06:11:44 PM PDT 24
Peak memory 214996 kb
Host smart-1801c4c5-e926-4b8a-9c15-bd0576e44e53
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321888597 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.1321888597
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.98218120
Short name T9
Test name
Test status
Simulation time 45610943 ps
CPU time 0.99 seconds
Started Aug 18 06:11:35 PM PDT 24
Finished Aug 18 06:11:36 PM PDT 24
Peak memory 218652 kb
Host smart-e220c20b-8e2c-4136-ad0b-588dafe5e953
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98218120 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_dis
able_auto_req_mode.98218120
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.2638647567
Short name T390
Test name
Test status
Simulation time 32300832 ps
CPU time 0.85 seconds
Started Aug 18 06:11:33 PM PDT 24
Finished Aug 18 06:11:34 PM PDT 24
Peak memory 218364 kb
Host smart-d25b4d59-d971-4f15-a5b8-e402cd12ec1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638647567 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.2638647567
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_intr.1985925702
Short name T719
Test name
Test status
Simulation time 23134249 ps
CPU time 1.04 seconds
Started Aug 18 06:11:32 PM PDT 24
Finished Aug 18 06:11:33 PM PDT 24
Peak memory 215512 kb
Host smart-ee526461-ebae-47ff-94a2-439eec4dc295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985925702 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.1985925702
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.3005919445
Short name T74
Test name
Test status
Simulation time 42329167 ps
CPU time 0.97 seconds
Started Aug 18 06:11:34 PM PDT 24
Finished Aug 18 06:11:35 PM PDT 24
Peak memory 215344 kb
Host smart-05ffb353-a221-4568-859a-88ca8536cea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005919445 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3005919445
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.4254080152
Short name T665
Test name
Test status
Simulation time 852138965 ps
CPU time 4.65 seconds
Started Aug 18 06:11:33 PM PDT 24
Finished Aug 18 06:11:37 PM PDT 24
Peak memory 217564 kb
Host smart-b036f7c5-d7fa-4196-b91f-42800d3acc9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254080152 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.4254080152
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.2391499780
Short name T605
Test name
Test status
Simulation time 5374122572 ps
CPU time 32.64 seconds
Started Aug 18 06:11:36 PM PDT 24
Finished Aug 18 06:12:09 PM PDT 24
Peak memory 219068 kb
Host smart-a8a9349c-4e35-4154-8f9a-26aa9f6b0f86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391499780 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.2391499780
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.2837832790
Short name T377
Test name
Test status
Simulation time 28060732 ps
CPU time 1.28 seconds
Started Aug 18 06:11:33 PM PDT 24
Finished Aug 18 06:11:34 PM PDT 24
Peak memory 219848 kb
Host smart-835ee038-58a2-4728-86ff-582ea3892fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837832790 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2837832790
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.3604374435
Short name T704
Test name
Test status
Simulation time 15531310 ps
CPU time 0.97 seconds
Started Aug 18 06:11:32 PM PDT 24
Finished Aug 18 06:11:33 PM PDT 24
Peak memory 206776 kb
Host smart-34a862e2-9bc4-499b-9459-3995f8f6c9d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604374435 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3604374435
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.2633102060
Short name T97
Test name
Test status
Simulation time 10646403 ps
CPU time 0.92 seconds
Started Aug 18 06:11:33 PM PDT 24
Finished Aug 18 06:11:34 PM PDT 24
Peak memory 215172 kb
Host smart-29d615eb-49a4-4c58-b6c7-2ad8549e0b15
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633102060 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2633102060
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.3469553459
Short name T938
Test name
Test status
Simulation time 37003693 ps
CPU time 1.3 seconds
Started Aug 18 06:11:36 PM PDT 24
Finished Aug 18 06:11:37 PM PDT 24
Peak memory 216992 kb
Host smart-1b3cf740-326b-4828-82b4-77262b8cf145
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469553459 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.3469553459
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.3912093803
Short name T739
Test name
Test status
Simulation time 48887934 ps
CPU time 0.81 seconds
Started Aug 18 06:11:36 PM PDT 24
Finished Aug 18 06:11:37 PM PDT 24
Peak memory 218120 kb
Host smart-2a1c6f50-2bb0-4b26-9bc5-4ad6f8844b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912093803 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3912093803
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3910793340
Short name T364
Test name
Test status
Simulation time 355491798 ps
CPU time 1.43 seconds
Started Aug 18 06:11:33 PM PDT 24
Finished Aug 18 06:11:34 PM PDT 24
Peak memory 219408 kb
Host smart-ea668622-6476-4af9-bef1-beb09e148a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910793340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3910793340
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.3297202431
Short name T266
Test name
Test status
Simulation time 28352748 ps
CPU time 1.05 seconds
Started Aug 18 06:11:42 PM PDT 24
Finished Aug 18 06:11:44 PM PDT 24
Peak memory 215476 kb
Host smart-4e51e4f6-9ecf-4aa1-a2d7-5f02fd48ad13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297202431 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3297202431
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.185764678
Short name T59
Test name
Test status
Simulation time 32240458 ps
CPU time 0.96 seconds
Started Aug 18 06:11:36 PM PDT 24
Finished Aug 18 06:11:37 PM PDT 24
Peak memory 215384 kb
Host smart-342940d7-9347-4a03-bce9-71099ccf6525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185764678 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.185764678
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.353426544
Short name T551
Test name
Test status
Simulation time 71259483 ps
CPU time 1.98 seconds
Started Aug 18 06:11:42 PM PDT 24
Finished Aug 18 06:11:45 PM PDT 24
Peak memory 214840 kb
Host smart-20739f71-9260-45d3-9734-23eadf1b1a38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353426544 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.353426544
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3130050656
Short name T244
Test name
Test status
Simulation time 3795183156 ps
CPU time 101.99 seconds
Started Aug 18 06:11:36 PM PDT 24
Finished Aug 18 06:13:18 PM PDT 24
Peak memory 217848 kb
Host smart-2fa92ba9-d731-4913-b075-ede6b97f8ef3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130050656 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3130050656
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.2151409006
Short name T188
Test name
Test status
Simulation time 36665299 ps
CPU time 1.11 seconds
Started Aug 18 06:10:15 PM PDT 24
Finished Aug 18 06:10:17 PM PDT 24
Peak memory 218648 kb
Host smart-b6b122e0-786f-4b0c-8fbe-7fb0bf303334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151409006 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.2151409006
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.4000294448
Short name T535
Test name
Test status
Simulation time 53636932 ps
CPU time 0.9 seconds
Started Aug 18 06:10:17 PM PDT 24
Finished Aug 18 06:10:18 PM PDT 24
Peak memory 206788 kb
Host smart-c32906c2-b90f-4dde-a752-3ef3c2ec0055
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000294448 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.4000294448
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.1544486359
Short name T970
Test name
Test status
Simulation time 35665242 ps
CPU time 1.23 seconds
Started Aug 18 06:10:15 PM PDT 24
Finished Aug 18 06:10:17 PM PDT 24
Peak memory 218672 kb
Host smart-4f28a07e-6731-4573-9755-23cd70bf9d06
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544486359 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.1544486359
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.1651846222
Short name T772
Test name
Test status
Simulation time 31654586 ps
CPU time 0.96 seconds
Started Aug 18 06:10:15 PM PDT 24
Finished Aug 18 06:10:16 PM PDT 24
Peak memory 223972 kb
Host smart-30a89b13-4f8a-4e4f-af06-9093f1cbcccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651846222 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.1651846222
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1163873915
Short name T368
Test name
Test status
Simulation time 373040559 ps
CPU time 3.9 seconds
Started Aug 18 06:10:17 PM PDT 24
Finished Aug 18 06:10:21 PM PDT 24
Peak memory 220580 kb
Host smart-6bdb62e8-5aec-42fa-b7f5-da4d0e5248a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163873915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1163873915
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.1359736076
Short name T268
Test name
Test status
Simulation time 27165475 ps
CPU time 1.01 seconds
Started Aug 18 06:10:17 PM PDT 24
Finished Aug 18 06:10:18 PM PDT 24
Peak memory 224256 kb
Host smart-d79f3dde-1432-4236-8f65-26db7e1db730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359736076 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1359736076
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.691098974
Short name T653
Test name
Test status
Simulation time 34232962 ps
CPU time 0.86 seconds
Started Aug 18 06:10:18 PM PDT 24
Finished Aug 18 06:10:19 PM PDT 24
Peak memory 207152 kb
Host smart-781c958b-b732-4bea-96e3-c7b4f6194ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691098974 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.691098974
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.535096489
Short name T91
Test name
Test status
Simulation time 18756364 ps
CPU time 1.02 seconds
Started Aug 18 06:10:10 PM PDT 24
Finished Aug 18 06:10:11 PM PDT 24
Peak memory 215324 kb
Host smart-b57e7a14-7932-43c1-b66b-99186397809a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535096489 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.535096489
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.3621025655
Short name T693
Test name
Test status
Simulation time 291869864 ps
CPU time 3.33 seconds
Started Aug 18 06:10:18 PM PDT 24
Finished Aug 18 06:10:21 PM PDT 24
Peak memory 220480 kb
Host smart-de6d0895-33ce-4b95-82cd-d48af2965069
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621025655 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.3621025655
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.4073180120
Short name T787
Test name
Test status
Simulation time 5545425489 ps
CPU time 74.06 seconds
Started Aug 18 06:10:19 PM PDT 24
Finished Aug 18 06:11:33 PM PDT 24
Peak memory 221448 kb
Host smart-fcdc6af5-caac-473c-b0c9-a02066a32ef1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073180120 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.4073180120
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.1204442372
Short name T655
Test name
Test status
Simulation time 36662950 ps
CPU time 1.06 seconds
Started Aug 18 06:11:43 PM PDT 24
Finished Aug 18 06:11:44 PM PDT 24
Peak memory 219868 kb
Host smart-08576a9e-7827-4e0c-b488-847141e5eb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204442372 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.1204442372
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.856053323
Short name T56
Test name
Test status
Simulation time 32603237 ps
CPU time 1.08 seconds
Started Aug 18 06:11:42 PM PDT 24
Finished Aug 18 06:11:44 PM PDT 24
Peak memory 224168 kb
Host smart-3085e7c0-6132-479a-a880-718e76e287a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856053323 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.856053323
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.2320932729
Short name T931
Test name
Test status
Simulation time 39880939 ps
CPU time 1.44 seconds
Started Aug 18 06:11:37 PM PDT 24
Finished Aug 18 06:11:38 PM PDT 24
Peak memory 218656 kb
Host smart-1f5b43cf-bf66-4729-b0fb-c3f6e269609f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320932729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2320932729
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.3072137386
Short name T439
Test name
Test status
Simulation time 35959018 ps
CPU time 1.08 seconds
Started Aug 18 06:11:42 PM PDT 24
Finished Aug 18 06:11:44 PM PDT 24
Peak memory 218828 kb
Host smart-2bef9b68-9c1c-4b20-a7ab-1b9e9c19b742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072137386 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.3072137386
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.3845529814
Short name T823
Test name
Test status
Simulation time 20285835 ps
CPU time 1.08 seconds
Started Aug 18 06:11:39 PM PDT 24
Finished Aug 18 06:11:40 PM PDT 24
Peak memory 219548 kb
Host smart-75be4c33-3988-45fe-8394-e9f57b61abd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845529814 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.3845529814
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.3747289992
Short name T361
Test name
Test status
Simulation time 110252260 ps
CPU time 1.41 seconds
Started Aug 18 06:11:41 PM PDT 24
Finished Aug 18 06:11:43 PM PDT 24
Peak memory 219280 kb
Host smart-c7dbc5d2-51ee-4920-9b4b-5d5744e9d52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747289992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.3747289992
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.2341517702
Short name T116
Test name
Test status
Simulation time 354488484 ps
CPU time 1.38 seconds
Started Aug 18 06:11:41 PM PDT 24
Finished Aug 18 06:11:42 PM PDT 24
Peak memory 219804 kb
Host smart-7ceb919d-ef57-4bd9-bb3a-a9ac81b48f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341517702 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.2341517702
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_genbits.1429937932
Short name T440
Test name
Test status
Simulation time 49495681 ps
CPU time 1.19 seconds
Started Aug 18 06:11:45 PM PDT 24
Finished Aug 18 06:11:46 PM PDT 24
Peak memory 218672 kb
Host smart-7fc9d2e8-817f-45e5-844d-5cc482e97b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429937932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1429937932
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.3401350008
Short name T47
Test name
Test status
Simulation time 72931993 ps
CPU time 1.1 seconds
Started Aug 18 06:11:39 PM PDT 24
Finished Aug 18 06:11:41 PM PDT 24
Peak memory 219632 kb
Host smart-2fed93be-88ff-402a-98c6-527e05576090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401350008 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.3401350008
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.371184516
Short name T456
Test name
Test status
Simulation time 40372939 ps
CPU time 1.14 seconds
Started Aug 18 06:11:43 PM PDT 24
Finished Aug 18 06:11:44 PM PDT 24
Peak memory 220776 kb
Host smart-aeb67f00-b1de-482f-be3b-f01317e0ff24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371184516 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.371184516
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.3202517095
Short name T940
Test name
Test status
Simulation time 51648004 ps
CPU time 1.18 seconds
Started Aug 18 06:11:44 PM PDT 24
Finished Aug 18 06:11:45 PM PDT 24
Peak memory 217456 kb
Host smart-9ab54162-5588-49a8-b765-d6088c1fdd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202517095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.3202517095
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.144348674
Short name T729
Test name
Test status
Simulation time 154793271 ps
CPU time 1.17 seconds
Started Aug 18 06:11:42 PM PDT 24
Finished Aug 18 06:11:43 PM PDT 24
Peak memory 218524 kb
Host smart-d4dfa307-0c38-4f82-811d-884ac082f977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144348674 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.144348674
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.2501703507
Short name T671
Test name
Test status
Simulation time 20090695 ps
CPU time 1.06 seconds
Started Aug 18 06:11:41 PM PDT 24
Finished Aug 18 06:11:43 PM PDT 24
Peak memory 218628 kb
Host smart-17c6b183-444d-4036-ae83-d61b531f11de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501703507 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2501703507
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.4150964778
Short name T851
Test name
Test status
Simulation time 48082605 ps
CPU time 1.21 seconds
Started Aug 18 06:11:41 PM PDT 24
Finished Aug 18 06:11:42 PM PDT 24
Peak memory 218672 kb
Host smart-ac12f465-ad71-44f4-9141-e3b02b59d829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150964778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.4150964778
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.398074878
Short name T155
Test name
Test status
Simulation time 267453399 ps
CPU time 1.27 seconds
Started Aug 18 06:11:40 PM PDT 24
Finished Aug 18 06:11:41 PM PDT 24
Peak memory 215704 kb
Host smart-0320097b-e8f0-48dd-bd4a-101905a009c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398074878 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.398074878
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.4122666833
Short name T654
Test name
Test status
Simulation time 26503125 ps
CPU time 1.17 seconds
Started Aug 18 06:11:40 PM PDT 24
Finished Aug 18 06:11:41 PM PDT 24
Peak memory 220588 kb
Host smart-1a73178f-7afb-4a12-a9a7-7da83008b8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122666833 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.4122666833
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.3335817533
Short name T972
Test name
Test status
Simulation time 80583215 ps
CPU time 2.65 seconds
Started Aug 18 06:11:40 PM PDT 24
Finished Aug 18 06:11:43 PM PDT 24
Peak memory 218628 kb
Host smart-85df656f-3d74-4beb-9b1a-465ecc247323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335817533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3335817533
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.3686349199
Short name T102
Test name
Test status
Simulation time 37096596 ps
CPU time 1.15 seconds
Started Aug 18 06:11:40 PM PDT 24
Finished Aug 18 06:11:41 PM PDT 24
Peak memory 218796 kb
Host smart-4fa43736-a5af-41f4-a0ee-bef3245d842d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686349199 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.3686349199
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.2820433086
Short name T233
Test name
Test status
Simulation time 68908330 ps
CPU time 1.36 seconds
Started Aug 18 06:11:41 PM PDT 24
Finished Aug 18 06:11:42 PM PDT 24
Peak memory 219812 kb
Host smart-97252439-708a-4b2b-a712-78bd12d24565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820433086 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.2820433086
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.2194461314
Short name T41
Test name
Test status
Simulation time 73364255 ps
CPU time 1.2 seconds
Started Aug 18 06:11:42 PM PDT 24
Finished Aug 18 06:11:43 PM PDT 24
Peak memory 217304 kb
Host smart-57db4706-5924-4554-be66-ff2b0043b512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194461314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2194461314
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.702174831
Short name T956
Test name
Test status
Simulation time 86653852 ps
CPU time 1.3 seconds
Started Aug 18 06:11:38 PM PDT 24
Finished Aug 18 06:11:39 PM PDT 24
Peak memory 218588 kb
Host smart-76bcaf35-d35c-4295-9c1f-b185cdf64ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702174831 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.702174831
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.4020409637
Short name T200
Test name
Test status
Simulation time 25627011 ps
CPU time 0.93 seconds
Started Aug 18 06:11:41 PM PDT 24
Finished Aug 18 06:11:42 PM PDT 24
Peak memory 218496 kb
Host smart-18fc6a40-d252-4520-b308-5f64b0d52cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020409637 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.4020409637
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.1297458208
Short name T464
Test name
Test status
Simulation time 50484360 ps
CPU time 1.2 seconds
Started Aug 18 06:11:41 PM PDT 24
Finished Aug 18 06:11:43 PM PDT 24
Peak memory 220428 kb
Host smart-96504b57-2efb-41ee-97d1-72b04e071669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297458208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.1297458208
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.3347666141
Short name T785
Test name
Test status
Simulation time 89998374 ps
CPU time 1.21 seconds
Started Aug 18 06:11:43 PM PDT 24
Finished Aug 18 06:11:44 PM PDT 24
Peak memory 220848 kb
Host smart-33ab334f-5b66-4e14-9771-391b27ae94c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347666141 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.3347666141
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.574048730
Short name T897
Test name
Test status
Simulation time 27083935 ps
CPU time 1.14 seconds
Started Aug 18 06:11:40 PM PDT 24
Finished Aug 18 06:11:41 PM PDT 24
Peak memory 218688 kb
Host smart-7914db89-fd3d-4165-b639-897b07078204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574048730 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.574048730
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.3201668905
Short name T573
Test name
Test status
Simulation time 71402540 ps
CPU time 1.31 seconds
Started Aug 18 06:11:41 PM PDT 24
Finished Aug 18 06:11:42 PM PDT 24
Peak memory 218788 kb
Host smart-c104a713-f2de-4c4f-8034-0e1c60441f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201668905 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.3201668905
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.1731279904
Short name T208
Test name
Test status
Simulation time 87004967 ps
CPU time 1.2 seconds
Started Aug 18 06:11:39 PM PDT 24
Finished Aug 18 06:11:41 PM PDT 24
Peak memory 220824 kb
Host smart-5c231d88-b5e4-46d7-9239-37d8d2b90d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731279904 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.1731279904
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.2081583664
Short name T742
Test name
Test status
Simulation time 25184844 ps
CPU time 1.17 seconds
Started Aug 18 06:11:41 PM PDT 24
Finished Aug 18 06:11:43 PM PDT 24
Peak memory 224136 kb
Host smart-ad1dc5c9-5b06-4efe-851d-4a6fee226778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081583664 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.2081583664
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.1152641750
Short name T449
Test name
Test status
Simulation time 30990738 ps
CPU time 1.06 seconds
Started Aug 18 06:11:40 PM PDT 24
Finished Aug 18 06:11:41 PM PDT 24
Peak memory 217412 kb
Host smart-c795b952-39bd-44d4-9405-5d4c67788e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152641750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.1152641750
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.825145504
Short name T234
Test name
Test status
Simulation time 216685526 ps
CPU time 1.21 seconds
Started Aug 18 06:10:17 PM PDT 24
Finished Aug 18 06:10:19 PM PDT 24
Peak memory 215756 kb
Host smart-66f513db-5007-41c5-b80c-6d241fcf03ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825145504 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.825145504
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.1312423345
Short name T592
Test name
Test status
Simulation time 30607355 ps
CPU time 0.88 seconds
Started Aug 18 06:10:16 PM PDT 24
Finished Aug 18 06:10:17 PM PDT 24
Peak memory 206852 kb
Host smart-3969547d-e379-44bb-8646-51d65ffb434e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312423345 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.1312423345
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.4287028427
Short name T191
Test name
Test status
Simulation time 16752183 ps
CPU time 0.83 seconds
Started Aug 18 06:10:16 PM PDT 24
Finished Aug 18 06:10:17 PM PDT 24
Peak memory 215348 kb
Host smart-c109e386-b5d2-4779-ae24-c72b47a2bc02
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287028427 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.4287028427
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_err.4265548949
Short name T934
Test name
Test status
Simulation time 20498451 ps
CPU time 1.2 seconds
Started Aug 18 06:10:17 PM PDT 24
Finished Aug 18 06:10:18 PM PDT 24
Peak memory 224076 kb
Host smart-57b81591-5c11-4435-8ff6-9ee8c65be8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265548949 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.4265548949
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.2359549821
Short name T859
Test name
Test status
Simulation time 49226768 ps
CPU time 1.33 seconds
Started Aug 18 06:10:17 PM PDT 24
Finished Aug 18 06:10:19 PM PDT 24
Peak memory 218692 kb
Host smart-6de3866d-f392-41c2-902a-9150dc3f5caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359549821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.2359549821
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.3010797927
Short name T104
Test name
Test status
Simulation time 19972171 ps
CPU time 1.05 seconds
Started Aug 18 06:10:20 PM PDT 24
Finished Aug 18 06:10:21 PM PDT 24
Peak memory 215884 kb
Host smart-0a2a87dc-fe7a-4998-9fd9-5f2eb3bb9ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010797927 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.3010797927
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.3343681541
Short name T335
Test name
Test status
Simulation time 15798031 ps
CPU time 1 seconds
Started Aug 18 06:10:20 PM PDT 24
Finished Aug 18 06:10:21 PM PDT 24
Peak memory 207156 kb
Host smart-3782904a-b973-425d-9e15-1a550fcab527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343681541 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.3343681541
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.4005387912
Short name T640
Test name
Test status
Simulation time 143760049 ps
CPU time 0.85 seconds
Started Aug 18 06:10:17 PM PDT 24
Finished Aug 18 06:10:17 PM PDT 24
Peak memory 215208 kb
Host smart-fbdb2e3f-866f-462d-a54b-63448535146f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005387912 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.4005387912
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.1613956701
Short name T792
Test name
Test status
Simulation time 267650377 ps
CPU time 5.35 seconds
Started Aug 18 06:10:21 PM PDT 24
Finished Aug 18 06:10:26 PM PDT 24
Peak memory 219904 kb
Host smart-4f22775f-d881-4219-a384-f87a77904812
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613956701 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.1613956701
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.3287326563
Short name T791
Test name
Test status
Simulation time 11002418430 ps
CPU time 45.68 seconds
Started Aug 18 06:10:17 PM PDT 24
Finished Aug 18 06:11:03 PM PDT 24
Peak memory 221392 kb
Host smart-799ac9c4-af3a-4f6e-bfdd-f554796f0bf2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287326563 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.3287326563
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.1461576703
Short name T474
Test name
Test status
Simulation time 73028054 ps
CPU time 1.12 seconds
Started Aug 18 06:11:42 PM PDT 24
Finished Aug 18 06:11:43 PM PDT 24
Peak memory 218636 kb
Host smart-74122485-2641-440f-8db8-cd265d13f734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461576703 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.1461576703
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.1589261484
Short name T112
Test name
Test status
Simulation time 19163459 ps
CPU time 1.06 seconds
Started Aug 18 06:11:43 PM PDT 24
Finished Aug 18 06:11:44 PM PDT 24
Peak memory 218540 kb
Host smart-2890f0bb-4cd0-4c2c-800d-9d56467f9555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589261484 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1589261484
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.2344793103
Short name T863
Test name
Test status
Simulation time 50636764 ps
CPU time 1.29 seconds
Started Aug 18 06:11:42 PM PDT 24
Finished Aug 18 06:11:44 PM PDT 24
Peak memory 218612 kb
Host smart-cfc44fa7-8464-442e-9b57-52e915058c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344793103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.2344793103
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.1591627592
Short name T618
Test name
Test status
Simulation time 33523853 ps
CPU time 1.16 seconds
Started Aug 18 06:11:41 PM PDT 24
Finished Aug 18 06:11:43 PM PDT 24
Peak memory 219164 kb
Host smart-4e35f06e-0c49-48d2-9b71-7d7fe1fdbd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591627592 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.1591627592
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.299237988
Short name T602
Test name
Test status
Simulation time 19355208 ps
CPU time 1.15 seconds
Started Aug 18 06:11:42 PM PDT 24
Finished Aug 18 06:11:43 PM PDT 24
Peak memory 224128 kb
Host smart-f7c01170-b33f-4f32-90cf-bd98dcc4a200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299237988 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.299237988
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.4289646367
Short name T533
Test name
Test status
Simulation time 53475004 ps
CPU time 1.09 seconds
Started Aug 18 06:11:42 PM PDT 24
Finished Aug 18 06:11:43 PM PDT 24
Peak memory 217296 kb
Host smart-28395e1a-6449-441c-8564-0c8150fd520c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289646367 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.4289646367
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.3198246487
Short name T416
Test name
Test status
Simulation time 91679933 ps
CPU time 1.24 seconds
Started Aug 18 06:11:41 PM PDT 24
Finished Aug 18 06:11:42 PM PDT 24
Peak memory 219756 kb
Host smart-92bc78c0-ab51-4af3-a028-6693044bf372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198246487 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.3198246487
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.603353983
Short name T224
Test name
Test status
Simulation time 28011191 ps
CPU time 1.26 seconds
Started Aug 18 06:11:41 PM PDT 24
Finished Aug 18 06:11:42 PM PDT 24
Peak memory 219760 kb
Host smart-ea92db86-133e-40f6-8203-054abde90934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603353983 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.603353983
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.2723223771
Short name T700
Test name
Test status
Simulation time 78982307 ps
CPU time 2.62 seconds
Started Aug 18 06:11:41 PM PDT 24
Finished Aug 18 06:11:43 PM PDT 24
Peak memory 219660 kb
Host smart-b1000a5a-a2a3-40d9-a442-cf3ff467edb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723223771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2723223771
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.2976754027
Short name T584
Test name
Test status
Simulation time 25699396 ps
CPU time 1.21 seconds
Started Aug 18 06:11:44 PM PDT 24
Finished Aug 18 06:11:45 PM PDT 24
Peak memory 215900 kb
Host smart-8a12e9d7-74a7-4968-a35a-2955b99d2817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976754027 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.2976754027
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.3260246971
Short name T802
Test name
Test status
Simulation time 54173374 ps
CPU time 0.95 seconds
Started Aug 18 06:11:40 PM PDT 24
Finished Aug 18 06:11:41 PM PDT 24
Peak memory 223944 kb
Host smart-55daad9e-3c01-4caf-a9ba-f2692b1907de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260246971 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.3260246971
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.2599049636
Short name T953
Test name
Test status
Simulation time 63042820 ps
CPU time 1.32 seconds
Started Aug 18 06:11:43 PM PDT 24
Finished Aug 18 06:11:44 PM PDT 24
Peak memory 217540 kb
Host smart-79e9c801-a221-47ec-81f9-35b2f89c9e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599049636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2599049636
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.1854337111
Short name T900
Test name
Test status
Simulation time 29406695 ps
CPU time 1.27 seconds
Started Aug 18 06:11:50 PM PDT 24
Finished Aug 18 06:11:51 PM PDT 24
Peak memory 215924 kb
Host smart-add4bc7d-eaf4-4390-b23d-920104010fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854337111 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.1854337111
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.191988245
Short name T170
Test name
Test status
Simulation time 62843566 ps
CPU time 1.01 seconds
Started Aug 18 06:11:49 PM PDT 24
Finished Aug 18 06:11:50 PM PDT 24
Peak memory 220808 kb
Host smart-7a20166d-9d4e-4dae-abbe-071e67ce0426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191988245 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.191988245
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.390873122
Short name T441
Test name
Test status
Simulation time 96715896 ps
CPU time 1.28 seconds
Started Aug 18 06:11:50 PM PDT 24
Finished Aug 18 06:11:51 PM PDT 24
Peak memory 220188 kb
Host smart-76e70905-9976-4607-91fa-adf9300d288f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390873122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.390873122
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.2039248598
Short name T893
Test name
Test status
Simulation time 23475698 ps
CPU time 1.17 seconds
Started Aug 18 06:11:50 PM PDT 24
Finished Aug 18 06:11:51 PM PDT 24
Peak memory 220556 kb
Host smart-4c64446e-4638-453e-b1d4-80974bf421ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039248598 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.2039248598
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_genbits.3115206682
Short name T365
Test name
Test status
Simulation time 93396044 ps
CPU time 2.04 seconds
Started Aug 18 06:11:50 PM PDT 24
Finished Aug 18 06:11:52 PM PDT 24
Peak memory 218732 kb
Host smart-548e7fa1-7231-4cb7-8af1-42a6c9e733db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115206682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3115206682
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.2160404252
Short name T236
Test name
Test status
Simulation time 23661114 ps
CPU time 1.24 seconds
Started Aug 18 06:11:52 PM PDT 24
Finished Aug 18 06:11:53 PM PDT 24
Peak memory 218832 kb
Host smart-68be9e3e-50ee-4f51-8d92-668bd1251763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160404252 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.2160404252
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_genbits.2353809961
Short name T509
Test name
Test status
Simulation time 50857825 ps
CPU time 1.25 seconds
Started Aug 18 06:11:49 PM PDT 24
Finished Aug 18 06:11:51 PM PDT 24
Peak memory 218704 kb
Host smart-3528e668-00b1-4e30-a3e3-3a6729f7581c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353809961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.2353809961
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.1883473535
Short name T716
Test name
Test status
Simulation time 158797273 ps
CPU time 1.19 seconds
Started Aug 18 06:11:50 PM PDT 24
Finished Aug 18 06:11:51 PM PDT 24
Peak memory 218544 kb
Host smart-76ef718e-3d1d-445a-b005-484ac662f671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883473535 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.1883473535
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.1317190127
Short name T797
Test name
Test status
Simulation time 25400871 ps
CPU time 1.03 seconds
Started Aug 18 06:11:53 PM PDT 24
Finished Aug 18 06:11:54 PM PDT 24
Peak memory 219872 kb
Host smart-c2692adf-bcad-4471-b833-68912ec950e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317190127 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1317190127
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.2446548323
Short name T387
Test name
Test status
Simulation time 657430194 ps
CPU time 4.37 seconds
Started Aug 18 06:11:48 PM PDT 24
Finished Aug 18 06:11:53 PM PDT 24
Peak memory 220828 kb
Host smart-b4468602-72d0-4cce-a3e7-0a2240da6647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446548323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.2446548323
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.2786007129
Short name T87
Test name
Test status
Simulation time 28016213 ps
CPU time 1.13 seconds
Started Aug 18 06:11:50 PM PDT 24
Finished Aug 18 06:11:52 PM PDT 24
Peak memory 221052 kb
Host smart-700821e2-7165-4c2b-9062-35c2b3229878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786007129 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.2786007129
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.4089853419
Short name T78
Test name
Test status
Simulation time 27937848 ps
CPU time 0.9 seconds
Started Aug 18 06:11:48 PM PDT 24
Finished Aug 18 06:11:49 PM PDT 24
Peak memory 218244 kb
Host smart-7b747355-1e5b-4ec6-85ac-b7f713b1edae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089853419 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.4089853419
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.2978528036
Short name T590
Test name
Test status
Simulation time 103296132 ps
CPU time 1.23 seconds
Started Aug 18 06:11:51 PM PDT 24
Finished Aug 18 06:11:53 PM PDT 24
Peak memory 217424 kb
Host smart-de542c40-509e-478d-bb16-1e3ee15cecb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978528036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2978528036
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.2125724665
Short name T433
Test name
Test status
Simulation time 87936684 ps
CPU time 1.17 seconds
Started Aug 18 06:11:48 PM PDT 24
Finished Aug 18 06:11:49 PM PDT 24
Peak memory 221920 kb
Host smart-bd891ef3-4b3c-4d0a-b138-6feb6fd81794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125724665 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.2125724665
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.1435896096
Short name T53
Test name
Test status
Simulation time 30353963 ps
CPU time 1.35 seconds
Started Aug 18 06:11:50 PM PDT 24
Finished Aug 18 06:11:51 PM PDT 24
Peak memory 225800 kb
Host smart-efe7e586-6680-4239-bd79-f65078ae8b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435896096 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.1435896096
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.2545821616
Short name T793
Test name
Test status
Simulation time 214590569 ps
CPU time 1.52 seconds
Started Aug 18 06:11:49 PM PDT 24
Finished Aug 18 06:11:50 PM PDT 24
Peak memory 219264 kb
Host smart-41012cb7-764e-409d-bed8-00c8ce487448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545821616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.2545821616
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.1533152409
Short name T917
Test name
Test status
Simulation time 180558162 ps
CPU time 1.2 seconds
Started Aug 18 06:10:20 PM PDT 24
Finished Aug 18 06:10:22 PM PDT 24
Peak memory 219724 kb
Host smart-62d14287-a2af-47c7-8c75-606c8791d4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533152409 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1533152409
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.3409423469
Short name T875
Test name
Test status
Simulation time 80539883 ps
CPU time 0.97 seconds
Started Aug 18 06:10:24 PM PDT 24
Finished Aug 18 06:10:25 PM PDT 24
Peak memory 206792 kb
Host smart-71bcb29a-3b00-4344-b14e-8859a97e8d76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409423469 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3409423469
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.2755682742
Short name T911
Test name
Test status
Simulation time 12830532 ps
CPU time 0.94 seconds
Started Aug 18 06:10:27 PM PDT 24
Finished Aug 18 06:10:28 PM PDT 24
Peak memory 215740 kb
Host smart-eba4d020-11ca-4809-b11a-b586ae293742
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755682742 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.2755682742
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.657552398
Short name T401
Test name
Test status
Simulation time 64992587 ps
CPU time 0.99 seconds
Started Aug 18 06:10:22 PM PDT 24
Finished Aug 18 06:10:23 PM PDT 24
Peak memory 216832 kb
Host smart-604a0cab-04b3-412f-8918-e843238d2160
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657552398 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_dis
able_auto_req_mode.657552398
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.596302379
Short name T798
Test name
Test status
Simulation time 71193386 ps
CPU time 0.88 seconds
Started Aug 18 06:10:22 PM PDT 24
Finished Aug 18 06:10:23 PM PDT 24
Peak memory 218588 kb
Host smart-bff78357-7ef0-42da-bbb7-2132323c78e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596302379 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.596302379
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.57102293
Short name T450
Test name
Test status
Simulation time 91126204 ps
CPU time 1.52 seconds
Started Aug 18 06:10:18 PM PDT 24
Finished Aug 18 06:10:20 PM PDT 24
Peak memory 219052 kb
Host smart-380247a8-1fda-4e9e-a389-676351c6b0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57102293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.57102293
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.161054738
Short name T545
Test name
Test status
Simulation time 52319312 ps
CPU time 0.78 seconds
Started Aug 18 06:10:20 PM PDT 24
Finished Aug 18 06:10:21 PM PDT 24
Peak memory 215496 kb
Host smart-4e6172b9-d3e5-4b87-9125-1bf8fce60b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161054738 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.161054738
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.667922086
Short name T756
Test name
Test status
Simulation time 33403822 ps
CPU time 0.99 seconds
Started Aug 18 06:10:19 PM PDT 24
Finished Aug 18 06:10:20 PM PDT 24
Peak memory 207140 kb
Host smart-842fe00b-0da1-494c-b4ca-a58fad13b76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667922086 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.667922086
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.4232997340
Short name T845
Test name
Test status
Simulation time 26179162 ps
CPU time 0.94 seconds
Started Aug 18 06:10:18 PM PDT 24
Finished Aug 18 06:10:19 PM PDT 24
Peak memory 215328 kb
Host smart-3dda0514-0927-4506-9045-8ce1fb9ee7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232997340 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.4232997340
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1076894849
Short name T279
Test name
Test status
Simulation time 579495603 ps
CPU time 3.39 seconds
Started Aug 18 06:10:17 PM PDT 24
Finished Aug 18 06:10:20 PM PDT 24
Peak memory 217296 kb
Host smart-15505c28-f5c4-431c-94c1-81e290714876
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076894849 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1076894849
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/70.edn_alert.2847086160
Short name T36
Test name
Test status
Simulation time 273696000 ps
CPU time 1.29 seconds
Started Aug 18 06:11:52 PM PDT 24
Finished Aug 18 06:11:54 PM PDT 24
Peak memory 218644 kb
Host smart-24a04624-6e5b-4f18-85dd-33f48e95577b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847086160 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.2847086160
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.2784904444
Short name T7
Test name
Test status
Simulation time 25145505 ps
CPU time 1.05 seconds
Started Aug 18 06:11:50 PM PDT 24
Finished Aug 18 06:11:51 PM PDT 24
Peak memory 219904 kb
Host smart-73659167-7be1-407b-84d4-f5fa632b68d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784904444 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2784904444
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.614272610
Short name T360
Test name
Test status
Simulation time 61283058 ps
CPU time 1.09 seconds
Started Aug 18 06:11:52 PM PDT 24
Finished Aug 18 06:11:53 PM PDT 24
Peak memory 217240 kb
Host smart-2855f663-8c5e-483a-8bf3-65d584ebeb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614272610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.614272610
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.3215309608
Short name T76
Test name
Test status
Simulation time 72170304 ps
CPU time 1.14 seconds
Started Aug 18 06:11:53 PM PDT 24
Finished Aug 18 06:11:55 PM PDT 24
Peak memory 219624 kb
Host smart-1cc3748c-77ee-4db5-a23d-14138c0f1522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215309608 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.3215309608
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.2454886901
Short name T806
Test name
Test status
Simulation time 75961025 ps
CPU time 1.06 seconds
Started Aug 18 06:11:50 PM PDT 24
Finished Aug 18 06:11:51 PM PDT 24
Peak memory 215500 kb
Host smart-1ab54f8f-40a8-4437-b1ac-de39b2df47ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454886901 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2454886901
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.2316601662
Short name T270
Test name
Test status
Simulation time 77494742 ps
CPU time 1.11 seconds
Started Aug 18 06:11:51 PM PDT 24
Finished Aug 18 06:11:53 PM PDT 24
Peak memory 217368 kb
Host smart-2b45adbe-77d3-4ecb-a16e-fd94724f58f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316601662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.2316601662
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.1483956272
Short name T165
Test name
Test status
Simulation time 90195809 ps
CPU time 1.17 seconds
Started Aug 18 06:11:52 PM PDT 24
Finished Aug 18 06:11:54 PM PDT 24
Peak memory 220752 kb
Host smart-a3d43ddb-fe68-43aa-992a-b7383de5d164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483956272 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.1483956272
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.1772104139
Short name T184
Test name
Test status
Simulation time 23451850 ps
CPU time 0.96 seconds
Started Aug 18 06:11:51 PM PDT 24
Finished Aug 18 06:11:52 PM PDT 24
Peak memory 218404 kb
Host smart-8b3acfbe-f6bc-4452-aa4f-12bbaf99c395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772104139 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.1772104139
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.2084708962
Short name T532
Test name
Test status
Simulation time 46732568 ps
CPU time 1.63 seconds
Started Aug 18 06:11:52 PM PDT 24
Finished Aug 18 06:11:54 PM PDT 24
Peak memory 218624 kb
Host smart-9145252e-f97e-49e6-ac30-5cf66ffcc30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084708962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2084708962
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.580909400
Short name T707
Test name
Test status
Simulation time 28796788 ps
CPU time 1.38 seconds
Started Aug 18 06:11:50 PM PDT 24
Finished Aug 18 06:11:51 PM PDT 24
Peak memory 218756 kb
Host smart-cb60d701-89a3-41b7-a62a-4ab179898869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580909400 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.580909400
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.3496426410
Short name T51
Test name
Test status
Simulation time 27574923 ps
CPU time 0.97 seconds
Started Aug 18 06:11:51 PM PDT 24
Finished Aug 18 06:11:53 PM PDT 24
Peak memory 223952 kb
Host smart-ccda25a0-0f44-4eed-adc6-c21839be191e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496426410 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.3496426410
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.3651198407
Short name T412
Test name
Test status
Simulation time 106044711 ps
CPU time 1.59 seconds
Started Aug 18 06:11:50 PM PDT 24
Finished Aug 18 06:11:52 PM PDT 24
Peak memory 219108 kb
Host smart-a639b8c5-f488-495a-bf7e-57ca9e247954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651198407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.3651198407
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.2289474561
Short name T286
Test name
Test status
Simulation time 95020265 ps
CPU time 1.21 seconds
Started Aug 18 06:11:54 PM PDT 24
Finished Aug 18 06:11:55 PM PDT 24
Peak memory 215900 kb
Host smart-2587240f-0f80-404a-b781-f75874572057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289474561 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.2289474561
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.1436422156
Short name T758
Test name
Test status
Simulation time 27272096 ps
CPU time 1.04 seconds
Started Aug 18 06:11:51 PM PDT 24
Finished Aug 18 06:11:52 PM PDT 24
Peak memory 224176 kb
Host smart-ca87a3a6-2822-44c5-9646-b803a2a0239e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436422156 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.1436422156
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.2274045164
Short name T502
Test name
Test status
Simulation time 30029533 ps
CPU time 1.36 seconds
Started Aug 18 06:11:52 PM PDT 24
Finished Aug 18 06:11:54 PM PDT 24
Peak memory 218792 kb
Host smart-5447bcaf-b45c-40e3-84ce-2a811d1ac5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274045164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2274045164
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.4262874624
Short name T460
Test name
Test status
Simulation time 46372381 ps
CPU time 1.11 seconds
Started Aug 18 06:11:49 PM PDT 24
Finished Aug 18 06:11:50 PM PDT 24
Peak memory 220232 kb
Host smart-4a50521a-1240-4c17-bf3b-8d21580d4ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262874624 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.4262874624
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.4152346639
Short name T159
Test name
Test status
Simulation time 43120349 ps
CPU time 1.22 seconds
Started Aug 18 06:11:58 PM PDT 24
Finished Aug 18 06:11:59 PM PDT 24
Peak memory 229380 kb
Host smart-8c671549-e3ef-4763-9183-ebffdb4fb75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152346639 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.4152346639
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.106566167
Short name T912
Test name
Test status
Simulation time 241980015 ps
CPU time 2.72 seconds
Started Aug 18 06:11:53 PM PDT 24
Finished Aug 18 06:11:56 PM PDT 24
Peak memory 220648 kb
Host smart-7debf6b8-d053-4a2e-94e6-cdea1b752110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106566167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.106566167
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.564317213
Short name T329
Test name
Test status
Simulation time 344742813 ps
CPU time 1.3 seconds
Started Aug 18 06:11:52 PM PDT 24
Finished Aug 18 06:11:53 PM PDT 24
Peak memory 219652 kb
Host smart-d7989173-fbc3-4828-99c0-e6845b37a2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564317213 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.564317213
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.3919840888
Short name T1
Test name
Test status
Simulation time 18663223 ps
CPU time 1.15 seconds
Started Aug 18 06:11:54 PM PDT 24
Finished Aug 18 06:11:55 PM PDT 24
Peak memory 224280 kb
Host smart-38250174-c7b3-40ec-9979-d04ac5e74a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919840888 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.3919840888
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.2085668275
Short name T918
Test name
Test status
Simulation time 131967849 ps
CPU time 1.32 seconds
Started Aug 18 06:11:52 PM PDT 24
Finished Aug 18 06:11:54 PM PDT 24
Peak memory 219576 kb
Host smart-15ed37cb-ff78-49b2-a9c1-e4fa3e328349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085668275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2085668275
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.120335361
Short name T648
Test name
Test status
Simulation time 220560721 ps
CPU time 1.34 seconds
Started Aug 18 06:11:52 PM PDT 24
Finished Aug 18 06:11:53 PM PDT 24
Peak memory 219712 kb
Host smart-15797154-626f-4ca5-99c9-db8fd0d68a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120335361 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.120335361
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.4112784189
Short name T118
Test name
Test status
Simulation time 25835919 ps
CPU time 0.94 seconds
Started Aug 18 06:11:49 PM PDT 24
Finished Aug 18 06:11:50 PM PDT 24
Peak memory 218528 kb
Host smart-7f043334-5453-4274-bfa3-a20d6efad51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112784189 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.4112784189
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.2814317522
Short name T67
Test name
Test status
Simulation time 92347522 ps
CPU time 1.48 seconds
Started Aug 18 06:11:50 PM PDT 24
Finished Aug 18 06:11:52 PM PDT 24
Peak memory 218800 kb
Host smart-657f2c92-8603-43e9-80ed-89ba1aaccc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814317522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.2814317522
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.1552613392
Short name T381
Test name
Test status
Simulation time 23502889 ps
CPU time 1.14 seconds
Started Aug 18 06:11:51 PM PDT 24
Finished Aug 18 06:11:52 PM PDT 24
Peak memory 219612 kb
Host smart-140282e7-ebc2-475f-8ede-57631041f62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552613392 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.1552613392
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.1489074997
Short name T795
Test name
Test status
Simulation time 19605893 ps
CPU time 1.11 seconds
Started Aug 18 06:11:51 PM PDT 24
Finished Aug 18 06:11:52 PM PDT 24
Peak memory 218668 kb
Host smart-a619a014-5611-4218-9068-2cd2df2e347c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489074997 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.1489074997
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.1571233765
Short name T347
Test name
Test status
Simulation time 50257298 ps
CPU time 1.77 seconds
Started Aug 18 06:11:58 PM PDT 24
Finished Aug 18 06:12:00 PM PDT 24
Peak memory 218480 kb
Host smart-16daed0f-6ae3-4103-8212-76393577becf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571233765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.1571233765
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.3942231289
Short name T451
Test name
Test status
Simulation time 53246811 ps
CPU time 1.29 seconds
Started Aug 18 06:11:50 PM PDT 24
Finished Aug 18 06:11:52 PM PDT 24
Peak memory 218620 kb
Host smart-4a49a085-fbc6-47c2-b203-e43d67718a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942231289 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.3942231289
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.4018676064
Short name T462
Test name
Test status
Simulation time 58927852 ps
CPU time 1.16 seconds
Started Aug 18 06:11:51 PM PDT 24
Finished Aug 18 06:11:53 PM PDT 24
Peak memory 224176 kb
Host smart-8a28045e-0201-4f2e-9e29-813abbdb14ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018676064 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.4018676064
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.1588718968
Short name T352
Test name
Test status
Simulation time 55675805 ps
CPU time 2.36 seconds
Started Aug 18 06:11:50 PM PDT 24
Finished Aug 18 06:11:52 PM PDT 24
Peak memory 218716 kb
Host smart-c1b4127e-e46e-4fbc-b72d-7dadfc9b40a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588718968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.1588718968
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.2276071140
Short name T771
Test name
Test status
Simulation time 118093109 ps
CPU time 1.22 seconds
Started Aug 18 06:10:25 PM PDT 24
Finished Aug 18 06:10:27 PM PDT 24
Peak memory 219904 kb
Host smart-83ac4764-3f5c-4161-8bdd-19b88cf1b48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276071140 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2276071140
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.788479354
Short name T631
Test name
Test status
Simulation time 29083263 ps
CPU time 0.89 seconds
Started Aug 18 06:10:24 PM PDT 24
Finished Aug 18 06:10:25 PM PDT 24
Peak memory 214956 kb
Host smart-ef67e4c5-613f-4430-b014-7004ff04d974
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788479354 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.788479354
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.3194989540
Short name T741
Test name
Test status
Simulation time 42253317 ps
CPU time 0.81 seconds
Started Aug 18 06:10:26 PM PDT 24
Finished Aug 18 06:10:27 PM PDT 24
Peak memory 215196 kb
Host smart-fec177f9-3b56-4b09-aa3f-3a5e4cf99055
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194989540 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3194989540
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.3645997192
Short name T223
Test name
Test status
Simulation time 49813524 ps
CPU time 1.56 seconds
Started Aug 18 06:10:24 PM PDT 24
Finished Aug 18 06:10:25 PM PDT 24
Peak memory 218192 kb
Host smart-7b410db6-ea13-4826-a6b7-60688f9278bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645997192 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.3645997192
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3389057388
Short name T817
Test name
Test status
Simulation time 21704486 ps
CPU time 1.05 seconds
Started Aug 18 06:10:25 PM PDT 24
Finished Aug 18 06:10:26 PM PDT 24
Peak memory 219584 kb
Host smart-f5710f59-2193-4641-bc7d-00d9e874bf3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389057388 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3389057388
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.1547491243
Short name T445
Test name
Test status
Simulation time 73263099 ps
CPU time 1.09 seconds
Started Aug 18 06:10:23 PM PDT 24
Finished Aug 18 06:10:24 PM PDT 24
Peak memory 217460 kb
Host smart-f1140e8f-2115-4604-ba17-b3c513aa92fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547491243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1547491243
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.3225572146
Short name T891
Test name
Test status
Simulation time 24805517 ps
CPU time 0.99 seconds
Started Aug 18 06:10:25 PM PDT 24
Finished Aug 18 06:10:26 PM PDT 24
Peak memory 215496 kb
Host smart-4b1656cf-f972-4005-abd5-d1c7543f0171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225572146 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3225572146
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.4037641239
Short name T950
Test name
Test status
Simulation time 123694539 ps
CPU time 0.96 seconds
Started Aug 18 06:10:24 PM PDT 24
Finished Aug 18 06:10:25 PM PDT 24
Peak memory 207220 kb
Host smart-4171a5d8-215e-4364-952d-5e056b993f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037641239 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.4037641239
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.264011232
Short name T369
Test name
Test status
Simulation time 18197857 ps
CPU time 1.05 seconds
Started Aug 18 06:10:24 PM PDT 24
Finished Aug 18 06:10:26 PM PDT 24
Peak memory 215476 kb
Host smart-569283f3-7a87-4049-aa8f-b2c851a2dfe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264011232 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.264011232
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.747977238
Short name T600
Test name
Test status
Simulation time 172804867 ps
CPU time 1.96 seconds
Started Aug 18 06:10:26 PM PDT 24
Finished Aug 18 06:10:28 PM PDT 24
Peak memory 218856 kb
Host smart-e0b82e58-6e4d-4996-9196-5e5a94e9f0f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747977238 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.747977238
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.788480160
Short name T250
Test name
Test status
Simulation time 21777198138 ps
CPU time 140.92 seconds
Started Aug 18 06:10:24 PM PDT 24
Finished Aug 18 06:12:45 PM PDT 24
Peak memory 219044 kb
Host smart-41256187-384b-4c34-a10f-1f349520f755
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788480160 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.788480160
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.1090317134
Short name T748
Test name
Test status
Simulation time 24044171 ps
CPU time 1.2 seconds
Started Aug 18 06:12:01 PM PDT 24
Finished Aug 18 06:12:02 PM PDT 24
Peak memory 219816 kb
Host smart-632d7416-4313-4f24-905b-ac170ae7e6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090317134 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.1090317134
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.3862867316
Short name T872
Test name
Test status
Simulation time 56524252 ps
CPU time 0.98 seconds
Started Aug 18 06:11:57 PM PDT 24
Finished Aug 18 06:11:58 PM PDT 24
Peak memory 218700 kb
Host smart-364c1a27-3a10-4e9f-8867-1ae4756e750a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862867316 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3862867316
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.644914436
Short name T554
Test name
Test status
Simulation time 36794874 ps
CPU time 1.48 seconds
Started Aug 18 06:11:57 PM PDT 24
Finished Aug 18 06:11:59 PM PDT 24
Peak memory 218444 kb
Host smart-8f19951e-ccfb-4f06-9b6c-642a1e7a7ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644914436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.644914436
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.3844036436
Short name T162
Test name
Test status
Simulation time 119501793 ps
CPU time 1.16 seconds
Started Aug 18 06:11:58 PM PDT 24
Finished Aug 18 06:11:59 PM PDT 24
Peak memory 218728 kb
Host smart-70d469d3-fac1-4757-848b-e6c76bdef35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844036436 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.3844036436
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.1708115613
Short name T212
Test name
Test status
Simulation time 20791356 ps
CPU time 1.27 seconds
Started Aug 18 06:11:58 PM PDT 24
Finished Aug 18 06:11:59 PM PDT 24
Peak memory 229696 kb
Host smart-8c8e0cca-da9d-4e0b-a445-df523704b7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708115613 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.1708115613
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.1374200867
Short name T357
Test name
Test status
Simulation time 76920250 ps
CPU time 1.26 seconds
Started Aug 18 06:11:55 PM PDT 24
Finished Aug 18 06:11:56 PM PDT 24
Peak memory 218604 kb
Host smart-02d6997a-a9f9-47d5-9dbe-3e22fc228f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374200867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.1374200867
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.60533057
Short name T202
Test name
Test status
Simulation time 76362855 ps
CPU time 1.19 seconds
Started Aug 18 06:11:57 PM PDT 24
Finished Aug 18 06:11:58 PM PDT 24
Peak memory 220528 kb
Host smart-c23dea00-4aa2-4ada-8d72-dd90f685d7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60533057 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.60533057
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.1889590793
Short name T210
Test name
Test status
Simulation time 29114977 ps
CPU time 0.92 seconds
Started Aug 18 06:11:58 PM PDT 24
Finished Aug 18 06:11:59 PM PDT 24
Peak memory 219288 kb
Host smart-88c5b3ea-83cb-4a34-922a-77cdb353dde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889590793 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1889590793
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/83.edn_alert.21608705
Short name T568
Test name
Test status
Simulation time 29969897 ps
CPU time 1.35 seconds
Started Aug 18 06:11:55 PM PDT 24
Finished Aug 18 06:11:56 PM PDT 24
Peak memory 215776 kb
Host smart-bca84134-9881-4956-b950-b13a583ac970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21608705 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.21608705
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.3223006059
Short name T695
Test name
Test status
Simulation time 34740499 ps
CPU time 0.91 seconds
Started Aug 18 06:12:01 PM PDT 24
Finished Aug 18 06:12:02 PM PDT 24
Peak memory 215184 kb
Host smart-15296353-a54d-48f4-810c-22f89f737734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223006059 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.3223006059
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.1765771218
Short name T666
Test name
Test status
Simulation time 48601195 ps
CPU time 1.19 seconds
Started Aug 18 06:11:59 PM PDT 24
Finished Aug 18 06:12:01 PM PDT 24
Peak memory 218784 kb
Host smart-fa37df3b-e97d-40e3-9b9f-f4b9a733e30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765771218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.1765771218
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.2748683332
Short name T969
Test name
Test status
Simulation time 180503492 ps
CPU time 1.21 seconds
Started Aug 18 06:12:02 PM PDT 24
Finished Aug 18 06:12:03 PM PDT 24
Peak memory 219784 kb
Host smart-281cf70b-46ed-44dc-9007-773e02e7f893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748683332 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.2748683332
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.4017505512
Short name T153
Test name
Test status
Simulation time 34856554 ps
CPU time 1.12 seconds
Started Aug 18 06:12:02 PM PDT 24
Finished Aug 18 06:12:03 PM PDT 24
Peak memory 229776 kb
Host smart-ad62a750-d964-42fe-b2c2-c3878f1787c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017505512 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.4017505512
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.2730154070
Short name T645
Test name
Test status
Simulation time 81674779 ps
CPU time 1.18 seconds
Started Aug 18 06:11:56 PM PDT 24
Finished Aug 18 06:11:58 PM PDT 24
Peak memory 217472 kb
Host smart-2b7b26c3-a44d-4d43-b1e5-382141356df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730154070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2730154070
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.676545477
Short name T625
Test name
Test status
Simulation time 56649003 ps
CPU time 1.07 seconds
Started Aug 18 06:12:02 PM PDT 24
Finished Aug 18 06:12:03 PM PDT 24
Peak memory 219764 kb
Host smart-7af2de5a-1294-47fb-b261-db79c36eef81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676545477 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.676545477
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.1091655468
Short name T924
Test name
Test status
Simulation time 43154224 ps
CPU time 1.08 seconds
Started Aug 18 06:12:01 PM PDT 24
Finished Aug 18 06:12:02 PM PDT 24
Peak memory 224212 kb
Host smart-8bff628d-eb58-406a-be06-ca64622b2466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091655468 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1091655468
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.181983918
Short name T919
Test name
Test status
Simulation time 25696409 ps
CPU time 1.37 seconds
Started Aug 18 06:11:58 PM PDT 24
Finished Aug 18 06:12:00 PM PDT 24
Peak memory 218508 kb
Host smart-eba228cd-4a8e-43b5-a5a1-e7a5d5b8c23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181983918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.181983918
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.2481968567
Short name T312
Test name
Test status
Simulation time 53661042 ps
CPU time 1.38 seconds
Started Aug 18 06:11:58 PM PDT 24
Finished Aug 18 06:11:59 PM PDT 24
Peak memory 215756 kb
Host smart-a15a485a-4827-49e8-8d85-bc69d0febd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481968567 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.2481968567
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.2739319146
Short name T213
Test name
Test status
Simulation time 32709881 ps
CPU time 0.9 seconds
Started Aug 18 06:11:59 PM PDT 24
Finished Aug 18 06:12:00 PM PDT 24
Peak memory 219244 kb
Host smart-254d4bbf-61a7-4402-828b-1daa94fc9ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739319146 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2739319146
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.1404459403
Short name T276
Test name
Test status
Simulation time 40449436 ps
CPU time 1.47 seconds
Started Aug 18 06:11:58 PM PDT 24
Finished Aug 18 06:12:00 PM PDT 24
Peak memory 218748 kb
Host smart-e04d7ac8-ae72-453e-b23a-266049cb14b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404459403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.1404459403
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.2440962521
Short name T628
Test name
Test status
Simulation time 59050613 ps
CPU time 1.18 seconds
Started Aug 18 06:11:56 PM PDT 24
Finished Aug 18 06:11:57 PM PDT 24
Peak memory 215804 kb
Host smart-3144d343-fdaa-48e1-bea4-c99c078e8621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440962521 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.2440962521
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.3455131892
Short name T723
Test name
Test status
Simulation time 35575685 ps
CPU time 0.93 seconds
Started Aug 18 06:11:57 PM PDT 24
Finished Aug 18 06:11:58 PM PDT 24
Peak memory 218332 kb
Host smart-7958f45a-aa9e-4ee8-8e31-3cf4238793e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455131892 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3455131892
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.1897938383
Short name T577
Test name
Test status
Simulation time 62066006 ps
CPU time 1.09 seconds
Started Aug 18 06:11:57 PM PDT 24
Finished Aug 18 06:11:58 PM PDT 24
Peak memory 217488 kb
Host smart-db93bb79-14e2-416a-a258-41f17ecee2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897938383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.1897938383
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.2849577618
Short name T498
Test name
Test status
Simulation time 23975185 ps
CPU time 1.22 seconds
Started Aug 18 06:12:03 PM PDT 24
Finished Aug 18 06:12:05 PM PDT 24
Peak memory 219988 kb
Host smart-d590f8dc-74d1-4eec-9632-951468c669f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849577618 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.2849577618
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.1595280540
Short name T141
Test name
Test status
Simulation time 30011307 ps
CPU time 1.14 seconds
Started Aug 18 06:12:01 PM PDT 24
Finished Aug 18 06:12:02 PM PDT 24
Peak memory 229884 kb
Host smart-25b6a07c-ee69-4a0d-9ce4-869d58a02598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595280540 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.1595280540
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.2772445422
Short name T345
Test name
Test status
Simulation time 260221932 ps
CPU time 3.86 seconds
Started Aug 18 06:11:57 PM PDT 24
Finished Aug 18 06:12:01 PM PDT 24
Peak memory 220336 kb
Host smart-03228ef5-9cf1-423f-a050-b0149d0e1170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772445422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.2772445422
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.3950148131
Short name T898
Test name
Test status
Simulation time 86658485 ps
CPU time 1.14 seconds
Started Aug 18 06:12:01 PM PDT 24
Finished Aug 18 06:12:03 PM PDT 24
Peak memory 218600 kb
Host smart-49e85a35-2ff6-49d2-b9fe-342c63cfea47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950148131 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.3950148131
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.3954072693
Short name T54
Test name
Test status
Simulation time 18866045 ps
CPU time 1.16 seconds
Started Aug 18 06:11:56 PM PDT 24
Finished Aug 18 06:11:57 PM PDT 24
Peak memory 224116 kb
Host smart-ce02d66a-1b06-46b9-a79a-bf6a5888504d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954072693 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.3954072693
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/9.edn_alert.1815535292
Short name T522
Test name
Test status
Simulation time 97507690 ps
CPU time 1.17 seconds
Started Aug 18 06:10:25 PM PDT 24
Finished Aug 18 06:10:26 PM PDT 24
Peak memory 220444 kb
Host smart-d0cb9e1d-8b74-4d65-89e2-04904fc8b4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815535292 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1815535292
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.2152938596
Short name T391
Test name
Test status
Simulation time 14904754 ps
CPU time 0.93 seconds
Started Aug 18 06:10:25 PM PDT 24
Finished Aug 18 06:10:26 PM PDT 24
Peak memory 206776 kb
Host smart-f39bbea3-6e7b-4f3f-aabd-cef4cd0e4bf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152938596 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.2152938596
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.1877643095
Short name T734
Test name
Test status
Simulation time 12729241 ps
CPU time 0.92 seconds
Started Aug 18 06:10:25 PM PDT 24
Finished Aug 18 06:10:26 PM PDT 24
Peak memory 215588 kb
Host smart-66e3d70d-1348-4054-8c01-26f35787d591
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877643095 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1877643095
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_err.447153472
Short name T452
Test name
Test status
Simulation time 25452674 ps
CPU time 0.95 seconds
Started Aug 18 06:10:24 PM PDT 24
Finished Aug 18 06:10:25 PM PDT 24
Peak memory 219796 kb
Host smart-9b60fbb0-1955-4439-b38e-f715497c2315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447153472 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.447153472
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.4277181534
Short name T878
Test name
Test status
Simulation time 50556332 ps
CPU time 1.86 seconds
Started Aug 18 06:10:25 PM PDT 24
Finished Aug 18 06:10:27 PM PDT 24
Peak memory 218564 kb
Host smart-c962537e-c62f-4b7c-b856-9fbfacc01ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277181534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.4277181534
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.21400264
Short name T747
Test name
Test status
Simulation time 21063780 ps
CPU time 1.13 seconds
Started Aug 18 06:10:25 PM PDT 24
Finished Aug 18 06:10:26 PM PDT 24
Peak memory 215520 kb
Host smart-efde4c6c-5840-454f-b657-1aba6a9e4d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21400264 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.21400264
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.3134936370
Short name T25
Test name
Test status
Simulation time 26815812 ps
CPU time 0.93 seconds
Started Aug 18 06:10:27 PM PDT 24
Finished Aug 18 06:10:28 PM PDT 24
Peak memory 207320 kb
Host smart-d5cb0013-16b0-41c7-aef9-576c6016ba4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134936370 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.3134936370
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.2755170196
Short name T892
Test name
Test status
Simulation time 41952816 ps
CPU time 0.91 seconds
Started Aug 18 06:10:23 PM PDT 24
Finished Aug 18 06:10:24 PM PDT 24
Peak memory 215280 kb
Host smart-60ef7cff-6e86-4f6e-b630-e35421d7709b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755170196 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2755170196
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1455160730
Short name T500
Test name
Test status
Simulation time 277602767 ps
CPU time 5.43 seconds
Started Aug 18 06:10:26 PM PDT 24
Finished Aug 18 06:10:31 PM PDT 24
Peak memory 215356 kb
Host smart-53c6a18f-c22c-443d-a62e-f109d30909c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455160730 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1455160730
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.2888963030
Short name T967
Test name
Test status
Simulation time 1057076755 ps
CPU time 27.36 seconds
Started Aug 18 06:10:25 PM PDT 24
Finished Aug 18 06:10:53 PM PDT 24
Peak memory 218616 kb
Host smart-dcc15cd3-7222-4158-aba8-3cdea340a599
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888963030 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.2888963030
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.1534957928
Short name T175
Test name
Test status
Simulation time 22860417 ps
CPU time 1.15 seconds
Started Aug 18 06:12:00 PM PDT 24
Finished Aug 18 06:12:01 PM PDT 24
Peak memory 218648 kb
Host smart-7aecdbab-7d6e-4c33-a349-61c1166cd611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534957928 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.1534957928
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.244672213
Short name T166
Test name
Test status
Simulation time 33017895 ps
CPU time 0.91 seconds
Started Aug 18 06:11:54 PM PDT 24
Finished Aug 18 06:11:55 PM PDT 24
Peak memory 219816 kb
Host smart-555ae033-6d4a-4e08-98a9-6abeb31e8df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244672213 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.244672213
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.1100962541
Short name T92
Test name
Test status
Simulation time 59075592 ps
CPU time 1.49 seconds
Started Aug 18 06:12:00 PM PDT 24
Finished Aug 18 06:12:01 PM PDT 24
Peak memory 217580 kb
Host smart-d4927bfd-ad3e-41d3-a49c-84aee36484c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100962541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1100962541
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.2993756477
Short name T375
Test name
Test status
Simulation time 47919153 ps
CPU time 1.22 seconds
Started Aug 18 06:12:02 PM PDT 24
Finished Aug 18 06:12:04 PM PDT 24
Peak memory 219560 kb
Host smart-207a71c9-09ba-4d98-8157-0e6fa8b2d199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993756477 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.2993756477
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.2863236522
Short name T642
Test name
Test status
Simulation time 42375801 ps
CPU time 0.84 seconds
Started Aug 18 06:11:57 PM PDT 24
Finished Aug 18 06:11:57 PM PDT 24
Peak memory 219160 kb
Host smart-5888c808-7a1f-4352-8843-78c10a0d3f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863236522 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.2863236522
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.2780533162
Short name T415
Test name
Test status
Simulation time 42852321 ps
CPU time 1.46 seconds
Started Aug 18 06:11:56 PM PDT 24
Finished Aug 18 06:11:57 PM PDT 24
Peak memory 220036 kb
Host smart-240e22e0-5656-4cd0-b074-d422ad801380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780533162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.2780533162
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.977566908
Short name T598
Test name
Test status
Simulation time 75412049 ps
CPU time 1.14 seconds
Started Aug 18 06:11:55 PM PDT 24
Finished Aug 18 06:11:57 PM PDT 24
Peak memory 220768 kb
Host smart-e124ff1b-2695-4e0e-8afe-31135ed390ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977566908 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.977566908
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.1856394435
Short name T183
Test name
Test status
Simulation time 134686855 ps
CPU time 1.06 seconds
Started Aug 18 06:11:58 PM PDT 24
Finished Aug 18 06:11:59 PM PDT 24
Peak memory 215400 kb
Host smart-a81d394b-241b-4fce-b729-72a1ba62106b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856394435 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.1856394435
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.274794703
Short name T607
Test name
Test status
Simulation time 80919583 ps
CPU time 1.83 seconds
Started Aug 18 06:11:58 PM PDT 24
Finished Aug 18 06:12:00 PM PDT 24
Peak memory 218708 kb
Host smart-8ca54d9e-c9b0-4753-a18e-ce96cc8c30be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274794703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.274794703
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.1534239702
Short name T448
Test name
Test status
Simulation time 43112958 ps
CPU time 1.11 seconds
Started Aug 18 06:11:56 PM PDT 24
Finished Aug 18 06:11:58 PM PDT 24
Peak memory 218896 kb
Host smart-70eea22e-d933-41cd-9d82-9c9fb19dbafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534239702 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.1534239702
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.2743238299
Short name T180
Test name
Test status
Simulation time 39874872 ps
CPU time 0.92 seconds
Started Aug 18 06:12:00 PM PDT 24
Finished Aug 18 06:12:01 PM PDT 24
Peak memory 218548 kb
Host smart-871cbf6a-c98c-408b-af1a-ddd5a82f60ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743238299 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.2743238299
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.3895585529
Short name T620
Test name
Test status
Simulation time 68097917 ps
CPU time 1.82 seconds
Started Aug 18 06:11:56 PM PDT 24
Finished Aug 18 06:11:58 PM PDT 24
Peak memory 220528 kb
Host smart-c0c440d0-4f59-4b38-994a-9eba80b58ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895585529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.3895585529
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.3967497409
Short name T241
Test name
Test status
Simulation time 24415065 ps
CPU time 1.2 seconds
Started Aug 18 06:12:00 PM PDT 24
Finished Aug 18 06:12:01 PM PDT 24
Peak memory 215788 kb
Host smart-ea4eafec-5f3e-4b0f-8f4b-65c8bfb1e2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967497409 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.3967497409
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.3023344625
Short name T62
Test name
Test status
Simulation time 54498113 ps
CPU time 1.05 seconds
Started Aug 18 06:11:56 PM PDT 24
Finished Aug 18 06:11:57 PM PDT 24
Peak memory 218880 kb
Host smart-9bed3b8a-983f-41af-bdb2-b826af510dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023344625 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3023344625
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.2671197541
Short name T690
Test name
Test status
Simulation time 29502531 ps
CPU time 1.35 seconds
Started Aug 18 06:11:56 PM PDT 24
Finished Aug 18 06:11:57 PM PDT 24
Peak memory 217432 kb
Host smart-8ccb82db-cecf-4fe9-a757-bb774e15f77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671197541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2671197541
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.821086394
Short name T207
Test name
Test status
Simulation time 89616037 ps
CPU time 1.08 seconds
Started Aug 18 06:11:55 PM PDT 24
Finished Aug 18 06:11:57 PM PDT 24
Peak memory 220908 kb
Host smart-3de5f349-0e52-45f9-8072-2519f0bbc8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821086394 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.821086394
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.255272922
Short name T883
Test name
Test status
Simulation time 23487203 ps
CPU time 0.99 seconds
Started Aug 18 06:11:58 PM PDT 24
Finished Aug 18 06:12:00 PM PDT 24
Peak memory 218436 kb
Host smart-b06a8ee4-621d-4e58-95d5-99e99958b4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255272922 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.255272922
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.3942711534
Short name T397
Test name
Test status
Simulation time 84900117 ps
CPU time 1.23 seconds
Started Aug 18 06:11:57 PM PDT 24
Finished Aug 18 06:11:58 PM PDT 24
Peak memory 220512 kb
Host smart-d663523f-71fe-47e8-87f9-e5eeed18460c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942711534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.3942711534
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.2359157655
Short name T679
Test name
Test status
Simulation time 243592679 ps
CPU time 1.35 seconds
Started Aug 18 06:12:01 PM PDT 24
Finished Aug 18 06:12:03 PM PDT 24
Peak memory 219772 kb
Host smart-6630dd09-f09a-4cc9-9b46-a7f10bd0be8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359157655 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.2359157655
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.3024404376
Short name T147
Test name
Test status
Simulation time 28806238 ps
CPU time 1.04 seconds
Started Aug 18 06:11:59 PM PDT 24
Finished Aug 18 06:12:00 PM PDT 24
Peak memory 219568 kb
Host smart-8cd1bb11-94c4-4a39-b319-6c9cf47283f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024404376 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3024404376
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.2284762946
Short name T974
Test name
Test status
Simulation time 172970884 ps
CPU time 1.31 seconds
Started Aug 18 06:11:59 PM PDT 24
Finished Aug 18 06:12:01 PM PDT 24
Peak memory 217252 kb
Host smart-b8a39d87-2ded-4737-adb2-e88003941ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284762946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2284762946
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.3934522956
Short name T181
Test name
Test status
Simulation time 135100547 ps
CPU time 1.21 seconds
Started Aug 18 06:11:58 PM PDT 24
Finished Aug 18 06:12:00 PM PDT 24
Peak memory 220800 kb
Host smart-3d974cdb-bf9f-4749-b832-29f055b36888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934522956 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.3934522956
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.1571318821
Short name T177
Test name
Test status
Simulation time 51589699 ps
CPU time 0.88 seconds
Started Aug 18 06:11:57 PM PDT 24
Finished Aug 18 06:11:58 PM PDT 24
Peak memory 218404 kb
Host smart-b03d1300-1930-4007-b1b2-06ec20409a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571318821 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.1571318821
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.1398485844
Short name T358
Test name
Test status
Simulation time 41403467 ps
CPU time 1.64 seconds
Started Aug 18 06:11:57 PM PDT 24
Finished Aug 18 06:11:58 PM PDT 24
Peak memory 220052 kb
Host smart-38877609-046f-4472-979c-b9bb075ba970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398485844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.1398485844
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.2126930061
Short name T501
Test name
Test status
Simulation time 25927729 ps
CPU time 1.22 seconds
Started Aug 18 06:11:59 PM PDT 24
Finished Aug 18 06:12:01 PM PDT 24
Peak memory 219316 kb
Host smart-502061a6-06f3-474a-b15c-897951295c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126930061 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.2126930061
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.3796128024
Short name T588
Test name
Test status
Simulation time 79411704 ps
CPU time 0.91 seconds
Started Aug 18 06:11:55 PM PDT 24
Finished Aug 18 06:11:56 PM PDT 24
Peak memory 218364 kb
Host smart-37759a48-28e0-4936-b9f0-73ed8fd177ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796128024 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.3796128024
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2802840823
Short name T93
Test name
Test status
Simulation time 66718340 ps
CPU time 2.36 seconds
Started Aug 18 06:11:56 PM PDT 24
Finished Aug 18 06:11:59 PM PDT 24
Peak memory 217500 kb
Host smart-7349a057-397c-4400-9591-d24595463698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802840823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2802840823
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.796396690
Short name T699
Test name
Test status
Simulation time 99241094 ps
CPU time 1.11 seconds
Started Aug 18 06:12:03 PM PDT 24
Finished Aug 18 06:12:04 PM PDT 24
Peak memory 218676 kb
Host smart-e0733473-aef0-4131-9802-31aaa4a2f3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796396690 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.796396690
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.35108483
Short name T55
Test name
Test status
Simulation time 31211864 ps
CPU time 1.04 seconds
Started Aug 18 06:12:02 PM PDT 24
Finished Aug 18 06:12:03 PM PDT 24
Peak memory 229688 kb
Host smart-deb29a73-958b-44c9-8d23-84b76c32ba9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35108483 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.35108483
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.408200620
Short name T408
Test name
Test status
Simulation time 34951820 ps
CPU time 1.34 seconds
Started Aug 18 06:12:02 PM PDT 24
Finished Aug 18 06:12:04 PM PDT 24
Peak memory 220296 kb
Host smart-4f253364-2177-4f7a-9a06-6da7841934a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408200620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.408200620
Directory /workspace/99.edn_genbits/latest
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