Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.77 98.25 93.91 97.02 91.86 96.37 99.77 93.18


Total test records in report: 1118
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T269 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1711828133 Aug 19 05:00:24 PM PDT 24 Aug 19 05:00:25 PM PDT 24 34454808 ps
T1013 /workspace/coverage/cover_reg_top/34.edn_intr_test.217322813 Aug 19 05:01:11 PM PDT 24 Aug 19 05:01:12 PM PDT 24 25055744 ps
T1014 /workspace/coverage/cover_reg_top/9.edn_tl_errors.1109754346 Aug 19 05:00:24 PM PDT 24 Aug 19 05:00:26 PM PDT 24 39663208 ps
T1015 /workspace/coverage/cover_reg_top/5.edn_tl_errors.3153574764 Aug 19 05:00:14 PM PDT 24 Aug 19 05:00:16 PM PDT 24 48747267 ps
T1016 /workspace/coverage/cover_reg_top/49.edn_intr_test.3364848488 Aug 19 05:01:28 PM PDT 24 Aug 19 05:01:29 PM PDT 24 80474665 ps
T1017 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3848488754 Aug 19 04:59:53 PM PDT 24 Aug 19 04:59:57 PM PDT 24 730645102 ps
T1018 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.656777229 Aug 19 05:00:04 PM PDT 24 Aug 19 05:00:07 PM PDT 24 18258946 ps
T1019 /workspace/coverage/cover_reg_top/2.edn_intr_test.1113730086 Aug 19 04:59:51 PM PDT 24 Aug 19 04:59:52 PM PDT 24 44358135 ps
T270 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1077820383 Aug 19 05:00:53 PM PDT 24 Aug 19 05:00:54 PM PDT 24 21067352 ps
T271 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1904511238 Aug 19 04:59:50 PM PDT 24 Aug 19 04:59:51 PM PDT 24 61200254 ps
T1020 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2250989528 Aug 19 05:00:38 PM PDT 24 Aug 19 05:00:40 PM PDT 24 112568138 ps
T1021 /workspace/coverage/cover_reg_top/36.edn_intr_test.3250534541 Aug 19 05:01:12 PM PDT 24 Aug 19 05:01:13 PM PDT 24 74477358 ps
T1022 /workspace/coverage/cover_reg_top/40.edn_intr_test.2501320924 Aug 19 05:01:14 PM PDT 24 Aug 19 05:01:15 PM PDT 24 11600064 ps
T1023 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2609468068 Aug 19 05:00:02 PM PDT 24 Aug 19 05:00:07 PM PDT 24 37366921 ps
T1024 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3929544489 Aug 19 05:00:04 PM PDT 24 Aug 19 05:00:07 PM PDT 24 37141962 ps
T1025 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.4270216185 Aug 19 04:59:39 PM PDT 24 Aug 19 04:59:40 PM PDT 24 28877530 ps
T1026 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2830264918 Aug 19 05:00:48 PM PDT 24 Aug 19 05:00:50 PM PDT 24 211404979 ps
T1027 /workspace/coverage/cover_reg_top/5.edn_intr_test.1623861330 Aug 19 05:00:13 PM PDT 24 Aug 19 05:00:14 PM PDT 24 46524218 ps
T1028 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2103471921 Aug 19 04:59:40 PM PDT 24 Aug 19 04:59:46 PM PDT 24 2139145737 ps
T287 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.316273407 Aug 19 05:00:16 PM PDT 24 Aug 19 05:00:19 PM PDT 24 124714991 ps
T1029 /workspace/coverage/cover_reg_top/17.edn_tl_errors.3109014334 Aug 19 05:00:57 PM PDT 24 Aug 19 05:00:59 PM PDT 24 119548361 ps
T1030 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1329689198 Aug 19 05:00:38 PM PDT 24 Aug 19 05:00:39 PM PDT 24 84001053 ps
T1031 /workspace/coverage/cover_reg_top/19.edn_csr_rw.2302381000 Aug 19 05:00:58 PM PDT 24 Aug 19 05:00:59 PM PDT 24 44565463 ps
T1032 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.184077771 Aug 19 05:00:59 PM PDT 24 Aug 19 05:01:01 PM PDT 24 18683863 ps
T1033 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.853768813 Aug 19 05:00:03 PM PDT 24 Aug 19 05:00:07 PM PDT 24 156491404 ps
T256 /workspace/coverage/cover_reg_top/4.edn_csr_rw.964154924 Aug 19 05:00:02 PM PDT 24 Aug 19 05:00:07 PM PDT 24 13842038 ps
T1034 /workspace/coverage/cover_reg_top/16.edn_tl_errors.3694153960 Aug 19 05:00:48 PM PDT 24 Aug 19 05:00:50 PM PDT 24 32379191 ps
T1035 /workspace/coverage/cover_reg_top/9.edn_intr_test.3624140651 Aug 19 05:00:36 PM PDT 24 Aug 19 05:00:37 PM PDT 24 102173691 ps
T1036 /workspace/coverage/cover_reg_top/28.edn_intr_test.4261434902 Aug 19 05:01:12 PM PDT 24 Aug 19 05:01:13 PM PDT 24 25146077 ps
T1037 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.496873625 Aug 19 05:01:00 PM PDT 24 Aug 19 05:01:01 PM PDT 24 193937520 ps
T1038 /workspace/coverage/cover_reg_top/35.edn_intr_test.3279653839 Aug 19 05:01:13 PM PDT 24 Aug 19 05:01:15 PM PDT 24 16544924 ps
T1039 /workspace/coverage/cover_reg_top/10.edn_intr_test.1165004869 Aug 19 05:00:24 PM PDT 24 Aug 19 05:00:25 PM PDT 24 31524947 ps
T1040 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.364435293 Aug 19 05:00:02 PM PDT 24 Aug 19 05:00:11 PM PDT 24 702649230 ps
T1041 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2377602885 Aug 19 05:00:36 PM PDT 24 Aug 19 05:00:38 PM PDT 24 143435079 ps
T257 /workspace/coverage/cover_reg_top/10.edn_csr_rw.3868750225 Aug 19 05:00:24 PM PDT 24 Aug 19 05:00:25 PM PDT 24 76360259 ps
T1042 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.840929090 Aug 19 05:00:19 PM PDT 24 Aug 19 05:00:20 PM PDT 24 18154055 ps
T1043 /workspace/coverage/cover_reg_top/5.edn_csr_rw.1714119251 Aug 19 05:00:15 PM PDT 24 Aug 19 05:00:16 PM PDT 24 23374361 ps
T1044 /workspace/coverage/cover_reg_top/12.edn_intr_test.1144777295 Aug 19 05:00:53 PM PDT 24 Aug 19 05:00:54 PM PDT 24 15740041 ps
T1045 /workspace/coverage/cover_reg_top/18.edn_tl_errors.1274084848 Aug 19 05:00:57 PM PDT 24 Aug 19 05:00:59 PM PDT 24 24084145 ps
T1046 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1501056719 Aug 19 05:00:24 PM PDT 24 Aug 19 05:00:25 PM PDT 24 33274125 ps
T1047 /workspace/coverage/cover_reg_top/8.edn_tl_errors.3480532565 Aug 19 05:00:26 PM PDT 24 Aug 19 05:00:29 PM PDT 24 122578442 ps
T1048 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.418147597 Aug 19 04:59:50 PM PDT 24 Aug 19 04:59:52 PM PDT 24 58060892 ps
T1049 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1679929308 Aug 19 05:00:16 PM PDT 24 Aug 19 05:00:18 PM PDT 24 58407655 ps
T1050 /workspace/coverage/cover_reg_top/22.edn_intr_test.3482970827 Aug 19 05:01:11 PM PDT 24 Aug 19 05:01:12 PM PDT 24 13273200 ps
T1051 /workspace/coverage/cover_reg_top/3.edn_tl_errors.4131245604 Aug 19 04:59:50 PM PDT 24 Aug 19 04:59:53 PM PDT 24 86909851 ps
T1052 /workspace/coverage/cover_reg_top/41.edn_intr_test.272654254 Aug 19 05:01:13 PM PDT 24 Aug 19 05:01:14 PM PDT 24 12065068 ps
T1053 /workspace/coverage/cover_reg_top/14.edn_tl_errors.3712314505 Aug 19 05:00:53 PM PDT 24 Aug 19 05:00:55 PM PDT 24 33490689 ps
T1054 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.609916388 Aug 19 05:00:23 PM PDT 24 Aug 19 05:00:25 PM PDT 24 40594252 ps
T1055 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3409542842 Aug 19 04:59:40 PM PDT 24 Aug 19 04:59:41 PM PDT 24 48973682 ps
T1056 /workspace/coverage/cover_reg_top/24.edn_intr_test.947593842 Aug 19 05:01:14 PM PDT 24 Aug 19 05:01:15 PM PDT 24 15954573 ps
T1057 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.706554375 Aug 19 05:00:59 PM PDT 24 Aug 19 05:01:00 PM PDT 24 61080577 ps
T1058 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1586062224 Aug 19 04:59:42 PM PDT 24 Aug 19 04:59:43 PM PDT 24 24356086 ps
T289 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2980607089 Aug 19 05:00:24 PM PDT 24 Aug 19 05:00:25 PM PDT 24 84893667 ps
T1059 /workspace/coverage/cover_reg_top/11.edn_tl_errors.1672751367 Aug 19 05:00:22 PM PDT 24 Aug 19 05:00:24 PM PDT 24 32104878 ps
T258 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3571789992 Aug 19 04:59:41 PM PDT 24 Aug 19 04:59:43 PM PDT 24 35295054 ps
T1060 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2058045661 Aug 19 05:00:24 PM PDT 24 Aug 19 05:00:27 PM PDT 24 269307930 ps
T1061 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.4259217136 Aug 19 04:59:50 PM PDT 24 Aug 19 04:59:52 PM PDT 24 258786439 ps
T1062 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.501922282 Aug 19 04:59:29 PM PDT 24 Aug 19 04:59:30 PM PDT 24 105499834 ps
T1063 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.479583151 Aug 19 05:00:03 PM PDT 24 Aug 19 05:00:07 PM PDT 24 44563501 ps
T1064 /workspace/coverage/cover_reg_top/10.edn_tl_errors.627552306 Aug 19 05:00:24 PM PDT 24 Aug 19 05:00:26 PM PDT 24 97900113 ps
T1065 /workspace/coverage/cover_reg_top/11.edn_intr_test.3320756791 Aug 19 05:00:37 PM PDT 24 Aug 19 05:00:38 PM PDT 24 43302167 ps
T1066 /workspace/coverage/cover_reg_top/0.edn_intr_test.3117327075 Aug 19 04:59:31 PM PDT 24 Aug 19 04:59:32 PM PDT 24 26580072 ps
T1067 /workspace/coverage/cover_reg_top/47.edn_intr_test.755876189 Aug 19 05:01:25 PM PDT 24 Aug 19 05:01:26 PM PDT 24 12123794 ps
T1068 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1379645601 Aug 19 05:00:59 PM PDT 24 Aug 19 05:01:01 PM PDT 24 22868926 ps
T1069 /workspace/coverage/cover_reg_top/13.edn_tl_errors.4029259695 Aug 19 05:00:37 PM PDT 24 Aug 19 05:00:41 PM PDT 24 103342721 ps
T1070 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3657117997 Aug 19 05:00:12 PM PDT 24 Aug 19 05:00:15 PM PDT 24 151937790 ps
T1071 /workspace/coverage/cover_reg_top/19.edn_tl_errors.1221264620 Aug 19 05:00:59 PM PDT 24 Aug 19 05:01:03 PM PDT 24 175669864 ps
T1072 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2960777086 Aug 19 05:00:35 PM PDT 24 Aug 19 05:00:38 PM PDT 24 74696098 ps
T259 /workspace/coverage/cover_reg_top/1.edn_csr_rw.3581646478 Aug 19 04:59:41 PM PDT 24 Aug 19 04:59:42 PM PDT 24 11242799 ps
T1073 /workspace/coverage/cover_reg_top/13.edn_csr_rw.3012578142 Aug 19 05:00:35 PM PDT 24 Aug 19 05:00:36 PM PDT 24 19478841 ps
T1074 /workspace/coverage/cover_reg_top/39.edn_intr_test.252018903 Aug 19 05:01:12 PM PDT 24 Aug 19 05:01:13 PM PDT 24 51479031 ps
T1075 /workspace/coverage/cover_reg_top/2.edn_csr_rw.3552696139 Aug 19 04:59:51 PM PDT 24 Aug 19 04:59:52 PM PDT 24 38294065 ps
T260 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.4033475275 Aug 19 04:59:40 PM PDT 24 Aug 19 04:59:41 PM PDT 24 25735587 ps
T261 /workspace/coverage/cover_reg_top/16.edn_csr_rw.3358238815 Aug 19 05:00:59 PM PDT 24 Aug 19 05:01:01 PM PDT 24 17070691 ps
T1076 /workspace/coverage/cover_reg_top/3.edn_intr_test.3171582278 Aug 19 04:59:58 PM PDT 24 Aug 19 04:59:59 PM PDT 24 27449158 ps
T1077 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3850572938 Aug 19 05:00:24 PM PDT 24 Aug 19 05:00:26 PM PDT 24 105452766 ps
T1078 /workspace/coverage/cover_reg_top/6.edn_tl_errors.683054489 Aug 19 05:00:12 PM PDT 24 Aug 19 05:00:15 PM PDT 24 208705652 ps
T1079 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3919880872 Aug 19 05:00:35 PM PDT 24 Aug 19 05:00:37 PM PDT 24 25716353 ps
T1080 /workspace/coverage/cover_reg_top/19.edn_intr_test.1923394567 Aug 19 05:01:00 PM PDT 24 Aug 19 05:01:01 PM PDT 24 37911309 ps
T1081 /workspace/coverage/cover_reg_top/8.edn_csr_rw.592351895 Aug 19 05:00:22 PM PDT 24 Aug 19 05:00:23 PM PDT 24 39833016 ps
T1082 /workspace/coverage/cover_reg_top/33.edn_intr_test.1622580763 Aug 19 05:01:12 PM PDT 24 Aug 19 05:01:13 PM PDT 24 14695733 ps
T1083 /workspace/coverage/cover_reg_top/48.edn_intr_test.593721082 Aug 19 05:01:29 PM PDT 24 Aug 19 05:01:30 PM PDT 24 36556648 ps
T1084 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3349716092 Aug 19 04:59:40 PM PDT 24 Aug 19 04:59:42 PM PDT 24 172816622 ps
T1085 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.4132803822 Aug 19 04:59:40 PM PDT 24 Aug 19 04:59:41 PM PDT 24 32095549 ps
T1086 /workspace/coverage/cover_reg_top/8.edn_intr_test.3558096204 Aug 19 05:00:36 PM PDT 24 Aug 19 05:00:37 PM PDT 24 19975272 ps
T1087 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2844690963 Aug 19 05:00:14 PM PDT 24 Aug 19 05:00:15 PM PDT 24 71735032 ps
T1088 /workspace/coverage/cover_reg_top/6.edn_intr_test.2126044016 Aug 19 05:00:13 PM PDT 24 Aug 19 05:00:15 PM PDT 24 14120913 ps
T1089 /workspace/coverage/cover_reg_top/44.edn_intr_test.3032278721 Aug 19 05:01:25 PM PDT 24 Aug 19 05:01:26 PM PDT 24 13554615 ps
T1090 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2457160033 Aug 19 04:59:58 PM PDT 24 Aug 19 04:59:59 PM PDT 24 35828337 ps
T1091 /workspace/coverage/cover_reg_top/7.edn_csr_rw.1982972460 Aug 19 05:00:13 PM PDT 24 Aug 19 05:00:14 PM PDT 24 90148603 ps
T1092 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3896837533 Aug 19 05:00:03 PM PDT 24 Aug 19 05:00:07 PM PDT 24 111070349 ps
T1093 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.4183851353 Aug 19 05:00:12 PM PDT 24 Aug 19 05:00:15 PM PDT 24 93434826 ps
T1094 /workspace/coverage/cover_reg_top/26.edn_intr_test.2802192201 Aug 19 05:01:13 PM PDT 24 Aug 19 05:01:14 PM PDT 24 12393326 ps
T1095 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3506857372 Aug 19 05:00:57 PM PDT 24 Aug 19 05:00:59 PM PDT 24 274991276 ps
T1096 /workspace/coverage/cover_reg_top/3.edn_csr_rw.254261811 Aug 19 04:59:51 PM PDT 24 Aug 19 04:59:52 PM PDT 24 20525369 ps
T1097 /workspace/coverage/cover_reg_top/16.edn_intr_test.1243308284 Aug 19 05:01:00 PM PDT 24 Aug 19 05:01:01 PM PDT 24 14556518 ps
T1098 /workspace/coverage/cover_reg_top/6.edn_csr_rw.1262051753 Aug 19 05:00:11 PM PDT 24 Aug 19 05:00:12 PM PDT 24 40370701 ps
T1099 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.4257905177 Aug 19 05:00:46 PM PDT 24 Aug 19 05:00:48 PM PDT 24 73664262 ps
T1100 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2457899149 Aug 19 05:00:37 PM PDT 24 Aug 19 05:00:39 PM PDT 24 168369062 ps
T1101 /workspace/coverage/cover_reg_top/11.edn_csr_rw.2950916694 Aug 19 05:00:53 PM PDT 24 Aug 19 05:00:54 PM PDT 24 14077418 ps
T1102 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2205838614 Aug 19 05:00:47 PM PDT 24 Aug 19 05:00:48 PM PDT 24 151527704 ps
T1103 /workspace/coverage/cover_reg_top/7.edn_tl_errors.1663664428 Aug 19 05:00:13 PM PDT 24 Aug 19 05:00:16 PM PDT 24 81555489 ps
T1104 /workspace/coverage/cover_reg_top/15.edn_tl_errors.3491171562 Aug 19 05:00:47 PM PDT 24 Aug 19 05:00:49 PM PDT 24 25219534 ps
T1105 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3444320637 Aug 19 04:59:51 PM PDT 24 Aug 19 04:59:53 PM PDT 24 65545456 ps
T1106 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.438231539 Aug 19 05:00:22 PM PDT 24 Aug 19 05:00:24 PM PDT 24 41237913 ps
T1107 /workspace/coverage/cover_reg_top/27.edn_intr_test.2377548206 Aug 19 05:01:13 PM PDT 24 Aug 19 05:01:14 PM PDT 24 28377370 ps
T1108 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.4095555324 Aug 19 05:00:45 PM PDT 24 Aug 19 05:00:46 PM PDT 24 160105460 ps
T1109 /workspace/coverage/cover_reg_top/31.edn_intr_test.2926572111 Aug 19 05:01:12 PM PDT 24 Aug 19 05:01:13 PM PDT 24 50775300 ps
T1110 /workspace/coverage/cover_reg_top/18.edn_intr_test.584418426 Aug 19 05:00:58 PM PDT 24 Aug 19 05:00:59 PM PDT 24 44932105 ps
T1111 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.638919442 Aug 19 05:00:25 PM PDT 24 Aug 19 05:00:26 PM PDT 24 236091680 ps
T1112 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1264862126 Aug 19 05:00:28 PM PDT 24 Aug 19 05:00:29 PM PDT 24 25402316 ps
T1113 /workspace/coverage/cover_reg_top/17.edn_csr_rw.2895917193 Aug 19 05:00:57 PM PDT 24 Aug 19 05:00:58 PM PDT 24 42261366 ps
T1114 /workspace/coverage/cover_reg_top/38.edn_intr_test.662565806 Aug 19 05:01:15 PM PDT 24 Aug 19 05:01:16 PM PDT 24 18240060 ps
T262 /workspace/coverage/cover_reg_top/12.edn_csr_rw.242944108 Aug 19 05:00:36 PM PDT 24 Aug 19 05:00:37 PM PDT 24 23050429 ps
T1115 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3453798941 Aug 19 04:59:41 PM PDT 24 Aug 19 04:59:43 PM PDT 24 235750007 ps
T1116 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1658711922 Aug 19 05:00:13 PM PDT 24 Aug 19 05:00:15 PM PDT 24 101845128 ps
T1117 /workspace/coverage/cover_reg_top/45.edn_intr_test.333206766 Aug 19 05:01:26 PM PDT 24 Aug 19 05:01:27 PM PDT 24 14007202 ps
T1118 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3936098521 Aug 19 05:00:58 PM PDT 24 Aug 19 05:01:00 PM PDT 24 217911589 ps

Test location /workspace/coverage/default/7.edn_genbits.3005509890
Short name T25
Test name
Test status
Simulation time 130901057 ps
CPU time 1.68 seconds
Started Aug 19 05:52:36 PM PDT 24
Finished Aug 19 05:52:38 PM PDT 24
Peak memory 219112 kb
Host smart-827d6ba4-b257-4318-9811-db8967b11cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005509890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.3005509890
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.471617858
Short name T39
Test name
Test status
Simulation time 123358821 ps
CPU time 1.33 seconds
Started Aug 19 05:53:58 PM PDT 24
Finished Aug 19 05:54:00 PM PDT 24
Peak memory 218760 kb
Host smart-939de26c-34cd-4caa-aa0f-3e30f1969268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471617858 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.471617858
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.116636708
Short name T36
Test name
Test status
Simulation time 3635163803 ps
CPU time 100.34 seconds
Started Aug 19 05:52:34 PM PDT 24
Finished Aug 19 05:54:15 PM PDT 24
Peak memory 220868 kb
Host smart-cf1d437a-d97a-4c1e-b279-ef57c055b60d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116636708 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.116636708
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_sec_cm.570049979
Short name T18
Test name
Test status
Simulation time 652993924 ps
CPU time 10.72 seconds
Started Aug 19 05:52:50 PM PDT 24
Finished Aug 19 05:53:00 PM PDT 24
Peak memory 237356 kb
Host smart-079607bc-b757-40fb-ae4f-69f3934ffc41
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570049979 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.570049979
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/44.edn_genbits.748494631
Short name T49
Test name
Test status
Simulation time 28699832 ps
CPU time 1.16 seconds
Started Aug 19 05:53:35 PM PDT 24
Finished Aug 19 05:53:36 PM PDT 24
Peak memory 220364 kb
Host smart-c0f9679d-8f67-46f7-b84d-4ffc4f6a002a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748494631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.748494631
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.34472604
Short name T3
Test name
Test status
Simulation time 72509210 ps
CPU time 1.1 seconds
Started Aug 19 05:53:31 PM PDT 24
Finished Aug 19 05:53:33 PM PDT 24
Peak memory 215504 kb
Host smart-ea72a638-5f17-4e48-bc11-36ba5fa99b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34472604 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.34472604
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/21.edn_disable.1977343214
Short name T41
Test name
Test status
Simulation time 37937566 ps
CPU time 0.91 seconds
Started Aug 19 05:53:10 PM PDT 24
Finished Aug 19 05:53:11 PM PDT 24
Peak memory 215416 kb
Host smart-1f86a0e7-bcc6-4eba-abe0-60e0b6bd876f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977343214 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1977343214
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.2097666531
Short name T22
Test name
Test status
Simulation time 42415464 ps
CPU time 1.34 seconds
Started Aug 19 05:53:18 PM PDT 24
Finished Aug 19 05:53:19 PM PDT 24
Peak memory 216852 kb
Host smart-4359a553-6e07-456b-8a52-fbaae81154a4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097666531 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.2097666531
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/64.edn_alert.1871718398
Short name T172
Test name
Test status
Simulation time 103249012 ps
CPU time 1.22 seconds
Started Aug 19 05:53:41 PM PDT 24
Finished Aug 19 05:53:42 PM PDT 24
Peak memory 215792 kb
Host smart-3c21df7c-a7ad-4be6-81a0-280ccf614cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871718398 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.1871718398
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.4771650
Short name T214
Test name
Test status
Simulation time 8513029298 ps
CPU time 53.93 seconds
Started Aug 19 05:52:35 PM PDT 24
Finished Aug 19 05:53:30 PM PDT 24
Peak memory 218484 kb
Host smart-f33fdbaf-104c-4e47-8596-7f57ae808a10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4771650 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.4771650
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.edn_alert.1070871171
Short name T116
Test name
Test status
Simulation time 74488956 ps
CPU time 1.11 seconds
Started Aug 19 05:53:55 PM PDT 24
Finished Aug 19 05:53:57 PM PDT 24
Peak memory 218828 kb
Host smart-773e5129-de3f-4020-901e-b164b49f513c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070871171 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.1070871171
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/17.edn_err.3350665516
Short name T53
Test name
Test status
Simulation time 23087508 ps
CPU time 1.04 seconds
Started Aug 19 05:53:04 PM PDT 24
Finished Aug 19 05:53:05 PM PDT 24
Peak memory 224276 kb
Host smart-99523a42-91f6-4427-b2fb-a22480c26d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350665516 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.3350665516
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/168.edn_alert.1005816982
Short name T217
Test name
Test status
Simulation time 27897520 ps
CPU time 1.26 seconds
Started Aug 19 05:54:15 PM PDT 24
Finished Aug 19 05:54:17 PM PDT 24
Peak memory 218588 kb
Host smart-afd6a05d-3c16-4e76-bb4a-c4b6d267830d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005816982 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.1005816982
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.137955439
Short name T254
Test name
Test status
Simulation time 32929216 ps
CPU time 0.88 seconds
Started Aug 19 05:00:47 PM PDT 24
Finished Aug 19 05:00:48 PM PDT 24
Peak memory 207020 kb
Host smart-cf173e79-c9bd-4c47-8d6e-f604ddc94cfd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137955439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.137955439
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/default/58.edn_err.1937186387
Short name T107
Test name
Test status
Simulation time 19944206 ps
CPU time 1.13 seconds
Started Aug 19 05:53:36 PM PDT 24
Finished Aug 19 05:53:38 PM PDT 24
Peak memory 218676 kb
Host smart-6e830fd4-5c26-43d4-bbee-1855662e083f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937186387 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.1937186387
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/3.edn_regwen.1117492193
Short name T294
Test name
Test status
Simulation time 16559976 ps
CPU time 0.95 seconds
Started Aug 19 05:52:30 PM PDT 24
Finished Aug 19 05:52:31 PM PDT 24
Peak memory 207176 kb
Host smart-86473b21-607a-4f03-b32b-149d36f83bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117492193 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1117492193
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3884623150
Short name T278
Test name
Test status
Simulation time 235140382 ps
CPU time 2.08 seconds
Started Aug 19 05:00:39 PM PDT 24
Finished Aug 19 05:00:41 PM PDT 24
Peak memory 207196 kb
Host smart-c1499729-2428-4538-9a9b-8c1f61f31941
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884623150 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3884623150
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/default/37.edn_disable.697337719
Short name T191
Test name
Test status
Simulation time 31366087 ps
CPU time 0.89 seconds
Started Aug 19 05:53:25 PM PDT 24
Finished Aug 19 05:53:26 PM PDT 24
Peak memory 215464 kb
Host smart-07f79173-8ffe-46bd-bec6-fa3536f92833
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697337719 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.697337719
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable.3645077594
Short name T210
Test name
Test status
Simulation time 105786246 ps
CPU time 0.88 seconds
Started Aug 19 05:52:59 PM PDT 24
Finished Aug 19 05:53:00 PM PDT 24
Peak memory 215436 kb
Host smart-f0b7fffb-617e-4115-bd0d-1ff433f32427
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645077594 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3645077594
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/67.edn_alert.3723756499
Short name T117
Test name
Test status
Simulation time 60952300 ps
CPU time 1.08 seconds
Started Aug 19 05:53:34 PM PDT 24
Finished Aug 19 05:53:36 PM PDT 24
Peak memory 219256 kb
Host smart-6f3dfd5b-e12f-46f6-9670-c41647ce10b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723756499 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.3723756499
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/53.edn_genbits.2329369491
Short name T86
Test name
Test status
Simulation time 181182939 ps
CPU time 1.54 seconds
Started Aug 19 05:53:40 PM PDT 24
Finished Aug 19 05:53:42 PM PDT 24
Peak memory 218724 kb
Host smart-dc056df5-bd54-48c6-9f11-7a43022f289a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329369491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.2329369491
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.1543760618
Short name T95
Test name
Test status
Simulation time 26033833 ps
CPU time 1.27 seconds
Started Aug 19 05:53:46 PM PDT 24
Finished Aug 19 05:53:48 PM PDT 24
Peak memory 219976 kb
Host smart-32dd793f-8752-4682-818b-6ffa1b72f453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543760618 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.1543760618
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/93.edn_alert.1728704622
Short name T130
Test name
Test status
Simulation time 28681589 ps
CPU time 1.3 seconds
Started Aug 19 05:54:04 PM PDT 24
Finished Aug 19 05:54:05 PM PDT 24
Peak memory 220652 kb
Host smart-381d6b83-1bc9-4b3f-b4ad-c12332c90347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728704622 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.1728704622
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/193.edn_alert.2095142952
Short name T68
Test name
Test status
Simulation time 33757469 ps
CPU time 1.35 seconds
Started Aug 19 05:54:19 PM PDT 24
Finished Aug 19 05:54:20 PM PDT 24
Peak memory 215804 kb
Host smart-02f83989-3dce-4702-bda7-71acfdb2fd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095142952 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.2095142952
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.30525293
Short name T89
Test name
Test status
Simulation time 40197208 ps
CPU time 0.96 seconds
Started Aug 19 05:53:34 PM PDT 24
Finished Aug 19 05:53:35 PM PDT 24
Peak memory 217112 kb
Host smart-71c9baf4-b2cf-4db2-a410-a992086ba340
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30525293 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_dis
able_auto_req_mode.30525293
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/117.edn_alert.1048183726
Short name T404
Test name
Test status
Simulation time 32793731 ps
CPU time 1.12 seconds
Started Aug 19 05:54:10 PM PDT 24
Finished Aug 19 05:54:12 PM PDT 24
Peak memory 218476 kb
Host smart-6fcfeb31-89b1-4b52-ad7e-443007799d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048183726 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.1048183726
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/136.edn_alert.1583278762
Short name T11
Test name
Test status
Simulation time 41898055 ps
CPU time 1.14 seconds
Started Aug 19 05:54:18 PM PDT 24
Finished Aug 19 05:54:20 PM PDT 24
Peak memory 218944 kb
Host smart-c43a49f6-6560-4ee2-89c1-650367dedfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583278762 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.1583278762
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert.4102376838
Short name T114
Test name
Test status
Simulation time 152354386 ps
CPU time 1.19 seconds
Started Aug 19 05:53:28 PM PDT 24
Finished Aug 19 05:53:29 PM PDT 24
Peak memory 215804 kb
Host smart-babe0d60-f18b-4712-8266-51cca19baf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102376838 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.4102376838
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/20.edn_intr.1269500128
Short name T33
Test name
Test status
Simulation time 20934168 ps
CPU time 1.09 seconds
Started Aug 19 05:53:10 PM PDT 24
Finished Aug 19 05:53:11 PM PDT 24
Peak memory 216060 kb
Host smart-a8c4ea7d-1ab8-41a3-93d0-91e30fe28e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269500128 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1269500128
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/101.edn_genbits.3766833465
Short name T233
Test name
Test status
Simulation time 85718849 ps
CPU time 1.43 seconds
Started Aug 19 05:54:11 PM PDT 24
Finished Aug 19 05:54:13 PM PDT 24
Peak memory 218928 kb
Host smart-6cb5b545-613e-4aa2-99aa-7282aa7e53ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766833465 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3766833465
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.3714291967
Short name T540
Test name
Test status
Simulation time 39545949 ps
CPU time 1.09 seconds
Started Aug 19 05:53:54 PM PDT 24
Finished Aug 19 05:53:56 PM PDT 24
Peak memory 220176 kb
Host smart-8c0550d9-392b-4791-b6c8-fe3239ec953b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714291967 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.3714291967
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/103.edn_alert.3118593501
Short name T809
Test name
Test status
Simulation time 40763107 ps
CPU time 1.17 seconds
Started Aug 19 05:53:59 PM PDT 24
Finished Aug 19 05:54:01 PM PDT 24
Peak memory 220532 kb
Host smart-33be9d71-3771-4cb2-8c00-ac5f3136d092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118593501 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.3118593501
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/7.edn_disable.3928556518
Short name T500
Test name
Test status
Simulation time 39391592 ps
CPU time 0.85 seconds
Started Aug 19 05:52:33 PM PDT 24
Finished Aug 19 05:52:34 PM PDT 24
Peak memory 215476 kb
Host smart-e525c0ac-e0f4-44cd-9946-727e91f7e253
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928556518 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3928556518
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/65.edn_alert.349040918
Short name T2
Test name
Test status
Simulation time 62219436 ps
CPU time 1.14 seconds
Started Aug 19 05:53:44 PM PDT 24
Finished Aug 19 05:53:45 PM PDT 24
Peak memory 219812 kb
Host smart-bf124f80-46fc-4e82-bdc7-51d1674f72b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349040918 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.349040918
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/11.edn_intr.1201244671
Short name T31
Test name
Test status
Simulation time 25465288 ps
CPU time 1 seconds
Started Aug 19 05:52:54 PM PDT 24
Finished Aug 19 05:52:55 PM PDT 24
Peak memory 215928 kb
Host smart-a64b2c4c-6092-44a0-8ab7-a59970bb000b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201244671 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1201244671
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.1585492609
Short name T157
Test name
Test status
Simulation time 107457368 ps
CPU time 1.06 seconds
Started Aug 19 05:52:36 PM PDT 24
Finished Aug 19 05:52:37 PM PDT 24
Peak memory 216908 kb
Host smart-eaa8995c-50a0-4af8-ae90-34cf89742dd2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585492609 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.1585492609
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2840070641
Short name T551
Test name
Test status
Simulation time 116237608 ps
CPU time 1.15 seconds
Started Aug 19 05:52:29 PM PDT 24
Finished Aug 19 05:52:30 PM PDT 24
Peak memory 216904 kb
Host smart-8c4dcf33-b2df-4aed-915a-dcc083e3c8e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840070641 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2840070641
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_disable.451422515
Short name T216
Test name
Test status
Simulation time 12996754 ps
CPU time 0.92 seconds
Started Aug 19 05:52:49 PM PDT 24
Finished Aug 19 05:52:50 PM PDT 24
Peak memory 215568 kb
Host smart-05627bfb-a8c9-4a45-ae18-75f48402cc02
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451422515 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.451422515
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/112.edn_alert.3178278262
Short name T663
Test name
Test status
Simulation time 46402879 ps
CPU time 1.2 seconds
Started Aug 19 05:54:07 PM PDT 24
Finished Aug 19 05:54:08 PM PDT 24
Peak memory 219912 kb
Host smart-a0e6ebff-dd86-4ec9-b01a-ada9cc904f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178278262 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.3178278262
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/12.edn_disable.1112475230
Short name T554
Test name
Test status
Simulation time 17944506 ps
CPU time 0.86 seconds
Started Aug 19 05:52:56 PM PDT 24
Finished Aug 19 05:52:57 PM PDT 24
Peak memory 207260 kb
Host smart-58e8ff52-2330-4cd9-add2-8a3d061ec530
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112475230 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1112475230
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/13.edn_err.837990061
Short name T195
Test name
Test status
Simulation time 77277988 ps
CPU time 0.9 seconds
Started Aug 19 05:52:44 PM PDT 24
Finished Aug 19 05:52:45 PM PDT 24
Peak memory 223972 kb
Host smart-b57bc4b7-d76d-41dd-8051-17cb1102b1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837990061 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.837990061
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/132.edn_alert.1227370894
Short name T143
Test name
Test status
Simulation time 40168464 ps
CPU time 1.09 seconds
Started Aug 19 05:54:14 PM PDT 24
Finished Aug 19 05:54:15 PM PDT 24
Peak memory 218680 kb
Host smart-6bad7c2f-ba68-493d-ae4e-7221bf2ef972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227370894 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.1227370894
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.1652327552
Short name T128
Test name
Test status
Simulation time 78966477 ps
CPU time 1.13 seconds
Started Aug 19 05:52:56 PM PDT 24
Finished Aug 19 05:52:57 PM PDT 24
Peak memory 216924 kb
Host smart-4d1fa5ea-7f60-458b-a913-d2dc220e1859
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652327552 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.1652327552
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_disable.36116293
Short name T202
Test name
Test status
Simulation time 29647032 ps
CPU time 0.82 seconds
Started Aug 19 05:52:32 PM PDT 24
Finished Aug 19 05:52:33 PM PDT 24
Peak memory 215432 kb
Host smart-d990926b-cc29-45f1-ac43-66ca53fde5e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36116293 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.36116293
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/34.edn_err.2942328021
Short name T197
Test name
Test status
Simulation time 19646365 ps
CPU time 1.21 seconds
Started Aug 19 05:53:18 PM PDT 24
Finished Aug 19 05:53:20 PM PDT 24
Peak memory 229752 kb
Host smart-a9202d46-8834-4220-88e6-d785d9a1c7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942328021 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.2942328021
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.1169844804
Short name T207
Test name
Test status
Simulation time 35367610 ps
CPU time 1.01 seconds
Started Aug 19 05:53:26 PM PDT 24
Finished Aug 19 05:53:27 PM PDT 24
Peak memory 217048 kb
Host smart-26594304-092f-42d2-9765-c8db34407675
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169844804 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.1169844804
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_alert_test.480952593
Short name T391
Test name
Test status
Simulation time 36107717 ps
CPU time 0.92 seconds
Started Aug 19 05:52:46 PM PDT 24
Finished Aug 19 05:52:47 PM PDT 24
Peak memory 206664 kb
Host smart-da352ec8-1ce9-48c1-b84f-97ba903c6fc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480952593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.480952593
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_genbits.3447531454
Short name T592
Test name
Test status
Simulation time 244278917 ps
CPU time 3.65 seconds
Started Aug 19 05:53:00 PM PDT 24
Finished Aug 19 05:53:04 PM PDT 24
Peak memory 219068 kb
Host smart-5130f646-c16a-4d1c-8ebb-ce2319d15b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447531454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3447531454
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.1712082927
Short name T330
Test name
Test status
Simulation time 386677531 ps
CPU time 4.08 seconds
Started Aug 19 05:54:08 PM PDT 24
Finished Aug 19 05:54:12 PM PDT 24
Peak memory 219708 kb
Host smart-4cf2698f-7a88-45e6-ace3-a8faf05e2c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712082927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1712082927
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.957881394
Short name T223
Test name
Test status
Simulation time 5643897906 ps
CPU time 87.47 seconds
Started Aug 19 05:52:43 PM PDT 24
Finished Aug 19 05:54:11 PM PDT 24
Peak memory 218584 kb
Host smart-6ce41350-2de8-4034-8015-c4e5686a6864
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957881394 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.957881394
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.edn_err.2793917896
Short name T285
Test name
Test status
Simulation time 52012289 ps
CPU time 1.4 seconds
Started Aug 19 05:53:05 PM PDT 24
Finished Aug 19 05:53:07 PM PDT 24
Peak memory 215740 kb
Host smart-ef897806-c818-4902-96ca-0ac116eea47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793917896 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.2793917896
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.2026613498
Short name T563
Test name
Test status
Simulation time 81072030 ps
CPU time 1.57 seconds
Started Aug 19 05:52:26 PM PDT 24
Finished Aug 19 05:52:28 PM PDT 24
Peak memory 219700 kb
Host smart-13953520-cb20-4647-8ea8-faca687d4888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026613498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.2026613498
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/270.edn_genbits.2016082623
Short name T5
Test name
Test status
Simulation time 58458205 ps
CPU time 1.25 seconds
Started Aug 19 05:54:30 PM PDT 24
Finished Aug 19 05:54:31 PM PDT 24
Peak memory 218576 kb
Host smart-24c8d329-6539-47ef-b9d6-fe522a5b5648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016082623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2016082623
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2457899149
Short name T1100
Test name
Test status
Simulation time 168369062 ps
CPU time 2.12 seconds
Started Aug 19 05:00:37 PM PDT 24
Finished Aug 19 05:00:39 PM PDT 24
Peak memory 207376 kb
Host smart-ba5e57f8-0c32-4ede-93e1-f1670e7fe3da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457899149 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2457899149
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_genbits.3895143906
Short name T293
Test name
Test status
Simulation time 47088754 ps
CPU time 1.79 seconds
Started Aug 19 05:52:36 PM PDT 24
Finished Aug 19 05:52:38 PM PDT 24
Peak memory 220568 kb
Host smart-395ac44a-e752-42f2-92da-0882e68ebd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895143906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.3895143906
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_regwen.1898619429
Short name T322
Test name
Test status
Simulation time 18953646 ps
CPU time 1.01 seconds
Started Aug 19 05:52:29 PM PDT 24
Finished Aug 19 05:52:30 PM PDT 24
Peak memory 207172 kb
Host smart-da9ddc7d-f9ed-4e53-b52b-32c98c05e992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898619429 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.1898619429
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.2859707457
Short name T822
Test name
Test status
Simulation time 19036252278 ps
CPU time 117.18 seconds
Started Aug 19 05:52:55 PM PDT 24
Finished Aug 19 05:54:52 PM PDT 24
Peak memory 217892 kb
Host smart-02293a6f-7ada-41b4-902d-b4f0535724b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859707457 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.2859707457
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/138.edn_genbits.1553479364
Short name T281
Test name
Test status
Simulation time 46497299 ps
CPU time 1.53 seconds
Started Aug 19 05:54:11 PM PDT 24
Finished Aug 19 05:54:13 PM PDT 24
Peak memory 218560 kb
Host smart-f471df75-32a0-4e1b-ba52-59267dd8efd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553479364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1553479364
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.612359256
Short name T302
Test name
Test status
Simulation time 67416425 ps
CPU time 1.29 seconds
Started Aug 19 05:54:14 PM PDT 24
Finished Aug 19 05:54:16 PM PDT 24
Peak memory 219084 kb
Host smart-f6b990be-2b6f-4e22-b478-c3425d420fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612359256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.612359256
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.4033285587
Short name T307
Test name
Test status
Simulation time 56944492 ps
CPU time 1.29 seconds
Started Aug 19 05:54:26 PM PDT 24
Finished Aug 19 05:54:27 PM PDT 24
Peak memory 219032 kb
Host smart-5b3c2988-73fe-4a72-8908-3b662d0861a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033285587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.4033285587
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_genbits.4273069901
Short name T305
Test name
Test status
Simulation time 48446251 ps
CPU time 1.27 seconds
Started Aug 19 05:53:14 PM PDT 24
Finished Aug 19 05:53:15 PM PDT 24
Peak memory 217684 kb
Host smart-28301248-4f77-4c36-b133-74fdb685aba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273069901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.4273069901
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.3534353700
Short name T310
Test name
Test status
Simulation time 350474365 ps
CPU time 2.88 seconds
Started Aug 19 05:54:43 PM PDT 24
Finished Aug 19 05:54:45 PM PDT 24
Peak memory 220792 kb
Host smart-b1b6a6c6-448d-4e19-b091-9a4895933c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534353700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.3534353700
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.297128281
Short name T282
Test name
Test status
Simulation time 50210475 ps
CPU time 1.08 seconds
Started Aug 19 05:53:33 PM PDT 24
Finished Aug 19 05:53:34 PM PDT 24
Peak memory 218636 kb
Host smart-4bdfcb95-a7af-4a4d-989f-b2f3d83dbcd9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297128281 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_di
sable_auto_req_mode.297128281
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_genbits.1073101977
Short name T316
Test name
Test status
Simulation time 54147341 ps
CPU time 1.48 seconds
Started Aug 19 05:53:31 PM PDT 24
Finished Aug 19 05:53:33 PM PDT 24
Peak memory 215480 kb
Host smart-ce56f16d-431d-4aeb-ad9e-a1b38f85fc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073101977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1073101977
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.2534559667
Short name T32
Test name
Test status
Simulation time 33540951 ps
CPU time 0.89 seconds
Started Aug 19 05:52:54 PM PDT 24
Finished Aug 19 05:52:55 PM PDT 24
Peak memory 215692 kb
Host smart-83814f6b-16f1-46c5-ad6a-1f5631723a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534559667 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2534559667
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/1.edn_intr.3221751498
Short name T806
Test name
Test status
Simulation time 21356455 ps
CPU time 1.12 seconds
Started Aug 19 05:52:29 PM PDT 24
Finished Aug 19 05:52:31 PM PDT 24
Peak memory 215856 kb
Host smart-04636b06-4028-403c-84c8-b491f6c533e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221751498 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.3221751498
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/10.edn_err.981980470
Short name T456
Test name
Test status
Simulation time 18894070 ps
CPU time 1.07 seconds
Started Aug 19 05:52:50 PM PDT 24
Finished Aug 19 05:52:51 PM PDT 24
Peak memory 218660 kb
Host smart-343275f4-3c09-46e2-9292-df7952e298cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981980470 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.981980470
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1586062224
Short name T1058
Test name
Test status
Simulation time 24356086 ps
CPU time 1.17 seconds
Started Aug 19 04:59:42 PM PDT 24
Finished Aug 19 04:59:43 PM PDT 24
Peak memory 207108 kb
Host smart-166b3a50-627d-4a68-aaea-9e5479416f7a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586062224 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1586062224
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2103471921
Short name T1028
Test name
Test status
Simulation time 2139145737 ps
CPU time 6.39 seconds
Started Aug 19 04:59:40 PM PDT 24
Finished Aug 19 04:59:46 PM PDT 24
Peak memory 206988 kb
Host smart-5868734e-c446-4fd7-b3a3-2af85c760bc1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103471921 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2103471921
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3132473269
Short name T255
Test name
Test status
Simulation time 23819341 ps
CPU time 0.89 seconds
Started Aug 19 04:59:42 PM PDT 24
Finished Aug 19 04:59:43 PM PDT 24
Peak memory 207112 kb
Host smart-6a4de7cb-5d14-47ea-adfe-c6b5802100d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132473269 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.3132473269
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3409542842
Short name T1055
Test name
Test status
Simulation time 48973682 ps
CPU time 1.39 seconds
Started Aug 19 04:59:40 PM PDT 24
Finished Aug 19 04:59:41 PM PDT 24
Peak memory 215372 kb
Host smart-cc211946-48c3-4cba-a7da-f465b45b98c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409542842 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3409542842
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.1642845755
Short name T268
Test name
Test status
Simulation time 21724776 ps
CPU time 0.88 seconds
Started Aug 19 04:59:38 PM PDT 24
Finished Aug 19 04:59:39 PM PDT 24
Peak memory 207080 kb
Host smart-f2bdf16a-75c1-4db0-87d9-1b889aad543b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642845755 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1642845755
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.3117327075
Short name T1066
Test name
Test status
Simulation time 26580072 ps
CPU time 0.9 seconds
Started Aug 19 04:59:31 PM PDT 24
Finished Aug 19 04:59:32 PM PDT 24
Peak memory 206940 kb
Host smart-a1912d67-6098-4102-a311-d0e0e2834b07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117327075 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.3117327075
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.4270216185
Short name T1025
Test name
Test status
Simulation time 28877530 ps
CPU time 0.94 seconds
Started Aug 19 04:59:39 PM PDT 24
Finished Aug 19 04:59:40 PM PDT 24
Peak memory 207232 kb
Host smart-eee935cb-03c0-40f2-a887-7685d21fff7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270216185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.4270216185
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.648273338
Short name T991
Test name
Test status
Simulation time 99563439 ps
CPU time 3.51 seconds
Started Aug 19 04:59:31 PM PDT 24
Finished Aug 19 04:59:35 PM PDT 24
Peak memory 215320 kb
Host smart-323005bd-a901-420e-a664-501665131c43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648273338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.648273338
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.501922282
Short name T1062
Test name
Test status
Simulation time 105499834 ps
CPU time 1.61 seconds
Started Aug 19 04:59:29 PM PDT 24
Finished Aug 19 04:59:30 PM PDT 24
Peak memory 207148 kb
Host smart-d84d9a28-1e6d-4b6d-9c6c-6a9f8151b211
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501922282 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.501922282
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3571789992
Short name T258
Test name
Test status
Simulation time 35295054 ps
CPU time 1.24 seconds
Started Aug 19 04:59:41 PM PDT 24
Finished Aug 19 04:59:43 PM PDT 24
Peak memory 206988 kb
Host smart-33558036-37b7-4fde-8c9e-3cd402c97447
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571789992 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.3571789992
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.807199189
Short name T1011
Test name
Test status
Simulation time 447243638 ps
CPU time 3.68 seconds
Started Aug 19 04:59:44 PM PDT 24
Finished Aug 19 04:59:47 PM PDT 24
Peak memory 207016 kb
Host smart-780155f0-c979-4d42-9071-b054538c2709
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807199189 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.807199189
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.4033475275
Short name T260
Test name
Test status
Simulation time 25735587 ps
CPU time 0.92 seconds
Started Aug 19 04:59:40 PM PDT 24
Finished Aug 19 04:59:41 PM PDT 24
Peak memory 207040 kb
Host smart-ba1afbb3-c950-44a9-a896-28d7a1a94029
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033475275 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.4033475275
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.4132803822
Short name T1085
Test name
Test status
Simulation time 32095549 ps
CPU time 1.09 seconds
Started Aug 19 04:59:40 PM PDT 24
Finished Aug 19 04:59:41 PM PDT 24
Peak memory 216960 kb
Host smart-32bc5a9c-b532-4149-8504-7022c019236b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132803822 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.4132803822
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.3581646478
Short name T259
Test name
Test status
Simulation time 11242799 ps
CPU time 0.85 seconds
Started Aug 19 04:59:41 PM PDT 24
Finished Aug 19 04:59:42 PM PDT 24
Peak memory 207068 kb
Host smart-c2b06306-8795-4b88-ab76-15210d17a430
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581646478 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3581646478
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.2384226352
Short name T983
Test name
Test status
Simulation time 14735057 ps
CPU time 0.9 seconds
Started Aug 19 04:59:41 PM PDT 24
Finished Aug 19 04:59:42 PM PDT 24
Peak memory 206956 kb
Host smart-136468c5-e29b-4f6f-812d-f284d2e48fbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384226352 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.2384226352
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3453798941
Short name T1115
Test name
Test status
Simulation time 235750007 ps
CPU time 1.12 seconds
Started Aug 19 04:59:41 PM PDT 24
Finished Aug 19 04:59:43 PM PDT 24
Peak memory 207132 kb
Host smart-4d077d73-391e-4271-bd0d-4db6ae6fcb25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453798941 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.3453798941
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.2472237488
Short name T1000
Test name
Test status
Simulation time 42993585 ps
CPU time 1.91 seconds
Started Aug 19 04:59:41 PM PDT 24
Finished Aug 19 04:59:43 PM PDT 24
Peak memory 215360 kb
Host smart-18a0b422-cf8d-426c-99c5-a049a0935a8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472237488 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2472237488
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3925655059
Short name T280
Test name
Test status
Simulation time 128560271 ps
CPU time 2.89 seconds
Started Aug 19 04:59:41 PM PDT 24
Finished Aug 19 04:59:44 PM PDT 24
Peak memory 207304 kb
Host smart-ede0f7fe-5b1f-4bee-88b1-094c6eab4b29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925655059 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3925655059
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3850572938
Short name T1077
Test name
Test status
Simulation time 105452766 ps
CPU time 1.7 seconds
Started Aug 19 05:00:24 PM PDT 24
Finished Aug 19 05:00:26 PM PDT 24
Peak memory 215408 kb
Host smart-b9d1d6c6-09f5-4496-881c-9c6b798ad92e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850572938 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3850572938
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.3868750225
Short name T257
Test name
Test status
Simulation time 76360259 ps
CPU time 0.86 seconds
Started Aug 19 05:00:24 PM PDT 24
Finished Aug 19 05:00:25 PM PDT 24
Peak memory 207016 kb
Host smart-2d32cd7c-5f8e-466a-91c5-d5982ac89a4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868750225 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3868750225
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.1165004869
Short name T1039
Test name
Test status
Simulation time 31524947 ps
CPU time 0.78 seconds
Started Aug 19 05:00:24 PM PDT 24
Finished Aug 19 05:00:25 PM PDT 24
Peak memory 206844 kb
Host smart-f9155992-5621-4b9a-a607-f83315cc4643
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165004869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1165004869
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1264862126
Short name T1112
Test name
Test status
Simulation time 25402316 ps
CPU time 1.12 seconds
Started Aug 19 05:00:28 PM PDT 24
Finished Aug 19 05:00:29 PM PDT 24
Peak memory 207092 kb
Host smart-1c12c108-392c-4358-bf5a-9f061fcbdb46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264862126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.1264862126
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.627552306
Short name T1064
Test name
Test status
Simulation time 97900113 ps
CPU time 1.75 seconds
Started Aug 19 05:00:24 PM PDT 24
Finished Aug 19 05:00:26 PM PDT 24
Peak memory 218964 kb
Host smart-46ba8efd-a2ea-4f76-a2c9-da9331f954c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627552306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.627552306
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.438231539
Short name T1106
Test name
Test status
Simulation time 41237913 ps
CPU time 1.54 seconds
Started Aug 19 05:00:22 PM PDT 24
Finished Aug 19 05:00:24 PM PDT 24
Peak memory 207188 kb
Host smart-38f724d2-64a8-4aa5-b5ea-8867e5648b9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438231539 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.438231539
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3919880872
Short name T1079
Test name
Test status
Simulation time 25716353 ps
CPU time 1.27 seconds
Started Aug 19 05:00:35 PM PDT 24
Finished Aug 19 05:00:37 PM PDT 24
Peak memory 215420 kb
Host smart-b63ce192-72e5-45e0-b200-ce7518c8e7a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919880872 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3919880872
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.2950916694
Short name T1101
Test name
Test status
Simulation time 14077418 ps
CPU time 0.88 seconds
Started Aug 19 05:00:53 PM PDT 24
Finished Aug 19 05:00:54 PM PDT 24
Peak memory 207036 kb
Host smart-ce39dac0-0e8f-418a-b97f-c7c544eb7641
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950916694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.2950916694
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.3320756791
Short name T1065
Test name
Test status
Simulation time 43302167 ps
CPU time 0.86 seconds
Started Aug 19 05:00:37 PM PDT 24
Finished Aug 19 05:00:38 PM PDT 24
Peak memory 207008 kb
Host smart-c76c8315-9181-480f-b3bb-4a7e419b4cec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320756791 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.3320756791
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2142274682
Short name T263
Test name
Test status
Simulation time 46973748 ps
CPU time 1.1 seconds
Started Aug 19 05:00:34 PM PDT 24
Finished Aug 19 05:00:36 PM PDT 24
Peak memory 207176 kb
Host smart-d2698699-6bf4-437b-883d-9fef4306d8ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142274682 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2142274682
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.1672751367
Short name T1059
Test name
Test status
Simulation time 32104878 ps
CPU time 2.19 seconds
Started Aug 19 05:00:22 PM PDT 24
Finished Aug 19 05:00:24 PM PDT 24
Peak memory 215376 kb
Host smart-db5e9443-8575-4d10-99cb-0d30fda18e83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672751367 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1672751367
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1329689198
Short name T1030
Test name
Test status
Simulation time 84001053 ps
CPU time 0.99 seconds
Started Aug 19 05:00:38 PM PDT 24
Finished Aug 19 05:00:39 PM PDT 24
Peak memory 216784 kb
Host smart-8dac16d3-b8dd-4d7f-a353-9a39d0e1ab1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329689198 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1329689198
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.242944108
Short name T262
Test name
Test status
Simulation time 23050429 ps
CPU time 0.89 seconds
Started Aug 19 05:00:36 PM PDT 24
Finished Aug 19 05:00:37 PM PDT 24
Peak memory 207080 kb
Host smart-c470c0ed-07ca-4625-a1a3-84cadd07b93f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242944108 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.242944108
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.1144777295
Short name T1044
Test name
Test status
Simulation time 15740041 ps
CPU time 0.85 seconds
Started Aug 19 05:00:53 PM PDT 24
Finished Aug 19 05:00:54 PM PDT 24
Peak memory 206980 kb
Host smart-f1e9b598-8967-4c13-a8ea-0226f8b886cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144777295 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.1144777295
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1077820383
Short name T270
Test name
Test status
Simulation time 21067352 ps
CPU time 1.09 seconds
Started Aug 19 05:00:53 PM PDT 24
Finished Aug 19 05:00:54 PM PDT 24
Peak memory 207104 kb
Host smart-d5bc1548-8d22-4f09-9856-0b2dbf3d85d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077820383 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1077820383
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3742913309
Short name T1004
Test name
Test status
Simulation time 347640019 ps
CPU time 1.93 seconds
Started Aug 19 05:00:33 PM PDT 24
Finished Aug 19 05:00:35 PM PDT 24
Peak memory 215296 kb
Host smart-d494ce23-bdc2-40dd-989b-3aec30946ca1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742913309 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3742913309
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2960777086
Short name T1072
Test name
Test status
Simulation time 74696098 ps
CPU time 2.09 seconds
Started Aug 19 05:00:35 PM PDT 24
Finished Aug 19 05:00:38 PM PDT 24
Peak memory 207312 kb
Host smart-3c61c035-b10e-4882-bdd4-06e2500a3436
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960777086 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.2960777086
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2830264918
Short name T1026
Test name
Test status
Simulation time 211404979 ps
CPU time 1.62 seconds
Started Aug 19 05:00:48 PM PDT 24
Finished Aug 19 05:00:50 PM PDT 24
Peak memory 215428 kb
Host smart-ce97eee9-63bb-4d1d-b3c2-42667df3ffc3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830264918 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2830264918
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3012578142
Short name T1073
Test name
Test status
Simulation time 19478841 ps
CPU time 0.8 seconds
Started Aug 19 05:00:35 PM PDT 24
Finished Aug 19 05:00:36 PM PDT 24
Peak memory 206844 kb
Host smart-1f123c4a-fa5a-4703-a5f6-ad7fa68fe244
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012578142 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3012578142
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.2796948827
Short name T985
Test name
Test status
Simulation time 54394346 ps
CPU time 0.89 seconds
Started Aug 19 05:00:35 PM PDT 24
Finished Aug 19 05:00:36 PM PDT 24
Peak memory 206960 kb
Host smart-45f6bbb1-ca1c-4578-8e08-b5aa447b7707
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796948827 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2796948827
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2250989528
Short name T1020
Test name
Test status
Simulation time 112568138 ps
CPU time 1.32 seconds
Started Aug 19 05:00:38 PM PDT 24
Finished Aug 19 05:00:40 PM PDT 24
Peak memory 207232 kb
Host smart-d65d815c-ae48-4904-97b5-e3d2ad4c0c55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250989528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2250989528
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.4029259695
Short name T1069
Test name
Test status
Simulation time 103342721 ps
CPU time 3.89 seconds
Started Aug 19 05:00:37 PM PDT 24
Finished Aug 19 05:00:41 PM PDT 24
Peak memory 215388 kb
Host smart-ac6a3477-5014-4fcf-a90c-bc924f97e6ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029259695 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.4029259695
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.4095555324
Short name T1108
Test name
Test status
Simulation time 160105460 ps
CPU time 1.34 seconds
Started Aug 19 05:00:45 PM PDT 24
Finished Aug 19 05:00:46 PM PDT 24
Peak memory 223344 kb
Host smart-60aa35d2-c78e-4b23-8943-59941b0842de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095555324 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.4095555324
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.737264923
Short name T986
Test name
Test status
Simulation time 14038941 ps
CPU time 0.86 seconds
Started Aug 19 05:00:47 PM PDT 24
Finished Aug 19 05:00:48 PM PDT 24
Peak memory 206992 kb
Host smart-e34f24af-6336-42ca-98f1-0b5d72679a6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737264923 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.737264923
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3682519183
Short name T265
Test name
Test status
Simulation time 56362015 ps
CPU time 1.08 seconds
Started Aug 19 05:00:48 PM PDT 24
Finished Aug 19 05:00:50 PM PDT 24
Peak memory 207144 kb
Host smart-8087007f-a08b-48e1-a317-c2f1a10dd4b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682519183 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.3682519183
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.3712314505
Short name T1053
Test name
Test status
Simulation time 33490689 ps
CPU time 2.24 seconds
Started Aug 19 05:00:53 PM PDT 24
Finished Aug 19 05:00:55 PM PDT 24
Peak memory 215308 kb
Host smart-18ddc4ff-2c49-49b9-998b-c877ab5abdfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712314505 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3712314505
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.121353341
Short name T279
Test name
Test status
Simulation time 88433695 ps
CPU time 1.67 seconds
Started Aug 19 05:00:47 PM PDT 24
Finished Aug 19 05:00:49 PM PDT 24
Peak memory 207376 kb
Host smart-b2c1109d-0702-40aa-98e6-76af03f5269c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121353341 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.121353341
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2205838614
Short name T1102
Test name
Test status
Simulation time 151527704 ps
CPU time 1.54 seconds
Started Aug 19 05:00:47 PM PDT 24
Finished Aug 19 05:00:48 PM PDT 24
Peak memory 215440 kb
Host smart-f6102d70-9c45-495e-9a93-7154dd2c1c17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205838614 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2205838614
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1367471682
Short name T1002
Test name
Test status
Simulation time 57410732 ps
CPU time 0.88 seconds
Started Aug 19 05:00:50 PM PDT 24
Finished Aug 19 05:00:51 PM PDT 24
Peak memory 207048 kb
Host smart-5c377186-4469-4103-b1b7-2b85f1aa64e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367471682 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1367471682
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.1733656937
Short name T1008
Test name
Test status
Simulation time 26325359 ps
CPU time 0.91 seconds
Started Aug 19 05:00:47 PM PDT 24
Finished Aug 19 05:00:48 PM PDT 24
Peak memory 206996 kb
Host smart-97c3046f-43f3-4c57-b4f2-b5953aaa4f0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733656937 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1733656937
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2025033040
Short name T267
Test name
Test status
Simulation time 38944394 ps
CPU time 1.58 seconds
Started Aug 19 05:00:48 PM PDT 24
Finished Aug 19 05:00:50 PM PDT 24
Peak memory 207124 kb
Host smart-36898b85-ceeb-4323-a39f-377f45c33669
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025033040 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.2025033040
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.3491171562
Short name T1104
Test name
Test status
Simulation time 25219534 ps
CPU time 1.6 seconds
Started Aug 19 05:00:47 PM PDT 24
Finished Aug 19 05:00:49 PM PDT 24
Peak memory 215296 kb
Host smart-8999b1e6-3277-4f74-bcc2-288388542d43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491171562 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.3491171562
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2897429067
Short name T1012
Test name
Test status
Simulation time 58076315 ps
CPU time 1.79 seconds
Started Aug 19 05:00:46 PM PDT 24
Finished Aug 19 05:00:48 PM PDT 24
Peak memory 215356 kb
Host smart-d617c819-a938-4d45-afc2-1653817c72da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897429067 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2897429067
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.184077771
Short name T1032
Test name
Test status
Simulation time 18683863 ps
CPU time 1.09 seconds
Started Aug 19 05:00:59 PM PDT 24
Finished Aug 19 05:01:01 PM PDT 24
Peak memory 215308 kb
Host smart-8b6e8343-89ba-4827-ac8e-182b8d2eb48c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184077771 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.184077771
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.3358238815
Short name T261
Test name
Test status
Simulation time 17070691 ps
CPU time 0.97 seconds
Started Aug 19 05:00:59 PM PDT 24
Finished Aug 19 05:01:01 PM PDT 24
Peak memory 207056 kb
Host smart-b994a981-73b8-40e7-a6b3-ca6e36c49ae6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358238815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.3358238815
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.1243308284
Short name T1097
Test name
Test status
Simulation time 14556518 ps
CPU time 0.89 seconds
Started Aug 19 05:01:00 PM PDT 24
Finished Aug 19 05:01:01 PM PDT 24
Peak memory 206916 kb
Host smart-d00da1fb-a350-4a6e-b2cf-193fa1956fdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243308284 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.1243308284
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1659692410
Short name T264
Test name
Test status
Simulation time 81134397 ps
CPU time 1.1 seconds
Started Aug 19 05:00:58 PM PDT 24
Finished Aug 19 05:00:59 PM PDT 24
Peak memory 207212 kb
Host smart-7466491d-a5d0-48c2-bb28-a4552b9d135d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659692410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.1659692410
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.3694153960
Short name T1034
Test name
Test status
Simulation time 32379191 ps
CPU time 1.5 seconds
Started Aug 19 05:00:48 PM PDT 24
Finished Aug 19 05:00:50 PM PDT 24
Peak memory 215188 kb
Host smart-b1b9bd4a-e4fc-452f-8bb2-b70c1db50328
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694153960 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3694153960
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.4257905177
Short name T1099
Test name
Test status
Simulation time 73664262 ps
CPU time 1.99 seconds
Started Aug 19 05:00:46 PM PDT 24
Finished Aug 19 05:00:48 PM PDT 24
Peak memory 207268 kb
Host smart-10d17559-7f6c-48cb-a19c-d3d4b6c65008
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257905177 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.4257905177
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1171251511
Short name T980
Test name
Test status
Simulation time 25872667 ps
CPU time 1.07 seconds
Started Aug 19 05:00:57 PM PDT 24
Finished Aug 19 05:00:58 PM PDT 24
Peak memory 216752 kb
Host smart-fcc8979e-2b22-436f-a467-b679901015d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171251511 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.1171251511
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.2895917193
Short name T1113
Test name
Test status
Simulation time 42261366 ps
CPU time 0.93 seconds
Started Aug 19 05:00:57 PM PDT 24
Finished Aug 19 05:00:58 PM PDT 24
Peak memory 206980 kb
Host smart-14c61095-c4cc-485f-b66e-cbb9a04a2c43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895917193 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2895917193
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.3168109787
Short name T982
Test name
Test status
Simulation time 23322056 ps
CPU time 0.8 seconds
Started Aug 19 05:01:04 PM PDT 24
Finished Aug 19 05:01:05 PM PDT 24
Peak memory 207040 kb
Host smart-c02300e1-b8c7-47cb-83a8-fc01bfb9a130
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168109787 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.3168109787
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.706554375
Short name T1057
Test name
Test status
Simulation time 61080577 ps
CPU time 1.49 seconds
Started Aug 19 05:00:59 PM PDT 24
Finished Aug 19 05:01:00 PM PDT 24
Peak memory 207148 kb
Host smart-4b396503-3bc4-4778-8ced-8e6b1458970b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706554375 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_ou
tstanding.706554375
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.3109014334
Short name T1029
Test name
Test status
Simulation time 119548361 ps
CPU time 2.45 seconds
Started Aug 19 05:00:57 PM PDT 24
Finished Aug 19 05:00:59 PM PDT 24
Peak memory 215376 kb
Host smart-a759592d-bce1-4249-b2a2-96ebd9e82ea3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109014334 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3109014334
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3506857372
Short name T1095
Test name
Test status
Simulation time 274991276 ps
CPU time 2.22 seconds
Started Aug 19 05:00:57 PM PDT 24
Finished Aug 19 05:00:59 PM PDT 24
Peak memory 215356 kb
Host smart-e7ae4eab-3bfd-4903-94ad-1c773bd3df61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506857372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3506857372
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2662794802
Short name T996
Test name
Test status
Simulation time 51222752 ps
CPU time 0.95 seconds
Started Aug 19 05:01:09 PM PDT 24
Finished Aug 19 05:01:10 PM PDT 24
Peak memory 207224 kb
Host smart-8d2a05f4-805a-46cb-96a8-a4edf1d26339
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662794802 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2662794802
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.3252023821
Short name T989
Test name
Test status
Simulation time 16867977 ps
CPU time 1.01 seconds
Started Aug 19 05:00:57 PM PDT 24
Finished Aug 19 05:00:58 PM PDT 24
Peak memory 207008 kb
Host smart-b47a2b4c-4f97-4b5b-96f8-97624448f06b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252023821 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.3252023821
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.584418426
Short name T1110
Test name
Test status
Simulation time 44932105 ps
CPU time 0.8 seconds
Started Aug 19 05:00:58 PM PDT 24
Finished Aug 19 05:00:59 PM PDT 24
Peak memory 206792 kb
Host smart-41f7971f-f6f8-4408-ae27-4db7d70dc8eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584418426 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.584418426
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1379645601
Short name T1068
Test name
Test status
Simulation time 22868926 ps
CPU time 1.01 seconds
Started Aug 19 05:00:59 PM PDT 24
Finished Aug 19 05:01:01 PM PDT 24
Peak memory 207232 kb
Host smart-a71e9a62-6236-4707-9dd1-36654e6b1799
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379645601 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.1379645601
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.1274084848
Short name T1045
Test name
Test status
Simulation time 24084145 ps
CPU time 1.75 seconds
Started Aug 19 05:00:57 PM PDT 24
Finished Aug 19 05:00:59 PM PDT 24
Peak memory 215248 kb
Host smart-7a8127a1-639b-4b20-9009-662aa4d452ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274084848 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.1274084848
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1206235949
Short name T1007
Test name
Test status
Simulation time 197784779 ps
CPU time 2.53 seconds
Started Aug 19 05:01:05 PM PDT 24
Finished Aug 19 05:01:07 PM PDT 24
Peak memory 207232 kb
Host smart-8a71d60c-9eb1-46d0-8c50-4d8ecb7871d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206235949 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1206235949
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.496873625
Short name T1037
Test name
Test status
Simulation time 193937520 ps
CPU time 1.58 seconds
Started Aug 19 05:01:00 PM PDT 24
Finished Aug 19 05:01:01 PM PDT 24
Peak memory 220204 kb
Host smart-0dfea8fd-7e8a-4ee6-aaae-36bef6455f1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496873625 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.496873625
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2302381000
Short name T1031
Test name
Test status
Simulation time 44565463 ps
CPU time 0.9 seconds
Started Aug 19 05:00:58 PM PDT 24
Finished Aug 19 05:00:59 PM PDT 24
Peak memory 207080 kb
Host smart-3a9e18ad-3521-4ee4-9067-1697fbb5c911
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302381000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2302381000
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.1923394567
Short name T1080
Test name
Test status
Simulation time 37911309 ps
CPU time 0.82 seconds
Started Aug 19 05:01:00 PM PDT 24
Finished Aug 19 05:01:01 PM PDT 24
Peak memory 206920 kb
Host smart-61a8debf-26f0-4a66-969b-a47d73ebaea9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923394567 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.1923394567
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3936098521
Short name T1118
Test name
Test status
Simulation time 217911589 ps
CPU time 1.46 seconds
Started Aug 19 05:00:58 PM PDT 24
Finished Aug 19 05:01:00 PM PDT 24
Peak memory 207212 kb
Host smart-75a815d8-98eb-45de-a29a-5dbb10e2f5e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936098521 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.3936098521
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1221264620
Short name T1071
Test name
Test status
Simulation time 175669864 ps
CPU time 3.65 seconds
Started Aug 19 05:00:59 PM PDT 24
Finished Aug 19 05:01:03 PM PDT 24
Peak memory 215384 kb
Host smart-7fe4077a-a52b-4351-9bb2-f9212a905509
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221264620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1221264620
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1631383041
Short name T288
Test name
Test status
Simulation time 78364919 ps
CPU time 1.61 seconds
Started Aug 19 05:00:58 PM PDT 24
Finished Aug 19 05:01:00 PM PDT 24
Peak memory 207096 kb
Host smart-47e91906-a6c3-4b4c-a95c-1dc48ed0bdc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631383041 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1631383041
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3444320637
Short name T1105
Test name
Test status
Simulation time 65545456 ps
CPU time 1.42 seconds
Started Aug 19 04:59:51 PM PDT 24
Finished Aug 19 04:59:53 PM PDT 24
Peak memory 207056 kb
Host smart-c723c848-46e9-4a44-bd28-f9f60e4f35bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444320637 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.3444320637
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3848488754
Short name T1017
Test name
Test status
Simulation time 730645102 ps
CPU time 3.13 seconds
Started Aug 19 04:59:53 PM PDT 24
Finished Aug 19 04:59:57 PM PDT 24
Peak memory 207096 kb
Host smart-f5738d37-1097-4ff3-84eb-e3d7d209b02f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848488754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3848488754
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3754927327
Short name T253
Test name
Test status
Simulation time 20063993 ps
CPU time 1.02 seconds
Started Aug 19 04:59:51 PM PDT 24
Finished Aug 19 04:59:52 PM PDT 24
Peak memory 207020 kb
Host smart-c948d4fc-0a3b-4987-a54b-9ad324fcafb7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754927327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3754927327
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.4259217136
Short name T1061
Test name
Test status
Simulation time 258786439 ps
CPU time 1.55 seconds
Started Aug 19 04:59:50 PM PDT 24
Finished Aug 19 04:59:52 PM PDT 24
Peak memory 215420 kb
Host smart-bd37457f-c022-4f3c-96ca-6710e1c40aeb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259217136 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.4259217136
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.3552696139
Short name T1075
Test name
Test status
Simulation time 38294065 ps
CPU time 0.84 seconds
Started Aug 19 04:59:51 PM PDT 24
Finished Aug 19 04:59:52 PM PDT 24
Peak memory 206924 kb
Host smart-55a78a4e-4d85-4dfd-802c-a3ec3d8cd836
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552696139 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3552696139
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1113730086
Short name T1019
Test name
Test status
Simulation time 44358135 ps
CPU time 0.81 seconds
Started Aug 19 04:59:51 PM PDT 24
Finished Aug 19 04:59:52 PM PDT 24
Peak memory 206996 kb
Host smart-8a1a3748-77ab-403b-b690-ceac5c0342c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113730086 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1113730086
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1904511238
Short name T271
Test name
Test status
Simulation time 61200254 ps
CPU time 1.08 seconds
Started Aug 19 04:59:50 PM PDT 24
Finished Aug 19 04:59:51 PM PDT 24
Peak memory 207200 kb
Host smart-2c2084c6-28e1-45bd-8068-c401d1d3ffd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904511238 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1904511238
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.3976325287
Short name T992
Test name
Test status
Simulation time 76564866 ps
CPU time 3.04 seconds
Started Aug 19 04:59:39 PM PDT 24
Finished Aug 19 04:59:42 PM PDT 24
Peak memory 215332 kb
Host smart-7143df8c-a463-4f9d-ae03-5cb280bbc53d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976325287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.3976325287
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3349716092
Short name T1084
Test name
Test status
Simulation time 172816622 ps
CPU time 2.45 seconds
Started Aug 19 04:59:40 PM PDT 24
Finished Aug 19 04:59:42 PM PDT 24
Peak memory 207236 kb
Host smart-fe93bdeb-bf25-49ff-bcd3-004833735aee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349716092 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3349716092
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.2014959943
Short name T1003
Test name
Test status
Simulation time 26019088 ps
CPU time 0.85 seconds
Started Aug 19 05:00:59 PM PDT 24
Finished Aug 19 05:00:59 PM PDT 24
Peak memory 207004 kb
Host smart-822490fd-edd6-4019-98bd-01ad2d0bb133
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014959943 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.2014959943
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.959019303
Short name T995
Test name
Test status
Simulation time 15000944 ps
CPU time 0.87 seconds
Started Aug 19 05:00:59 PM PDT 24
Finished Aug 19 05:00:59 PM PDT 24
Peak memory 207004 kb
Host smart-507b5b89-a076-4afa-abcd-1ab936ecd798
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959019303 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.959019303
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.3482970827
Short name T1050
Test name
Test status
Simulation time 13273200 ps
CPU time 0.84 seconds
Started Aug 19 05:01:11 PM PDT 24
Finished Aug 19 05:01:12 PM PDT 24
Peak memory 206968 kb
Host smart-c59b903c-2b17-4ca1-a4a7-8164f0c0afd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482970827 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3482970827
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.452847233
Short name T999
Test name
Test status
Simulation time 61151228 ps
CPU time 0.84 seconds
Started Aug 19 05:01:12 PM PDT 24
Finished Aug 19 05:01:13 PM PDT 24
Peak memory 206996 kb
Host smart-4444f105-255e-48c6-a3d1-ac3ee2eaebc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452847233 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.452847233
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.947593842
Short name T1056
Test name
Test status
Simulation time 15954573 ps
CPU time 0.94 seconds
Started Aug 19 05:01:14 PM PDT 24
Finished Aug 19 05:01:15 PM PDT 24
Peak memory 207016 kb
Host smart-73daf92f-c384-42b6-bf2d-7fe193494f62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947593842 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.947593842
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.2179045165
Short name T1010
Test name
Test status
Simulation time 72311540 ps
CPU time 0.91 seconds
Started Aug 19 05:01:14 PM PDT 24
Finished Aug 19 05:01:15 PM PDT 24
Peak memory 206960 kb
Host smart-c32018b9-0958-42b6-96e3-1a4008b6124b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179045165 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2179045165
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2802192201
Short name T1094
Test name
Test status
Simulation time 12393326 ps
CPU time 0.86 seconds
Started Aug 19 05:01:13 PM PDT 24
Finished Aug 19 05:01:14 PM PDT 24
Peak memory 206808 kb
Host smart-51a66967-11fd-49e8-b13c-c128f50f6582
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802192201 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2802192201
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.2377548206
Short name T1107
Test name
Test status
Simulation time 28377370 ps
CPU time 0.93 seconds
Started Aug 19 05:01:13 PM PDT 24
Finished Aug 19 05:01:14 PM PDT 24
Peak memory 206936 kb
Host smart-c61a792f-3207-4ff5-a338-9b83e63a0779
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377548206 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.2377548206
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.4261434902
Short name T1036
Test name
Test status
Simulation time 25146077 ps
CPU time 0.92 seconds
Started Aug 19 05:01:12 PM PDT 24
Finished Aug 19 05:01:13 PM PDT 24
Peak memory 206948 kb
Host smart-91a90f0c-4475-4192-b5a9-eb39d38cbd9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261434902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.4261434902
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2932424947
Short name T1006
Test name
Test status
Simulation time 15269819 ps
CPU time 0.93 seconds
Started Aug 19 05:01:14 PM PDT 24
Finished Aug 19 05:01:15 PM PDT 24
Peak memory 207008 kb
Host smart-179ee839-8ffc-4817-8fb2-af632836ae38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932424947 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2932424947
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3929544489
Short name T1024
Test name
Test status
Simulation time 37141962 ps
CPU time 1.56 seconds
Started Aug 19 05:00:04 PM PDT 24
Finished Aug 19 05:00:07 PM PDT 24
Peak memory 207084 kb
Host smart-aaa1eb04-9a5c-448d-840c-d91dc8182c3c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929544489 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3929544489
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.4050303764
Short name T984
Test name
Test status
Simulation time 342913108 ps
CPU time 5.23 seconds
Started Aug 19 04:59:58 PM PDT 24
Finished Aug 19 05:00:03 PM PDT 24
Peak memory 207088 kb
Host smart-eceaee35-58d5-4ef9-9f84-673e59548643
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050303764 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.4050303764
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2457160033
Short name T1090
Test name
Test status
Simulation time 35828337 ps
CPU time 0.91 seconds
Started Aug 19 04:59:58 PM PDT 24
Finished Aug 19 04:59:59 PM PDT 24
Peak memory 207024 kb
Host smart-4e632bae-1569-4ae2-984e-ced8bf143ad2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457160033 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2457160033
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3896837533
Short name T1092
Test name
Test status
Simulation time 111070349 ps
CPU time 0.99 seconds
Started Aug 19 05:00:03 PM PDT 24
Finished Aug 19 05:00:07 PM PDT 24
Peak memory 207172 kb
Host smart-aeb88154-66fd-4965-9181-65c453af7a52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896837533 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3896837533
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.254261811
Short name T1096
Test name
Test status
Simulation time 20525369 ps
CPU time 0.86 seconds
Started Aug 19 04:59:51 PM PDT 24
Finished Aug 19 04:59:52 PM PDT 24
Peak memory 207076 kb
Host smart-d3c49162-099b-435c-8ed5-e22f5cd4b03c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254261811 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.254261811
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.3171582278
Short name T1076
Test name
Test status
Simulation time 27449158 ps
CPU time 0.87 seconds
Started Aug 19 04:59:58 PM PDT 24
Finished Aug 19 04:59:59 PM PDT 24
Peak memory 206960 kb
Host smart-5645eded-993a-4f35-ad43-fd11445980d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171582278 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3171582278
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.853768813
Short name T1033
Test name
Test status
Simulation time 156491404 ps
CPU time 1.08 seconds
Started Aug 19 05:00:03 PM PDT 24
Finished Aug 19 05:00:07 PM PDT 24
Peak memory 207208 kb
Host smart-838efe20-f33c-4524-9596-79737fb8a333
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853768813 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_out
standing.853768813
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.4131245604
Short name T1051
Test name
Test status
Simulation time 86909851 ps
CPU time 3.41 seconds
Started Aug 19 04:59:50 PM PDT 24
Finished Aug 19 04:59:53 PM PDT 24
Peak memory 215360 kb
Host smart-97c399e7-f6f8-42b6-b363-391e7ef0d534
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131245604 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.4131245604
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.418147597
Short name T1048
Test name
Test status
Simulation time 58060892 ps
CPU time 1.78 seconds
Started Aug 19 04:59:50 PM PDT 24
Finished Aug 19 04:59:52 PM PDT 24
Peak memory 207300 kb
Host smart-fc3e78e1-4fa2-4d72-8844-5593947f38a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418147597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.418147597
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.3029356912
Short name T998
Test name
Test status
Simulation time 41664459 ps
CPU time 0.8 seconds
Started Aug 19 05:01:13 PM PDT 24
Finished Aug 19 05:01:14 PM PDT 24
Peak memory 206788 kb
Host smart-28c621d7-160a-4cd2-8119-cf80fb55340a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029356912 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.3029356912
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2926572111
Short name T1109
Test name
Test status
Simulation time 50775300 ps
CPU time 0.83 seconds
Started Aug 19 05:01:12 PM PDT 24
Finished Aug 19 05:01:13 PM PDT 24
Peak memory 206820 kb
Host smart-e8e6881f-de0f-46ee-8805-b4f32da0d817
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926572111 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2926572111
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.1403812956
Short name T990
Test name
Test status
Simulation time 16359403 ps
CPU time 0.96 seconds
Started Aug 19 05:01:13 PM PDT 24
Finished Aug 19 05:01:14 PM PDT 24
Peak memory 207000 kb
Host smart-b81de0a5-40d7-4bee-8a61-41ac268033c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403812956 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1403812956
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.1622580763
Short name T1082
Test name
Test status
Simulation time 14695733 ps
CPU time 0.82 seconds
Started Aug 19 05:01:12 PM PDT 24
Finished Aug 19 05:01:13 PM PDT 24
Peak memory 207000 kb
Host smart-aacaf398-e3d2-483e-aad1-aaf5c5d30b5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622580763 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.1622580763
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.217322813
Short name T1013
Test name
Test status
Simulation time 25055744 ps
CPU time 0.8 seconds
Started Aug 19 05:01:11 PM PDT 24
Finished Aug 19 05:01:12 PM PDT 24
Peak memory 206992 kb
Host smart-38a140a5-eb85-46e5-bd31-566366b1fe37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217322813 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.217322813
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.3279653839
Short name T1038
Test name
Test status
Simulation time 16544924 ps
CPU time 0.99 seconds
Started Aug 19 05:01:13 PM PDT 24
Finished Aug 19 05:01:15 PM PDT 24
Peak memory 206948 kb
Host smart-e5f8979f-111f-4a18-ad8c-4ccd923ef860
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279653839 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3279653839
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3250534541
Short name T1021
Test name
Test status
Simulation time 74477358 ps
CPU time 0.89 seconds
Started Aug 19 05:01:12 PM PDT 24
Finished Aug 19 05:01:13 PM PDT 24
Peak memory 207012 kb
Host smart-86f80131-03e4-4b69-ac1c-3783d058dc83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250534541 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3250534541
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.1881411759
Short name T994
Test name
Test status
Simulation time 25483860 ps
CPU time 0.9 seconds
Started Aug 19 05:01:12 PM PDT 24
Finished Aug 19 05:01:13 PM PDT 24
Peak memory 207012 kb
Host smart-e2674684-b102-44ee-ae35-5152a06a0e10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881411759 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1881411759
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.662565806
Short name T1114
Test name
Test status
Simulation time 18240060 ps
CPU time 0.86 seconds
Started Aug 19 05:01:15 PM PDT 24
Finished Aug 19 05:01:16 PM PDT 24
Peak memory 207008 kb
Host smart-0f34edc4-347f-40f6-a87a-8c775f8c1ebb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662565806 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.662565806
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.252018903
Short name T1074
Test name
Test status
Simulation time 51479031 ps
CPU time 0.92 seconds
Started Aug 19 05:01:12 PM PDT 24
Finished Aug 19 05:01:13 PM PDT 24
Peak memory 206992 kb
Host smart-d352b846-1bfd-4bb2-893e-9f087709bda5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252018903 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.252018903
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.479583151
Short name T1063
Test name
Test status
Simulation time 44563501 ps
CPU time 1.2 seconds
Started Aug 19 05:00:03 PM PDT 24
Finished Aug 19 05:00:07 PM PDT 24
Peak memory 207080 kb
Host smart-89ced8a3-71ba-47fc-9460-2e4d9d9c382a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479583151 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.479583151
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.364435293
Short name T1040
Test name
Test status
Simulation time 702649230 ps
CPU time 5.03 seconds
Started Aug 19 05:00:02 PM PDT 24
Finished Aug 19 05:00:11 PM PDT 24
Peak memory 207056 kb
Host smart-4536ca4d-9ba9-4c4d-97c3-23ab8c9b9dc0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364435293 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.364435293
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.656777229
Short name T1018
Test name
Test status
Simulation time 18258946 ps
CPU time 0.95 seconds
Started Aug 19 05:00:04 PM PDT 24
Finished Aug 19 05:00:07 PM PDT 24
Peak memory 207100 kb
Host smart-be8da41c-5f30-4e3b-a3a5-455343003772
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656777229 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.656777229
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2844690963
Short name T1087
Test name
Test status
Simulation time 71735032 ps
CPU time 1.1 seconds
Started Aug 19 05:00:14 PM PDT 24
Finished Aug 19 05:00:15 PM PDT 24
Peak memory 216864 kb
Host smart-0c08e6fc-dcb7-4266-a58b-3ccefdd3c0a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844690963 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.2844690963
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.964154924
Short name T256
Test name
Test status
Simulation time 13842038 ps
CPU time 0.94 seconds
Started Aug 19 05:00:02 PM PDT 24
Finished Aug 19 05:00:07 PM PDT 24
Peak memory 207048 kb
Host smart-f1fbf991-801a-4f7a-9396-a1792a789b7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964154924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.964154924
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.73621791
Short name T1001
Test name
Test status
Simulation time 19058946 ps
CPU time 0.98 seconds
Started Aug 19 05:00:02 PM PDT 24
Finished Aug 19 05:00:07 PM PDT 24
Peak memory 206944 kb
Host smart-26c80020-7ab7-4ec6-b995-04dfc14f1e56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73621791 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.73621791
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2609468068
Short name T1023
Test name
Test status
Simulation time 37366921 ps
CPU time 1.04 seconds
Started Aug 19 05:00:02 PM PDT 24
Finished Aug 19 05:00:07 PM PDT 24
Peak memory 207140 kb
Host smart-fb933f33-8caa-4f72-9fd3-e05fabaadf2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609468068 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.2609468068
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.2776198038
Short name T993
Test name
Test status
Simulation time 73283930 ps
CPU time 1.69 seconds
Started Aug 19 05:00:02 PM PDT 24
Finished Aug 19 05:00:07 PM PDT 24
Peak memory 215316 kb
Host smart-fb33c712-c5e3-4850-be14-5c0d8ac30e68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776198038 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2776198038
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3782566323
Short name T286
Test name
Test status
Simulation time 421666376 ps
CPU time 1.53 seconds
Started Aug 19 05:00:02 PM PDT 24
Finished Aug 19 05:00:07 PM PDT 24
Peak memory 207144 kb
Host smart-af315a91-3073-47a0-a9cf-065d9f76f564
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782566323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3782566323
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.2501320924
Short name T1022
Test name
Test status
Simulation time 11600064 ps
CPU time 0.86 seconds
Started Aug 19 05:01:14 PM PDT 24
Finished Aug 19 05:01:15 PM PDT 24
Peak memory 207036 kb
Host smart-f5b9bc98-028c-463a-9329-c846f27fa622
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501320924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.2501320924
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.272654254
Short name T1052
Test name
Test status
Simulation time 12065068 ps
CPU time 0.86 seconds
Started Aug 19 05:01:13 PM PDT 24
Finished Aug 19 05:01:14 PM PDT 24
Peak memory 206980 kb
Host smart-ad7d2ac4-2a68-4c80-ac2c-80058480d328
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272654254 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.272654254
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.1099016668
Short name T1009
Test name
Test status
Simulation time 45922728 ps
CPU time 0.79 seconds
Started Aug 19 05:01:14 PM PDT 24
Finished Aug 19 05:01:15 PM PDT 24
Peak memory 206792 kb
Host smart-cf418cca-467f-42b7-90b5-7d40560685ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099016668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.1099016668
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.1962178619
Short name T997
Test name
Test status
Simulation time 42881523 ps
CPU time 0.79 seconds
Started Aug 19 05:01:26 PM PDT 24
Finished Aug 19 05:01:27 PM PDT 24
Peak memory 206828 kb
Host smart-92dfc547-a977-4598-a396-a566c4ff8b11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962178619 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.1962178619
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.3032278721
Short name T1089
Test name
Test status
Simulation time 13554615 ps
CPU time 0.87 seconds
Started Aug 19 05:01:25 PM PDT 24
Finished Aug 19 05:01:26 PM PDT 24
Peak memory 207008 kb
Host smart-2742545c-b977-4b7b-83c1-2c4790afc9b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032278721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3032278721
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.333206766
Short name T1117
Test name
Test status
Simulation time 14007202 ps
CPU time 0.87 seconds
Started Aug 19 05:01:26 PM PDT 24
Finished Aug 19 05:01:27 PM PDT 24
Peak memory 207004 kb
Host smart-9350ef90-3eca-4a7c-935d-ccc974bf29c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333206766 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.333206766
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.623709736
Short name T981
Test name
Test status
Simulation time 27767747 ps
CPU time 0.86 seconds
Started Aug 19 05:01:27 PM PDT 24
Finished Aug 19 05:01:28 PM PDT 24
Peak memory 206992 kb
Host smart-82da2833-2320-481e-9e25-925a22ec06c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623709736 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.623709736
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.755876189
Short name T1067
Test name
Test status
Simulation time 12123794 ps
CPU time 0.83 seconds
Started Aug 19 05:01:25 PM PDT 24
Finished Aug 19 05:01:26 PM PDT 24
Peak memory 206956 kb
Host smart-a3af8e21-9cc4-4d1d-b356-31acd9066408
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755876189 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.755876189
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.593721082
Short name T1083
Test name
Test status
Simulation time 36556648 ps
CPU time 0.81 seconds
Started Aug 19 05:01:29 PM PDT 24
Finished Aug 19 05:01:30 PM PDT 24
Peak memory 206844 kb
Host smart-68613a74-7669-48e7-ac34-78e2127dccbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593721082 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.593721082
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.3364848488
Short name T1016
Test name
Test status
Simulation time 80474665 ps
CPU time 0.82 seconds
Started Aug 19 05:01:28 PM PDT 24
Finished Aug 19 05:01:29 PM PDT 24
Peak memory 206840 kb
Host smart-ad21b2e8-67f0-4a77-b90e-f783f1033dd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364848488 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.3364848488
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1658711922
Short name T1116
Test name
Test status
Simulation time 101845128 ps
CPU time 1.74 seconds
Started Aug 19 05:00:13 PM PDT 24
Finished Aug 19 05:00:15 PM PDT 24
Peak memory 215392 kb
Host smart-2b94904c-1036-4a3a-87e1-09ec11cabbb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658711922 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1658711922
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.1714119251
Short name T1043
Test name
Test status
Simulation time 23374361 ps
CPU time 0.9 seconds
Started Aug 19 05:00:15 PM PDT 24
Finished Aug 19 05:00:16 PM PDT 24
Peak memory 207064 kb
Host smart-cc463945-d4d1-4d24-9c5b-4cf2da7475b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714119251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.1714119251
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1623861330
Short name T1027
Test name
Test status
Simulation time 46524218 ps
CPU time 0.89 seconds
Started Aug 19 05:00:13 PM PDT 24
Finished Aug 19 05:00:14 PM PDT 24
Peak memory 206956 kb
Host smart-b465accb-0e88-48df-bb90-2b3b2e7bec92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623861330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1623861330
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1679929308
Short name T1049
Test name
Test status
Simulation time 58407655 ps
CPU time 1.13 seconds
Started Aug 19 05:00:16 PM PDT 24
Finished Aug 19 05:00:18 PM PDT 24
Peak memory 207160 kb
Host smart-a1579d5d-cb94-4ddb-94c8-e8133d268a66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679929308 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1679929308
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.3153574764
Short name T1015
Test name
Test status
Simulation time 48747267 ps
CPU time 1.98 seconds
Started Aug 19 05:00:14 PM PDT 24
Finished Aug 19 05:00:16 PM PDT 24
Peak memory 215332 kb
Host smart-806bc713-83ad-4556-a74a-e2e6494275a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153574764 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.3153574764
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.4183851353
Short name T1093
Test name
Test status
Simulation time 93434826 ps
CPU time 2.48 seconds
Started Aug 19 05:00:12 PM PDT 24
Finished Aug 19 05:00:15 PM PDT 24
Peak memory 207144 kb
Host smart-88f7c1e9-aec4-4bb9-9f91-4fc77343284c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183851353 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.4183851353
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1224195607
Short name T1005
Test name
Test status
Simulation time 64541736 ps
CPU time 1.56 seconds
Started Aug 19 05:00:14 PM PDT 24
Finished Aug 19 05:00:16 PM PDT 24
Peak memory 215448 kb
Host smart-0c9d15f2-3c06-4ee7-b4e8-9aee195bcf5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224195607 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1224195607
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.1262051753
Short name T1098
Test name
Test status
Simulation time 40370701 ps
CPU time 0.82 seconds
Started Aug 19 05:00:11 PM PDT 24
Finished Aug 19 05:00:12 PM PDT 24
Peak memory 206988 kb
Host smart-2ad1211c-9abd-4713-8470-e552b0ddabf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262051753 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1262051753
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.2126044016
Short name T1088
Test name
Test status
Simulation time 14120913 ps
CPU time 0.89 seconds
Started Aug 19 05:00:13 PM PDT 24
Finished Aug 19 05:00:15 PM PDT 24
Peak memory 207000 kb
Host smart-c96ea725-5c14-4b85-80ee-e9de07c75167
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126044016 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.2126044016
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.840929090
Short name T1042
Test name
Test status
Simulation time 18154055 ps
CPU time 1.1 seconds
Started Aug 19 05:00:19 PM PDT 24
Finished Aug 19 05:00:20 PM PDT 24
Peak memory 207132 kb
Host smart-5ccdb11e-273f-4894-9c5c-7cc61d3a556d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840929090 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out
standing.840929090
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.683054489
Short name T1078
Test name
Test status
Simulation time 208705652 ps
CPU time 2.86 seconds
Started Aug 19 05:00:12 PM PDT 24
Finished Aug 19 05:00:15 PM PDT 24
Peak memory 215348 kb
Host smart-5a528ff4-5dff-4fcc-aefb-754f5f8f9ade
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683054489 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.683054489
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.316273407
Short name T287
Test name
Test status
Simulation time 124714991 ps
CPU time 2.41 seconds
Started Aug 19 05:00:16 PM PDT 24
Finished Aug 19 05:00:19 PM PDT 24
Peak memory 207128 kb
Host smart-61a87d8b-fcfb-4836-81d7-3bbdffe1d063
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316273407 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.316273407
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.609916388
Short name T1054
Test name
Test status
Simulation time 40594252 ps
CPU time 1.12 seconds
Started Aug 19 05:00:23 PM PDT 24
Finished Aug 19 05:00:25 PM PDT 24
Peak memory 215376 kb
Host smart-aea1e1a7-2b28-4b46-a060-6fb7fc9243bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609916388 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.609916388
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1982972460
Short name T1091
Test name
Test status
Simulation time 90148603 ps
CPU time 0.82 seconds
Started Aug 19 05:00:13 PM PDT 24
Finished Aug 19 05:00:14 PM PDT 24
Peak memory 206828 kb
Host smart-d3134864-895f-4a58-8891-e80217e8b241
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982972460 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1982972460
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.805403107
Short name T987
Test name
Test status
Simulation time 23534973 ps
CPU time 0.84 seconds
Started Aug 19 05:00:13 PM PDT 24
Finished Aug 19 05:00:15 PM PDT 24
Peak memory 207096 kb
Host smart-9bc035c0-650e-4958-a8b7-24a87f0ba436
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805403107 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.805403107
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1501056719
Short name T1046
Test name
Test status
Simulation time 33274125 ps
CPU time 1.38 seconds
Started Aug 19 05:00:24 PM PDT 24
Finished Aug 19 05:00:25 PM PDT 24
Peak memory 207172 kb
Host smart-87dde756-3577-4ba1-a7af-fbaf7b75aab9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501056719 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1501056719
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.1663664428
Short name T1103
Test name
Test status
Simulation time 81555489 ps
CPU time 3.13 seconds
Started Aug 19 05:00:13 PM PDT 24
Finished Aug 19 05:00:16 PM PDT 24
Peak memory 215372 kb
Host smart-beb5ab9d-54c0-46be-a6cd-0c2a6aac9b77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663664428 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.1663664428
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3657117997
Short name T1070
Test name
Test status
Simulation time 151937790 ps
CPU time 2.46 seconds
Started Aug 19 05:00:12 PM PDT 24
Finished Aug 19 05:00:15 PM PDT 24
Peak memory 215392 kb
Host smart-5b5b5641-7f04-43bd-96c3-c6cb9c3f1457
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657117997 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.3657117997
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2377602885
Short name T1041
Test name
Test status
Simulation time 143435079 ps
CPU time 1.65 seconds
Started Aug 19 05:00:36 PM PDT 24
Finished Aug 19 05:00:38 PM PDT 24
Peak memory 215380 kb
Host smart-cc969ca2-d16c-48c8-a8cb-e8f51651da42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377602885 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.2377602885
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.592351895
Short name T1081
Test name
Test status
Simulation time 39833016 ps
CPU time 0.92 seconds
Started Aug 19 05:00:22 PM PDT 24
Finished Aug 19 05:00:23 PM PDT 24
Peak memory 207088 kb
Host smart-18128cbb-56ee-4868-a3e2-c8c34e7ccd41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592351895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.592351895
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.3558096204
Short name T1086
Test name
Test status
Simulation time 19975272 ps
CPU time 0.82 seconds
Started Aug 19 05:00:36 PM PDT 24
Finished Aug 19 05:00:37 PM PDT 24
Peak memory 206820 kb
Host smart-b40d494a-bcb9-4b98-abe7-fc830898fa01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558096204 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3558096204
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.638919442
Short name T1111
Test name
Test status
Simulation time 236091680 ps
CPU time 1.24 seconds
Started Aug 19 05:00:25 PM PDT 24
Finished Aug 19 05:00:26 PM PDT 24
Peak memory 207160 kb
Host smart-506b6518-cab9-42ec-8d37-616ccf06c51e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638919442 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_out
standing.638919442
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.3480532565
Short name T1047
Test name
Test status
Simulation time 122578442 ps
CPU time 2.73 seconds
Started Aug 19 05:00:26 PM PDT 24
Finished Aug 19 05:00:29 PM PDT 24
Peak memory 215412 kb
Host smart-6f6c1fc9-df88-492f-8b51-e687fb9500d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480532565 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3480532565
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2058045661
Short name T1060
Test name
Test status
Simulation time 269307930 ps
CPU time 2.14 seconds
Started Aug 19 05:00:24 PM PDT 24
Finished Aug 19 05:00:27 PM PDT 24
Peak memory 207372 kb
Host smart-f50200c6-40c5-4021-96e7-4fb9b14480af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058045661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2058045661
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.132102108
Short name T988
Test name
Test status
Simulation time 51942989 ps
CPU time 0.93 seconds
Started Aug 19 05:00:25 PM PDT 24
Finished Aug 19 05:00:26 PM PDT 24
Peak memory 207152 kb
Host smart-9dc3dc9e-3638-4cf3-a159-d28fca6f0000
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132102108 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.132102108
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2634099742
Short name T266
Test name
Test status
Simulation time 32685269 ps
CPU time 0.86 seconds
Started Aug 19 05:00:24 PM PDT 24
Finished Aug 19 05:00:25 PM PDT 24
Peak memory 207032 kb
Host smart-bec50d79-53e7-4ea7-9e41-a246d8573baa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634099742 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2634099742
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.3624140651
Short name T1035
Test name
Test status
Simulation time 102173691 ps
CPU time 0.85 seconds
Started Aug 19 05:00:36 PM PDT 24
Finished Aug 19 05:00:37 PM PDT 24
Peak memory 206820 kb
Host smart-fcc02f83-52a5-4de4-9323-bba517250cee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624140651 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.3624140651
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1711828133
Short name T269
Test name
Test status
Simulation time 34454808 ps
CPU time 1.09 seconds
Started Aug 19 05:00:24 PM PDT 24
Finished Aug 19 05:00:25 PM PDT 24
Peak memory 207224 kb
Host smart-18322409-396b-4de0-a7ca-11c20d2360f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711828133 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1711828133
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.1109754346
Short name T1014
Test name
Test status
Simulation time 39663208 ps
CPU time 1.54 seconds
Started Aug 19 05:00:24 PM PDT 24
Finished Aug 19 05:00:26 PM PDT 24
Peak memory 215380 kb
Host smart-7f878644-7e71-4f97-b08c-090ac9ec8336
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109754346 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1109754346
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2980607089
Short name T289
Test name
Test status
Simulation time 84893667 ps
CPU time 1.65 seconds
Started Aug 19 05:00:24 PM PDT 24
Finished Aug 19 05:00:25 PM PDT 24
Peak memory 207192 kb
Host smart-c3e3bf87-2862-4e1b-b9ea-0bc26a8cab47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980607089 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2980607089
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.2183346683
Short name T969
Test name
Test status
Simulation time 44261652 ps
CPU time 1.23 seconds
Started Aug 19 05:52:35 PM PDT 24
Finished Aug 19 05:52:36 PM PDT 24
Peak memory 221436 kb
Host smart-45d93fd7-deb5-4212-b659-bb64dec34ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183346683 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.2183346683
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.1305014554
Short name T863
Test name
Test status
Simulation time 25792807 ps
CPU time 0.88 seconds
Started Aug 19 05:52:32 PM PDT 24
Finished Aug 19 05:52:33 PM PDT 24
Peak memory 206848 kb
Host smart-ee0b2b5e-5fd9-4a70-b607-b5c8ea60009f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305014554 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.1305014554
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.2044490786
Short name T768
Test name
Test status
Simulation time 31700465 ps
CPU time 0.94 seconds
Started Aug 19 05:52:27 PM PDT 24
Finished Aug 19 05:52:28 PM PDT 24
Peak memory 215232 kb
Host smart-90917b5b-658b-4112-b2d4-cca623394fe5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044490786 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2044490786
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_err.1362424835
Short name T799
Test name
Test status
Simulation time 20232917 ps
CPU time 1.17 seconds
Started Aug 19 05:52:31 PM PDT 24
Finished Aug 19 05:52:33 PM PDT 24
Peak memory 224136 kb
Host smart-29f33279-7589-4785-8519-6cf4405715a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362424835 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1362424835
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_intr.1181643389
Short name T489
Test name
Test status
Simulation time 38042476 ps
CPU time 0.95 seconds
Started Aug 19 05:52:32 PM PDT 24
Finished Aug 19 05:52:33 PM PDT 24
Peak memory 224280 kb
Host smart-025c7236-f07f-4226-809f-dd74a4211d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181643389 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1181643389
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.779729977
Short name T27
Test name
Test status
Simulation time 16309172 ps
CPU time 1 seconds
Started Aug 19 05:52:33 PM PDT 24
Finished Aug 19 05:52:34 PM PDT 24
Peak memory 207192 kb
Host smart-d8260fe3-20cb-46b1-b3bb-64e938c13dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779729977 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.779729977
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.695919582
Short name T19
Test name
Test status
Simulation time 1618873029 ps
CPU time 10.28 seconds
Started Aug 19 05:53:00 PM PDT 24
Finished Aug 19 05:53:11 PM PDT 24
Peak memory 237944 kb
Host smart-a900748e-339c-42c1-a8b7-b4e7ba39aea3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695919582 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.695919582
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.4132793291
Short name T452
Test name
Test status
Simulation time 16823158 ps
CPU time 0.98 seconds
Started Aug 19 05:52:34 PM PDT 24
Finished Aug 19 05:52:35 PM PDT 24
Peak memory 215372 kb
Host smart-3f1e62ce-4332-4580-bc17-3ee8dae6bf20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132793291 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.4132793291
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.2205697707
Short name T450
Test name
Test status
Simulation time 1682874402 ps
CPU time 4.06 seconds
Started Aug 19 05:52:25 PM PDT 24
Finished Aug 19 05:52:29 PM PDT 24
Peak memory 215452 kb
Host smart-4537d559-22a5-47a6-866e-0686ae9ea1fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205697707 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2205697707
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_alert.4113071743
Short name T515
Test name
Test status
Simulation time 23923226 ps
CPU time 1.14 seconds
Started Aug 19 05:53:28 PM PDT 24
Finished Aug 19 05:53:29 PM PDT 24
Peak memory 219864 kb
Host smart-0afafde9-d523-4d84-9f89-66bdb329964d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113071743 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.4113071743
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_disable.3923744382
Short name T211
Test name
Test status
Simulation time 90140250 ps
CPU time 0.88 seconds
Started Aug 19 05:52:35 PM PDT 24
Finished Aug 19 05:52:37 PM PDT 24
Peak memory 215468 kb
Host smart-74336a52-ffc1-4539-a9f0-3798a91f43dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923744382 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3923744382
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_err.684602038
Short name T176
Test name
Test status
Simulation time 25450118 ps
CPU time 1.04 seconds
Started Aug 19 05:52:30 PM PDT 24
Finished Aug 19 05:52:32 PM PDT 24
Peak memory 224208 kb
Host smart-f34a5a06-55ec-4549-bc27-3a7fed15e1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684602038 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.684602038
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.4232596221
Short name T329
Test name
Test status
Simulation time 141641451 ps
CPU time 3 seconds
Started Aug 19 05:52:34 PM PDT 24
Finished Aug 19 05:52:37 PM PDT 24
Peak memory 220372 kb
Host smart-c34bced2-7243-4729-89f9-5f14c3fea591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232596221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.4232596221
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_sec_cm.2897546441
Short name T62
Test name
Test status
Simulation time 3884126095 ps
CPU time 8.99 seconds
Started Aug 19 05:52:31 PM PDT 24
Finished Aug 19 05:52:40 PM PDT 24
Peak memory 238484 kb
Host smart-4691cfd3-2d0c-4a3f-b1a5-a8a18691caeb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897546441 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.2897546441
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.2758047347
Short name T246
Test name
Test status
Simulation time 19844752 ps
CPU time 1.01 seconds
Started Aug 19 05:52:20 PM PDT 24
Finished Aug 19 05:52:21 PM PDT 24
Peak memory 215384 kb
Host smart-de845f5e-47a3-4fcb-83ae-a008ffa137e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758047347 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.2758047347
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.2369872849
Short name T954
Test name
Test status
Simulation time 646351097 ps
CPU time 3.64 seconds
Started Aug 19 05:52:27 PM PDT 24
Finished Aug 19 05:52:31 PM PDT 24
Peak memory 217536 kb
Host smart-befbc38f-c271-46b5-9fe0-92f88b2cb736
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369872849 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2369872849
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_alert.2055389331
Short name T112
Test name
Test status
Simulation time 96771327 ps
CPU time 1.21 seconds
Started Aug 19 05:52:59 PM PDT 24
Finished Aug 19 05:53:01 PM PDT 24
Peak memory 215720 kb
Host smart-07e029be-5508-43ba-ad1b-5dc4e322802f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055389331 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.2055389331
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.1162984095
Short name T553
Test name
Test status
Simulation time 55023688 ps
CPU time 0.96 seconds
Started Aug 19 05:52:39 PM PDT 24
Finished Aug 19 05:52:40 PM PDT 24
Peak memory 206892 kb
Host smart-1738f12c-f53a-48de-bdf5-3e429e25a157
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162984095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.1162984095
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3296176194
Short name T878
Test name
Test status
Simulation time 34683781 ps
CPU time 1.17 seconds
Started Aug 19 05:52:43 PM PDT 24
Finished Aug 19 05:52:44 PM PDT 24
Peak memory 218652 kb
Host smart-668073ce-6433-411a-b56b-0565373cab3d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296176194 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3296176194
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_genbits.842211097
Short name T564
Test name
Test status
Simulation time 34917301 ps
CPU time 1.12 seconds
Started Aug 19 05:52:51 PM PDT 24
Finished Aug 19 05:52:53 PM PDT 24
Peak memory 219560 kb
Host smart-246bfe72-0cc6-48e9-8294-146bb68a6fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842211097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.842211097
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.3939835994
Short name T57
Test name
Test status
Simulation time 26623281 ps
CPU time 1.08 seconds
Started Aug 19 05:52:44 PM PDT 24
Finished Aug 19 05:52:45 PM PDT 24
Peak memory 224292 kb
Host smart-e0a78776-3666-4208-a291-cff7e2e8a808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939835994 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3939835994
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.176776621
Short name T915
Test name
Test status
Simulation time 24378295 ps
CPU time 0.99 seconds
Started Aug 19 05:52:44 PM PDT 24
Finished Aug 19 05:52:45 PM PDT 24
Peak memory 215428 kb
Host smart-3720fc9d-5d31-47fd-be58-c19cb41eca7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176776621 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.176776621
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.892241241
Short name T375
Test name
Test status
Simulation time 437088783 ps
CPU time 5.01 seconds
Started Aug 19 05:52:49 PM PDT 24
Finished Aug 19 05:52:54 PM PDT 24
Peak memory 217184 kb
Host smart-82ff250c-ca73-40e6-b86c-c5e63234acc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892241241 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.892241241
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/100.edn_alert.1191941451
Short name T856
Test name
Test status
Simulation time 27725970 ps
CPU time 1.2 seconds
Started Aug 19 05:54:14 PM PDT 24
Finished Aug 19 05:54:15 PM PDT 24
Peak memory 218620 kb
Host smart-f6a6110a-844b-4f5d-b321-42cc9f198410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191941451 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.1191941451
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.53792345
Short name T373
Test name
Test status
Simulation time 34956351 ps
CPU time 1.75 seconds
Started Aug 19 05:54:02 PM PDT 24
Finished Aug 19 05:54:04 PM PDT 24
Peak memory 218708 kb
Host smart-60d8fc8b-f656-4b49-83e5-e9e52e5a8f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53792345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.53792345
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.1045925891
Short name T518
Test name
Test status
Simulation time 83641336 ps
CPU time 1.17 seconds
Started Aug 19 05:54:04 PM PDT 24
Finished Aug 19 05:54:05 PM PDT 24
Peak memory 220628 kb
Host smart-62b52377-85f9-44dc-a3f6-d0fe6805c8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045925891 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.1045925891
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.537405495
Short name T328
Test name
Test status
Simulation time 26978289 ps
CPU time 1.18 seconds
Started Aug 19 05:54:12 PM PDT 24
Finished Aug 19 05:54:13 PM PDT 24
Peak memory 219860 kb
Host smart-6b9b1d64-245f-48c9-9395-86078c4e25a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537405495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.537405495
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.100346360
Short name T400
Test name
Test status
Simulation time 210387629 ps
CPU time 1.33 seconds
Started Aug 19 05:54:11 PM PDT 24
Finished Aug 19 05:54:13 PM PDT 24
Peak memory 217540 kb
Host smart-109ab450-f294-47f1-bd9a-eb2a5d53207e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100346360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.100346360
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.3275899765
Short name T864
Test name
Test status
Simulation time 70442156 ps
CPU time 1.18 seconds
Started Aug 19 05:53:54 PM PDT 24
Finished Aug 19 05:53:55 PM PDT 24
Peak memory 218836 kb
Host smart-620bb254-2ac0-41d5-91b7-21dc275199b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275899765 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.3275899765
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.628404041
Short name T371
Test name
Test status
Simulation time 72214404 ps
CPU time 1.16 seconds
Started Aug 19 05:54:04 PM PDT 24
Finished Aug 19 05:54:05 PM PDT 24
Peak memory 218996 kb
Host smart-3ecb8c64-7d7a-4326-87bb-9121d509c263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628404041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.628404041
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.2429757149
Short name T192
Test name
Test status
Simulation time 101358102 ps
CPU time 1.15 seconds
Started Aug 19 05:54:11 PM PDT 24
Finished Aug 19 05:54:12 PM PDT 24
Peak memory 220416 kb
Host smart-0e9fde43-7dbd-436a-9d9e-3e0662a5dd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429757149 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.2429757149
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/105.edn_genbits.3522147800
Short name T749
Test name
Test status
Simulation time 49956253 ps
CPU time 1.5 seconds
Started Aug 19 05:54:07 PM PDT 24
Finished Aug 19 05:54:09 PM PDT 24
Peak memory 218592 kb
Host smart-934b93bb-e2da-4b26-a533-02fe77d678aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522147800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.3522147800
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.309440540
Short name T272
Test name
Test status
Simulation time 86587468 ps
CPU time 1.21 seconds
Started Aug 19 05:54:09 PM PDT 24
Finished Aug 19 05:54:10 PM PDT 24
Peak memory 218492 kb
Host smart-6e592e4e-d0fd-4e41-823f-84f97fcf53ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309440540 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.309440540
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.652123523
Short name T904
Test name
Test status
Simulation time 44935057 ps
CPU time 1.19 seconds
Started Aug 19 05:54:13 PM PDT 24
Finished Aug 19 05:54:14 PM PDT 24
Peak memory 217500 kb
Host smart-d82bc11f-d10e-4276-9c5e-1ff2892699c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652123523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.652123523
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.4189491390
Short name T111
Test name
Test status
Simulation time 73807757 ps
CPU time 1.36 seconds
Started Aug 19 05:54:04 PM PDT 24
Finished Aug 19 05:54:05 PM PDT 24
Peak memory 220944 kb
Host smart-923aaf59-1136-4757-96c4-0eb712094e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189491390 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.4189491390
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.2433668735
Short name T388
Test name
Test status
Simulation time 86437454 ps
CPU time 2.15 seconds
Started Aug 19 05:54:00 PM PDT 24
Finished Aug 19 05:54:02 PM PDT 24
Peak memory 218972 kb
Host smart-6d81f4ee-6e11-4cfe-bb3f-aec8215a0f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433668735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2433668735
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.418052925
Short name T729
Test name
Test status
Simulation time 75536078 ps
CPU time 1.13 seconds
Started Aug 19 05:54:08 PM PDT 24
Finished Aug 19 05:54:09 PM PDT 24
Peak memory 220816 kb
Host smart-4de2ba90-75d4-4c3a-8783-b6c519985489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418052925 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.418052925
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.2681126660
Short name T446
Test name
Test status
Simulation time 77477295 ps
CPU time 1.4 seconds
Started Aug 19 05:54:15 PM PDT 24
Finished Aug 19 05:54:17 PM PDT 24
Peak memory 217504 kb
Host smart-7dc46814-a3b5-415d-b330-73588474f719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681126660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2681126660
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.1767788333
Short name T927
Test name
Test status
Simulation time 73660500 ps
CPU time 1.22 seconds
Started Aug 19 05:54:00 PM PDT 24
Finished Aug 19 05:54:01 PM PDT 24
Peak memory 218648 kb
Host smart-012928cd-774e-481e-911f-998a92e9e754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767788333 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.1767788333
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.1531967037
Short name T761
Test name
Test status
Simulation time 44084794 ps
CPU time 1.6 seconds
Started Aug 19 05:53:55 PM PDT 24
Finished Aug 19 05:53:57 PM PDT 24
Peak memory 218748 kb
Host smart-7b8248d2-791e-402e-a8ea-268e899c2ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531967037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1531967037
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.298465257
Short name T967
Test name
Test status
Simulation time 43898760 ps
CPU time 1.25 seconds
Started Aug 19 05:52:59 PM PDT 24
Finished Aug 19 05:53:01 PM PDT 24
Peak memory 220204 kb
Host smart-83de359b-8a08-4a93-869c-8c191044fedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298465257 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.298465257
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.2463804972
Short name T66
Test name
Test status
Simulation time 12919659 ps
CPU time 0.9 seconds
Started Aug 19 05:52:50 PM PDT 24
Finished Aug 19 05:52:51 PM PDT 24
Peak memory 206796 kb
Host smart-96592311-3fcf-4383-a328-0092d97562b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463804972 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.2463804972
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.4090413755
Short name T321
Test name
Test status
Simulation time 14452296 ps
CPU time 0.98 seconds
Started Aug 19 05:52:52 PM PDT 24
Finished Aug 19 05:52:53 PM PDT 24
Peak memory 207108 kb
Host smart-e1000fb2-bb98-44c9-a9d9-84202feb08ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090413755 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.4090413755
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.3045716656
Short name T682
Test name
Test status
Simulation time 83070183 ps
CPU time 1.03 seconds
Started Aug 19 05:52:41 PM PDT 24
Finished Aug 19 05:52:42 PM PDT 24
Peak memory 218756 kb
Host smart-6c59bcfd-11fd-4ec6-92ef-29cac00227cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045716656 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.3045716656
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.589952570
Short name T122
Test name
Test status
Simulation time 45452954 ps
CPU time 0.99 seconds
Started Aug 19 05:52:51 PM PDT 24
Finished Aug 19 05:52:52 PM PDT 24
Peak memory 219952 kb
Host smart-32735b01-7939-4b67-82be-5b09f3265e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589952570 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.589952570
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.3372579522
Short name T532
Test name
Test status
Simulation time 74360877 ps
CPU time 2.53 seconds
Started Aug 19 05:52:41 PM PDT 24
Finished Aug 19 05:52:44 PM PDT 24
Peak memory 219672 kb
Host smart-b7ab50c9-d075-44fd-8900-96af9b3c8c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372579522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.3372579522
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_smoke.2433603355
Short name T616
Test name
Test status
Simulation time 15515579 ps
CPU time 0.99 seconds
Started Aug 19 05:52:44 PM PDT 24
Finished Aug 19 05:52:45 PM PDT 24
Peak memory 207196 kb
Host smart-45acebb1-4022-4364-95af-367f77b2ea66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433603355 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.2433603355
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.2584059454
Short name T374
Test name
Test status
Simulation time 630065707 ps
CPU time 2.89 seconds
Started Aug 19 05:52:49 PM PDT 24
Finished Aug 19 05:52:52 PM PDT 24
Peak memory 215408 kb
Host smart-83522a9d-ab25-48ac-b736-e6c1dca53856
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584059454 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2584059454
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/110.edn_alert.1662591614
Short name T119
Test name
Test status
Simulation time 27459572 ps
CPU time 1.2 seconds
Started Aug 19 05:53:58 PM PDT 24
Finished Aug 19 05:53:59 PM PDT 24
Peak memory 218892 kb
Host smart-0762981c-9247-4d97-a08a-0a25977c605b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662591614 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.1662591614
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.1582557119
Short name T676
Test name
Test status
Simulation time 40539786 ps
CPU time 1.73 seconds
Started Aug 19 05:54:05 PM PDT 24
Finished Aug 19 05:54:07 PM PDT 24
Peak memory 218696 kb
Host smart-a690d147-2878-4dec-8857-1222a1e3b297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582557119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.1582557119
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.4267539065
Short name T193
Test name
Test status
Simulation time 36332328 ps
CPU time 1.13 seconds
Started Aug 19 05:54:08 PM PDT 24
Finished Aug 19 05:54:09 PM PDT 24
Peak memory 219100 kb
Host smart-afab6aad-0892-47f9-9ade-04611cdc8fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267539065 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.4267539065
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.3623128317
Short name T517
Test name
Test status
Simulation time 91464159 ps
CPU time 1.48 seconds
Started Aug 19 05:54:00 PM PDT 24
Finished Aug 19 05:54:02 PM PDT 24
Peak memory 217532 kb
Host smart-418a5828-4b24-44ab-a471-ddcb09f77f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623128317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.3623128317
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.3217308027
Short name T718
Test name
Test status
Simulation time 115864335 ps
CPU time 1.37 seconds
Started Aug 19 05:54:08 PM PDT 24
Finished Aug 19 05:54:10 PM PDT 24
Peak memory 217724 kb
Host smart-9cc295ab-eaca-4ac5-bbc6-1bc521032872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217308027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.3217308027
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.3254117136
Short name T621
Test name
Test status
Simulation time 23756200 ps
CPU time 1.22 seconds
Started Aug 19 05:54:08 PM PDT 24
Finished Aug 19 05:54:09 PM PDT 24
Peak memory 219708 kb
Host smart-8a813fe6-0530-4391-8275-649c98d562e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254117136 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.3254117136
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.706842791
Short name T451
Test name
Test status
Simulation time 277793600 ps
CPU time 3.97 seconds
Started Aug 19 05:54:16 PM PDT 24
Finished Aug 19 05:54:20 PM PDT 24
Peak memory 220648 kb
Host smart-298764c1-a041-48e6-800b-972529e7f89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706842791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.706842791
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.3370864282
Short name T782
Test name
Test status
Simulation time 41710760 ps
CPU time 1.09 seconds
Started Aug 19 05:54:13 PM PDT 24
Finished Aug 19 05:54:14 PM PDT 24
Peak memory 218632 kb
Host smart-15c3e0a3-f0d2-4f4c-b926-57b933c7613a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370864282 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.3370864282
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.3145484122
Short name T845
Test name
Test status
Simulation time 68451113 ps
CPU time 2.38 seconds
Started Aug 19 05:54:05 PM PDT 24
Finished Aug 19 05:54:08 PM PDT 24
Peak memory 220452 kb
Host smart-c1a9f503-1064-43d7-ae77-ebb85648cbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145484122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3145484122
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.2034605342
Short name T273
Test name
Test status
Simulation time 167087442 ps
CPU time 1.32 seconds
Started Aug 19 05:54:14 PM PDT 24
Finished Aug 19 05:54:16 PM PDT 24
Peak memory 220160 kb
Host smart-121c4575-2206-4abc-a62f-f470bad303b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034605342 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.2034605342
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.950914936
Short name T492
Test name
Test status
Simulation time 35623712 ps
CPU time 1.28 seconds
Started Aug 19 05:54:12 PM PDT 24
Finished Aug 19 05:54:13 PM PDT 24
Peak memory 220384 kb
Host smart-42ae17b9-27d0-4a9e-86b1-7535aa8d1467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950914936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.950914936
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.1768950518
Short name T174
Test name
Test status
Simulation time 25712723 ps
CPU time 1.19 seconds
Started Aug 19 05:54:12 PM PDT 24
Finished Aug 19 05:54:13 PM PDT 24
Peak memory 219888 kb
Host smart-aefb2fc8-fbb9-41bd-b8f6-3ce20ce04a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768950518 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.1768950518
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.1060090460
Short name T661
Test name
Test status
Simulation time 50902360 ps
CPU time 1.7 seconds
Started Aug 19 05:53:59 PM PDT 24
Finished Aug 19 05:54:01 PM PDT 24
Peak memory 215380 kb
Host smart-59348d58-1690-4dd0-81e0-8f6599fd708c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060090460 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1060090460
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.316559953
Short name T842
Test name
Test status
Simulation time 35214806 ps
CPU time 1.32 seconds
Started Aug 19 05:54:12 PM PDT 24
Finished Aug 19 05:54:14 PM PDT 24
Peak memory 218580 kb
Host smart-eb2f4762-1095-4d82-938c-585d29c56340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316559953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.316559953
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.3659409025
Short name T629
Test name
Test status
Simulation time 59424848 ps
CPU time 1.26 seconds
Started Aug 19 05:53:56 PM PDT 24
Finished Aug 19 05:53:58 PM PDT 24
Peak memory 221384 kb
Host smart-b2d26173-1602-442f-b202-6e586cffffb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659409025 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.3659409025
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.3970630678
Short name T583
Test name
Test status
Simulation time 117461717 ps
CPU time 1.88 seconds
Started Aug 19 05:54:02 PM PDT 24
Finished Aug 19 05:54:04 PM PDT 24
Peak memory 219328 kb
Host smart-d78136f3-b603-43c6-95c6-ccec1fac45bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970630678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3970630678
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.1148744889
Short name T568
Test name
Test status
Simulation time 94532031 ps
CPU time 1.3 seconds
Started Aug 19 05:54:21 PM PDT 24
Finished Aug 19 05:54:23 PM PDT 24
Peak memory 218468 kb
Host smart-b1d716f8-1fc3-4e8d-a941-741b51524de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148744889 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.1148744889
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.1712585735
Short name T506
Test name
Test status
Simulation time 87811805 ps
CPU time 1.11 seconds
Started Aug 19 05:54:21 PM PDT 24
Finished Aug 19 05:54:22 PM PDT 24
Peak memory 217424 kb
Host smart-fe534b12-b686-4825-b433-052fd0106677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712585735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.1712585735
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.1248013088
Short name T109
Test name
Test status
Simulation time 44926206 ps
CPU time 1.15 seconds
Started Aug 19 05:53:02 PM PDT 24
Finished Aug 19 05:53:04 PM PDT 24
Peak memory 218660 kb
Host smart-f851a956-5a20-46c4-b45b-ab1964d9204e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248013088 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.1248013088
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.3614397011
Short name T512
Test name
Test status
Simulation time 19218423 ps
CPU time 0.91 seconds
Started Aug 19 05:53:47 PM PDT 24
Finished Aug 19 05:53:53 PM PDT 24
Peak memory 206636 kb
Host smart-ef9d2323-f6e3-4e5b-a6ca-f20c7a70afa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614397011 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3614397011
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.1960549573
Short name T520
Test name
Test status
Simulation time 52885177 ps
CPU time 1.15 seconds
Started Aug 19 05:52:42 PM PDT 24
Finished Aug 19 05:52:44 PM PDT 24
Peak memory 217048 kb
Host smart-99bbcd23-7f5c-401b-be2c-0503339f268d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960549573 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.1960549573
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.2539150224
Short name T888
Test name
Test status
Simulation time 32372069 ps
CPU time 0.9 seconds
Started Aug 19 05:52:42 PM PDT 24
Finished Aug 19 05:52:43 PM PDT 24
Peak memory 218340 kb
Host smart-7e7b73af-4e55-413c-9d25-42adfdb5e251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539150224 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.2539150224
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.3804120061
Short name T326
Test name
Test status
Simulation time 229814673 ps
CPU time 2.79 seconds
Started Aug 19 05:52:46 PM PDT 24
Finished Aug 19 05:52:49 PM PDT 24
Peak memory 219832 kb
Host smart-632dcb7b-70ec-4418-8e64-722fc8233802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804120061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.3804120061
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.3178574682
Short name T741
Test name
Test status
Simulation time 40365018 ps
CPU time 0.91 seconds
Started Aug 19 05:52:37 PM PDT 24
Finished Aug 19 05:52:38 PM PDT 24
Peak memory 215796 kb
Host smart-da1cb094-ef11-4e2a-bb97-280babea8081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178574682 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3178574682
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.62893092
Short name T28
Test name
Test status
Simulation time 18979957 ps
CPU time 1.03 seconds
Started Aug 19 05:52:48 PM PDT 24
Finished Aug 19 05:52:49 PM PDT 24
Peak memory 207216 kb
Host smart-78ef43ad-f10e-4818-9df7-89c7ac8254d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62893092 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.62893092
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.1380362573
Short name T948
Test name
Test status
Simulation time 287141548 ps
CPU time 2.84 seconds
Started Aug 19 05:52:48 PM PDT 24
Finished Aug 19 05:52:51 PM PDT 24
Peak memory 215432 kb
Host smart-b4b268c1-53dd-4345-83a6-895e4179f64f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380362573 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1380362573
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/120.edn_alert.2801741417
Short name T290
Test name
Test status
Simulation time 22930286 ps
CPU time 1.29 seconds
Started Aug 19 05:54:08 PM PDT 24
Finished Aug 19 05:54:10 PM PDT 24
Peak memory 220120 kb
Host smart-d38cdb0c-4a15-4e15-b61a-d6d0252c4032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801741417 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.2801741417
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.397987981
Short name T619
Test name
Test status
Simulation time 46118410 ps
CPU time 1.79 seconds
Started Aug 19 05:54:12 PM PDT 24
Finished Aug 19 05:54:14 PM PDT 24
Peak memory 217756 kb
Host smart-136bf0f7-f437-4132-8c20-f4ca063e3d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397987981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.397987981
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.1533690154
Short name T744
Test name
Test status
Simulation time 47258470 ps
CPU time 1.18 seconds
Started Aug 19 05:54:20 PM PDT 24
Finished Aug 19 05:54:21 PM PDT 24
Peak memory 218584 kb
Host smart-3ec63401-f25e-4a5d-99a4-f4561fcda1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533690154 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.1533690154
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/122.edn_alert.1220774061
Short name T965
Test name
Test status
Simulation time 63507508 ps
CPU time 1.14 seconds
Started Aug 19 05:54:11 PM PDT 24
Finished Aug 19 05:54:12 PM PDT 24
Peak memory 219012 kb
Host smart-3ce1bf4a-6f96-4a72-b378-cb526569ea17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220774061 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.1220774061
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.940493547
Short name T284
Test name
Test status
Simulation time 75602042 ps
CPU time 1.29 seconds
Started Aug 19 05:54:13 PM PDT 24
Finished Aug 19 05:54:14 PM PDT 24
Peak memory 218764 kb
Host smart-36526d28-5189-45a9-9dbc-1f51a3291c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940493547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.940493547
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.850131294
Short name T721
Test name
Test status
Simulation time 51336377 ps
CPU time 1.25 seconds
Started Aug 19 05:54:14 PM PDT 24
Finished Aug 19 05:54:15 PM PDT 24
Peak memory 220676 kb
Host smart-61d9cae9-5e04-43f4-a6ed-d65e7511ef68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850131294 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.850131294
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.323993334
Short name T698
Test name
Test status
Simulation time 27642741 ps
CPU time 1.24 seconds
Started Aug 19 05:54:07 PM PDT 24
Finished Aug 19 05:54:13 PM PDT 24
Peak memory 217540 kb
Host smart-1503ea42-6fd5-4337-a8df-a3a913bd9277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323993334 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.323993334
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.2439747759
Short name T588
Test name
Test status
Simulation time 42122505 ps
CPU time 1.09 seconds
Started Aug 19 05:54:10 PM PDT 24
Finished Aug 19 05:54:11 PM PDT 24
Peak memory 218460 kb
Host smart-7df4c4d8-a972-489d-a0df-db1b53c4862a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439747759 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.2439747759
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.4135576426
Short name T292
Test name
Test status
Simulation time 79670197 ps
CPU time 1.1 seconds
Started Aug 19 05:54:16 PM PDT 24
Finished Aug 19 05:54:18 PM PDT 24
Peak memory 217492 kb
Host smart-f4250593-c32b-413c-aa1c-21698d4151fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135576426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.4135576426
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.1918379148
Short name T277
Test name
Test status
Simulation time 48861713 ps
CPU time 1.12 seconds
Started Aug 19 05:54:12 PM PDT 24
Finished Aug 19 05:54:13 PM PDT 24
Peak memory 218828 kb
Host smart-d0586295-89dc-4b1f-bdc0-837fc2f33b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918379148 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.1918379148
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/125.edn_genbits.4121862518
Short name T234
Test name
Test status
Simulation time 45918766 ps
CPU time 1.37 seconds
Started Aug 19 05:54:17 PM PDT 24
Finished Aug 19 05:54:18 PM PDT 24
Peak memory 218800 kb
Host smart-a8e1e63a-b1a8-425b-a55d-cd28cefb758f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121862518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.4121862518
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.541126789
Short name T72
Test name
Test status
Simulation time 26501850 ps
CPU time 1.22 seconds
Started Aug 19 05:54:12 PM PDT 24
Finished Aug 19 05:54:13 PM PDT 24
Peak memory 219760 kb
Host smart-6cbcb790-dc79-4fee-98fd-771a93e65db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541126789 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.541126789
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.1932476456
Short name T566
Test name
Test status
Simulation time 54535616 ps
CPU time 1.41 seconds
Started Aug 19 05:54:14 PM PDT 24
Finished Aug 19 05:54:16 PM PDT 24
Peak memory 218556 kb
Host smart-7ae0cb50-8bb3-4bde-b0b4-a222ca68eac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932476456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1932476456
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.3127382092
Short name T274
Test name
Test status
Simulation time 224679664 ps
CPU time 1.09 seconds
Started Aug 19 05:54:07 PM PDT 24
Finished Aug 19 05:54:09 PM PDT 24
Peak memory 218756 kb
Host smart-d331009e-93b1-462a-94ab-027b1bd6672c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127382092 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.3127382092
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.2535889818
Short name T908
Test name
Test status
Simulation time 45720974 ps
CPU time 1.67 seconds
Started Aug 19 05:54:15 PM PDT 24
Finished Aug 19 05:54:17 PM PDT 24
Peak memory 218624 kb
Host smart-09fbc6db-0b7b-479d-8ed9-fd34283ccd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535889818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2535889818
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.2892723389
Short name T889
Test name
Test status
Simulation time 30173360 ps
CPU time 1.28 seconds
Started Aug 19 05:54:10 PM PDT 24
Finished Aug 19 05:54:12 PM PDT 24
Peak memory 219732 kb
Host smart-964d67a0-0179-4d56-8153-b1841b74ef9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892723389 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.2892723389
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.160235719
Short name T393
Test name
Test status
Simulation time 39641864 ps
CPU time 1.5 seconds
Started Aug 19 05:54:18 PM PDT 24
Finished Aug 19 05:54:20 PM PDT 24
Peak memory 218656 kb
Host smart-b6dab2bb-c9a9-43ec-ad0f-ec268b173551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160235719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.160235719
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_alert.2569574231
Short name T487
Test name
Test status
Simulation time 24570474 ps
CPU time 1.12 seconds
Started Aug 19 05:54:23 PM PDT 24
Finished Aug 19 05:54:24 PM PDT 24
Peak memory 219792 kb
Host smart-0be6dd70-02b4-4386-b6c0-d23254dbe6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569574231 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.2569574231
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.4214633385
Short name T434
Test name
Test status
Simulation time 53245004 ps
CPU time 1.1 seconds
Started Aug 19 05:54:24 PM PDT 24
Finished Aug 19 05:54:25 PM PDT 24
Peak memory 217556 kb
Host smart-c7d259b3-65d4-4dac-9231-3e248ad8d694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214633385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.4214633385
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.936263348
Short name T584
Test name
Test status
Simulation time 29423263 ps
CPU time 1.27 seconds
Started Aug 19 05:52:54 PM PDT 24
Finished Aug 19 05:52:55 PM PDT 24
Peak memory 221188 kb
Host smart-3e73e48b-5e1a-4187-ae8e-b32964407f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936263348 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.936263348
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.4098806242
Short name T632
Test name
Test status
Simulation time 47417111 ps
CPU time 0.93 seconds
Started Aug 19 05:52:45 PM PDT 24
Finished Aug 19 05:52:46 PM PDT 24
Peak memory 206864 kb
Host smart-24f7f108-8251-4049-a085-9fe68aab38a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098806242 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.4098806242
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.793460750
Short name T380
Test name
Test status
Simulation time 89709319 ps
CPU time 0.78 seconds
Started Aug 19 05:52:51 PM PDT 24
Finished Aug 19 05:52:52 PM PDT 24
Peak memory 215240 kb
Host smart-0dfaad40-9fd3-406f-9673-9657076abcb5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793460750 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.793460750
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.1127706514
Short name T979
Test name
Test status
Simulation time 85649069 ps
CPU time 1.03 seconds
Started Aug 19 05:53:02 PM PDT 24
Finished Aug 19 05:53:04 PM PDT 24
Peak memory 218440 kb
Host smart-73f7f268-74eb-47f1-9cfc-f4458e44f594
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127706514 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.1127706514
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_intr.1653659205
Short name T100
Test name
Test status
Simulation time 26006653 ps
CPU time 0.98 seconds
Started Aug 19 05:52:55 PM PDT 24
Finished Aug 19 05:52:56 PM PDT 24
Peak memory 215840 kb
Host smart-228b76c4-1729-451f-a8fa-92434b0cbedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653659205 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.1653659205
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.4027367268
Short name T350
Test name
Test status
Simulation time 188125005 ps
CPU time 0.89 seconds
Started Aug 19 05:53:35 PM PDT 24
Finished Aug 19 05:53:41 PM PDT 24
Peak memory 207184 kb
Host smart-a37127a3-7be0-4949-a325-a5324c7594eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027367268 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.4027367268
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.4102670717
Short name T423
Test name
Test status
Simulation time 98783965 ps
CPU time 2.21 seconds
Started Aug 19 05:52:33 PM PDT 24
Finished Aug 19 05:52:35 PM PDT 24
Peak memory 215248 kb
Host smart-a7afceb6-91db-4330-ad8c-ccd2795b5403
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102670717 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.4102670717
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/130.edn_alert.1882154941
Short name T124
Test name
Test status
Simulation time 102237851 ps
CPU time 1.31 seconds
Started Aug 19 05:54:13 PM PDT 24
Finished Aug 19 05:54:15 PM PDT 24
Peak memory 218560 kb
Host smart-cd285130-3990-440f-a6e4-56f4cedc1bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882154941 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.1882154941
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.3475062227
Short name T521
Test name
Test status
Simulation time 103460215 ps
CPU time 1.27 seconds
Started Aug 19 05:54:13 PM PDT 24
Finished Aug 19 05:54:15 PM PDT 24
Peak memory 217348 kb
Host smart-ef5db089-33e3-4560-8d2b-edcabe54521a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475062227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.3475062227
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.1100054078
Short name T83
Test name
Test status
Simulation time 24316692 ps
CPU time 1.14 seconds
Started Aug 19 05:54:09 PM PDT 24
Finished Aug 19 05:54:10 PM PDT 24
Peak memory 218876 kb
Host smart-7b753cda-7d1c-4d43-83b5-245057b9f7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100054078 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.1100054078
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.1627732723
Short name T369
Test name
Test status
Simulation time 46696946 ps
CPU time 1.14 seconds
Started Aug 19 05:54:18 PM PDT 24
Finished Aug 19 05:54:20 PM PDT 24
Peak memory 219664 kb
Host smart-73a25d0b-3565-47ac-861e-d825c0281ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627732723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.1627732723
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.1602089123
Short name T410
Test name
Test status
Simulation time 65319895 ps
CPU time 1.09 seconds
Started Aug 19 05:54:14 PM PDT 24
Finished Aug 19 05:54:16 PM PDT 24
Peak memory 220188 kb
Host smart-12c35f50-cb71-4207-9d3d-5afa38dec46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602089123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1602089123
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.3263518644
Short name T164
Test name
Test status
Simulation time 41146010 ps
CPU time 1.14 seconds
Started Aug 19 05:54:10 PM PDT 24
Finished Aug 19 05:54:11 PM PDT 24
Peak memory 218892 kb
Host smart-92825865-4684-4c34-b2f6-31d4743f34ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263518644 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.3263518644
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.1203584812
Short name T490
Test name
Test status
Simulation time 48287715 ps
CPU time 1.14 seconds
Started Aug 19 05:54:09 PM PDT 24
Finished Aug 19 05:54:10 PM PDT 24
Peak memory 220316 kb
Host smart-a3aa4f3f-3d28-4ee7-aee3-7a4e6fbdf4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203584812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1203584812
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.1335819701
Short name T150
Test name
Test status
Simulation time 35411649 ps
CPU time 1.23 seconds
Started Aug 19 05:54:13 PM PDT 24
Finished Aug 19 05:54:14 PM PDT 24
Peak memory 221116 kb
Host smart-eb09a96d-67b5-4f02-a0b1-2537d454e74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335819701 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.1335819701
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.1598006298
Short name T440
Test name
Test status
Simulation time 87777691 ps
CPU time 1.32 seconds
Started Aug 19 05:54:17 PM PDT 24
Finished Aug 19 05:54:19 PM PDT 24
Peak memory 219180 kb
Host smart-28bd56ea-8aec-475e-9abb-6842cdd57159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598006298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.1598006298
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.4037537995
Short name T239
Test name
Test status
Simulation time 29884848 ps
CPU time 1.39 seconds
Started Aug 19 05:54:12 PM PDT 24
Finished Aug 19 05:54:13 PM PDT 24
Peak memory 219924 kb
Host smart-0fed9408-1b3a-44c9-9785-d760f8a6588b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037537995 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.4037537995
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.2512664926
Short name T361
Test name
Test status
Simulation time 45523414 ps
CPU time 1.59 seconds
Started Aug 19 05:54:15 PM PDT 24
Finished Aug 19 05:54:16 PM PDT 24
Peak memory 217320 kb
Host smart-9015d81f-f523-4a51-ba74-59b946179811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512664926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.2512664926
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.3560028008
Short name T359
Test name
Test status
Simulation time 43266372 ps
CPU time 1.55 seconds
Started Aug 19 05:54:22 PM PDT 24
Finished Aug 19 05:54:24 PM PDT 24
Peak memory 218784 kb
Host smart-e74b1472-fb64-411f-be4b-c146b06cf2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560028008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3560028008
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.2131037566
Short name T837
Test name
Test status
Simulation time 87131991 ps
CPU time 1.23 seconds
Started Aug 19 05:54:15 PM PDT 24
Finished Aug 19 05:54:17 PM PDT 24
Peak memory 219396 kb
Host smart-24430ed0-6fe0-4c9a-8333-4b0fe1f18b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131037566 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.2131037566
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.610932050
Short name T84
Test name
Test status
Simulation time 52812482 ps
CPU time 1.17 seconds
Started Aug 19 05:54:15 PM PDT 24
Finished Aug 19 05:54:16 PM PDT 24
Peak memory 217556 kb
Host smart-df892161-2bc7-4e63-9ad0-08aac672627e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610932050 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.610932050
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.3233078334
Short name T538
Test name
Test status
Simulation time 31125989 ps
CPU time 1.36 seconds
Started Aug 19 05:54:28 PM PDT 24
Finished Aug 19 05:54:29 PM PDT 24
Peak memory 215800 kb
Host smart-2e8fb308-bcc2-46b7-afe1-9c4936029966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233078334 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.3233078334
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/139.edn_alert.3138484512
Short name T820
Test name
Test status
Simulation time 33061281 ps
CPU time 1.3 seconds
Started Aug 19 05:54:16 PM PDT 24
Finished Aug 19 05:54:17 PM PDT 24
Peak memory 215700 kb
Host smart-207b939f-3c02-4dab-a798-f914801fc9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138484512 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.3138484512
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.3352460969
Short name T301
Test name
Test status
Simulation time 37305485 ps
CPU time 1.56 seconds
Started Aug 19 05:54:13 PM PDT 24
Finished Aug 19 05:54:14 PM PDT 24
Peak memory 218740 kb
Host smart-f5a25e2e-b8f9-4f6a-b401-e861ed36ecc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352460969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3352460969
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.585333945
Short name T786
Test name
Test status
Simulation time 30318857 ps
CPU time 1.16 seconds
Started Aug 19 05:53:11 PM PDT 24
Finished Aug 19 05:53:12 PM PDT 24
Peak memory 218768 kb
Host smart-e1d83c6b-77c1-4f57-a4b0-2583f1840c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585333945 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.585333945
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.3197808811
Short name T713
Test name
Test status
Simulation time 37607989 ps
CPU time 0.84 seconds
Started Aug 19 05:52:58 PM PDT 24
Finished Aug 19 05:52:59 PM PDT 24
Peak memory 214832 kb
Host smart-9056a74a-b6bd-4678-85b3-90c4fd87fe88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197808811 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3197808811
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.4024043339
Short name T940
Test name
Test status
Simulation time 20283590 ps
CPU time 0.89 seconds
Started Aug 19 05:52:49 PM PDT 24
Finished Aug 19 05:52:50 PM PDT 24
Peak memory 215300 kb
Host smart-58a0d737-5fac-473a-8a7b-10f8c6bba886
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024043339 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.4024043339
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.3465793785
Short name T534
Test name
Test status
Simulation time 48619157 ps
CPU time 1.03 seconds
Started Aug 19 05:52:46 PM PDT 24
Finished Aug 19 05:52:47 PM PDT 24
Peak memory 218612 kb
Host smart-81c8564b-0e49-48ea-ad18-5237e0f5a430
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465793785 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.3465793785
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.2340964403
Short name T125
Test name
Test status
Simulation time 51830160 ps
CPU time 1.01 seconds
Started Aug 19 05:52:54 PM PDT 24
Finished Aug 19 05:52:55 PM PDT 24
Peak memory 220628 kb
Host smart-be4d7e59-4b6e-4bed-b5a5-38988c0806d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340964403 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.2340964403
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.2002127460
Short name T722
Test name
Test status
Simulation time 63854481 ps
CPU time 1.31 seconds
Started Aug 19 05:52:54 PM PDT 24
Finished Aug 19 05:52:55 PM PDT 24
Peak memory 217392 kb
Host smart-b17833cd-c610-4c13-8df9-af102ab9ac72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002127460 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2002127460
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.2939374316
Short name T104
Test name
Test status
Simulation time 26983844 ps
CPU time 0.88 seconds
Started Aug 19 05:52:52 PM PDT 24
Finished Aug 19 05:52:53 PM PDT 24
Peak memory 215768 kb
Host smart-0dab2d90-adfd-4995-a458-d1bdaae68003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939374316 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.2939374316
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.1088588405
Short name T832
Test name
Test status
Simulation time 45988529 ps
CPU time 0.92 seconds
Started Aug 19 05:52:45 PM PDT 24
Finished Aug 19 05:52:46 PM PDT 24
Peak memory 215396 kb
Host smart-f0f6be59-0790-4d76-a85a-00aec792f559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088588405 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.1088588405
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.3094318944
Short name T567
Test name
Test status
Simulation time 1015786666 ps
CPU time 4.68 seconds
Started Aug 19 05:52:42 PM PDT 24
Finished Aug 19 05:52:46 PM PDT 24
Peak memory 215404 kb
Host smart-6bd7cffa-e533-43e3-beb3-cf8ddd0fa423
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094318944 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3094318944
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.306563286
Short name T614
Test name
Test status
Simulation time 3663305315 ps
CPU time 109.11 seconds
Started Aug 19 05:53:03 PM PDT 24
Finished Aug 19 05:54:52 PM PDT 24
Peak memory 218244 kb
Host smart-5998fd74-8e75-4933-9e10-f99ca5a73fc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306563286 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.306563286
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.4135277560
Short name T491
Test name
Test status
Simulation time 28725508 ps
CPU time 1.21 seconds
Started Aug 19 05:54:16 PM PDT 24
Finished Aug 19 05:54:17 PM PDT 24
Peak memory 220904 kb
Host smart-9f007329-4ba7-4a61-93c1-9bfb433dc3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135277560 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.4135277560
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.505358350
Short name T313
Test name
Test status
Simulation time 67260256 ps
CPU time 2.4 seconds
Started Aug 19 05:54:17 PM PDT 24
Finished Aug 19 05:54:20 PM PDT 24
Peak memory 220352 kb
Host smart-ed6cfec9-a4bc-43b8-85b4-f171dae65cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505358350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.505358350
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.833708628
Short name T670
Test name
Test status
Simulation time 41224986 ps
CPU time 1.19 seconds
Started Aug 19 05:54:17 PM PDT 24
Finished Aug 19 05:54:18 PM PDT 24
Peak memory 218832 kb
Host smart-2bc2ec67-e155-436e-8af2-c3303871a5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833708628 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.833708628
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.511917430
Short name T381
Test name
Test status
Simulation time 52413758 ps
CPU time 1.29 seconds
Started Aug 19 05:54:14 PM PDT 24
Finished Aug 19 05:54:15 PM PDT 24
Peak memory 218024 kb
Host smart-47749491-2a8d-42ad-b3d6-97a445dc0294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511917430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.511917430
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.686591924
Short name T789
Test name
Test status
Simulation time 140666109 ps
CPU time 1.18 seconds
Started Aug 19 05:54:04 PM PDT 24
Finished Aug 19 05:54:05 PM PDT 24
Peak memory 215800 kb
Host smart-c59e77bb-3e7e-439e-a7a9-3d922dcf3b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686591924 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.686591924
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.1921933127
Short name T918
Test name
Test status
Simulation time 27815567 ps
CPU time 1.28 seconds
Started Aug 19 05:54:23 PM PDT 24
Finished Aug 19 05:54:24 PM PDT 24
Peak memory 218648 kb
Host smart-d7ee6cc4-3206-436e-9422-36ef56588eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921933127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1921933127
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.2973471363
Short name T129
Test name
Test status
Simulation time 45087893 ps
CPU time 1.19 seconds
Started Aug 19 05:54:20 PM PDT 24
Finished Aug 19 05:54:21 PM PDT 24
Peak memory 219868 kb
Host smart-961850ce-1df4-42f4-92e4-05eaee5e4900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973471363 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.2973471363
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.4038868702
Short name T690
Test name
Test status
Simulation time 205250709 ps
CPU time 2.75 seconds
Started Aug 19 05:54:23 PM PDT 24
Finished Aug 19 05:54:26 PM PDT 24
Peak memory 220672 kb
Host smart-83d7134e-5b0c-4495-9564-a76d28276216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038868702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.4038868702
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.1895446433
Short name T891
Test name
Test status
Simulation time 35760738 ps
CPU time 1.13 seconds
Started Aug 19 05:54:42 PM PDT 24
Finished Aug 19 05:54:45 PM PDT 24
Peak memory 220068 kb
Host smart-f2c95f34-2438-4bb1-8437-e5bdec20f802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895446433 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.1895446433
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.742206412
Short name T448
Test name
Test status
Simulation time 172154506 ps
CPU time 1.19 seconds
Started Aug 19 05:54:19 PM PDT 24
Finished Aug 19 05:54:20 PM PDT 24
Peak memory 217572 kb
Host smart-7e8c0df9-f4c0-4aab-9be8-274b9508fcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742206412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.742206412
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.2056462144
Short name T737
Test name
Test status
Simulation time 36788501 ps
CPU time 1.23 seconds
Started Aug 19 05:54:15 PM PDT 24
Finished Aug 19 05:54:16 PM PDT 24
Peak memory 219912 kb
Host smart-1b866dba-7c29-482f-9f1b-a4a478d6ec68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056462144 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.2056462144
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.113577833
Short name T298
Test name
Test status
Simulation time 31011102 ps
CPU time 1.28 seconds
Started Aug 19 05:54:22 PM PDT 24
Finished Aug 19 05:54:24 PM PDT 24
Peak memory 218656 kb
Host smart-37672fb4-b78c-49b2-a796-c9a98a85e630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113577833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.113577833
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.2983620616
Short name T70
Test name
Test status
Simulation time 110517684 ps
CPU time 1.25 seconds
Started Aug 19 05:54:15 PM PDT 24
Finished Aug 19 05:54:17 PM PDT 24
Peak memory 219444 kb
Host smart-aaa76c44-2578-48f9-ae1c-80432fb6cdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983620616 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.2983620616
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.1581621733
Short name T508
Test name
Test status
Simulation time 43057780 ps
CPU time 1.2 seconds
Started Aug 19 05:54:16 PM PDT 24
Finished Aug 19 05:54:17 PM PDT 24
Peak memory 219524 kb
Host smart-e2e10821-ab05-416a-abc2-fbfc6e5170f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581621733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1581621733
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.664006588
Short name T85
Test name
Test status
Simulation time 49445729 ps
CPU time 1.19 seconds
Started Aug 19 05:54:37 PM PDT 24
Finished Aug 19 05:54:39 PM PDT 24
Peak memory 220180 kb
Host smart-5e0241e8-3cee-41cf-ad5e-027d4ac0d798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664006588 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.664006588
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.297174389
Short name T524
Test name
Test status
Simulation time 40356107 ps
CPU time 1.53 seconds
Started Aug 19 05:54:41 PM PDT 24
Finished Aug 19 05:54:43 PM PDT 24
Peak memory 220456 kb
Host smart-e3dc48b3-ceb7-4bb6-b100-3425c0bd7b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297174389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.297174389
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.1081563040
Short name T218
Test name
Test status
Simulation time 24400904 ps
CPU time 1.18 seconds
Started Aug 19 05:54:22 PM PDT 24
Finished Aug 19 05:54:24 PM PDT 24
Peak memory 219900 kb
Host smart-dd9f01fe-d116-4450-a265-82c7effb3a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081563040 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.1081563040
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.2671646698
Short name T947
Test name
Test status
Simulation time 64804940 ps
CPU time 1.08 seconds
Started Aug 19 05:54:19 PM PDT 24
Finished Aug 19 05:54:20 PM PDT 24
Peak memory 220248 kb
Host smart-f1e0383e-ecb6-4d00-9e28-06365ce25399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671646698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2671646698
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.1789199312
Short name T972
Test name
Test status
Simulation time 62421180 ps
CPU time 1.25 seconds
Started Aug 19 05:54:31 PM PDT 24
Finished Aug 19 05:54:33 PM PDT 24
Peak memory 219680 kb
Host smart-48d51595-f9d2-4bc1-87b0-fa2240988973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789199312 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.1789199312
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.64297004
Short name T378
Test name
Test status
Simulation time 65926502 ps
CPU time 1.17 seconds
Started Aug 19 05:54:15 PM PDT 24
Finished Aug 19 05:54:16 PM PDT 24
Peak memory 217432 kb
Host smart-6183ae84-4e30-4e61-87f9-7d6c38c36a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64297004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.64297004
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.2496452677
Short name T585
Test name
Test status
Simulation time 31371718 ps
CPU time 1.3 seconds
Started Aug 19 05:52:53 PM PDT 24
Finished Aug 19 05:52:55 PM PDT 24
Peak memory 220108 kb
Host smart-ae6ce457-0bf3-4653-a1d8-8acb875092db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496452677 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.2496452677
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.173309307
Short name T843
Test name
Test status
Simulation time 23692143 ps
CPU time 0.95 seconds
Started Aug 19 05:52:52 PM PDT 24
Finished Aug 19 05:52:53 PM PDT 24
Peak memory 215036 kb
Host smart-e1778017-4506-4131-82e4-42954e68aa03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173309307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.173309307
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.4025707600
Short name T460
Test name
Test status
Simulation time 10740326 ps
CPU time 0.88 seconds
Started Aug 19 05:52:54 PM PDT 24
Finished Aug 19 05:52:55 PM PDT 24
Peak memory 215456 kb
Host smart-9d921138-772c-4ada-ac7d-65c6d1c0e0a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025707600 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.4025707600
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.386022879
Short name T156
Test name
Test status
Simulation time 85306616 ps
CPU time 1.05 seconds
Started Aug 19 05:53:00 PM PDT 24
Finished Aug 19 05:53:01 PM PDT 24
Peak memory 216964 kb
Host smart-405c2359-6419-4f82-bea4-7913944db32a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386022879 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_di
sable_auto_req_mode.386022879
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.4089141681
Short name T139
Test name
Test status
Simulation time 25840039 ps
CPU time 1.17 seconds
Started Aug 19 05:52:44 PM PDT 24
Finished Aug 19 05:52:45 PM PDT 24
Peak memory 220728 kb
Host smart-5890733c-22a3-42b1-96bb-347daca397e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089141681 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.4089141681
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.4199733164
Short name T841
Test name
Test status
Simulation time 96190639 ps
CPU time 1.56 seconds
Started Aug 19 05:52:52 PM PDT 24
Finished Aug 19 05:52:54 PM PDT 24
Peak memory 219140 kb
Host smart-33cf9f04-8293-46c0-b135-c6b1a1964e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199733164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.4199733164
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.3216437069
Short name T384
Test name
Test status
Simulation time 52700040 ps
CPU time 0.86 seconds
Started Aug 19 05:52:46 PM PDT 24
Finished Aug 19 05:52:47 PM PDT 24
Peak memory 215500 kb
Host smart-71e59a4a-f442-4d36-b052-862e3a5e16c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216437069 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.3216437069
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.2385083447
Short name T340
Test name
Test status
Simulation time 92047810 ps
CPU time 0.89 seconds
Started Aug 19 05:52:53 PM PDT 24
Finished Aug 19 05:52:54 PM PDT 24
Peak memory 215184 kb
Host smart-57cff06a-0d3a-467f-b32c-9e58b2e2e6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385083447 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2385083447
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.3785088023
Short name T757
Test name
Test status
Simulation time 531550073 ps
CPU time 3.26 seconds
Started Aug 19 05:52:44 PM PDT 24
Finished Aug 19 05:52:47 PM PDT 24
Peak memory 217272 kb
Host smart-15f1801f-913a-43c4-8ea0-ab9ccb3066b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785088023 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.3785088023
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2981756603
Short name T909
Test name
Test status
Simulation time 277995614 ps
CPU time 10.35 seconds
Started Aug 19 05:52:57 PM PDT 24
Finished Aug 19 05:53:08 PM PDT 24
Peak memory 218952 kb
Host smart-410cabb9-2a76-4d02-8a24-e49449d0c2ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981756603 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2981756603
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.361736689
Short name T759
Test name
Test status
Simulation time 38883029 ps
CPU time 1.17 seconds
Started Aug 19 05:54:18 PM PDT 24
Finished Aug 19 05:54:19 PM PDT 24
Peak memory 220148 kb
Host smart-47fdae04-773b-48d6-9149-8c54ec8a2927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361736689 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.361736689
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.3041895752
Short name T603
Test name
Test status
Simulation time 37491587 ps
CPU time 1.44 seconds
Started Aug 19 05:54:20 PM PDT 24
Finished Aug 19 05:54:22 PM PDT 24
Peak memory 218720 kb
Host smart-2ef10050-31bb-4b01-b101-8b19fe8048dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041895752 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3041895752
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.2773981936
Short name T182
Test name
Test status
Simulation time 88334982 ps
CPU time 1.21 seconds
Started Aug 19 05:54:24 PM PDT 24
Finished Aug 19 05:54:25 PM PDT 24
Peak memory 215780 kb
Host smart-49228d6b-5983-4dfd-a644-e11f0712fec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773981936 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.2773981936
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.3962568266
Short name T767
Test name
Test status
Simulation time 37346095 ps
CPU time 1.35 seconds
Started Aug 19 05:54:29 PM PDT 24
Finished Aug 19 05:54:31 PM PDT 24
Peak memory 217504 kb
Host smart-884e3798-de42-4d6a-b84a-5dcac2e5e695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962568266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.3962568266
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.3483415832
Short name T523
Test name
Test status
Simulation time 28051583 ps
CPU time 1.23 seconds
Started Aug 19 05:54:28 PM PDT 24
Finished Aug 19 05:54:30 PM PDT 24
Peak memory 218924 kb
Host smart-e12bfa64-4839-4096-8360-be62cfa39133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483415832 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.3483415832
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/153.edn_alert.827731650
Short name T115
Test name
Test status
Simulation time 48320866 ps
CPU time 1.17 seconds
Started Aug 19 05:54:23 PM PDT 24
Finished Aug 19 05:54:24 PM PDT 24
Peak memory 219076 kb
Host smart-b990b00f-6b49-4e01-95f4-33b176009375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827731650 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.827731650
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.1680342479
Short name T499
Test name
Test status
Simulation time 278118774 ps
CPU time 2.46 seconds
Started Aug 19 05:54:25 PM PDT 24
Finished Aug 19 05:54:28 PM PDT 24
Peak memory 218704 kb
Host smart-086450b6-ee07-49e0-94a5-22bf1a927b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680342479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.1680342479
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.3440246055
Short name T907
Test name
Test status
Simulation time 41990868 ps
CPU time 1.18 seconds
Started Aug 19 05:54:19 PM PDT 24
Finished Aug 19 05:54:21 PM PDT 24
Peak memory 219736 kb
Host smart-689936d9-dde0-4438-b858-ab281b980d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440246055 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.3440246055
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.1213893176
Short name T360
Test name
Test status
Simulation time 40623317 ps
CPU time 1.32 seconds
Started Aug 19 05:54:24 PM PDT 24
Finished Aug 19 05:54:26 PM PDT 24
Peak memory 218680 kb
Host smart-85aa91b0-8371-4059-952d-58cfd18c20e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213893176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1213893176
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.2029912763
Short name T898
Test name
Test status
Simulation time 64858521 ps
CPU time 1.05 seconds
Started Aug 19 05:54:18 PM PDT 24
Finished Aug 19 05:54:19 PM PDT 24
Peak memory 218872 kb
Host smart-56761c8b-dee1-486e-bd09-238b62a251c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029912763 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.2029912763
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.796145734
Short name T45
Test name
Test status
Simulation time 58455968 ps
CPU time 1.61 seconds
Started Aug 19 05:54:25 PM PDT 24
Finished Aug 19 05:54:27 PM PDT 24
Peak memory 218712 kb
Host smart-840b41e5-0cb3-44b0-a173-698d0ce4111e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796145734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.796145734
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.1242929152
Short name T738
Test name
Test status
Simulation time 48668201 ps
CPU time 1.2 seconds
Started Aug 19 05:54:32 PM PDT 24
Finished Aug 19 05:54:33 PM PDT 24
Peak memory 219212 kb
Host smart-29844f09-85dc-45be-87a3-742b88d6a8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242929152 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.1242929152
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.4154646429
Short name T348
Test name
Test status
Simulation time 55510059 ps
CPU time 1.79 seconds
Started Aug 19 05:54:20 PM PDT 24
Finished Aug 19 05:54:22 PM PDT 24
Peak memory 217456 kb
Host smart-c20bb5d9-ca08-45f4-b2ef-402a52a026e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154646429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.4154646429
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.2331793898
Short name T599
Test name
Test status
Simulation time 34507307 ps
CPU time 1.2 seconds
Started Aug 19 05:54:14 PM PDT 24
Finished Aug 19 05:54:16 PM PDT 24
Peak memory 218984 kb
Host smart-905fa084-cf7b-4bec-98d0-52b5a546e22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331793898 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.2331793898
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.4229073817
Short name T296
Test name
Test status
Simulation time 67341523 ps
CPU time 1.1 seconds
Started Aug 19 05:54:22 PM PDT 24
Finished Aug 19 05:54:23 PM PDT 24
Peak memory 220472 kb
Host smart-50268715-69e8-4440-99ef-3f4f9e4e6f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229073817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.4229073817
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.3770002995
Short name T673
Test name
Test status
Simulation time 22595886 ps
CPU time 1.16 seconds
Started Aug 19 05:54:26 PM PDT 24
Finished Aug 19 05:54:27 PM PDT 24
Peak memory 220640 kb
Host smart-8dc2d9fa-8f76-42e6-af44-1613384dbe6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770002995 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.3770002995
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.2226778869
Short name T776
Test name
Test status
Simulation time 52715255 ps
CPU time 1.07 seconds
Started Aug 19 05:54:18 PM PDT 24
Finished Aug 19 05:54:19 PM PDT 24
Peak memory 217516 kb
Host smart-b0e470e0-12a2-4591-9f4d-5e68c6336542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226778869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2226778869
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.3796305387
Short name T736
Test name
Test status
Simulation time 30452233 ps
CPU time 1.27 seconds
Started Aug 19 05:54:22 PM PDT 24
Finished Aug 19 05:54:23 PM PDT 24
Peak memory 219860 kb
Host smart-2ffc8c1d-f0f5-409a-b2a8-d33f168bb6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796305387 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.3796305387
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.1292398492
Short name T943
Test name
Test status
Simulation time 66975613 ps
CPU time 1.04 seconds
Started Aug 19 05:54:15 PM PDT 24
Finished Aug 19 05:54:16 PM PDT 24
Peak memory 217376 kb
Host smart-c85e9cee-b018-4930-8ca8-a430a2b0a17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292398492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1292398492
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.3930065312
Short name T220
Test name
Test status
Simulation time 36301909 ps
CPU time 1.09 seconds
Started Aug 19 05:52:53 PM PDT 24
Finished Aug 19 05:52:54 PM PDT 24
Peak memory 218636 kb
Host smart-2940d949-1278-4344-858b-501cadda9e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930065312 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3930065312
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.498607425
Short name T893
Test name
Test status
Simulation time 16019765 ps
CPU time 1.02 seconds
Started Aug 19 05:52:47 PM PDT 24
Finished Aug 19 05:52:48 PM PDT 24
Peak memory 215424 kb
Host smart-c3baaba5-e52c-4cc7-a8a5-236a2115d311
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498607425 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.498607425
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.261548802
Short name T644
Test name
Test status
Simulation time 60658206 ps
CPU time 0.84 seconds
Started Aug 19 05:52:47 PM PDT 24
Finished Aug 19 05:52:48 PM PDT 24
Peak memory 215492 kb
Host smart-20cb4670-8671-44ae-82a9-1c0485d91caf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261548802 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.261548802
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.3311800666
Short name T212
Test name
Test status
Simulation time 42187055 ps
CPU time 1.16 seconds
Started Aug 19 05:52:56 PM PDT 24
Finished Aug 19 05:52:57 PM PDT 24
Peak memory 217012 kb
Host smart-4e5c8cf0-94ca-4cbd-aaae-9f92543243e6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311800666 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.3311800666
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.234635248
Short name T6
Test name
Test status
Simulation time 57049712 ps
CPU time 1.17 seconds
Started Aug 19 05:52:58 PM PDT 24
Finished Aug 19 05:52:59 PM PDT 24
Peak memory 229800 kb
Host smart-e2e048d1-e5ea-4784-b01c-bb1e45175e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234635248 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.234635248
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.175609499
Short name T346
Test name
Test status
Simulation time 74235093 ps
CPU time 1.43 seconds
Started Aug 19 05:52:55 PM PDT 24
Finished Aug 19 05:52:56 PM PDT 24
Peak memory 218948 kb
Host smart-b76467aa-4cca-412f-9b6c-38b0a47a3eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175609499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.175609499
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_smoke.4154476344
Short name T975
Test name
Test status
Simulation time 44237596 ps
CPU time 0.96 seconds
Started Aug 19 05:52:50 PM PDT 24
Finished Aug 19 05:52:51 PM PDT 24
Peak memory 215380 kb
Host smart-25205ae1-cfc7-41a8-b696-89f088756739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154476344 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.4154476344
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.2386534483
Short name T389
Test name
Test status
Simulation time 451865784 ps
CPU time 5.05 seconds
Started Aug 19 05:52:47 PM PDT 24
Finished Aug 19 05:52:53 PM PDT 24
Peak memory 220224 kb
Host smart-1bb724d4-61ee-4303-b12f-cc373ddb208a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386534483 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2386534483
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.1034182782
Short name T562
Test name
Test status
Simulation time 7787576920 ps
CPU time 56.03 seconds
Started Aug 19 05:52:54 PM PDT 24
Finished Aug 19 05:53:50 PM PDT 24
Peak memory 217616 kb
Host smart-b4fa7474-6fc2-40ca-8643-79baaeec2198
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034182782 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.1034182782
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.1623954808
Short name T798
Test name
Test status
Simulation time 71020509 ps
CPU time 1.1 seconds
Started Aug 19 05:54:23 PM PDT 24
Finished Aug 19 05:54:24 PM PDT 24
Peak memory 218648 kb
Host smart-3a5bc239-2b15-4f53-a9f6-5b7d7a577d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623954808 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.1623954808
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.1241484527
Short name T44
Test name
Test status
Simulation time 70180169 ps
CPU time 1.3 seconds
Started Aug 19 05:54:27 PM PDT 24
Finished Aug 19 05:54:28 PM PDT 24
Peak memory 218464 kb
Host smart-e82fcf98-6588-4f52-99ad-b44f1f3eca63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241484527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1241484527
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.2531369253
Short name T469
Test name
Test status
Simulation time 24882170 ps
CPU time 1.18 seconds
Started Aug 19 05:54:22 PM PDT 24
Finished Aug 19 05:54:23 PM PDT 24
Peak memory 218756 kb
Host smart-e1612ac7-32c7-4b2f-8361-750cd796afab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531369253 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.2531369253
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.2266040011
Short name T516
Test name
Test status
Simulation time 106170490 ps
CPU time 1.06 seconds
Started Aug 19 05:54:18 PM PDT 24
Finished Aug 19 05:54:19 PM PDT 24
Peak memory 217380 kb
Host smart-668fe5d8-5a81-4ed2-94cd-3c1fa61f11f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266040011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.2266040011
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.84036370
Short name T829
Test name
Test status
Simulation time 83816096 ps
CPU time 1.18 seconds
Started Aug 19 05:54:15 PM PDT 24
Finished Aug 19 05:54:16 PM PDT 24
Peak memory 218824 kb
Host smart-b862d938-2005-456c-bd7d-550114139c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84036370 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.84036370
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/163.edn_alert.637065441
Short name T173
Test name
Test status
Simulation time 91804114 ps
CPU time 1.12 seconds
Started Aug 19 05:54:12 PM PDT 24
Finished Aug 19 05:54:13 PM PDT 24
Peak memory 220076 kb
Host smart-abe045d6-5b4f-48f1-a747-0c570fd9ad4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637065441 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.637065441
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.2799434433
Short name T565
Test name
Test status
Simulation time 75736651 ps
CPU time 1.09 seconds
Started Aug 19 05:54:19 PM PDT 24
Finished Aug 19 05:54:20 PM PDT 24
Peak memory 217460 kb
Host smart-13a5174c-6653-4202-9bfb-c17ee6f10227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799434433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2799434433
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.510911018
Short name T535
Test name
Test status
Simulation time 23578058 ps
CPU time 1.18 seconds
Started Aug 19 05:54:18 PM PDT 24
Finished Aug 19 05:54:19 PM PDT 24
Peak memory 218708 kb
Host smart-ceb5ff35-e95b-4fc7-83fe-b86b2cc02f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510911018 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.510911018
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.2082565127
Short name T913
Test name
Test status
Simulation time 99339325 ps
CPU time 1.42 seconds
Started Aug 19 05:54:21 PM PDT 24
Finished Aug 19 05:54:22 PM PDT 24
Peak memory 218936 kb
Host smart-979892ac-ece4-4033-b778-05049bcc834d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082565127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2082565127
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.2558023209
Short name T900
Test name
Test status
Simulation time 24797379 ps
CPU time 1.18 seconds
Started Aug 19 05:54:32 PM PDT 24
Finished Aug 19 05:54:34 PM PDT 24
Peak memory 219772 kb
Host smart-079bd2f8-1d2c-4a07-95d3-019b23ba643e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558023209 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.2558023209
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.2743294256
Short name T327
Test name
Test status
Simulation time 63263036 ps
CPU time 2.27 seconds
Started Aug 19 05:54:16 PM PDT 24
Finished Aug 19 05:54:18 PM PDT 24
Peak memory 218896 kb
Host smart-f91ebf15-450a-43f7-b9b1-127ff72bbc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743294256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.2743294256
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.1290633224
Short name T838
Test name
Test status
Simulation time 63798891 ps
CPU time 1.02 seconds
Started Aug 19 05:54:15 PM PDT 24
Finished Aug 19 05:54:17 PM PDT 24
Peak memory 219668 kb
Host smart-c9e1bb11-8277-487c-8898-f049c5f788c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290633224 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.1290633224
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.2294980731
Short name T932
Test name
Test status
Simulation time 35494239 ps
CPU time 1.56 seconds
Started Aug 19 05:54:26 PM PDT 24
Finished Aug 19 05:54:28 PM PDT 24
Peak memory 220032 kb
Host smart-52c2d5c1-58ea-45d1-ba1c-d1d6d85593d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294980731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.2294980731
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.614249749
Short name T219
Test name
Test status
Simulation time 30465681 ps
CPU time 1.29 seconds
Started Aug 19 05:54:30 PM PDT 24
Finished Aug 19 05:54:32 PM PDT 24
Peak memory 221120 kb
Host smart-47eb64d8-b136-40cf-ac4d-cbc841c29f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614249749 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.614249749
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.1530519556
Short name T944
Test name
Test status
Simulation time 44186653 ps
CPU time 1.33 seconds
Started Aug 19 05:54:16 PM PDT 24
Finished Aug 19 05:54:17 PM PDT 24
Peak memory 218908 kb
Host smart-f0bacc1e-dd6a-41f6-8f80-a04dd2ddf2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530519556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1530519556
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.3342908928
Short name T601
Test name
Test status
Simulation time 73246554 ps
CPU time 2.68 seconds
Started Aug 19 05:54:33 PM PDT 24
Finished Aug 19 05:54:36 PM PDT 24
Peak memory 220528 kb
Host smart-990e5918-caf0-46fb-b85b-6e8f993c1dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342908928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.3342908928
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.247186772
Short name T600
Test name
Test status
Simulation time 48192010 ps
CPU time 1.21 seconds
Started Aug 19 05:54:24 PM PDT 24
Finished Aug 19 05:54:26 PM PDT 24
Peak memory 220064 kb
Host smart-b71cb26b-f79a-4379-9f27-00eff7b96995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247186772 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.247186772
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.4052293074
Short name T725
Test name
Test status
Simulation time 75640572 ps
CPU time 1.2 seconds
Started Aug 19 05:54:29 PM PDT 24
Finished Aug 19 05:54:30 PM PDT 24
Peak memory 219344 kb
Host smart-028c2f4d-8479-4b8b-b9db-ebbdfc564572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052293074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.4052293074
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.1281524759
Short name T976
Test name
Test status
Simulation time 29814878 ps
CPU time 1.22 seconds
Started Aug 19 05:52:54 PM PDT 24
Finished Aug 19 05:52:55 PM PDT 24
Peak memory 219988 kb
Host smart-66d59f64-4561-4e28-a1b6-c1bb17bd2d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281524759 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1281524759
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.2890878377
Short name T763
Test name
Test status
Simulation time 19868863 ps
CPU time 0.97 seconds
Started Aug 19 05:53:10 PM PDT 24
Finished Aug 19 05:53:11 PM PDT 24
Peak memory 214980 kb
Host smart-69d4b692-e7c7-4002-8c70-ca3a3e96cb9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890878377 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2890878377
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.779851015
Short name T846
Test name
Test status
Simulation time 54689429 ps
CPU time 1.58 seconds
Started Aug 19 05:53:03 PM PDT 24
Finished Aug 19 05:53:05 PM PDT 24
Peak memory 217160 kb
Host smart-1496c574-ee8a-4356-bfec-cc65f2cf78b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779851015 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_di
sable_auto_req_mode.779851015
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_genbits.1369437490
Short name T654
Test name
Test status
Simulation time 47591551 ps
CPU time 0.98 seconds
Started Aug 19 05:52:44 PM PDT 24
Finished Aug 19 05:52:45 PM PDT 24
Peak memory 215684 kb
Host smart-31db0071-be5e-4893-9fc5-c368b9f7463a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369437490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1369437490
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.1618227438
Short name T669
Test name
Test status
Simulation time 26059978 ps
CPU time 1.06 seconds
Started Aug 19 05:52:44 PM PDT 24
Finished Aug 19 05:52:45 PM PDT 24
Peak memory 224388 kb
Host smart-8622d6b5-55be-4a60-87ff-7d76453377da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618227438 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1618227438
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.4207261457
Short name T473
Test name
Test status
Simulation time 30772087 ps
CPU time 0.95 seconds
Started Aug 19 05:52:57 PM PDT 24
Finished Aug 19 05:52:58 PM PDT 24
Peak memory 215404 kb
Host smart-6e347c6b-aa1e-4926-9d0a-3d2202aa5e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207261457 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.4207261457
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1659362477
Short name T108
Test name
Test status
Simulation time 724609594 ps
CPU time 3.44 seconds
Started Aug 19 05:52:47 PM PDT 24
Finished Aug 19 05:52:50 PM PDT 24
Peak memory 215408 kb
Host smart-e19bdd7e-d0f5-4d90-a43a-88abfb02a83b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659362477 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1659362477
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.811571813
Short name T243
Test name
Test status
Simulation time 9390794399 ps
CPU time 128.63 seconds
Started Aug 19 05:52:56 PM PDT 24
Finished Aug 19 05:55:05 PM PDT 24
Peak memory 218584 kb
Host smart-78b4c7b5-33ca-4556-9aba-759149ad80f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811571813 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.811571813
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.399954515
Short name T406
Test name
Test status
Simulation time 39644856 ps
CPU time 1.07 seconds
Started Aug 19 05:54:29 PM PDT 24
Finished Aug 19 05:54:30 PM PDT 24
Peak memory 218868 kb
Host smart-358b0a7b-5724-4b59-ba92-ef49487bade0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399954515 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.399954515
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.1073500858
Short name T618
Test name
Test status
Simulation time 41705050 ps
CPU time 1.14 seconds
Started Aug 19 05:54:27 PM PDT 24
Finished Aug 19 05:54:28 PM PDT 24
Peak memory 220252 kb
Host smart-a5d2a509-866a-4475-b924-112516ab8840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073500858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1073500858
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.3379112126
Short name T853
Test name
Test status
Simulation time 25475313 ps
CPU time 1.21 seconds
Started Aug 19 05:54:39 PM PDT 24
Finished Aug 19 05:54:41 PM PDT 24
Peak memory 219404 kb
Host smart-25033680-66c0-495c-ac8c-37a64a0cebe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379112126 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.3379112126
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.3782866181
Short name T357
Test name
Test status
Simulation time 73145037 ps
CPU time 1.27 seconds
Started Aug 19 05:54:23 PM PDT 24
Finished Aug 19 05:54:24 PM PDT 24
Peak memory 218776 kb
Host smart-f8a56b80-57f5-4886-84c5-7d115fbee832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782866181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.3782866181
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.617010965
Short name T962
Test name
Test status
Simulation time 57954841 ps
CPU time 1.25 seconds
Started Aug 19 05:54:31 PM PDT 24
Finished Aug 19 05:54:33 PM PDT 24
Peak memory 215844 kb
Host smart-e0a761cb-4381-4d87-a98e-3a409c04f187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617010965 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.617010965
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.1143010329
Short name T772
Test name
Test status
Simulation time 28610644 ps
CPU time 0.99 seconds
Started Aug 19 05:54:20 PM PDT 24
Finished Aug 19 05:54:21 PM PDT 24
Peak memory 217520 kb
Host smart-b8ec8505-b55d-4933-bc54-739869468611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143010329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.1143010329
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.2395458469
Short name T147
Test name
Test status
Simulation time 139034091 ps
CPU time 1.14 seconds
Started Aug 19 05:54:30 PM PDT 24
Finished Aug 19 05:54:31 PM PDT 24
Peak memory 218632 kb
Host smart-221d5f6e-0176-46b2-aa3f-0a5e17a31d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395458469 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.2395458469
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.3372676966
Short name T511
Test name
Test status
Simulation time 45513219 ps
CPU time 1.12 seconds
Started Aug 19 05:54:24 PM PDT 24
Finished Aug 19 05:54:25 PM PDT 24
Peak memory 217444 kb
Host smart-211b8cb8-08cd-47e8-a4df-4725777f286c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372676966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.3372676966
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.73318087
Short name T276
Test name
Test status
Simulation time 33503441 ps
CPU time 1.25 seconds
Started Aug 19 05:54:37 PM PDT 24
Finished Aug 19 05:54:39 PM PDT 24
Peak memory 218696 kb
Host smart-d25eb7bc-0e03-4d1f-9806-3b09cf008713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73318087 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.73318087
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.3588281740
Short name T355
Test name
Test status
Simulation time 47689876 ps
CPU time 1.74 seconds
Started Aug 19 05:54:21 PM PDT 24
Finished Aug 19 05:54:23 PM PDT 24
Peak memory 218828 kb
Host smart-14a2b2b0-bb21-4de9-9b0f-c02bb888e99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588281740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3588281740
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.3104013818
Short name T528
Test name
Test status
Simulation time 85440258 ps
CPU time 1.21 seconds
Started Aug 19 05:54:27 PM PDT 24
Finished Aug 19 05:54:29 PM PDT 24
Peak memory 218724 kb
Host smart-2ed94c01-5e3e-4b71-ba93-0e3f6e22abec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104013818 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.3104013818
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.3045444485
Short name T465
Test name
Test status
Simulation time 70696479 ps
CPU time 1.14 seconds
Started Aug 19 05:54:28 PM PDT 24
Finished Aug 19 05:54:29 PM PDT 24
Peak memory 217476 kb
Host smart-be923c84-1c99-4e73-a9b9-ac46766ffe86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045444485 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.3045444485
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.3924035548
Short name T953
Test name
Test status
Simulation time 25554084 ps
CPU time 1.17 seconds
Started Aug 19 05:54:26 PM PDT 24
Finished Aug 19 05:54:28 PM PDT 24
Peak memory 220056 kb
Host smart-a7105387-d814-416f-858a-2989be746d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924035548 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.3924035548
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.1123769027
Short name T695
Test name
Test status
Simulation time 210814211 ps
CPU time 1.11 seconds
Started Aug 19 05:54:21 PM PDT 24
Finished Aug 19 05:54:23 PM PDT 24
Peak memory 220476 kb
Host smart-6f2950d5-2dc2-4aac-b538-c89046172e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123769027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1123769027
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.2080151068
Short name T598
Test name
Test status
Simulation time 27922776 ps
CPU time 1.19 seconds
Started Aug 19 05:54:16 PM PDT 24
Finished Aug 19 05:54:17 PM PDT 24
Peak memory 218668 kb
Host smart-28e835fe-74bc-48e7-bb9a-5fbbe1ebef22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080151068 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.2080151068
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.2436507668
Short name T303
Test name
Test status
Simulation time 55207742 ps
CPU time 1.33 seconds
Started Aug 19 05:54:29 PM PDT 24
Finished Aug 19 05:54:31 PM PDT 24
Peak memory 218708 kb
Host smart-75574a29-ec60-4ea2-a222-dffe398b7c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436507668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2436507668
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.18360054
Short name T252
Test name
Test status
Simulation time 92036683 ps
CPU time 1.22 seconds
Started Aug 19 05:54:15 PM PDT 24
Finished Aug 19 05:54:17 PM PDT 24
Peak memory 218444 kb
Host smart-efb413ad-97be-4e8b-9543-dd9c0611b0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18360054 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.18360054
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.1377761514
Short name T88
Test name
Test status
Simulation time 101029205 ps
CPU time 1.91 seconds
Started Aug 19 05:54:21 PM PDT 24
Finished Aug 19 05:54:23 PM PDT 24
Peak memory 218664 kb
Host smart-859db937-28c1-4d12-b31a-890309cf78b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377761514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1377761514
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.2617541018
Short name T610
Test name
Test status
Simulation time 22851217 ps
CPU time 1.18 seconds
Started Aug 19 05:54:23 PM PDT 24
Finished Aug 19 05:54:25 PM PDT 24
Peak memory 221000 kb
Host smart-4649720c-7cdf-4ce3-bdf5-478bf7f8b025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617541018 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.2617541018
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.2904462559
Short name T546
Test name
Test status
Simulation time 25301528 ps
CPU time 1.17 seconds
Started Aug 19 05:54:22 PM PDT 24
Finished Aug 19 05:54:24 PM PDT 24
Peak memory 218720 kb
Host smart-2f7898f6-373d-4b6e-aa5e-bfb71e3870bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904462559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2904462559
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.604573459
Short name T960
Test name
Test status
Simulation time 24141857 ps
CPU time 1.2 seconds
Started Aug 19 05:53:09 PM PDT 24
Finished Aug 19 05:53:11 PM PDT 24
Peak memory 219628 kb
Host smart-cc4b9492-ebe9-43c5-95de-f6a2c024e7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604573459 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.604573459
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.3152249275
Short name T692
Test name
Test status
Simulation time 15329784 ps
CPU time 0.9 seconds
Started Aug 19 05:53:07 PM PDT 24
Finished Aug 19 05:53:08 PM PDT 24
Peak memory 207104 kb
Host smart-9dd3ad95-0ad8-4871-8c18-1bd4e711ae6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152249275 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.3152249275
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.2849515440
Short name T936
Test name
Test status
Simulation time 11946871 ps
CPU time 0.89 seconds
Started Aug 19 05:52:53 PM PDT 24
Finished Aug 19 05:52:54 PM PDT 24
Peak memory 207260 kb
Host smart-999486b4-f3fd-4e31-8df3-07a18de4e260
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849515440 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2849515440
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.1644243059
Short name T96
Test name
Test status
Simulation time 25109871 ps
CPU time 1.15 seconds
Started Aug 19 05:52:55 PM PDT 24
Finished Aug 19 05:52:56 PM PDT 24
Peak memory 218740 kb
Host smart-921f648c-efd8-49b3-82d0-d344ef46ae87
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644243059 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.1644243059
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.511791875
Short name T17
Test name
Test status
Simulation time 19856258 ps
CPU time 1.2 seconds
Started Aug 19 05:52:55 PM PDT 24
Finished Aug 19 05:52:57 PM PDT 24
Peak memory 224276 kb
Host smart-0db0cf12-bc8b-4b6a-a3a1-c60fede8f301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511791875 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.511791875
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.2536658177
Short name T844
Test name
Test status
Simulation time 99228747 ps
CPU time 1.72 seconds
Started Aug 19 05:52:59 PM PDT 24
Finished Aug 19 05:53:01 PM PDT 24
Peak memory 219072 kb
Host smart-5ee76774-11aa-430a-91c2-982e892618a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536658177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2536658177
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.2433942419
Short name T106
Test name
Test status
Simulation time 28858991 ps
CPU time 0.85 seconds
Started Aug 19 05:52:54 PM PDT 24
Finished Aug 19 05:53:00 PM PDT 24
Peak memory 215684 kb
Host smart-24c47e66-41ed-4df8-b6c3-f48e28d97266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433942419 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.2433942419
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.4142748734
Short name T470
Test name
Test status
Simulation time 37269319 ps
CPU time 0.92 seconds
Started Aug 19 05:53:17 PM PDT 24
Finished Aug 19 05:53:18 PM PDT 24
Peak memory 215400 kb
Host smart-43f47fa9-952d-43f3-aad2-0c5fc6d79837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142748734 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.4142748734
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.2404569731
Short name T959
Test name
Test status
Simulation time 67709799 ps
CPU time 1.41 seconds
Started Aug 19 05:53:01 PM PDT 24
Finished Aug 19 05:53:03 PM PDT 24
Peak memory 218368 kb
Host smart-d0dc31a5-5881-4f37-99b2-94c8613482c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404569731 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.2404569731
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.933538598
Short name T745
Test name
Test status
Simulation time 7055341619 ps
CPU time 39.05 seconds
Started Aug 19 05:53:08 PM PDT 24
Finished Aug 19 05:53:47 PM PDT 24
Peak memory 218708 kb
Host smart-d4e9242f-605d-490e-a1e3-82213bdaa643
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933538598 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.933538598
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.1593496170
Short name T814
Test name
Test status
Simulation time 23566223 ps
CPU time 1.21 seconds
Started Aug 19 05:54:26 PM PDT 24
Finished Aug 19 05:54:27 PM PDT 24
Peak memory 219592 kb
Host smart-9b938b80-0d4b-46e2-8931-33e71e302b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593496170 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.1593496170
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.1710490956
Short name T495
Test name
Test status
Simulation time 90471957 ps
CPU time 1.07 seconds
Started Aug 19 05:54:33 PM PDT 24
Finished Aug 19 05:54:34 PM PDT 24
Peak memory 217536 kb
Host smart-f8809109-e001-4092-909b-8cebff6fa3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710490956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.1710490956
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.2566404288
Short name T830
Test name
Test status
Simulation time 21420486 ps
CPU time 1.15 seconds
Started Aug 19 05:54:26 PM PDT 24
Finished Aug 19 05:54:28 PM PDT 24
Peak memory 218644 kb
Host smart-d6cdb2b4-27f3-43e6-b57e-67940ab87135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566404288 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.2566404288
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.1228690330
Short name T409
Test name
Test status
Simulation time 77096095 ps
CPU time 1.51 seconds
Started Aug 19 05:54:37 PM PDT 24
Finished Aug 19 05:54:38 PM PDT 24
Peak memory 218908 kb
Host smart-b62bd983-3c33-4d27-a859-ab09ca600c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228690330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.1228690330
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.670812063
Short name T421
Test name
Test status
Simulation time 72392557 ps
CPU time 1.17 seconds
Started Aug 19 05:54:35 PM PDT 24
Finished Aug 19 05:54:36 PM PDT 24
Peak memory 219760 kb
Host smart-63577735-0a62-4b86-a648-4a624cf1a645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670812063 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.670812063
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.1623978771
Short name T318
Test name
Test status
Simulation time 19254271 ps
CPU time 1.06 seconds
Started Aug 19 05:54:28 PM PDT 24
Finished Aug 19 05:54:29 PM PDT 24
Peak memory 217496 kb
Host smart-4a050f06-21df-4570-bc17-fbbd5a95751c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623978771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.1623978771
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.2758749528
Short name T471
Test name
Test status
Simulation time 289641510 ps
CPU time 1.26 seconds
Started Aug 19 05:54:35 PM PDT 24
Finished Aug 19 05:54:36 PM PDT 24
Peak memory 218560 kb
Host smart-4c166798-ac0a-4f76-9817-d295ddf7cbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758749528 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.2758749528
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.2029152932
Short name T50
Test name
Test status
Simulation time 61271291 ps
CPU time 1.39 seconds
Started Aug 19 05:54:32 PM PDT 24
Finished Aug 19 05:54:33 PM PDT 24
Peak memory 217348 kb
Host smart-a20d39fe-b4ae-4592-92b7-989140a5eedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029152932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.2029152932
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.4267521251
Short name T622
Test name
Test status
Simulation time 54425554 ps
CPU time 1.22 seconds
Started Aug 19 05:54:39 PM PDT 24
Finished Aug 19 05:54:41 PM PDT 24
Peak memory 215796 kb
Host smart-3d227be0-6e6b-4c1f-bd8c-7e2f06fceb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267521251 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.4267521251
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.104331433
Short name T778
Test name
Test status
Simulation time 59252596 ps
CPU time 1.54 seconds
Started Aug 19 05:54:27 PM PDT 24
Finished Aug 19 05:54:29 PM PDT 24
Peak memory 217552 kb
Host smart-4dbb7557-d525-487a-be43-65fa9f99cb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104331433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.104331433
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.1450600002
Short name T751
Test name
Test status
Simulation time 273378526 ps
CPU time 1.28 seconds
Started Aug 19 05:54:35 PM PDT 24
Finished Aug 19 05:54:36 PM PDT 24
Peak memory 219816 kb
Host smart-c3fa045a-25c5-4d87-8964-198c7b79dd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450600002 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.1450600002
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.4271824681
Short name T938
Test name
Test status
Simulation time 58731063 ps
CPU time 1.44 seconds
Started Aug 19 05:54:24 PM PDT 24
Finished Aug 19 05:54:26 PM PDT 24
Peak memory 218824 kb
Host smart-39155630-51fa-426d-9e0c-b577773a71b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271824681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.4271824681
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.3837897269
Short name T699
Test name
Test status
Simulation time 39290924 ps
CPU time 1.15 seconds
Started Aug 19 05:54:33 PM PDT 24
Finished Aug 19 05:54:35 PM PDT 24
Peak memory 219624 kb
Host smart-bc719d9e-153d-4b00-ac90-82d12f07a91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837897269 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.3837897269
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.19421036
Short name T839
Test name
Test status
Simulation time 37571696 ps
CPU time 1.05 seconds
Started Aug 19 05:54:24 PM PDT 24
Finished Aug 19 05:54:26 PM PDT 24
Peak memory 217644 kb
Host smart-5057e025-fcf5-49e2-99a3-35ce1a189af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19421036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.19421036
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.1423340249
Short name T667
Test name
Test status
Simulation time 80656166 ps
CPU time 1.27 seconds
Started Aug 19 05:54:38 PM PDT 24
Finished Aug 19 05:54:40 PM PDT 24
Peak memory 218812 kb
Host smart-a18d5c89-7f63-462d-801c-a692a9f963c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423340249 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.1423340249
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.2897530170
Short name T71
Test name
Test status
Simulation time 57143359 ps
CPU time 0.95 seconds
Started Aug 19 05:54:29 PM PDT 24
Finished Aug 19 05:54:30 PM PDT 24
Peak memory 217488 kb
Host smart-189df493-e4aa-42c6-86f6-9966973edd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897530170 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2897530170
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.2702337214
Short name T477
Test name
Test status
Simulation time 93077144 ps
CPU time 1.21 seconds
Started Aug 19 05:54:24 PM PDT 24
Finished Aug 19 05:54:26 PM PDT 24
Peak memory 215740 kb
Host smart-6134f03f-ed35-49d4-be80-e5c5eb0c4776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702337214 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.2702337214
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.1587665521
Short name T503
Test name
Test status
Simulation time 92534751 ps
CPU time 3.57 seconds
Started Aug 19 05:54:35 PM PDT 24
Finished Aug 19 05:54:39 PM PDT 24
Peak memory 219324 kb
Host smart-b5285f0a-ea63-47c2-a65c-982c6b7d6c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587665521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1587665521
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.1594849956
Short name T648
Test name
Test status
Simulation time 60821479 ps
CPU time 1.27 seconds
Started Aug 19 05:54:41 PM PDT 24
Finished Aug 19 05:54:42 PM PDT 24
Peak memory 218720 kb
Host smart-5566df7a-589a-44a4-9a70-6ae4014bd663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594849956 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.1594849956
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.831502901
Short name T945
Test name
Test status
Simulation time 200912223 ps
CPU time 2.76 seconds
Started Aug 19 05:54:41 PM PDT 24
Finished Aug 19 05:54:44 PM PDT 24
Peak memory 217712 kb
Host smart-3e29e7ac-c825-47f0-a9df-288203df0427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831502901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.831502901
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.1870391126
Short name T464
Test name
Test status
Simulation time 89077920 ps
CPU time 1.27 seconds
Started Aug 19 05:53:06 PM PDT 24
Finished Aug 19 05:53:07 PM PDT 24
Peak memory 220000 kb
Host smart-61979f8a-e40e-44e1-aff8-a064afa1af33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870391126 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.1870391126
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.1306300473
Short name T640
Test name
Test status
Simulation time 35307000 ps
CPU time 0.85 seconds
Started Aug 19 05:53:04 PM PDT 24
Finished Aug 19 05:53:05 PM PDT 24
Peak memory 206932 kb
Host smart-6e9c64fc-fb55-48e1-b7a3-621a3d8a7bf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306300473 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.1306300473
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.3002322369
Short name T693
Test name
Test status
Simulation time 55058915 ps
CPU time 0.85 seconds
Started Aug 19 05:52:57 PM PDT 24
Finished Aug 19 05:52:58 PM PDT 24
Peak memory 215416 kb
Host smart-9f2e3c64-6fba-4082-822f-20190f1358b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002322369 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.3002322369
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_genbits.1733865083
Short name T633
Test name
Test status
Simulation time 86905192 ps
CPU time 1.13 seconds
Started Aug 19 05:53:09 PM PDT 24
Finished Aug 19 05:53:11 PM PDT 24
Peak memory 217388 kb
Host smart-8feb5331-e070-4c23-932d-0f634c992e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733865083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.1733865083
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.4185227286
Short name T97
Test name
Test status
Simulation time 31670874 ps
CPU time 0.94 seconds
Started Aug 19 05:53:04 PM PDT 24
Finished Aug 19 05:53:05 PM PDT 24
Peak memory 215776 kb
Host smart-00389405-2857-40cf-b79a-d4baf1854155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185227286 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.4185227286
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.1106420343
Short name T826
Test name
Test status
Simulation time 17769809 ps
CPU time 1.02 seconds
Started Aug 19 05:53:03 PM PDT 24
Finished Aug 19 05:53:04 PM PDT 24
Peak memory 215380 kb
Host smart-74243339-d11e-4aba-8194-100793cd612d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106420343 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.1106420343
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.4032026762
Short name T529
Test name
Test status
Simulation time 161017562 ps
CPU time 1.89 seconds
Started Aug 19 05:52:54 PM PDT 24
Finished Aug 19 05:52:56 PM PDT 24
Peak memory 217312 kb
Host smart-da86b0f7-97a4-4636-8344-6d125979fde3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032026762 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.4032026762
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.3419174191
Short name T497
Test name
Test status
Simulation time 2632040182 ps
CPU time 32.44 seconds
Started Aug 19 05:52:55 PM PDT 24
Finished Aug 19 05:53:27 PM PDT 24
Peak memory 218764 kb
Host smart-e1be01d7-0443-4991-9cb3-981e8dda36a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419174191 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.3419174191
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.2501866773
Short name T659
Test name
Test status
Simulation time 106570353 ps
CPU time 1.34 seconds
Started Aug 19 05:54:28 PM PDT 24
Finished Aug 19 05:54:29 PM PDT 24
Peak memory 215792 kb
Host smart-7797aa96-2c3e-4ac6-b428-12dfae463ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501866773 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.2501866773
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.3460537132
Short name T467
Test name
Test status
Simulation time 73797532 ps
CPU time 1.11 seconds
Started Aug 19 05:54:24 PM PDT 24
Finished Aug 19 05:54:26 PM PDT 24
Peak memory 218900 kb
Host smart-ecafde5c-7e5e-48b6-b9b3-d8d059982099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460537132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3460537132
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.3673212637
Short name T240
Test name
Test status
Simulation time 44249703 ps
CPU time 1.18 seconds
Started Aug 19 05:54:50 PM PDT 24
Finished Aug 19 05:54:51 PM PDT 24
Peak memory 218704 kb
Host smart-3e105416-be55-4cc1-b957-7715afe0ff79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673212637 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.3673212637
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.530225706
Short name T684
Test name
Test status
Simulation time 78153180 ps
CPU time 1.2 seconds
Started Aug 19 05:54:24 PM PDT 24
Finished Aug 19 05:54:25 PM PDT 24
Peak memory 219560 kb
Host smart-36b2d8fa-cf5c-44e9-a40a-92c52d8277e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530225706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.530225706
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.327911204
Short name T831
Test name
Test status
Simulation time 82432575 ps
CPU time 1.35 seconds
Started Aug 19 05:54:54 PM PDT 24
Finished Aug 19 05:54:55 PM PDT 24
Peak memory 220396 kb
Host smart-7e372e27-f73c-48c3-a876-583698c20b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327911204 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.327911204
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.4105197955
Short name T665
Test name
Test status
Simulation time 101776743 ps
CPU time 1.22 seconds
Started Aug 19 05:54:44 PM PDT 24
Finished Aug 19 05:54:45 PM PDT 24
Peak memory 219256 kb
Host smart-0fb07095-6d6d-4903-ae10-2bbeaeeecddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105197955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.4105197955
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.3239595706
Short name T382
Test name
Test status
Simulation time 39003376 ps
CPU time 1.34 seconds
Started Aug 19 05:54:26 PM PDT 24
Finished Aug 19 05:54:27 PM PDT 24
Peak memory 218580 kb
Host smart-0d591ca3-72b9-4e04-ba97-e4bc9cb485bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239595706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3239595706
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.3598856457
Short name T608
Test name
Test status
Simulation time 25689830 ps
CPU time 1.19 seconds
Started Aug 19 05:54:32 PM PDT 24
Finished Aug 19 05:54:33 PM PDT 24
Peak memory 220896 kb
Host smart-639428df-8719-4b92-a214-e420203b515e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598856457 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.3598856457
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.635071347
Short name T791
Test name
Test status
Simulation time 48299466 ps
CPU time 1.57 seconds
Started Aug 19 05:54:29 PM PDT 24
Finished Aug 19 05:54:31 PM PDT 24
Peak memory 220000 kb
Host smart-a83e6684-85f5-4183-b091-56dab97f8464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635071347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.635071347
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.3855798282
Short name T479
Test name
Test status
Simulation time 69035933 ps
CPU time 1.08 seconds
Started Aug 19 05:54:34 PM PDT 24
Finished Aug 19 05:54:35 PM PDT 24
Peak memory 218664 kb
Host smart-19dca73d-e4ca-4993-b7d5-753bc8547401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855798282 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.3855798282
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.2098187873
Short name T407
Test name
Test status
Simulation time 40475549 ps
CPU time 1.27 seconds
Started Aug 19 05:54:32 PM PDT 24
Finished Aug 19 05:54:34 PM PDT 24
Peak memory 218736 kb
Host smart-f5fcc49b-978c-48b3-b4ec-869d726f2bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098187873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.2098187873
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.266548663
Short name T352
Test name
Test status
Simulation time 27789846 ps
CPU time 1.24 seconds
Started Aug 19 05:54:33 PM PDT 24
Finished Aug 19 05:54:35 PM PDT 24
Peak memory 215768 kb
Host smart-ef21a488-4fc5-4c99-981c-47d288f63779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266548663 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.266548663
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.2634808671
Short name T775
Test name
Test status
Simulation time 68324661 ps
CPU time 1.37 seconds
Started Aug 19 05:54:18 PM PDT 24
Finished Aug 19 05:54:19 PM PDT 24
Peak memory 219196 kb
Host smart-27c42c01-c5a3-413b-ae4d-33d284649885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634808671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2634808671
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.1139261888
Short name T783
Test name
Test status
Simulation time 37560616 ps
CPU time 1.13 seconds
Started Aug 19 05:54:33 PM PDT 24
Finished Aug 19 05:54:35 PM PDT 24
Peak memory 219932 kb
Host smart-f3ba1e65-32ff-484f-916b-9ffb02d7eca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139261888 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.1139261888
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.887424532
Short name T433
Test name
Test status
Simulation time 76553101 ps
CPU time 1.2 seconds
Started Aug 19 05:54:45 PM PDT 24
Finished Aug 19 05:54:46 PM PDT 24
Peak memory 217444 kb
Host smart-e533a69f-d313-4cb0-82f8-15bac0afb1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887424532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.887424532
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.3512698706
Short name T556
Test name
Test status
Simulation time 57314591 ps
CPU time 1.25 seconds
Started Aug 19 05:54:19 PM PDT 24
Finished Aug 19 05:54:20 PM PDT 24
Peak memory 215828 kb
Host smart-71b621d7-4e58-46f8-858e-6ee3294ed11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512698706 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.3512698706
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.2543317975
Short name T764
Test name
Test status
Simulation time 160019276 ps
CPU time 3.34 seconds
Started Aug 19 05:54:27 PM PDT 24
Finished Aug 19 05:54:30 PM PDT 24
Peak memory 220688 kb
Host smart-e1c70916-4e59-4027-999d-a9113b136987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543317975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2543317975
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.1662054591
Short name T526
Test name
Test status
Simulation time 326067556 ps
CPU time 1.27 seconds
Started Aug 19 05:54:35 PM PDT 24
Finished Aug 19 05:54:36 PM PDT 24
Peak memory 219676 kb
Host smart-51f79afa-6e38-4b24-b9c9-98df6b6ebf64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662054591 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.1662054591
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.2916355118
Short name T666
Test name
Test status
Simulation time 37796280 ps
CPU time 1.34 seconds
Started Aug 19 05:54:47 PM PDT 24
Finished Aug 19 05:54:49 PM PDT 24
Peak memory 218576 kb
Host smart-60e714ea-31c2-4f01-b7ac-45b65fb025d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916355118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2916355118
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.2447797881
Short name T624
Test name
Test status
Simulation time 95075334 ps
CPU time 1.21 seconds
Started Aug 19 05:52:29 PM PDT 24
Finished Aug 19 05:52:31 PM PDT 24
Peak memory 219720 kb
Host smart-8be7bd78-3fc4-43f5-9e58-5d7995f4e193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447797881 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2447797881
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.3151029039
Short name T24
Test name
Test status
Simulation time 21054534 ps
CPU time 0.88 seconds
Started Aug 19 05:52:32 PM PDT 24
Finished Aug 19 05:52:33 PM PDT 24
Peak memory 206848 kb
Host smart-30890a6c-f499-4d8e-b36b-07edd80b0a93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151029039 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3151029039
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.2716919590
Short name T184
Test name
Test status
Simulation time 11601581 ps
CPU time 0.86 seconds
Started Aug 19 05:52:35 PM PDT 24
Finished Aug 19 05:52:36 PM PDT 24
Peak memory 215584 kb
Host smart-f2c3f1e6-b7ba-459b-9f5f-2a8a791d07e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716919590 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2716919590
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.1313270666
Short name T158
Test name
Test status
Simulation time 49003646 ps
CPU time 1.53 seconds
Started Aug 19 05:52:38 PM PDT 24
Finished Aug 19 05:52:40 PM PDT 24
Peak memory 216916 kb
Host smart-38c66f9a-80b7-4f1b-93c7-dc31695111d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313270666 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.1313270666
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.2341869221
Short name T7
Test name
Test status
Simulation time 63950556 ps
CPU time 1.04 seconds
Started Aug 19 05:52:35 PM PDT 24
Finished Aug 19 05:52:37 PM PDT 24
Peak memory 220888 kb
Host smart-0f2f52e3-d572-47fc-bb5c-0d8410a11cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341869221 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.2341869221
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.3496357786
Short name T542
Test name
Test status
Simulation time 99182350 ps
CPU time 1.07 seconds
Started Aug 19 05:52:51 PM PDT 24
Finished Aug 19 05:52:52 PM PDT 24
Peak memory 217660 kb
Host smart-7280cd9b-e777-4154-b997-734c30d0d49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496357786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3496357786
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.3453415949
Short name T4
Test name
Test status
Simulation time 24781823 ps
CPU time 0.95 seconds
Started Aug 19 05:52:30 PM PDT 24
Finished Aug 19 05:52:31 PM PDT 24
Peak memory 215616 kb
Host smart-83b32f0c-f898-46c8-80bc-d06900d63463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453415949 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3453415949
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.275788819
Short name T873
Test name
Test status
Simulation time 23929984 ps
CPU time 0.91 seconds
Started Aug 19 05:52:42 PM PDT 24
Finished Aug 19 05:52:43 PM PDT 24
Peak memory 207196 kb
Host smart-ea8f1d26-d11d-47e1-a1c6-4473f34328ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275788819 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.275788819
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.3380256632
Short name T63
Test name
Test status
Simulation time 2114329319 ps
CPU time 8.94 seconds
Started Aug 19 05:52:30 PM PDT 24
Finished Aug 19 05:52:39 PM PDT 24
Peak memory 237596 kb
Host smart-5d001b54-d49f-4a65-a315-1b9b16a2ce33
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380256632 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.3380256632
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.2180608047
Short name T78
Test name
Test status
Simulation time 15881596 ps
CPU time 1 seconds
Started Aug 19 05:52:32 PM PDT 24
Finished Aug 19 05:52:33 PM PDT 24
Peak memory 215416 kb
Host smart-e9846589-0290-4f12-a9d3-4f505fa4850a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180608047 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.2180608047
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.3630924985
Short name T236
Test name
Test status
Simulation time 854000214 ps
CPU time 3.76 seconds
Started Aug 19 05:52:38 PM PDT 24
Finished Aug 19 05:52:42 PM PDT 24
Peak memory 215480 kb
Host smart-0c8f4ad0-9144-47bd-83b5-bd59c9016f1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630924985 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.3630924985
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.2060487327
Short name T38
Test name
Test status
Simulation time 4988966716 ps
CPU time 117.47 seconds
Started Aug 19 05:52:37 PM PDT 24
Finished Aug 19 05:54:35 PM PDT 24
Peak memory 218088 kb
Host smart-928f2055-9e55-4a54-8895-8f87f7d9b3fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060487327 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.2060487327
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.2050016366
Short name T855
Test name
Test status
Simulation time 46510048 ps
CPU time 1.19 seconds
Started Aug 19 05:52:59 PM PDT 24
Finished Aug 19 05:53:00 PM PDT 24
Peak memory 218876 kb
Host smart-2da78e9f-0632-41df-9669-5db84405a433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050016366 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.2050016366
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.1598940255
Short name T707
Test name
Test status
Simulation time 19351442 ps
CPU time 0.97 seconds
Started Aug 19 05:52:52 PM PDT 24
Finished Aug 19 05:52:54 PM PDT 24
Peak memory 206888 kb
Host smart-139f0c38-2d54-44a1-8359-eccacc0d5be5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598940255 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.1598940255
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.3530515884
Short name T48
Test name
Test status
Simulation time 13313403 ps
CPU time 0.94 seconds
Started Aug 19 05:53:03 PM PDT 24
Finished Aug 19 05:53:04 PM PDT 24
Peak memory 215624 kb
Host smart-449b2f3d-6cb0-47d8-b4e6-4c83c220af09
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530515884 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3530515884
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.3127585050
Short name T630
Test name
Test status
Simulation time 21590942 ps
CPU time 1.13 seconds
Started Aug 19 05:53:04 PM PDT 24
Finished Aug 19 05:53:05 PM PDT 24
Peak memory 217000 kb
Host smart-220e714d-f51a-4fa0-a703-67b67bef9397
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127585050 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.3127585050
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.716620349
Short name T457
Test name
Test status
Simulation time 24560405 ps
CPU time 0.91 seconds
Started Aug 19 05:52:45 PM PDT 24
Finished Aug 19 05:52:46 PM PDT 24
Peak memory 218196 kb
Host smart-77f72b3a-93f7-44f9-8fd4-e1b00cef96a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716620349 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.716620349
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.565894694
Short name T620
Test name
Test status
Simulation time 134752448 ps
CPU time 1.53 seconds
Started Aug 19 05:53:04 PM PDT 24
Finished Aug 19 05:53:06 PM PDT 24
Peak memory 218740 kb
Host smart-289920ed-a784-4c52-b8c3-11e616d957d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565894694 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.565894694
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_smoke.1588192356
Short name T723
Test name
Test status
Simulation time 44704804 ps
CPU time 0.96 seconds
Started Aug 19 05:53:12 PM PDT 24
Finished Aug 19 05:53:13 PM PDT 24
Peak memory 215384 kb
Host smart-ab6d26c5-63d3-4065-8254-20e2c56fc465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588192356 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.1588192356
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.2977842941
Short name T356
Test name
Test status
Simulation time 239164069 ps
CPU time 2.69 seconds
Started Aug 19 05:52:57 PM PDT 24
Finished Aug 19 05:53:00 PM PDT 24
Peak memory 215408 kb
Host smart-48166b13-1f6f-42d4-b63c-6ec6f0c557f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977842941 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2977842941
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.893999237
Short name T662
Test name
Test status
Simulation time 11638098033 ps
CPU time 73.38 seconds
Started Aug 19 05:52:53 PM PDT 24
Finished Aug 19 05:54:06 PM PDT 24
Peak memory 218964 kb
Host smart-3bb296b8-5539-4e2b-8e2c-db2470923dcd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893999237 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.893999237
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.2879702313
Short name T494
Test name
Test status
Simulation time 42714903 ps
CPU time 1.7 seconds
Started Aug 19 05:54:21 PM PDT 24
Finished Aug 19 05:54:23 PM PDT 24
Peak memory 218816 kb
Host smart-62500679-2c73-49f0-9bb9-b9003d7ffd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879702313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2879702313
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.292088973
Short name T61
Test name
Test status
Simulation time 33661695 ps
CPU time 1.28 seconds
Started Aug 19 05:54:55 PM PDT 24
Finished Aug 19 05:54:56 PM PDT 24
Peak memory 218584 kb
Host smart-96b2f0c9-1aa9-4c89-bfa2-39055b0d59cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292088973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.292088973
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.1689781015
Short name T848
Test name
Test status
Simulation time 149656966 ps
CPU time 2.73 seconds
Started Aug 19 05:54:34 PM PDT 24
Finished Aug 19 05:54:37 PM PDT 24
Peak memory 220720 kb
Host smart-fcbf12b3-3f6b-42c9-8ffa-be8f2b07a763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689781015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.1689781015
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.4041329203
Short name T315
Test name
Test status
Simulation time 42625926 ps
CPU time 1.61 seconds
Started Aug 19 05:54:22 PM PDT 24
Finished Aug 19 05:54:24 PM PDT 24
Peak memory 218716 kb
Host smart-f08081a2-437c-4124-8600-7959f7d32e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041329203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.4041329203
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.3756920052
Short name T92
Test name
Test status
Simulation time 28554715 ps
CPU time 1.16 seconds
Started Aug 19 05:54:27 PM PDT 24
Finished Aug 19 05:54:29 PM PDT 24
Peak memory 215396 kb
Host smart-2dbbca01-8094-45e0-84d9-04513fb1a5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756920052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3756920052
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.4080584041
Short name T47
Test name
Test status
Simulation time 105779724 ps
CPU time 1.41 seconds
Started Aug 19 05:54:25 PM PDT 24
Finished Aug 19 05:54:27 PM PDT 24
Peak memory 219240 kb
Host smart-39da87b1-9198-49da-9b46-4bb6cfaf4165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080584041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.4080584041
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2204045752
Short name T46
Test name
Test status
Simulation time 33261435 ps
CPU time 1.31 seconds
Started Aug 19 05:54:57 PM PDT 24
Finished Aug 19 05:54:58 PM PDT 24
Peak memory 215424 kb
Host smart-2d949ce7-1f13-4aa1-bb32-479ef1453c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204045752 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2204045752
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.4101755805
Short name T432
Test name
Test status
Simulation time 99732301 ps
CPU time 1.25 seconds
Started Aug 19 05:54:32 PM PDT 24
Finished Aug 19 05:54:34 PM PDT 24
Peak memory 218740 kb
Host smart-c5f1bc2a-c329-4c3f-acf2-21801886dd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101755805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.4101755805
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.1711779080
Short name T59
Test name
Test status
Simulation time 67137927 ps
CPU time 0.97 seconds
Started Aug 19 05:54:27 PM PDT 24
Finished Aug 19 05:54:28 PM PDT 24
Peak memory 217324 kb
Host smart-f5f6905c-4c77-48a5-be80-543c65eb415b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711779080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.1711779080
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.2832351446
Short name T484
Test name
Test status
Simulation time 55819720 ps
CPU time 1.39 seconds
Started Aug 19 05:54:32 PM PDT 24
Finished Aug 19 05:54:33 PM PDT 24
Peak memory 218736 kb
Host smart-111dbd5f-80e2-4828-bff7-33464bd137a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832351446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2832351446
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.2295792572
Short name T719
Test name
Test status
Simulation time 20870184 ps
CPU time 1.1 seconds
Started Aug 19 05:52:57 PM PDT 24
Finished Aug 19 05:52:58 PM PDT 24
Peak memory 218444 kb
Host smart-1fde3812-c6d9-456e-b9a7-266ee372f65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295792572 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.2295792572
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.1528954479
Short name T787
Test name
Test status
Simulation time 105857892 ps
CPU time 0.91 seconds
Started Aug 19 05:53:04 PM PDT 24
Finished Aug 19 05:53:05 PM PDT 24
Peak memory 206864 kb
Host smart-4c446b54-2aa5-455b-8954-e971d4f790c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528954479 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.1528954479
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.3630197008
Short name T323
Test name
Test status
Simulation time 62492168 ps
CPU time 1 seconds
Started Aug 19 05:52:55 PM PDT 24
Finished Aug 19 05:52:56 PM PDT 24
Peak memory 215228 kb
Host smart-988db624-481b-4927-a9ca-c0b523c677e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630197008 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.3630197008
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.2043908082
Short name T58
Test name
Test status
Simulation time 22403808 ps
CPU time 1.01 seconds
Started Aug 19 05:53:16 PM PDT 24
Finished Aug 19 05:53:17 PM PDT 24
Peak memory 224136 kb
Host smart-69923801-3d8c-44d3-97e7-b77f1f174f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043908082 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.2043908082
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.3968387325
Short name T314
Test name
Test status
Simulation time 44610059 ps
CPU time 1.39 seconds
Started Aug 19 05:53:00 PM PDT 24
Finished Aug 19 05:53:01 PM PDT 24
Peak memory 218624 kb
Host smart-e35488fa-e4bc-4089-83b1-5598333023a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968387325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3968387325
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.2150201907
Short name T54
Test name
Test status
Simulation time 31755979 ps
CPU time 0.99 seconds
Started Aug 19 05:52:57 PM PDT 24
Finished Aug 19 05:52:58 PM PDT 24
Peak memory 224264 kb
Host smart-e4201669-39f3-4c70-abe9-54d2fb575270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150201907 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.2150201907
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.1518235556
Short name T408
Test name
Test status
Simulation time 25007643 ps
CPU time 0.92 seconds
Started Aug 19 05:53:14 PM PDT 24
Finished Aug 19 05:53:15 PM PDT 24
Peak memory 215428 kb
Host smart-f7d9d6e7-308e-4cd9-84fc-52e9ae5d6a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518235556 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.1518235556
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.3178589263
Short name T700
Test name
Test status
Simulation time 275766527 ps
CPU time 5.37 seconds
Started Aug 19 05:52:59 PM PDT 24
Finished Aug 19 05:53:05 PM PDT 24
Peak memory 215324 kb
Host smart-9bf570be-39d6-4fb3-81a8-6e26485eddc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178589263 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.3178589263
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2222148033
Short name T696
Test name
Test status
Simulation time 13673373910 ps
CPU time 83.35 seconds
Started Aug 19 05:53:01 PM PDT 24
Finished Aug 19 05:54:25 PM PDT 24
Peak memory 221924 kb
Host smart-8b9b20f9-e701-497e-a29d-7a28fd2129f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222148033 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.2222148033
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.2893427594
Short name T766
Test name
Test status
Simulation time 88377363 ps
CPU time 1.18 seconds
Started Aug 19 05:54:24 PM PDT 24
Finished Aug 19 05:54:25 PM PDT 24
Peak memory 220420 kb
Host smart-a39f819e-5e9e-4933-8326-863b92460956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893427594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.2893427594
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.670754024
Short name T580
Test name
Test status
Simulation time 79375951 ps
CPU time 1.91 seconds
Started Aug 19 05:54:50 PM PDT 24
Finished Aug 19 05:54:52 PM PDT 24
Peak memory 218888 kb
Host smart-8bc8b1a3-3b47-4d41-a68f-a14577d386f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670754024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.670754024
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.2368178815
Short name T781
Test name
Test status
Simulation time 49868732 ps
CPU time 0.95 seconds
Started Aug 19 05:54:29 PM PDT 24
Finished Aug 19 05:54:30 PM PDT 24
Peak memory 217572 kb
Host smart-df35f7ad-00e4-49c4-8ddc-177a455f8039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368178815 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2368178815
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3036950928
Short name T347
Test name
Test status
Simulation time 61975370 ps
CPU time 1 seconds
Started Aug 19 05:54:27 PM PDT 24
Finished Aug 19 05:54:28 PM PDT 24
Peak memory 217492 kb
Host smart-c98c2122-7548-42bd-9717-ca4e4c043083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036950928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3036950928
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.50442509
Short name T594
Test name
Test status
Simulation time 71631893 ps
CPU time 1.47 seconds
Started Aug 19 05:54:33 PM PDT 24
Finished Aug 19 05:54:34 PM PDT 24
Peak memory 218808 kb
Host smart-c9efec62-9206-49de-bde1-b58c2db54dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50442509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.50442509
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.607338920
Short name T668
Test name
Test status
Simulation time 80157604 ps
CPU time 1.34 seconds
Started Aug 19 05:54:38 PM PDT 24
Finished Aug 19 05:54:39 PM PDT 24
Peak memory 218520 kb
Host smart-8235a708-9d0b-408f-bc06-2151f5b7bfaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607338920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.607338920
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.660325084
Short name T805
Test name
Test status
Simulation time 48597531 ps
CPU time 1.25 seconds
Started Aug 19 05:54:20 PM PDT 24
Finished Aug 19 05:54:22 PM PDT 24
Peak memory 218944 kb
Host smart-8b6df300-3f98-4bd3-aec3-86de895905cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660325084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.660325084
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.1709296220
Short name T715
Test name
Test status
Simulation time 75506336 ps
CPU time 1.31 seconds
Started Aug 19 05:54:29 PM PDT 24
Finished Aug 19 05:54:31 PM PDT 24
Peak memory 219628 kb
Host smart-77eddc0b-c0a7-4d64-bf36-124aa0f90a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709296220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.1709296220
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2516908300
Short name T755
Test name
Test status
Simulation time 36607637 ps
CPU time 1.4 seconds
Started Aug 19 05:54:43 PM PDT 24
Finished Aug 19 05:54:45 PM PDT 24
Peak memory 217268 kb
Host smart-bbf6e7d7-1f4a-4b4d-87c0-b072956b4df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516908300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2516908300
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.126773223
Short name T896
Test name
Test status
Simulation time 34427537 ps
CPU time 1.34 seconds
Started Aug 19 05:54:36 PM PDT 24
Finished Aug 19 05:54:37 PM PDT 24
Peak memory 218588 kb
Host smart-8774bf85-ea54-4717-8c72-e14dbd764233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126773223 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.126773223
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.1077866344
Short name T750
Test name
Test status
Simulation time 91275439 ps
CPU time 1.28 seconds
Started Aug 19 05:53:00 PM PDT 24
Finished Aug 19 05:53:01 PM PDT 24
Peak memory 220664 kb
Host smart-322efba0-5608-4ef7-ae05-3fb641774034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077866344 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.1077866344
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.1715430353
Short name T770
Test name
Test status
Simulation time 244397664 ps
CPU time 1.03 seconds
Started Aug 19 05:53:00 PM PDT 24
Finished Aug 19 05:53:01 PM PDT 24
Peak memory 215180 kb
Host smart-c2e57efb-f335-4aff-8f66-0965090a6053
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715430353 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1715430353
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.2146081229
Short name T627
Test name
Test status
Simulation time 19635748 ps
CPU time 0.82 seconds
Started Aug 19 05:53:02 PM PDT 24
Finished Aug 19 05:53:03 PM PDT 24
Peak memory 215428 kb
Host smart-40baa619-17a9-4d0d-8de8-0f516971060a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146081229 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2146081229
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.1983468478
Short name T127
Test name
Test status
Simulation time 368922990 ps
CPU time 1.16 seconds
Started Aug 19 05:52:55 PM PDT 24
Finished Aug 19 05:52:56 PM PDT 24
Peak memory 217020 kb
Host smart-dc0ad535-419f-4b24-b85c-347e11ddafb2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983468478 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.1983468478
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.504169699
Short name T710
Test name
Test status
Simulation time 57006947 ps
CPU time 1.12 seconds
Started Aug 19 05:53:00 PM PDT 24
Finished Aug 19 05:53:01 PM PDT 24
Peak memory 220508 kb
Host smart-648283fb-6121-4d58-b8c6-ab13a3c28027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504169699 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.504169699
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_intr.4071130651
Short name T35
Test name
Test status
Simulation time 20990044 ps
CPU time 1.1 seconds
Started Aug 19 05:53:07 PM PDT 24
Finished Aug 19 05:53:08 PM PDT 24
Peak memory 215852 kb
Host smart-3d3e87f4-4d46-40a4-a956-fa8a1ae89a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071130651 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.4071130651
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.2512175723
Short name T93
Test name
Test status
Simulation time 15764007 ps
CPU time 1 seconds
Started Aug 19 05:53:12 PM PDT 24
Finished Aug 19 05:53:14 PM PDT 24
Peak memory 215504 kb
Host smart-da47c665-9db3-45e9-9f6e-1a1ff59f3ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512175723 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2512175723
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.3668766233
Short name T73
Test name
Test status
Simulation time 45025818 ps
CPU time 1.06 seconds
Started Aug 19 05:53:03 PM PDT 24
Finished Aug 19 05:53:04 PM PDT 24
Peak memory 207012 kb
Host smart-2d678b59-66de-4a02-8b38-f5a574c51074
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668766233 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.3668766233
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.1849811487
Short name T225
Test name
Test status
Simulation time 9807986105 ps
CPU time 133.09 seconds
Started Aug 19 05:52:58 PM PDT 24
Finished Aug 19 05:55:11 PM PDT 24
Peak memory 218032 kb
Host smart-49ca7724-5501-41fd-8fe6-2fa51911fbf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849811487 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.1849811487
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.4220721180
Short name T14
Test name
Test status
Simulation time 33799388 ps
CPU time 1.41 seconds
Started Aug 19 05:54:45 PM PDT 24
Finished Aug 19 05:54:47 PM PDT 24
Peak memory 219728 kb
Host smart-29a69d6a-58de-486f-b9c0-d0d7632a0abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220721180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.4220721180
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.536553380
Short name T858
Test name
Test status
Simulation time 50768461 ps
CPU time 1.32 seconds
Started Aug 19 05:54:22 PM PDT 24
Finished Aug 19 05:54:24 PM PDT 24
Peak memory 218504 kb
Host smart-02735952-2a02-4cef-996f-2207589a3b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536553380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.536553380
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.613813169
Short name T920
Test name
Test status
Simulation time 24707727 ps
CPU time 1.19 seconds
Started Aug 19 05:55:01 PM PDT 24
Finished Aug 19 05:55:03 PM PDT 24
Peak memory 220328 kb
Host smart-a507be38-6258-45d1-9d1e-a14fa755af8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613813169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.613813169
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.2369513297
Short name T300
Test name
Test status
Simulation time 41525968 ps
CPU time 1.13 seconds
Started Aug 19 05:54:26 PM PDT 24
Finished Aug 19 05:54:27 PM PDT 24
Peak memory 219832 kb
Host smart-b85ccee8-58fc-435d-ae1a-b36986d8a49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369513297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2369513297
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.3875398456
Short name T493
Test name
Test status
Simulation time 59929361 ps
CPU time 1.09 seconds
Started Aug 19 05:54:23 PM PDT 24
Finished Aug 19 05:54:25 PM PDT 24
Peak memory 220316 kb
Host smart-a6e84960-0b1e-4e36-96ed-b59da97b9119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875398456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.3875398456
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.2601514306
Short name T504
Test name
Test status
Simulation time 76102932 ps
CPU time 2.9 seconds
Started Aug 19 05:54:49 PM PDT 24
Finished Aug 19 05:54:54 PM PDT 24
Peak memory 220596 kb
Host smart-ba85a505-b251-4769-a7e7-76c1b6c83117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601514306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2601514306
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3455312877
Short name T902
Test name
Test status
Simulation time 178842889 ps
CPU time 1.66 seconds
Started Aug 19 05:54:50 PM PDT 24
Finished Aug 19 05:54:51 PM PDT 24
Peak memory 218932 kb
Host smart-abb1a54b-0367-44c3-a313-0296f229c2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455312877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3455312877
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.3940569334
Short name T765
Test name
Test status
Simulation time 46369964 ps
CPU time 1.52 seconds
Started Aug 19 05:54:40 PM PDT 24
Finished Aug 19 05:54:42 PM PDT 24
Peak memory 219704 kb
Host smart-106819c5-ea39-4834-8094-7caad2200f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940569334 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3940569334
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.2639921848
Short name T894
Test name
Test status
Simulation time 234174265 ps
CPU time 1.07 seconds
Started Aug 19 05:54:53 PM PDT 24
Finished Aug 19 05:54:54 PM PDT 24
Peak memory 217552 kb
Host smart-007393d2-caf8-45ac-b318-0d518ce5c6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639921848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2639921848
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.885495509
Short name T899
Test name
Test status
Simulation time 59283755 ps
CPU time 1.96 seconds
Started Aug 19 05:54:51 PM PDT 24
Finished Aug 19 05:54:53 PM PDT 24
Peak memory 218620 kb
Host smart-2bfd7cf2-0534-4e9b-bdaf-eba65d3adf99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885495509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.885495509
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.1306548197
Short name T876
Test name
Test status
Simulation time 287241768 ps
CPU time 1.34 seconds
Started Aug 19 05:53:05 PM PDT 24
Finished Aug 19 05:53:07 PM PDT 24
Peak memory 219516 kb
Host smart-532fbe79-f2d4-4259-9c2a-a1165b329dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306548197 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1306548197
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.1037049136
Short name T606
Test name
Test status
Simulation time 23667949 ps
CPU time 0.86 seconds
Started Aug 19 05:52:47 PM PDT 24
Finished Aug 19 05:52:48 PM PDT 24
Peak memory 206904 kb
Host smart-6b08fda1-0e93-4604-9588-db42dc4bc239
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037049136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1037049136
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.4124344195
Short name T658
Test name
Test status
Simulation time 23186054 ps
CPU time 0.82 seconds
Started Aug 19 05:53:04 PM PDT 24
Finished Aug 19 05:53:05 PM PDT 24
Peak memory 207028 kb
Host smart-6a954c77-6f56-4da7-907d-456b3b9f8445
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124344195 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.4124344195
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.2963609654
Short name T928
Test name
Test status
Simulation time 57035914 ps
CPU time 1.11 seconds
Started Aug 19 05:52:55 PM PDT 24
Finished Aug 19 05:53:01 PM PDT 24
Peak memory 217000 kb
Host smart-20f6308b-53a4-445f-897e-895c82d07ca0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963609654 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.2963609654
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.3762108132
Short name T413
Test name
Test status
Simulation time 19612753 ps
CPU time 1.04 seconds
Started Aug 19 05:53:08 PM PDT 24
Finished Aug 19 05:53:09 PM PDT 24
Peak memory 218304 kb
Host smart-11d17a16-4166-4a48-99e1-b6f59593d6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762108132 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.3762108132
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.3250769438
Short name T735
Test name
Test status
Simulation time 27994796 ps
CPU time 1.36 seconds
Started Aug 19 05:52:58 PM PDT 24
Finished Aug 19 05:52:59 PM PDT 24
Peak memory 215364 kb
Host smart-4e8f50da-f1ef-4865-a065-826e048cf8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250769438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3250769438
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.371304046
Short name T971
Test name
Test status
Simulation time 22658176 ps
CPU time 1.17 seconds
Started Aug 19 05:53:01 PM PDT 24
Finished Aug 19 05:53:02 PM PDT 24
Peak memory 215808 kb
Host smart-63ee22a4-2662-47d1-90fa-fe2c1e49ded4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371304046 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.371304046
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.3738700600
Short name T597
Test name
Test status
Simulation time 70667314 ps
CPU time 0.88 seconds
Started Aug 19 05:53:22 PM PDT 24
Finished Aug 19 05:53:22 PM PDT 24
Peak memory 215412 kb
Host smart-d2bd8298-1f29-4fd1-8d36-a4b57d321b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738700600 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3738700600
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3766403624
Short name T895
Test name
Test status
Simulation time 126144300 ps
CPU time 2.76 seconds
Started Aug 19 05:53:04 PM PDT 24
Finished Aug 19 05:53:07 PM PDT 24
Peak memory 217384 kb
Host smart-7ba4ea47-c386-4edd-8e05-ea12fa801cbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766403624 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3766403624
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2534897723
Short name T911
Test name
Test status
Simulation time 1314513352 ps
CPU time 34.86 seconds
Started Aug 19 05:53:00 PM PDT 24
Finished Aug 19 05:53:35 PM PDT 24
Peak memory 218072 kb
Host smart-338afbac-d340-455f-a9ff-67c18220b0e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534897723 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2534897723
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.4292332838
Short name T365
Test name
Test status
Simulation time 52544389 ps
CPU time 1.21 seconds
Started Aug 19 05:54:26 PM PDT 24
Finished Aug 19 05:54:27 PM PDT 24
Peak memory 217300 kb
Host smart-9520b42c-d152-4c64-9e92-395f79d475cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292332838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.4292332838
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.3356105212
Short name T40
Test name
Test status
Simulation time 92598529 ps
CPU time 1.53 seconds
Started Aug 19 05:54:42 PM PDT 24
Finished Aug 19 05:54:43 PM PDT 24
Peak memory 219088 kb
Host smart-5cfa282d-a6e3-4ed2-a667-47a368e96fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356105212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3356105212
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.4044707183
Short name T882
Test name
Test status
Simulation time 88458680 ps
CPU time 0.95 seconds
Started Aug 19 05:54:32 PM PDT 24
Finished Aug 19 05:54:33 PM PDT 24
Peak memory 217644 kb
Host smart-422e1725-79b2-4ddd-9f0a-3bf97fac9c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044707183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.4044707183
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.355686339
Short name T836
Test name
Test status
Simulation time 34925139 ps
CPU time 1.5 seconds
Started Aug 19 05:54:40 PM PDT 24
Finished Aug 19 05:54:42 PM PDT 24
Peak memory 218640 kb
Host smart-fcb664e4-a9d2-451b-8281-8c04068df38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355686339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.355686339
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.3056272495
Short name T716
Test name
Test status
Simulation time 41424275 ps
CPU time 1.51 seconds
Started Aug 19 05:54:31 PM PDT 24
Finished Aug 19 05:54:32 PM PDT 24
Peak memory 218468 kb
Host smart-e23f7c9c-5dd7-493d-80ba-32d754092e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056272495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.3056272495
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.1256864650
Short name T390
Test name
Test status
Simulation time 67476579 ps
CPU time 1.38 seconds
Started Aug 19 05:54:52 PM PDT 24
Finished Aug 19 05:54:54 PM PDT 24
Peak memory 220288 kb
Host smart-7f4163da-26f8-4023-a0e8-56f9735596fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256864650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.1256864650
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.261192074
Short name T368
Test name
Test status
Simulation time 74991496 ps
CPU time 1.48 seconds
Started Aug 19 05:54:30 PM PDT 24
Finished Aug 19 05:54:31 PM PDT 24
Peak memory 218984 kb
Host smart-cb786ceb-8f18-419a-8e7b-8f276b44f032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261192074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.261192074
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.1669731293
Short name T810
Test name
Test status
Simulation time 31252667 ps
CPU time 1.28 seconds
Started Aug 19 05:54:26 PM PDT 24
Finished Aug 19 05:54:27 PM PDT 24
Peak memory 217796 kb
Host smart-387aa460-2f8d-4d67-a8d3-6db3eed49e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669731293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1669731293
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.3904658822
Short name T555
Test name
Test status
Simulation time 41873922 ps
CPU time 1.94 seconds
Started Aug 19 05:54:34 PM PDT 24
Finished Aug 19 05:54:36 PM PDT 24
Peak memory 220532 kb
Host smart-cd839581-5376-4fa4-9223-9e8a8121652a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904658822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3904658822
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.4027151789
Short name T336
Test name
Test status
Simulation time 32813869 ps
CPU time 1.24 seconds
Started Aug 19 05:54:46 PM PDT 24
Finished Aug 19 05:54:48 PM PDT 24
Peak memory 217192 kb
Host smart-d2a561bb-0b54-4953-aa4d-f1d9787000f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027151789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.4027151789
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert_test.4095798280
Short name T795
Test name
Test status
Simulation time 21643465 ps
CPU time 1.04 seconds
Started Aug 19 05:53:15 PM PDT 24
Finished Aug 19 05:53:16 PM PDT 24
Peak memory 206828 kb
Host smart-af541af2-9ccd-471c-82d9-af1743af57ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095798280 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.4095798280
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.2278386955
Short name T333
Test name
Test status
Simulation time 39266536 ps
CPU time 0.88 seconds
Started Aug 19 05:53:14 PM PDT 24
Finished Aug 19 05:53:15 PM PDT 24
Peak memory 215208 kb
Host smart-a54a5dfa-3cae-4842-8c32-558d60613ee7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278386955 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2278386955
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.328396126
Short name T154
Test name
Test status
Simulation time 61020100 ps
CPU time 1.31 seconds
Started Aug 19 05:53:10 PM PDT 24
Finished Aug 19 05:53:11 PM PDT 24
Peak memory 216948 kb
Host smart-f4ff2064-3ecc-4973-b1a6-341b440fae33
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328396126 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di
sable_auto_req_mode.328396126
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.1987453830
Short name T572
Test name
Test status
Simulation time 36787396 ps
CPU time 0.81 seconds
Started Aug 19 05:53:22 PM PDT 24
Finished Aug 19 05:53:22 PM PDT 24
Peak memory 218244 kb
Host smart-06d2901d-6f0a-433c-934f-88bb2eedc5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987453830 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.1987453830
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.1644885513
Short name T362
Test name
Test status
Simulation time 52457134 ps
CPU time 1.3 seconds
Started Aug 19 05:53:17 PM PDT 24
Finished Aug 19 05:53:19 PM PDT 24
Peak memory 220072 kb
Host smart-8d26044c-47df-421c-997c-fc577cb91712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644885513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1644885513
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.3692512270
Short name T519
Test name
Test status
Simulation time 28281493 ps
CPU time 0.96 seconds
Started Aug 19 05:53:11 PM PDT 24
Finished Aug 19 05:53:12 PM PDT 24
Peak memory 215504 kb
Host smart-81ddec0f-3939-434f-9674-ee7f06feea03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692512270 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3692512270
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.2027644085
Short name T949
Test name
Test status
Simulation time 27148391 ps
CPU time 0.96 seconds
Started Aug 19 05:52:55 PM PDT 24
Finished Aug 19 05:52:56 PM PDT 24
Peak memory 215244 kb
Host smart-5b1a15a6-135a-4ec8-8e1f-15065b3e9035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027644085 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.2027644085
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.3857015151
Short name T773
Test name
Test status
Simulation time 1118427586 ps
CPU time 5.02 seconds
Started Aug 19 05:53:23 PM PDT 24
Finished Aug 19 05:53:28 PM PDT 24
Peak memory 217280 kb
Host smart-1ce762a7-c7c9-45d5-b1f8-475031219e3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857015151 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3857015151
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1546147476
Short name T617
Test name
Test status
Simulation time 1897484300 ps
CPU time 46.01 seconds
Started Aug 19 05:53:23 PM PDT 24
Finished Aug 19 05:54:09 PM PDT 24
Peak memory 218676 kb
Host smart-81c9e746-e3da-4ad8-9c3f-3fe73e9b8ef6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546147476 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1546147476
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.1288126671
Short name T581
Test name
Test status
Simulation time 50948268 ps
CPU time 1.22 seconds
Started Aug 19 05:54:42 PM PDT 24
Finished Aug 19 05:54:44 PM PDT 24
Peak memory 217408 kb
Host smart-349445b9-34fa-4c0f-912c-a75e885a973e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288126671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.1288126671
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.2006294418
Short name T363
Test name
Test status
Simulation time 101623621 ps
CPU time 1.55 seconds
Started Aug 19 05:54:37 PM PDT 24
Finished Aug 19 05:54:39 PM PDT 24
Peak memory 219064 kb
Host smart-735c8acb-dd58-48af-b031-ac3b482a8ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006294418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.2006294418
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.77687679
Short name T574
Test name
Test status
Simulation time 53518018 ps
CPU time 1.99 seconds
Started Aug 19 05:54:30 PM PDT 24
Finished Aug 19 05:54:33 PM PDT 24
Peak memory 218672 kb
Host smart-002b1778-882d-4f2d-9ff6-f1f15934165f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77687679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.77687679
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.4025402235
Short name T679
Test name
Test status
Simulation time 102854687 ps
CPU time 1.31 seconds
Started Aug 19 05:54:39 PM PDT 24
Finished Aug 19 05:54:41 PM PDT 24
Peak memory 220320 kb
Host smart-55a4f625-f482-4f62-beba-216e958a3434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025402235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.4025402235
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.1663249546
Short name T438
Test name
Test status
Simulation time 188485172 ps
CPU time 1.05 seconds
Started Aug 19 05:54:27 PM PDT 24
Finished Aug 19 05:54:28 PM PDT 24
Peak memory 217280 kb
Host smart-9a510103-5633-4a53-a4e7-a700ae8a73a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663249546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.1663249546
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.617785333
Short name T445
Test name
Test status
Simulation time 519337632 ps
CPU time 3.99 seconds
Started Aug 19 05:54:30 PM PDT 24
Finished Aug 19 05:54:34 PM PDT 24
Peak memory 217744 kb
Host smart-0230360f-c80c-41f1-b468-8135a45ceb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617785333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.617785333
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.2766971549
Short name T405
Test name
Test status
Simulation time 243794101 ps
CPU time 3.54 seconds
Started Aug 19 05:54:51 PM PDT 24
Finished Aug 19 05:54:54 PM PDT 24
Peak memory 220592 kb
Host smart-1edefbb6-b05e-4785-b3ce-fd2246673d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766971549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.2766971549
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.4172709648
Short name T687
Test name
Test status
Simulation time 40110802 ps
CPU time 1.23 seconds
Started Aug 19 05:54:43 PM PDT 24
Finished Aug 19 05:54:44 PM PDT 24
Peak memory 218776 kb
Host smart-e1f8ea7d-8343-4eb3-b5aa-fc3facbde287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172709648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.4172709648
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.1845280653
Short name T797
Test name
Test status
Simulation time 38366954 ps
CPU time 1.05 seconds
Started Aug 19 05:54:43 PM PDT 24
Finished Aug 19 05:54:44 PM PDT 24
Peak memory 217412 kb
Host smart-20e2cde4-bd83-421a-8ab0-a82ff53042ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845280653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1845280653
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.2368463261
Short name T890
Test name
Test status
Simulation time 112646608 ps
CPU time 1.58 seconds
Started Aug 19 05:54:59 PM PDT 24
Finished Aug 19 05:55:00 PM PDT 24
Peak memory 217848 kb
Host smart-bc751870-e2c2-4bdf-a5fb-190a5e27e008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368463261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.2368463261
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.2500267603
Short name T966
Test name
Test status
Simulation time 322812421 ps
CPU time 1.09 seconds
Started Aug 19 05:53:18 PM PDT 24
Finished Aug 19 05:53:19 PM PDT 24
Peak memory 218712 kb
Host smart-1da079c1-730f-4983-8057-b255492fa5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500267603 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.2500267603
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.2644284950
Short name T544
Test name
Test status
Simulation time 11808152 ps
CPU time 0.83 seconds
Started Aug 19 05:53:30 PM PDT 24
Finished Aug 19 05:53:31 PM PDT 24
Peak memory 206896 kb
Host smart-ae2f492c-ae32-4bf3-b070-7ea2eb78f1b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644284950 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2644284950
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.1445861450
Short name T180
Test name
Test status
Simulation time 15273358 ps
CPU time 0.95 seconds
Started Aug 19 05:53:30 PM PDT 24
Finished Aug 19 05:53:31 PM PDT 24
Peak memory 215628 kb
Host smart-4adaa187-5ac0-4a5c-8ef0-238a504a09bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445861450 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.1445861450
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.2048860016
Short name T377
Test name
Test status
Simulation time 102219790 ps
CPU time 1.11 seconds
Started Aug 19 05:53:17 PM PDT 24
Finished Aug 19 05:53:19 PM PDT 24
Peak memory 217028 kb
Host smart-d7016253-9018-4476-b5c6-ede580f2c905
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048860016 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.2048860016
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.974587404
Short name T425
Test name
Test status
Simulation time 40424960 ps
CPU time 0.87 seconds
Started Aug 19 05:53:25 PM PDT 24
Finished Aug 19 05:53:26 PM PDT 24
Peak memory 218340 kb
Host smart-f43c0f90-9fec-465a-9c1a-aac186ac66b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974587404 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.974587404
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.2871538817
Short name T803
Test name
Test status
Simulation time 102340905 ps
CPU time 1.34 seconds
Started Aug 19 05:53:04 PM PDT 24
Finished Aug 19 05:53:05 PM PDT 24
Peak memory 217420 kb
Host smart-ef145740-8e35-4e2d-adce-02e600b1c324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871538817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.2871538817
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.3678963818
Short name T639
Test name
Test status
Simulation time 58087380 ps
CPU time 0.86 seconds
Started Aug 19 05:53:08 PM PDT 24
Finished Aug 19 05:53:09 PM PDT 24
Peak memory 215528 kb
Host smart-26a488c8-cb40-4a21-a382-002795210bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678963818 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.3678963818
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.385721484
Short name T753
Test name
Test status
Simulation time 21739334 ps
CPU time 0.88 seconds
Started Aug 19 05:53:23 PM PDT 24
Finished Aug 19 05:53:24 PM PDT 24
Peak memory 215400 kb
Host smart-f4ea4b81-96b3-4ea1-8302-e9825c91b64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385721484 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.385721484
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.891483589
Short name T708
Test name
Test status
Simulation time 208509630 ps
CPU time 2.81 seconds
Started Aug 19 05:53:23 PM PDT 24
Finished Aug 19 05:53:25 PM PDT 24
Peak memory 215380 kb
Host smart-40697a40-f9f1-4415-a331-bc0edcac324d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891483589 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.891483589
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/250.edn_genbits.37440036
Short name T914
Test name
Test status
Simulation time 85455917 ps
CPU time 1.18 seconds
Started Aug 19 05:54:24 PM PDT 24
Finished Aug 19 05:54:25 PM PDT 24
Peak memory 220396 kb
Host smart-8da70b58-3d5d-46f8-81b4-9d09b71b06de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37440036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.37440036
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.278707398
Short name T951
Test name
Test status
Simulation time 93262449 ps
CPU time 1.48 seconds
Started Aug 19 05:54:31 PM PDT 24
Finished Aug 19 05:54:32 PM PDT 24
Peak memory 219180 kb
Host smart-0d794045-3bfc-48f4-8e6c-ae33263d28ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278707398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.278707398
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.574949503
Short name T731
Test name
Test status
Simulation time 64845491 ps
CPU time 1.23 seconds
Started Aug 19 05:54:42 PM PDT 24
Finished Aug 19 05:54:43 PM PDT 24
Peak memory 217352 kb
Host smart-b9013fed-3fbf-4ca5-b641-0440b87ca860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574949503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.574949503
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.2947360262
Short name T525
Test name
Test status
Simulation time 354658213 ps
CPU time 1.06 seconds
Started Aug 19 05:54:37 PM PDT 24
Finished Aug 19 05:54:38 PM PDT 24
Peak memory 217272 kb
Host smart-f2f8aebe-8da6-495e-b54a-1c48f1c76edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947360262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.2947360262
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.1851862789
Short name T439
Test name
Test status
Simulation time 31397150 ps
CPU time 1.31 seconds
Started Aug 19 05:54:45 PM PDT 24
Finished Aug 19 05:54:47 PM PDT 24
Peak memory 217360 kb
Host smart-32644a5d-4377-4b3d-86f7-fed9fedfa3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851862789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.1851862789
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.1922984215
Short name T341
Test name
Test status
Simulation time 43868241 ps
CPU time 1.6 seconds
Started Aug 19 05:54:41 PM PDT 24
Finished Aug 19 05:54:43 PM PDT 24
Peak memory 218720 kb
Host smart-693217d4-dbcf-4e2f-b13e-00d0044a58b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922984215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.1922984215
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.2739538784
Short name T607
Test name
Test status
Simulation time 71083489 ps
CPU time 1.21 seconds
Started Aug 19 05:54:42 PM PDT 24
Finished Aug 19 05:54:43 PM PDT 24
Peak memory 217688 kb
Host smart-18cc9648-15ba-4873-8f7d-12d3cd34200d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739538784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.2739538784
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.251427764
Short name T712
Test name
Test status
Simulation time 206059215 ps
CPU time 2.7 seconds
Started Aug 19 05:54:44 PM PDT 24
Finished Aug 19 05:54:46 PM PDT 24
Peak memory 220464 kb
Host smart-98eb98c3-292a-453f-bcad-8f79120b7aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251427764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.251427764
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.916420422
Short name T299
Test name
Test status
Simulation time 72994773 ps
CPU time 2.5 seconds
Started Aug 19 05:54:40 PM PDT 24
Finished Aug 19 05:54:43 PM PDT 24
Peak memory 218692 kb
Host smart-8c49e949-b23a-4946-86c8-400fd8da0074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916420422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.916420422
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.841971782
Short name T227
Test name
Test status
Simulation time 40272441 ps
CPU time 1.48 seconds
Started Aug 19 05:54:47 PM PDT 24
Finished Aug 19 05:54:48 PM PDT 24
Peak memory 218564 kb
Host smart-b84a520a-4e50-4187-a379-c4e93bec43f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841971782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.841971782
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.1015498534
Short name T221
Test name
Test status
Simulation time 26542245 ps
CPU time 1.22 seconds
Started Aug 19 05:53:28 PM PDT 24
Finished Aug 19 05:53:29 PM PDT 24
Peak memory 219928 kb
Host smart-5311ed7b-7942-4958-a83e-75d31c9a6034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015498534 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.1015498534
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.638803482
Short name T860
Test name
Test status
Simulation time 44083276 ps
CPU time 1.06 seconds
Started Aug 19 05:53:10 PM PDT 24
Finished Aug 19 05:53:11 PM PDT 24
Peak memory 206720 kb
Host smart-a1969482-40c5-4f5f-9ddb-b73005fc47a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638803482 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.638803482
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.1731105699
Short name T431
Test name
Test status
Simulation time 10917539 ps
CPU time 0.87 seconds
Started Aug 19 05:53:20 PM PDT 24
Finished Aug 19 05:53:21 PM PDT 24
Peak memory 215520 kb
Host smart-779721bc-cbb8-46d6-8a51-274bd8a5785e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731105699 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1731105699
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.2935532661
Short name T834
Test name
Test status
Simulation time 168001908 ps
CPU time 1.17 seconds
Started Aug 19 05:53:32 PM PDT 24
Finished Aug 19 05:53:33 PM PDT 24
Peak memory 216916 kb
Host smart-397e35e3-40bd-4189-9a6d-8b00df8e9b8b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935532661 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.2935532661
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.3364483703
Short name T887
Test name
Test status
Simulation time 20979570 ps
CPU time 1.04 seconds
Started Aug 19 05:53:31 PM PDT 24
Finished Aug 19 05:53:33 PM PDT 24
Peak memory 224144 kb
Host smart-9809200c-7973-4e9d-aff3-96753ad6c781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364483703 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.3364483703
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.1335309299
Short name T312
Test name
Test status
Simulation time 60244660 ps
CPU time 2.08 seconds
Started Aug 19 05:53:12 PM PDT 24
Finished Aug 19 05:53:14 PM PDT 24
Peak memory 220440 kb
Host smart-8aa8bf01-8824-46d6-8f46-7cea5342a64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335309299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1335309299
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.4243364794
Short name T94
Test name
Test status
Simulation time 21229429 ps
CPU time 1.03 seconds
Started Aug 19 05:53:03 PM PDT 24
Finished Aug 19 05:53:04 PM PDT 24
Peak memory 215884 kb
Host smart-de36d9d0-a8a8-4d8f-a50c-566936e90746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243364794 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.4243364794
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.247234137
Short name T611
Test name
Test status
Simulation time 162328100 ps
CPU time 0.88 seconds
Started Aug 19 05:53:07 PM PDT 24
Finished Aug 19 05:53:08 PM PDT 24
Peak memory 215400 kb
Host smart-ea653457-a648-4d8d-9697-6d1c78696e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247234137 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.247234137
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.930641755
Short name T398
Test name
Test status
Simulation time 1660683916 ps
CPU time 5.59 seconds
Started Aug 19 05:53:15 PM PDT 24
Finished Aug 19 05:53:20 PM PDT 24
Peak memory 215424 kb
Host smart-344f9265-86bc-41a7-9263-7e4a504fb645
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930641755 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.930641755
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/260.edn_genbits.1750184312
Short name T502
Test name
Test status
Simulation time 62789255 ps
CPU time 0.99 seconds
Started Aug 19 05:54:40 PM PDT 24
Finished Aug 19 05:54:41 PM PDT 24
Peak memory 217276 kb
Host smart-685e5d4c-6c77-4301-9ebc-7e5cc6a75e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750184312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.1750184312
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.3224623651
Short name T353
Test name
Test status
Simulation time 66362639 ps
CPU time 1.16 seconds
Started Aug 19 05:54:33 PM PDT 24
Finished Aug 19 05:54:34 PM PDT 24
Peak memory 218612 kb
Host smart-5320892e-628a-44ea-aa3b-027ceaf6fb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224623651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3224623651
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.13413183
Short name T488
Test name
Test status
Simulation time 80630479 ps
CPU time 1.09 seconds
Started Aug 19 05:54:29 PM PDT 24
Finished Aug 19 05:54:31 PM PDT 24
Peak memory 217564 kb
Host smart-119c2942-01a5-4112-ba98-876ea808846f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13413183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.13413183
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.2114584834
Short name T482
Test name
Test status
Simulation time 144108596 ps
CPU time 1.13 seconds
Started Aug 19 05:54:28 PM PDT 24
Finished Aug 19 05:54:29 PM PDT 24
Peak memory 217452 kb
Host smart-eea8efba-16f1-4ee8-94bb-19cf122d0633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114584834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.2114584834
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.953017163
Short name T727
Test name
Test status
Simulation time 35713545 ps
CPU time 1.31 seconds
Started Aug 19 05:54:29 PM PDT 24
Finished Aug 19 05:54:30 PM PDT 24
Peak memory 219980 kb
Host smart-c1811e50-96f4-4b0c-9f67-7d1f3e08afa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953017163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.953017163
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.937601472
Short name T486
Test name
Test status
Simulation time 51295932 ps
CPU time 1.34 seconds
Started Aug 19 05:54:28 PM PDT 24
Finished Aug 19 05:54:30 PM PDT 24
Peak memory 215412 kb
Host smart-3188453b-8ba1-404a-8080-deb2e8c1cd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937601472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.937601472
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.3313257881
Short name T15
Test name
Test status
Simulation time 48829075 ps
CPU time 1.72 seconds
Started Aug 19 05:54:32 PM PDT 24
Finished Aug 19 05:54:34 PM PDT 24
Peak memory 220448 kb
Host smart-34ce1984-52b1-40fd-b685-6ebc2411ea6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313257881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.3313257881
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1723938679
Short name T308
Test name
Test status
Simulation time 76158436 ps
CPU time 1.14 seconds
Started Aug 19 05:54:30 PM PDT 24
Finished Aug 19 05:54:31 PM PDT 24
Peak memory 218768 kb
Host smart-4fad538b-2709-4223-bd55-e38c052f939f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723938679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1723938679
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.3841161848
Short name T578
Test name
Test status
Simulation time 66000915 ps
CPU time 1.09 seconds
Started Aug 19 05:54:33 PM PDT 24
Finished Aug 19 05:54:39 PM PDT 24
Peak memory 217396 kb
Host smart-20deee44-6e02-4a56-bfb8-4911b49ff1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841161848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3841161848
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.4071228545
Short name T635
Test name
Test status
Simulation time 29281535 ps
CPU time 1.23 seconds
Started Aug 19 05:53:18 PM PDT 24
Finished Aug 19 05:53:19 PM PDT 24
Peak memory 218636 kb
Host smart-131342a8-70c0-4085-a4d0-950344a18ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071228545 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.4071228545
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.2759968777
Short name T437
Test name
Test status
Simulation time 16183727 ps
CPU time 0.9 seconds
Started Aug 19 05:52:59 PM PDT 24
Finished Aug 19 05:53:00 PM PDT 24
Peak memory 206776 kb
Host smart-3710a8d1-04e3-4a64-995d-c78dbb6d3d89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759968777 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2759968777
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.3166189781
Short name T613
Test name
Test status
Simulation time 10826811 ps
CPU time 0.89 seconds
Started Aug 19 05:53:31 PM PDT 24
Finished Aug 19 05:53:32 PM PDT 24
Peak memory 215444 kb
Host smart-6fbb152f-3918-44e3-b82f-ffe16b3e3b2f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166189781 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3166189781
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.2852434790
Short name T674
Test name
Test status
Simulation time 26865251 ps
CPU time 1.13 seconds
Started Aug 19 05:53:23 PM PDT 24
Finished Aug 19 05:53:25 PM PDT 24
Peak memory 218208 kb
Host smart-8f57de67-796f-4d13-a822-bb64aed86eea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852434790 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.2852434790
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.3677614281
Short name T807
Test name
Test status
Simulation time 29563464 ps
CPU time 1.35 seconds
Started Aug 19 05:53:20 PM PDT 24
Finished Aug 19 05:53:21 PM PDT 24
Peak memory 225752 kb
Host smart-4728e831-f941-4ff6-b0af-28040388dbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677614281 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.3677614281
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.3446703752
Short name T573
Test name
Test status
Simulation time 60277264 ps
CPU time 0.99 seconds
Started Aug 19 05:53:18 PM PDT 24
Finished Aug 19 05:53:19 PM PDT 24
Peak memory 217384 kb
Host smart-23ea380d-0dff-4f6b-a906-f75c7f2b60cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446703752 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.3446703752
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.1659491851
Short name T615
Test name
Test status
Simulation time 21649132 ps
CPU time 1.12 seconds
Started Aug 19 05:53:25 PM PDT 24
Finished Aug 19 05:53:26 PM PDT 24
Peak memory 224396 kb
Host smart-72a25124-62e1-465f-b685-0f024405e13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659491851 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1659491851
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.3451639135
Short name T883
Test name
Test status
Simulation time 158969817 ps
CPU time 0.94 seconds
Started Aug 19 05:53:22 PM PDT 24
Finished Aug 19 05:53:24 PM PDT 24
Peak memory 215412 kb
Host smart-fb250b09-b7e9-4dcf-94b3-e990f9a7f4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451639135 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.3451639135
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1154838106
Short name T868
Test name
Test status
Simulation time 1075370614 ps
CPU time 5.35 seconds
Started Aug 19 05:53:06 PM PDT 24
Finished Aug 19 05:53:12 PM PDT 24
Peak memory 215420 kb
Host smart-e8c92430-bcff-4cdf-a824-bdfb5bc0b1a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154838106 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1154838106
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.3992381875
Short name T958
Test name
Test status
Simulation time 2694183151 ps
CPU time 65.53 seconds
Started Aug 19 05:53:36 PM PDT 24
Finished Aug 19 05:54:42 PM PDT 24
Peak memory 218856 kb
Host smart-dcf93709-d2a9-44f7-a751-bdf16d5fbff7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992381875 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.3992381875
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/271.edn_genbits.3923018351
Short name T485
Test name
Test status
Simulation time 35432696 ps
CPU time 1.42 seconds
Started Aug 19 05:54:51 PM PDT 24
Finished Aug 19 05:54:52 PM PDT 24
Peak memory 217556 kb
Host smart-24365996-5e88-41ef-9e45-d2f5c7f2e6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923018351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.3923018351
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.3151643838
Short name T821
Test name
Test status
Simulation time 52907763 ps
CPU time 1.27 seconds
Started Aug 19 05:54:37 PM PDT 24
Finished Aug 19 05:54:39 PM PDT 24
Peak memory 217356 kb
Host smart-42e17525-243a-4f11-94a7-36af9d53a33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151643838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.3151643838
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.2422691256
Short name T43
Test name
Test status
Simulation time 37458844 ps
CPU time 1.43 seconds
Started Aug 19 05:54:33 PM PDT 24
Finished Aug 19 05:54:34 PM PDT 24
Peak memory 218476 kb
Host smart-a4c169f7-3768-42f7-b13a-a8ebe373b206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422691256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2422691256
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3443410974
Short name T925
Test name
Test status
Simulation time 59302993 ps
CPU time 1.52 seconds
Started Aug 19 05:54:56 PM PDT 24
Finished Aug 19 05:54:57 PM PDT 24
Peak memory 215424 kb
Host smart-d1e1eb74-2ef7-4a1c-a9af-20bd089bbd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443410974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3443410974
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.3864425138
Short name T862
Test name
Test status
Simulation time 49474717 ps
CPU time 1.51 seconds
Started Aug 19 05:54:46 PM PDT 24
Finished Aug 19 05:54:48 PM PDT 24
Peak memory 218756 kb
Host smart-17485b1b-1c9b-4170-a22c-48e47d18dbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864425138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3864425138
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3149922356
Short name T559
Test name
Test status
Simulation time 75397730 ps
CPU time 1.21 seconds
Started Aug 19 05:54:53 PM PDT 24
Finished Aug 19 05:54:54 PM PDT 24
Peak memory 217320 kb
Host smart-931e4543-3112-408e-8d28-cb4db8629757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149922356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3149922356
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.1045748797
Short name T694
Test name
Test status
Simulation time 58538305 ps
CPU time 1.08 seconds
Started Aug 19 05:54:50 PM PDT 24
Finished Aug 19 05:54:52 PM PDT 24
Peak memory 220248 kb
Host smart-a5e3f4c1-eb77-49ae-a54f-5ed12af905b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045748797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.1045748797
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.811412931
Short name T418
Test name
Test status
Simulation time 65296492 ps
CPU time 1.25 seconds
Started Aug 19 05:54:58 PM PDT 24
Finished Aug 19 05:55:00 PM PDT 24
Peak memory 219896 kb
Host smart-d9e5a9e1-b72a-446f-b07f-1753ba94e481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811412931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.811412931
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.1636413251
Short name T964
Test name
Test status
Simulation time 44599252 ps
CPU time 1.56 seconds
Started Aug 19 05:54:50 PM PDT 24
Finished Aug 19 05:54:52 PM PDT 24
Peak memory 220192 kb
Host smart-302bb4a8-6d8e-4ceb-9ca7-a4a015f22eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636413251 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.1636413251
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.4203081031
Short name T817
Test name
Test status
Simulation time 93004912 ps
CPU time 1.12 seconds
Started Aug 19 05:53:23 PM PDT 24
Finished Aug 19 05:53:25 PM PDT 24
Peak memory 219696 kb
Host smart-204b5c85-35da-4f6c-ba3a-999fb9751ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203081031 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.4203081031
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.1280278780
Short name T75
Test name
Test status
Simulation time 150862095 ps
CPU time 0.98 seconds
Started Aug 19 05:53:12 PM PDT 24
Finished Aug 19 05:53:18 PM PDT 24
Peak memory 215088 kb
Host smart-a4642476-6f75-4715-8d00-0fd907ff79d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280278780 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.1280278780
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.3363047063
Short name T190
Test name
Test status
Simulation time 42786213 ps
CPU time 0.85 seconds
Started Aug 19 05:53:19 PM PDT 24
Finished Aug 19 05:53:20 PM PDT 24
Peak memory 215460 kb
Host smart-81bd8e5c-d280-4e4c-bbba-4051f559ea9d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363047063 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.3363047063
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.4257840680
Short name T941
Test name
Test status
Simulation time 107418237 ps
CPU time 1.18 seconds
Started Aug 19 05:53:27 PM PDT 24
Finished Aug 19 05:53:28 PM PDT 24
Peak memory 218508 kb
Host smart-b4945441-20b3-490f-9584-bc25d9c96724
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257840680 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.4257840680
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.2858448804
Short name T870
Test name
Test status
Simulation time 21337700 ps
CPU time 1.06 seconds
Started Aug 19 05:53:20 PM PDT 24
Finished Aug 19 05:53:22 PM PDT 24
Peak memory 224136 kb
Host smart-6104aad9-ff5e-4c39-a04f-342f2872e42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858448804 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2858448804
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.2745872833
Short name T643
Test name
Test status
Simulation time 28504478 ps
CPU time 1.3 seconds
Started Aug 19 05:53:08 PM PDT 24
Finished Aug 19 05:53:10 PM PDT 24
Peak memory 217728 kb
Host smart-65159213-4415-4d9b-a59e-6b71b37a959d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745872833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2745872833
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.4079119464
Short name T120
Test name
Test status
Simulation time 26311423 ps
CPU time 1.04 seconds
Started Aug 19 05:53:19 PM PDT 24
Finished Aug 19 05:53:21 PM PDT 24
Peak memory 215960 kb
Host smart-fe09d775-78e4-45df-af0f-ec5c6e220b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079119464 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.4079119464
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.914273470
Short name T351
Test name
Test status
Simulation time 48863727 ps
CPU time 0.94 seconds
Started Aug 19 05:53:07 PM PDT 24
Finished Aug 19 05:53:08 PM PDT 24
Peak memory 215420 kb
Host smart-79dcdb58-9928-4f02-aa14-633eb3760989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914273470 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.914273470
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.405747280
Short name T441
Test name
Test status
Simulation time 77502775 ps
CPU time 1.4 seconds
Started Aug 19 05:53:15 PM PDT 24
Finished Aug 19 05:53:17 PM PDT 24
Peak memory 207248 kb
Host smart-3023a2a5-4bd2-41dd-99c4-75edb55e24d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405747280 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.405747280
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2729948137
Short name T37
Test name
Test status
Simulation time 3640852548 ps
CPU time 91.08 seconds
Started Aug 19 05:53:12 PM PDT 24
Finished Aug 19 05:54:43 PM PDT 24
Peak memory 218328 kb
Host smart-2d67bc34-7611-44cf-bf43-d5f12c4b1ac8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729948137 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.2729948137
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.1142751014
Short name T924
Test name
Test status
Simulation time 24950192 ps
CPU time 1.27 seconds
Started Aug 19 05:54:31 PM PDT 24
Finished Aug 19 05:54:32 PM PDT 24
Peak memory 220260 kb
Host smart-bd4b830e-068a-4851-941e-f7cdc24eba49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142751014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1142751014
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.1096787790
Short name T536
Test name
Test status
Simulation time 41802001 ps
CPU time 1.6 seconds
Started Aug 19 05:54:54 PM PDT 24
Finished Aug 19 05:54:55 PM PDT 24
Peak memory 218576 kb
Host smart-2bbd1ac5-3d13-41cf-be49-9eb3b064f0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096787790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1096787790
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.4258895457
Short name T955
Test name
Test status
Simulation time 50423146 ps
CPU time 1.34 seconds
Started Aug 19 05:54:29 PM PDT 24
Finished Aug 19 05:54:31 PM PDT 24
Peak memory 218576 kb
Host smart-eab07b69-2c57-4e51-9958-1de7d36a9b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258895457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.4258895457
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.326286321
Short name T435
Test name
Test status
Simulation time 76618623 ps
CPU time 1.08 seconds
Started Aug 19 05:55:00 PM PDT 24
Finished Aug 19 05:55:02 PM PDT 24
Peak memory 219528 kb
Host smart-a37e44bb-58e3-450c-8e6c-930bd5011abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326286321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.326286321
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.2939229096
Short name T12
Test name
Test status
Simulation time 44186991 ps
CPU time 1.46 seconds
Started Aug 19 05:54:41 PM PDT 24
Finished Aug 19 05:54:45 PM PDT 24
Peak memory 220396 kb
Host smart-ec174995-f78a-4800-aff3-24c1e0881fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939229096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2939229096
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3955800961
Short name T379
Test name
Test status
Simulation time 60785753 ps
CPU time 1.27 seconds
Started Aug 19 05:54:52 PM PDT 24
Finished Aug 19 05:54:54 PM PDT 24
Peak memory 217400 kb
Host smart-fc8d8485-0a49-4f44-a4a2-645a922350b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955800961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3955800961
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.1236318448
Short name T711
Test name
Test status
Simulation time 52569410 ps
CPU time 1.24 seconds
Started Aug 19 05:54:42 PM PDT 24
Finished Aug 19 05:54:43 PM PDT 24
Peak memory 217516 kb
Host smart-f22dc102-b354-47bc-a31b-a7907fd4b387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236318448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.1236318448
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.3386678991
Short name T590
Test name
Test status
Simulation time 100177188 ps
CPU time 2.43 seconds
Started Aug 19 05:54:59 PM PDT 24
Finished Aug 19 05:55:01 PM PDT 24
Peak memory 220520 kb
Host smart-337c4d27-a3d7-4e66-b5f3-de7497e985a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386678991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.3386678991
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.55306660
Short name T833
Test name
Test status
Simulation time 38288432 ps
CPU time 1.35 seconds
Started Aug 19 05:54:47 PM PDT 24
Finished Aug 19 05:54:49 PM PDT 24
Peak memory 217268 kb
Host smart-c2a805f9-8c69-416a-89f7-73f948c03b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55306660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.55306660
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.304580803
Short name T283
Test name
Test status
Simulation time 121592936 ps
CPU time 1.36 seconds
Started Aug 19 05:55:02 PM PDT 24
Finished Aug 19 05:55:04 PM PDT 24
Peak memory 219160 kb
Host smart-6fcf7786-2346-45df-bc75-444e4714c58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304580803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.304580803
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.3360839091
Short name T970
Test name
Test status
Simulation time 26844639 ps
CPU time 1.33 seconds
Started Aug 19 05:53:12 PM PDT 24
Finished Aug 19 05:53:14 PM PDT 24
Peak memory 218716 kb
Host smart-7467ae8e-bebb-4d0a-b5b4-3fc42b1fdbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360839091 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.3360839091
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.2445667976
Short name T338
Test name
Test status
Simulation time 90871160 ps
CPU time 0.83 seconds
Started Aug 19 05:53:34 PM PDT 24
Finished Aug 19 05:53:35 PM PDT 24
Peak memory 206676 kb
Host smart-cad4e022-5b61-438d-8e53-1dd9a8471930
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445667976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.2445667976
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.2164955906
Short name T923
Test name
Test status
Simulation time 36482524 ps
CPU time 0.81 seconds
Started Aug 19 05:53:27 PM PDT 24
Finished Aug 19 05:53:28 PM PDT 24
Peak memory 215460 kb
Host smart-e1c88344-de9e-4673-afd7-ffa6b28903cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164955906 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2164955906
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_err.2327988913
Short name T118
Test name
Test status
Simulation time 32463131 ps
CPU time 1.17 seconds
Started Aug 19 05:53:29 PM PDT 24
Finished Aug 19 05:53:30 PM PDT 24
Peak memory 219860 kb
Host smart-d4673aad-bfde-4573-ac41-d01888e32537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327988913 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2327988913
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.3982264626
Short name T560
Test name
Test status
Simulation time 56319036 ps
CPU time 1.99 seconds
Started Aug 19 05:53:39 PM PDT 24
Finished Aug 19 05:53:41 PM PDT 24
Peak memory 220520 kb
Host smart-029509e5-7998-416e-9663-3e4ef9a30192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982264626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3982264626
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.4271552195
Short name T933
Test name
Test status
Simulation time 42079492 ps
CPU time 0.88 seconds
Started Aug 19 05:53:19 PM PDT 24
Finished Aug 19 05:53:20 PM PDT 24
Peak memory 215936 kb
Host smart-f6f9b8f3-68f0-4855-b70f-8e8b913c617b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271552195 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.4271552195
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.3591411286
Short name T531
Test name
Test status
Simulation time 65402141 ps
CPU time 0.87 seconds
Started Aug 19 05:53:23 PM PDT 24
Finished Aug 19 05:53:24 PM PDT 24
Peak memory 215392 kb
Host smart-953ff78e-b4b0-49bb-a208-8830e3f46e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591411286 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.3591411286
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.3584890243
Short name T777
Test name
Test status
Simulation time 112533345 ps
CPU time 2.56 seconds
Started Aug 19 05:53:16 PM PDT 24
Finished Aug 19 05:53:19 PM PDT 24
Peak memory 215328 kb
Host smart-5e4da784-a95a-4ba0-aa38-b6ac27443bc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584890243 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3584890243
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.1549173431
Short name T680
Test name
Test status
Simulation time 1968002873 ps
CPU time 49.66 seconds
Started Aug 19 05:53:21 PM PDT 24
Finished Aug 19 05:54:11 PM PDT 24
Peak memory 219428 kb
Host smart-34fb8afa-076e-4247-a1b8-2ced973f212b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549173431 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.1549173431
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.3668044340
Short name T857
Test name
Test status
Simulation time 34243445 ps
CPU time 1.31 seconds
Started Aug 19 05:54:50 PM PDT 24
Finished Aug 19 05:54:51 PM PDT 24
Peak memory 217284 kb
Host smart-ad3f04d2-a343-4fe6-ad0f-ba6176d1f5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668044340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.3668044340
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.2197445204
Short name T91
Test name
Test status
Simulation time 105733726 ps
CPU time 1.87 seconds
Started Aug 19 05:54:48 PM PDT 24
Finished Aug 19 05:54:50 PM PDT 24
Peak memory 219088 kb
Host smart-98824ff2-3d47-4a23-a53d-79d0d287f6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197445204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2197445204
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.3492317600
Short name T463
Test name
Test status
Simulation time 48089614 ps
CPU time 1.65 seconds
Started Aug 19 05:54:57 PM PDT 24
Finished Aug 19 05:54:59 PM PDT 24
Peak memory 217700 kb
Host smart-55872a1c-f3c0-47a3-9dc7-1dc301bb9b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492317600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3492317600
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2836038375
Short name T245
Test name
Test status
Simulation time 246591213 ps
CPU time 2.9 seconds
Started Aug 19 05:54:42 PM PDT 24
Finished Aug 19 05:54:45 PM PDT 24
Peak memory 219328 kb
Host smart-ce6bde7e-35d5-43af-a127-897f9d9afe67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836038375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2836038375
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.1732235731
Short name T476
Test name
Test status
Simulation time 50319896 ps
CPU time 1.21 seconds
Started Aug 19 05:55:04 PM PDT 24
Finished Aug 19 05:55:05 PM PDT 24
Peak memory 217492 kb
Host smart-bccec6aa-b231-4e5e-9c5d-6699d9358bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732235731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1732235731
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.15605895
Short name T462
Test name
Test status
Simulation time 88083510 ps
CPU time 1.15 seconds
Started Aug 19 05:54:33 PM PDT 24
Finished Aug 19 05:54:34 PM PDT 24
Peak memory 217504 kb
Host smart-d2891c54-8598-4437-b4d2-7a5fbf3d5996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15605895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.15605895
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.297658458
Short name T683
Test name
Test status
Simulation time 84159367 ps
CPU time 1.28 seconds
Started Aug 19 05:54:36 PM PDT 24
Finished Aug 19 05:54:37 PM PDT 24
Peak memory 219064 kb
Host smart-e2865e82-3b07-4387-927a-b6c759295320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297658458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.297658458
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.1377702360
Short name T717
Test name
Test status
Simulation time 60684364 ps
CPU time 1.33 seconds
Started Aug 19 05:55:06 PM PDT 24
Finished Aug 19 05:55:08 PM PDT 24
Peak memory 219756 kb
Host smart-0bd6f8fb-b837-4ce9-b40d-0674b6e4e8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377702360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1377702360
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.2655655866
Short name T401
Test name
Test status
Simulation time 67475380 ps
CPU time 1.2 seconds
Started Aug 19 05:54:56 PM PDT 24
Finished Aug 19 05:54:57 PM PDT 24
Peak memory 217228 kb
Host smart-52b8af1d-507e-4a99-a579-ca3abe399cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655655866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.2655655866
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.2507792376
Short name T678
Test name
Test status
Simulation time 468503355 ps
CPU time 5.12 seconds
Started Aug 19 05:54:42 PM PDT 24
Finished Aug 19 05:54:49 PM PDT 24
Peak memory 220544 kb
Host smart-45f13841-0c1f-4415-91f9-59423159c4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507792376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.2507792376
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.1577850649
Short name T811
Test name
Test status
Simulation time 23470110 ps
CPU time 1.14 seconds
Started Aug 19 05:52:39 PM PDT 24
Finished Aug 19 05:52:40 PM PDT 24
Peak memory 220004 kb
Host smart-b320501a-d5c9-4b75-9920-3f6c0f54a47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577850649 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1577850649
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.1629116926
Short name T74
Test name
Test status
Simulation time 22709773 ps
CPU time 1.13 seconds
Started Aug 19 05:52:31 PM PDT 24
Finished Aug 19 05:52:32 PM PDT 24
Peak memory 215108 kb
Host smart-d50ae6cd-fb27-45c0-ae38-e4b21ea02593
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629116926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.1629116926
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.1236735995
Short name T250
Test name
Test status
Simulation time 77619929 ps
CPU time 1.01 seconds
Started Aug 19 05:52:48 PM PDT 24
Finished Aug 19 05:52:49 PM PDT 24
Peak memory 216900 kb
Host smart-88752a09-0258-4d7f-a4ab-e71be9e86c05
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236735995 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.1236735995
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.2577668148
Short name T188
Test name
Test status
Simulation time 22409939 ps
CPU time 0.93 seconds
Started Aug 19 05:52:37 PM PDT 24
Finished Aug 19 05:52:38 PM PDT 24
Peak memory 218420 kb
Host smart-8eabe91c-8892-486b-aeb7-2f329f8f0072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577668148 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2577668148
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.1541564510
Short name T82
Test name
Test status
Simulation time 52972064 ps
CPU time 1.21 seconds
Started Aug 19 05:52:31 PM PDT 24
Finished Aug 19 05:52:33 PM PDT 24
Peak memory 218576 kb
Host smart-378d52fd-f5bb-4ba2-9e2f-3ecad6576c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541564510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1541564510
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.3156913866
Short name T897
Test name
Test status
Simulation time 19274217 ps
CPU time 1.07 seconds
Started Aug 19 05:52:36 PM PDT 24
Finished Aug 19 05:52:38 PM PDT 24
Peak memory 216020 kb
Host smart-0f4c4851-e5d8-4a45-a9a3-2c3698ef649b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156913866 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.3156913866
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_sec_cm.3633959864
Short name T20
Test name
Test status
Simulation time 447419041 ps
CPU time 7.8 seconds
Started Aug 19 05:52:33 PM PDT 24
Finished Aug 19 05:52:41 PM PDT 24
Peak memory 237168 kb
Host smart-05332309-a6cf-450c-a1ed-7c087af3e99c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633959864 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3633959864
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.3586347929
Short name T973
Test name
Test status
Simulation time 18139444 ps
CPU time 0.98 seconds
Started Aug 19 05:52:42 PM PDT 24
Finished Aug 19 05:52:44 PM PDT 24
Peak memory 215308 kb
Host smart-a99073d5-ab7d-4695-bba2-0bae4fa60b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586347929 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3586347929
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.2596015084
Short name T204
Test name
Test status
Simulation time 344941576 ps
CPU time 2.25 seconds
Started Aug 19 05:52:56 PM PDT 24
Finished Aug 19 05:52:58 PM PDT 24
Peak memory 217200 kb
Host smart-247a6783-15bd-4f50-8053-079dc2837eb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596015084 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2596015084
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3626749496
Short name T720
Test name
Test status
Simulation time 2096305493 ps
CPU time 33.09 seconds
Started Aug 19 05:52:31 PM PDT 24
Finished Aug 19 05:53:04 PM PDT 24
Peak memory 218260 kb
Host smart-7dc658b9-2749-4a90-b83a-12a74992d29a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626749496 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3626749496
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1915468072
Short name T937
Test name
Test status
Simulation time 113579616 ps
CPU time 1.04 seconds
Started Aug 19 05:53:25 PM PDT 24
Finished Aug 19 05:53:26 PM PDT 24
Peak memory 218872 kb
Host smart-1e4f10e5-eb60-4b20-af0f-f8a11d886934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915468072 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1915468072
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.1546137092
Short name T420
Test name
Test status
Simulation time 15290402 ps
CPU time 0.93 seconds
Started Aug 19 05:53:16 PM PDT 24
Finished Aug 19 05:53:17 PM PDT 24
Peak memory 206820 kb
Host smart-e14a6f91-e7b8-42a3-8b92-04bb70f69a26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546137092 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1546137092
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.232167001
Short name T206
Test name
Test status
Simulation time 15962549 ps
CPU time 0.86 seconds
Started Aug 19 05:53:26 PM PDT 24
Finished Aug 19 05:53:27 PM PDT 24
Peak memory 215460 kb
Host smart-91c59eea-a123-4a98-959b-3d05280ccf59
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232167001 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.232167001
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.481353614
Short name T871
Test name
Test status
Simulation time 93231178 ps
CPU time 1.1 seconds
Started Aug 19 05:53:15 PM PDT 24
Finished Aug 19 05:53:16 PM PDT 24
Peak memory 217132 kb
Host smart-318cbb09-f124-4ccb-93cd-6bba7dc70f5d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481353614 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_di
sable_auto_req_mode.481353614
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.1531394925
Short name T55
Test name
Test status
Simulation time 21339410 ps
CPU time 1.05 seconds
Started Aug 19 05:53:14 PM PDT 24
Finished Aug 19 05:53:15 PM PDT 24
Peak memory 224152 kb
Host smart-95392f3f-1bdc-4c19-8700-934a52bf546c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531394925 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.1531394925
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.2209451674
Short name T801
Test name
Test status
Simulation time 53127900 ps
CPU time 1.35 seconds
Started Aug 19 05:53:08 PM PDT 24
Finished Aug 19 05:53:10 PM PDT 24
Peak memory 219736 kb
Host smart-cc625e69-34a4-44c3-926a-c2df841db05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209451674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2209451674
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.94546514
Short name T743
Test name
Test status
Simulation time 20701637 ps
CPU time 1.16 seconds
Started Aug 19 05:53:30 PM PDT 24
Finished Aug 19 05:53:31 PM PDT 24
Peak memory 215960 kb
Host smart-88528b1c-b8de-485f-af8c-e88d66e19e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94546514 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.94546514
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.1730488815
Short name T60
Test name
Test status
Simulation time 17320400 ps
CPU time 0.98 seconds
Started Aug 19 05:53:14 PM PDT 24
Finished Aug 19 05:53:15 PM PDT 24
Peak memory 215348 kb
Host smart-35fd7f6e-94a7-4b57-9c7c-d84259a14d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730488815 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.1730488815
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.2488364950
Short name T241
Test name
Test status
Simulation time 670993863 ps
CPU time 4.34 seconds
Started Aug 19 05:53:10 PM PDT 24
Finished Aug 19 05:53:15 PM PDT 24
Peak memory 215412 kb
Host smart-94f787d6-b390-4d82-9acf-02cd7a5be6cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488364950 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.2488364950
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.1867563684
Short name T222
Test name
Test status
Simulation time 778274812 ps
CPU time 19.23 seconds
Started Aug 19 05:53:13 PM PDT 24
Finished Aug 19 05:53:32 PM PDT 24
Peak memory 218704 kb
Host smart-c80a2f9a-5550-4207-b0ac-bdf88a304797
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867563684 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.1867563684
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.2355277949
Short name T815
Test name
Test status
Simulation time 28485491 ps
CPU time 1.3 seconds
Started Aug 19 05:53:09 PM PDT 24
Finished Aug 19 05:53:11 PM PDT 24
Peak memory 220064 kb
Host smart-32680bc4-3b6f-4383-a8f1-6c864db08455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355277949 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.2355277949
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.2501988814
Short name T366
Test name
Test status
Simulation time 17499331 ps
CPU time 0.94 seconds
Started Aug 19 05:53:19 PM PDT 24
Finished Aug 19 05:53:20 PM PDT 24
Peak memory 206928 kb
Host smart-b66ab96a-e139-44d4-82dd-5e0f80a61650
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501988814 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2501988814
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.3217460577
Short name T87
Test name
Test status
Simulation time 21770549 ps
CPU time 0.89 seconds
Started Aug 19 05:53:24 PM PDT 24
Finished Aug 19 05:53:25 PM PDT 24
Peak memory 215468 kb
Host smart-426eceac-f1c9-495e-a557-cb27993406c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217460577 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3217460577
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2565452132
Short name T703
Test name
Test status
Simulation time 55610770 ps
CPU time 1.24 seconds
Started Aug 19 05:53:40 PM PDT 24
Finished Aug 19 05:53:42 PM PDT 24
Peak memory 217024 kb
Host smart-326899d5-6248-44d9-b583-ed3821d1c387
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565452132 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2565452132
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.3779600736
Short name T754
Test name
Test status
Simulation time 25959258 ps
CPU time 0.94 seconds
Started Aug 19 05:53:17 PM PDT 24
Finished Aug 19 05:53:18 PM PDT 24
Peak memory 219808 kb
Host smart-c9726891-f220-40fa-8271-e8de4927d53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779600736 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3779600736
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.3748129316
Short name T429
Test name
Test status
Simulation time 183693333 ps
CPU time 1.11 seconds
Started Aug 19 05:53:19 PM PDT 24
Finished Aug 19 05:53:20 PM PDT 24
Peak memory 217576 kb
Host smart-2a6ced91-d515-447a-bce6-ff063232fc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748129316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.3748129316
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.1822592199
Short name T200
Test name
Test status
Simulation time 21089668 ps
CPU time 1.08 seconds
Started Aug 19 05:53:33 PM PDT 24
Finished Aug 19 05:53:34 PM PDT 24
Peak memory 215540 kb
Host smart-8236d13e-7d76-4c78-b4e8-5d817d6715e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822592199 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.1822592199
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.3418203814
Short name T331
Test name
Test status
Simulation time 71232270 ps
CPU time 0.93 seconds
Started Aug 19 05:53:25 PM PDT 24
Finished Aug 19 05:53:26 PM PDT 24
Peak memory 215376 kb
Host smart-0a415725-5570-4ccc-b73a-893759b2bd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418203814 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.3418203814
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.1195079852
Short name T978
Test name
Test status
Simulation time 31908041 ps
CPU time 1.27 seconds
Started Aug 19 05:53:31 PM PDT 24
Finished Aug 19 05:53:33 PM PDT 24
Peak memory 215388 kb
Host smart-dbb3b1c5-9fed-4608-8616-ecb1fc8c17f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195079852 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1195079852
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_alert.1290211462
Short name T571
Test name
Test status
Simulation time 27772556 ps
CPU time 1.22 seconds
Started Aug 19 05:53:28 PM PDT 24
Finished Aug 19 05:53:29 PM PDT 24
Peak memory 218604 kb
Host smart-2e7155e3-f932-4ce6-bb6f-8595be3b8e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290211462 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1290211462
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.1528240703
Short name T800
Test name
Test status
Simulation time 47200413 ps
CPU time 0.93 seconds
Started Aug 19 05:53:13 PM PDT 24
Finished Aug 19 05:53:14 PM PDT 24
Peak memory 215308 kb
Host smart-6a30aed0-0af1-40a1-96a5-15aa81988343
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528240703 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.1528240703
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.1427342172
Short name T181
Test name
Test status
Simulation time 47779208 ps
CPU time 0.85 seconds
Started Aug 19 05:53:16 PM PDT 24
Finished Aug 19 05:53:17 PM PDT 24
Peak memory 215368 kb
Host smart-572b8412-a77f-4d3e-bb2e-ee6311b5428e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427342172 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.1427342172
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.3219329218
Short name T689
Test name
Test status
Simulation time 142869281 ps
CPU time 1.21 seconds
Started Aug 19 05:53:21 PM PDT 24
Finished Aug 19 05:53:22 PM PDT 24
Peak memory 217060 kb
Host smart-4f550c11-05cc-4140-ab32-b1e7ea824890
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219329218 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.3219329218
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.1318311672
Short name T167
Test name
Test status
Simulation time 24334480 ps
CPU time 0.94 seconds
Started Aug 19 05:53:16 PM PDT 24
Finished Aug 19 05:53:17 PM PDT 24
Peak memory 218676 kb
Host smart-18f1ff37-217d-4b30-b8a9-4cff2a82d7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318311672 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.1318311672
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.1511260870
Short name T430
Test name
Test status
Simulation time 25153334 ps
CPU time 1.24 seconds
Started Aug 19 05:53:21 PM PDT 24
Finished Aug 19 05:53:33 PM PDT 24
Peak memory 217476 kb
Host smart-73fe92e2-c6d4-42f2-aeee-be06a49346b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511260870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.1511260870
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.1070010689
Short name T921
Test name
Test status
Simulation time 23217672 ps
CPU time 1.19 seconds
Started Aug 19 05:53:16 PM PDT 24
Finished Aug 19 05:53:17 PM PDT 24
Peak memory 224288 kb
Host smart-989fbf58-0d85-4c27-b705-4e1aa073f6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070010689 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1070010689
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.450758124
Short name T334
Test name
Test status
Simulation time 18529676 ps
CPU time 1.05 seconds
Started Aug 19 05:53:13 PM PDT 24
Finished Aug 19 05:53:15 PM PDT 24
Peak memory 215384 kb
Host smart-edeb4bd4-7025-4724-9a66-92cd29352ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450758124 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.450758124
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.1929336532
Short name T961
Test name
Test status
Simulation time 179649122 ps
CPU time 1.61 seconds
Started Aug 19 05:53:15 PM PDT 24
Finished Aug 19 05:53:17 PM PDT 24
Peak memory 215428 kb
Host smart-0640ecf4-c23d-4d9e-a53b-c10ef67968dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929336532 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1929336532
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.3703669487
Short name T509
Test name
Test status
Simulation time 8015231233 ps
CPU time 35.15 seconds
Started Aug 19 05:54:08 PM PDT 24
Finished Aug 19 05:54:43 PM PDT 24
Peak memory 219560 kb
Host smart-15d71afc-1f4e-4089-bbad-2b9c86f258ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703669487 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.3703669487
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.1612893001
Short name T142
Test name
Test status
Simulation time 81053706 ps
CPU time 1.18 seconds
Started Aug 19 05:53:31 PM PDT 24
Finished Aug 19 05:53:33 PM PDT 24
Peak memory 219880 kb
Host smart-382d8290-2f2a-4fd2-b704-26a863245b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612893001 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.1612893001
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.1365807935
Short name T335
Test name
Test status
Simulation time 22520667 ps
CPU time 0.88 seconds
Started Aug 19 05:53:42 PM PDT 24
Finished Aug 19 05:53:43 PM PDT 24
Peak memory 206832 kb
Host smart-e3c96e6d-9247-4832-bffd-6f887a57a1bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365807935 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1365807935
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.2891654773
Short name T784
Test name
Test status
Simulation time 67453190 ps
CPU time 0.85 seconds
Started Aug 19 05:53:23 PM PDT 24
Finished Aug 19 05:53:24 PM PDT 24
Peak memory 215448 kb
Host smart-18184344-dac4-4b20-b6dc-3f2af94a4c4f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891654773 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.2891654773
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2406859938
Short name T21
Test name
Test status
Simulation time 32183510 ps
CPU time 1.24 seconds
Started Aug 19 05:53:22 PM PDT 24
Finished Aug 19 05:53:23 PM PDT 24
Peak memory 217044 kb
Host smart-cb907261-9194-4d8c-8dbe-47f3e96b8723
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406859938 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2406859938
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.506549071
Short name T194
Test name
Test status
Simulation time 18761194 ps
CPU time 1.02 seconds
Started Aug 19 05:53:33 PM PDT 24
Finished Aug 19 05:53:34 PM PDT 24
Peak memory 218420 kb
Host smart-d442ca74-1869-4406-a6db-0afc85bdf26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506549071 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.506549071
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.2401751527
Short name T337
Test name
Test status
Simulation time 54530805 ps
CPU time 1.25 seconds
Started Aug 19 05:53:24 PM PDT 24
Finished Aug 19 05:53:26 PM PDT 24
Peak memory 218752 kb
Host smart-b56222e9-639c-489b-9595-e1c1034daf2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401751527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2401751527
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.2187700019
Short name T790
Test name
Test status
Simulation time 25564501 ps
CPU time 0.93 seconds
Started Aug 19 05:53:23 PM PDT 24
Finished Aug 19 05:53:24 PM PDT 24
Peak memory 215944 kb
Host smart-045d834b-d5b9-45a5-8b8d-35dfb79fd1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187700019 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.2187700019
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.2075434189
Short name T793
Test name
Test status
Simulation time 31082557 ps
CPU time 0.98 seconds
Started Aug 19 05:53:26 PM PDT 24
Finished Aug 19 05:53:27 PM PDT 24
Peak memory 215380 kb
Host smart-9569e0a8-f87d-4739-bebc-263c2a322bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075434189 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.2075434189
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3128717561
Short name T444
Test name
Test status
Simulation time 173009014 ps
CPU time 3.99 seconds
Started Aug 19 05:53:25 PM PDT 24
Finished Aug 19 05:53:29 PM PDT 24
Peak memory 215476 kb
Host smart-eec7c40d-e498-4d34-8817-476a780b14f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128717561 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3128717561
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_alert.1281390475
Short name T934
Test name
Test status
Simulation time 73761296 ps
CPU time 1.18 seconds
Started Aug 19 05:53:29 PM PDT 24
Finished Aug 19 05:53:30 PM PDT 24
Peak memory 220540 kb
Host smart-70c4f9f3-b633-49dd-b2a7-33cf50aff734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281390475 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1281390475
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.1926541273
Short name T905
Test name
Test status
Simulation time 14090559 ps
CPU time 0.86 seconds
Started Aug 19 05:53:26 PM PDT 24
Finished Aug 19 05:53:27 PM PDT 24
Peak memory 206840 kb
Host smart-014adc5c-a283-49af-beee-8fa07fa05a77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926541273 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1926541273
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.644015731
Short name T605
Test name
Test status
Simulation time 18297508 ps
CPU time 0.85 seconds
Started Aug 19 05:53:23 PM PDT 24
Finished Aug 19 05:53:24 PM PDT 24
Peak memory 207068 kb
Host smart-54a1ebc8-374f-41a2-b3c8-e02759027496
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644015731 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.644015731
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_genbits.3724665222
Short name T468
Test name
Test status
Simulation time 25485313 ps
CPU time 1.16 seconds
Started Aug 19 05:53:29 PM PDT 24
Finished Aug 19 05:53:36 PM PDT 24
Peak memory 217388 kb
Host smart-dad9647b-19c4-4720-ac69-48c772740bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724665222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3724665222
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.3727757436
Short name T910
Test name
Test status
Simulation time 35434772 ps
CPU time 0.9 seconds
Started Aug 19 05:53:17 PM PDT 24
Finished Aug 19 05:53:18 PM PDT 24
Peak memory 215644 kb
Host smart-d1eb74a6-32ed-475d-a7c5-7fd16258fbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727757436 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.3727757436
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.3964213382
Short name T370
Test name
Test status
Simulation time 29646881 ps
CPU time 0.96 seconds
Started Aug 19 05:53:27 PM PDT 24
Finished Aug 19 05:53:28 PM PDT 24
Peak memory 215392 kb
Host smart-9e9eed32-663c-4dda-9bcf-733222bff94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964213382 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.3964213382
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.1643552701
Short name T51
Test name
Test status
Simulation time 572932456 ps
CPU time 5.75 seconds
Started Aug 19 05:53:36 PM PDT 24
Finished Aug 19 05:53:42 PM PDT 24
Peak memory 218652 kb
Host smart-79d3ff83-173b-4abc-8c23-43906617a4f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643552701 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1643552701
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_alert.1158952411
Short name T702
Test name
Test status
Simulation time 47039905 ps
CPU time 1.14 seconds
Started Aug 19 05:53:44 PM PDT 24
Finished Aug 19 05:53:45 PM PDT 24
Peak memory 219680 kb
Host smart-a5cf84f8-7246-4a2c-b54e-3b488ccdd00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158952411 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1158952411
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.3827916758
Short name T247
Test name
Test status
Simulation time 55022554 ps
CPU time 0.97 seconds
Started Aug 19 05:53:12 PM PDT 24
Finished Aug 19 05:53:14 PM PDT 24
Peak memory 215008 kb
Host smart-8dececa6-384d-4f32-a383-4d7d5dd1b8fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827916758 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.3827916758
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.3189400850
Short name T507
Test name
Test status
Simulation time 13611505 ps
CPU time 0.91 seconds
Started Aug 19 05:53:26 PM PDT 24
Finished Aug 19 05:53:27 PM PDT 24
Peak memory 207196 kb
Host smart-5804f083-f2ab-4a9b-af02-5803945fc00a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189400850 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.3189400850
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.1529448717
Short name T136
Test name
Test status
Simulation time 33472901 ps
CPU time 1.22 seconds
Started Aug 19 05:53:34 PM PDT 24
Finished Aug 19 05:53:36 PM PDT 24
Peak memory 216968 kb
Host smart-dec52088-9e99-454f-841c-6c372c57eed9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529448717 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.1529448717
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.4189126198
Short name T466
Test name
Test status
Simulation time 60774360 ps
CPU time 1.04 seconds
Started Aug 19 05:53:22 PM PDT 24
Finished Aug 19 05:53:23 PM PDT 24
Peak memory 220724 kb
Host smart-39dc3c7c-13c3-4b4d-b335-88ccd46b5551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189126198 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.4189126198
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.247920351
Short name T442
Test name
Test status
Simulation time 24740507 ps
CPU time 1.16 seconds
Started Aug 19 05:53:19 PM PDT 24
Finished Aug 19 05:53:20 PM PDT 24
Peak memory 217292 kb
Host smart-e6dbcde6-0f64-4944-9dac-533e9e88e636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247920351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.247920351
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.1531474634
Short name T655
Test name
Test status
Simulation time 25149549 ps
CPU time 0.99 seconds
Started Aug 19 05:53:31 PM PDT 24
Finished Aug 19 05:53:32 PM PDT 24
Peak memory 215536 kb
Host smart-1379a060-4130-4e09-9a7f-2e289279a733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531474634 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1531474634
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2397640149
Short name T730
Test name
Test status
Simulation time 32842633 ps
CPU time 0.89 seconds
Started Aug 19 05:53:20 PM PDT 24
Finished Aug 19 05:53:21 PM PDT 24
Peak memory 215388 kb
Host smart-983a58f9-0f4e-481b-a839-0f71a2cb567a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397640149 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2397640149
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2677286407
Short name T929
Test name
Test status
Simulation time 496416908 ps
CPU time 2.98 seconds
Started Aug 19 05:53:18 PM PDT 24
Finished Aug 19 05:53:21 PM PDT 24
Peak memory 215372 kb
Host smart-af0375d0-1279-4d59-aec1-66de796a2e51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677286407 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2677286407
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.235121678
Short name T232
Test name
Test status
Simulation time 14873713308 ps
CPU time 81.57 seconds
Started Aug 19 05:53:53 PM PDT 24
Finished Aug 19 05:55:15 PM PDT 24
Peak memory 223716 kb
Host smart-0a5d74d4-d710-4cde-a563-467fc65c331e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235121678 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.235121678
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.2775782813
Short name T77
Test name
Test status
Simulation time 43713895 ps
CPU time 1.14 seconds
Started Aug 19 05:53:36 PM PDT 24
Finished Aug 19 05:53:37 PM PDT 24
Peak memory 219384 kb
Host smart-a700bae6-27a2-4468-a91c-061116308288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775782813 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.2775782813
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.1183255026
Short name T589
Test name
Test status
Simulation time 19387321 ps
CPU time 1 seconds
Started Aug 19 05:53:33 PM PDT 24
Finished Aug 19 05:53:34 PM PDT 24
Peak memory 207020 kb
Host smart-d765d0de-c13f-4c7b-91c9-bc0774e3c355
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183255026 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.1183255026
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.3585227094
Short name T697
Test name
Test status
Simulation time 28197362 ps
CPU time 0.85 seconds
Started Aug 19 05:53:23 PM PDT 24
Finished Aug 19 05:53:24 PM PDT 24
Peak memory 215224 kb
Host smart-c8e76797-99f4-4a0e-b42b-1e8cb681a11b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585227094 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3585227094
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.2660229549
Short name T685
Test name
Test status
Simulation time 218763823 ps
CPU time 1.2 seconds
Started Aug 19 05:53:22 PM PDT 24
Finished Aug 19 05:53:24 PM PDT 24
Peak memory 217116 kb
Host smart-bdfa2753-505d-4dc8-ac34-e5e5fa3a71e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660229549 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.2660229549
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.680378980
Short name T102
Test name
Test status
Simulation time 28033570 ps
CPU time 0.83 seconds
Started Aug 19 05:53:25 PM PDT 24
Finished Aug 19 05:53:26 PM PDT 24
Peak memory 218128 kb
Host smart-7aefae82-6a6a-4fa1-8f19-3a9532b25d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680378980 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.680378980
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.3492519501
Short name T396
Test name
Test status
Simulation time 88129825 ps
CPU time 1.51 seconds
Started Aug 19 05:53:39 PM PDT 24
Finished Aug 19 05:53:40 PM PDT 24
Peak memory 218696 kb
Host smart-a77bb953-208c-450a-a470-adaed8fc09f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492519501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3492519501
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.824948601
Short name T625
Test name
Test status
Simulation time 30166386 ps
CPU time 0.86 seconds
Started Aug 19 05:53:28 PM PDT 24
Finished Aug 19 05:53:29 PM PDT 24
Peak memory 215720 kb
Host smart-797381a2-138a-4a99-8a16-69e9b643a7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824948601 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.824948601
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.2242228136
Short name T709
Test name
Test status
Simulation time 19373049 ps
CPU time 1 seconds
Started Aug 19 05:53:31 PM PDT 24
Finished Aug 19 05:53:32 PM PDT 24
Peak memory 207172 kb
Host smart-ec86324f-8286-4ba2-8045-479fcb57aaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242228136 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.2242228136
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.1485907542
Short name T732
Test name
Test status
Simulation time 70825129 ps
CPU time 1.82 seconds
Started Aug 19 05:53:27 PM PDT 24
Finished Aug 19 05:53:29 PM PDT 24
Peak memory 218516 kb
Host smart-7214c2b8-08a2-4bc7-a118-c991bc44cf07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485907542 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1485907542
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_alert.1767381390
Short name T808
Test name
Test status
Simulation time 77284785 ps
CPU time 1.17 seconds
Started Aug 19 05:53:35 PM PDT 24
Finished Aug 19 05:53:36 PM PDT 24
Peak memory 218572 kb
Host smart-79e38666-3186-40fd-94d5-695318c31be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767381390 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.1767381390
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.882052412
Short name T428
Test name
Test status
Simulation time 23381754 ps
CPU time 0.87 seconds
Started Aug 19 05:53:24 PM PDT 24
Finished Aug 19 05:53:25 PM PDT 24
Peak memory 206728 kb
Host smart-240a4e22-c708-427e-a99e-99c2cd27f404
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882052412 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.882052412
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_err.2879266990
Short name T769
Test name
Test status
Simulation time 27634068 ps
CPU time 1.02 seconds
Started Aug 19 05:53:17 PM PDT 24
Finished Aug 19 05:53:18 PM PDT 24
Peak memory 224152 kb
Host smart-be301f50-38b2-4dc8-ad58-9990947a7cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879266990 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2879266990
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.3047435774
Short name T367
Test name
Test status
Simulation time 60999700 ps
CPU time 1.54 seconds
Started Aug 19 05:53:23 PM PDT 24
Finished Aug 19 05:53:25 PM PDT 24
Peak memory 219104 kb
Host smart-0791d864-278a-4ebd-acd7-5dfbe66e2d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047435774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3047435774
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.1991657304
Short name T671
Test name
Test status
Simulation time 40492692 ps
CPU time 1 seconds
Started Aug 19 05:53:20 PM PDT 24
Finished Aug 19 05:53:21 PM PDT 24
Peak memory 224048 kb
Host smart-e91c5b55-b7d4-47a6-8eb2-8795ea6270fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991657304 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1991657304
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.2857996003
Short name T412
Test name
Test status
Simulation time 17041432 ps
CPU time 0.97 seconds
Started Aug 19 05:53:25 PM PDT 24
Finished Aug 19 05:53:26 PM PDT 24
Peak memory 215400 kb
Host smart-d9216bfd-da18-4d5f-8061-0338702782da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857996003 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.2857996003
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2566974712
Short name T244
Test name
Test status
Simulation time 588745490 ps
CPU time 6.07 seconds
Started Aug 19 05:53:44 PM PDT 24
Finished Aug 19 05:53:50 PM PDT 24
Peak memory 218712 kb
Host smart-60c13069-eeb6-4c25-88e5-4c0f8eb3ebe5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566974712 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2566974712
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3435581953
Short name T922
Test name
Test status
Simulation time 4214316862 ps
CPU time 106.4 seconds
Started Aug 19 05:53:32 PM PDT 24
Finished Aug 19 05:55:19 PM PDT 24
Peak memory 218024 kb
Host smart-ac458f6a-7811-405a-8899-74a43291081c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435581953 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.3435581953
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.3704564044
Short name T138
Test name
Test status
Simulation time 28703625 ps
CPU time 1.32 seconds
Started Aug 19 05:53:32 PM PDT 24
Finished Aug 19 05:53:33 PM PDT 24
Peak memory 220448 kb
Host smart-6d825794-1502-45ce-904e-d697ba1b2703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704564044 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3704564044
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.1953781515
Short name T539
Test name
Test status
Simulation time 16531561 ps
CPU time 0.94 seconds
Started Aug 19 05:53:29 PM PDT 24
Finished Aug 19 05:53:30 PM PDT 24
Peak memory 207024 kb
Host smart-e958ad31-a73f-445d-87df-5a240405c5ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953781515 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1953781515
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.1038346969
Short name T343
Test name
Test status
Simulation time 35336085 ps
CPU time 0.87 seconds
Started Aug 19 05:53:35 PM PDT 24
Finished Aug 19 05:53:36 PM PDT 24
Peak memory 215196 kb
Host smart-96cc1a32-db28-4357-9eee-9396bd147e26
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038346969 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1038346969
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.2200123437
Short name T498
Test name
Test status
Simulation time 31308523 ps
CPU time 1.01 seconds
Started Aug 19 05:55:46 PM PDT 24
Finished Aug 19 05:55:47 PM PDT 24
Peak memory 216876 kb
Host smart-2c4efb2b-5241-4f6d-a80c-3cd30edb2adc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200123437 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.2200123437
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.1451032162
Short name T52
Test name
Test status
Simulation time 32932013 ps
CPU time 0.99 seconds
Started Aug 19 05:53:45 PM PDT 24
Finished Aug 19 05:53:46 PM PDT 24
Peak memory 223936 kb
Host smart-68b21080-cf77-401d-9bde-92c3b7e1b902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451032162 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1451032162
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2670725723
Short name T746
Test name
Test status
Simulation time 47754177 ps
CPU time 1.4 seconds
Started Aug 19 05:53:30 PM PDT 24
Finished Aug 19 05:53:32 PM PDT 24
Peak memory 217536 kb
Host smart-c6649723-0774-400b-bb34-01f414678f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670725723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2670725723
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.392120974
Short name T99
Test name
Test status
Simulation time 19887161 ps
CPU time 1.01 seconds
Started Aug 19 05:53:27 PM PDT 24
Finished Aug 19 05:53:28 PM PDT 24
Peak memory 215848 kb
Host smart-0aceef97-e298-48d4-bdd0-b7c5a2528015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392120974 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.392120974
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.3409567307
Short name T851
Test name
Test status
Simulation time 21103584 ps
CPU time 1.05 seconds
Started Aug 19 05:53:29 PM PDT 24
Finished Aug 19 05:53:30 PM PDT 24
Peak memory 215392 kb
Host smart-98678f36-b574-423d-8b13-afb4bbe5417f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409567307 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3409567307
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.2681117795
Short name T426
Test name
Test status
Simulation time 189582611 ps
CPU time 4.19 seconds
Started Aug 19 05:53:26 PM PDT 24
Finished Aug 19 05:53:30 PM PDT 24
Peak memory 218760 kb
Host smart-7762a605-8ba6-4b7d-abc0-e9e228d88375
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681117795 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2681117795
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.2623245326
Short name T231
Test name
Test status
Simulation time 1583604956 ps
CPU time 37.23 seconds
Started Aug 19 05:53:31 PM PDT 24
Finished Aug 19 05:54:08 PM PDT 24
Peak memory 218484 kb
Host smart-4eb00fe0-d573-4bfd-b92e-83687f9c6fde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623245326 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.2623245326
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2692726962
Short name T419
Test name
Test status
Simulation time 66540857 ps
CPU time 1.23 seconds
Started Aug 19 05:53:35 PM PDT 24
Finished Aug 19 05:53:36 PM PDT 24
Peak memory 221220 kb
Host smart-81102efb-b896-4cb1-9f2a-59cbf458dbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692726962 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2692726962
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.3638061734
Short name T399
Test name
Test status
Simulation time 23143237 ps
CPU time 0.94 seconds
Started Aug 19 05:53:23 PM PDT 24
Finished Aug 19 05:53:24 PM PDT 24
Peak memory 206864 kb
Host smart-50870aa6-84df-4776-b67b-fb471c19d90c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638061734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3638061734
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.3165541372
Short name T950
Test name
Test status
Simulation time 11112983 ps
CPU time 0.9 seconds
Started Aug 19 05:53:22 PM PDT 24
Finished Aug 19 05:53:24 PM PDT 24
Peak memory 215492 kb
Host smart-f68c9e78-7422-42e8-9aef-d401b0fc7560
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165541372 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.3165541372
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_err.3761612546
Short name T148
Test name
Test status
Simulation time 60113428 ps
CPU time 0.89 seconds
Started Aug 19 05:53:35 PM PDT 24
Finished Aug 19 05:53:36 PM PDT 24
Peak memory 218252 kb
Host smart-f6651154-4f72-4bd8-8938-3b673392eced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761612546 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3761612546
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.2417296879
Short name T411
Test name
Test status
Simulation time 47889191 ps
CPU time 1.42 seconds
Started Aug 19 05:53:27 PM PDT 24
Finished Aug 19 05:53:29 PM PDT 24
Peak memory 218516 kb
Host smart-f968bf0f-1343-46d0-af5f-72fa2447557b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417296879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.2417296879
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.426234024
Short name T591
Test name
Test status
Simulation time 58430814 ps
CPU time 0.86 seconds
Started Aug 19 05:53:36 PM PDT 24
Finished Aug 19 05:53:37 PM PDT 24
Peak memory 215356 kb
Host smart-80233598-6467-4eda-8450-eba0bd3c8e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426234024 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.426234024
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.2546010268
Short name T242
Test name
Test status
Simulation time 30286604 ps
CPU time 0.92 seconds
Started Aug 19 05:53:34 PM PDT 24
Finished Aug 19 05:53:35 PM PDT 24
Peak memory 215400 kb
Host smart-d9727385-dc4e-40a6-90e1-3b4c4705d318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546010268 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.2546010268
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.643468907
Short name T631
Test name
Test status
Simulation time 268625574 ps
CPU time 5.7 seconds
Started Aug 19 05:53:32 PM PDT 24
Finished Aug 19 05:53:38 PM PDT 24
Peak memory 215472 kb
Host smart-3f9a6b77-a920-4e25-93e8-6c121832cdf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643468907 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.643468907
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.2229668994
Short name T869
Test name
Test status
Simulation time 1386111848 ps
CPU time 33.94 seconds
Started Aug 19 05:53:33 PM PDT 24
Finished Aug 19 05:54:07 PM PDT 24
Peak memory 217808 kb
Host smart-2e482dda-24de-44fd-a251-48dba9923a1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229668994 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.2229668994
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3856001608
Short name T505
Test name
Test status
Simulation time 97466048 ps
CPU time 1.29 seconds
Started Aug 19 05:52:37 PM PDT 24
Finished Aug 19 05:52:38 PM PDT 24
Peak memory 220016 kb
Host smart-9da53f3d-8eee-497c-9ee8-6a52575b8bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856001608 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3856001608
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.1115313201
Short name T558
Test name
Test status
Simulation time 16538676 ps
CPU time 0.96 seconds
Started Aug 19 05:52:43 PM PDT 24
Finished Aug 19 05:52:45 PM PDT 24
Peak memory 206800 kb
Host smart-c825cf4a-f6c9-4402-bb90-4849894deec5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115313201 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1115313201
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.2459888056
Short name T866
Test name
Test status
Simulation time 13895128 ps
CPU time 0.96 seconds
Started Aug 19 05:52:39 PM PDT 24
Finished Aug 19 05:52:40 PM PDT 24
Peak memory 215636 kb
Host smart-acc776b4-288d-4eab-8dbf-95629b4e7df6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459888056 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.2459888056
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.1262427629
Short name T637
Test name
Test status
Simulation time 283645453 ps
CPU time 1.19 seconds
Started Aug 19 05:52:37 PM PDT 24
Finished Aug 19 05:52:38 PM PDT 24
Peak memory 219532 kb
Host smart-8c415db6-acb6-4a1c-ae7e-4eee0c82f9ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262427629 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.1262427629
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.359381408
Short name T160
Test name
Test status
Simulation time 45619844 ps
CPU time 0.87 seconds
Started Aug 19 05:52:38 PM PDT 24
Finished Aug 19 05:52:39 PM PDT 24
Peak memory 218236 kb
Host smart-21b47e45-c061-43ba-99b6-61e4a47a838b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359381408 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.359381408
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.2587912398
Short name T458
Test name
Test status
Simulation time 57294359 ps
CPU time 1.11 seconds
Started Aug 19 05:52:41 PM PDT 24
Finished Aug 19 05:52:43 PM PDT 24
Peak memory 218600 kb
Host smart-3c9372ea-67ee-497f-b3a0-037548d9ea35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587912398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.2587912398
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.3311028457
Short name T652
Test name
Test status
Simulation time 60103388 ps
CPU time 0.81 seconds
Started Aug 19 05:52:47 PM PDT 24
Finished Aug 19 05:52:48 PM PDT 24
Peak memory 215796 kb
Host smart-f09ed244-19e7-4704-ba0f-d1463b803121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311028457 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3311028457
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.2692519699
Short name T609
Test name
Test status
Simulation time 27094317 ps
CPU time 0.97 seconds
Started Aug 19 05:52:33 PM PDT 24
Finished Aug 19 05:52:39 PM PDT 24
Peak memory 207192 kb
Host smart-a6bb4f73-5f2b-41ef-a823-f424b80cc1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692519699 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.2692519699
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.2192553156
Short name T235
Test name
Test status
Simulation time 60938056 ps
CPU time 0.89 seconds
Started Aug 19 05:52:32 PM PDT 24
Finished Aug 19 05:52:34 PM PDT 24
Peak memory 207012 kb
Host smart-4f2c5008-c876-4938-a25b-9ebf984edd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192553156 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.2192553156
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.2123674507
Short name T238
Test name
Test status
Simulation time 328984257 ps
CPU time 3.52 seconds
Started Aug 19 05:52:35 PM PDT 24
Finished Aug 19 05:52:39 PM PDT 24
Peak memory 217408 kb
Host smart-ccda14ed-30b9-4b5e-a180-484ade848134
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123674507 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2123674507
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.1119058130
Short name T636
Test name
Test status
Simulation time 14608392746 ps
CPU time 97.12 seconds
Started Aug 19 05:52:24 PM PDT 24
Finished Aug 19 05:54:01 PM PDT 24
Peak memory 219656 kb
Host smart-e505384d-b250-4334-87b6-356ad989bef1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119058130 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.1119058130
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.3547029396
Short name T461
Test name
Test status
Simulation time 22384198 ps
CPU time 1.14 seconds
Started Aug 19 05:53:37 PM PDT 24
Finished Aug 19 05:53:38 PM PDT 24
Peak memory 218772 kb
Host smart-3d571e35-80e0-4188-b5e9-2714c7ad23a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547029396 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.3547029396
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.2981619235
Short name T557
Test name
Test status
Simulation time 95630606 ps
CPU time 0.94 seconds
Started Aug 19 05:53:26 PM PDT 24
Finished Aug 19 05:53:27 PM PDT 24
Peak memory 206700 kb
Host smart-414986cb-b144-4dcf-a2c5-8167f094b1f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981619235 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2981619235
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.3028844133
Short name T647
Test name
Test status
Simulation time 67174599 ps
CPU time 0.86 seconds
Started Aug 19 05:53:26 PM PDT 24
Finished Aug 19 05:53:27 PM PDT 24
Peak memory 215472 kb
Host smart-0220de78-d1e1-4fcb-a180-89ae526448af
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028844133 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.3028844133
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.1145871059
Short name T126
Test name
Test status
Simulation time 58322913 ps
CPU time 1.16 seconds
Started Aug 19 05:53:41 PM PDT 24
Finished Aug 19 05:53:43 PM PDT 24
Peak memory 216960 kb
Host smart-64ac58a4-0906-4930-ac28-0580fa4babdb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145871059 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.1145871059
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.1471130588
Short name T957
Test name
Test status
Simulation time 37212445 ps
CPU time 1.46 seconds
Started Aug 19 05:53:23 PM PDT 24
Finished Aug 19 05:53:25 PM PDT 24
Peak memory 219788 kb
Host smart-c9603b5e-5baf-4fc8-8bfd-e558f03234c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471130588 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1471130588
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_intr.3135953409
Short name T762
Test name
Test status
Simulation time 21422273 ps
CPU time 1.08 seconds
Started Aug 19 05:53:32 PM PDT 24
Finished Aug 19 05:53:33 PM PDT 24
Peak memory 215936 kb
Host smart-162e4fa4-de90-42f9-8a04-062375bab883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135953409 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.3135953409
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.1854777741
Short name T332
Test name
Test status
Simulation time 27845642 ps
CPU time 0.95 seconds
Started Aug 19 05:53:36 PM PDT 24
Finished Aug 19 05:53:37 PM PDT 24
Peak memory 215344 kb
Host smart-609cdfed-5c11-4a46-a7af-2cf3bb24ec8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854777741 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1854777741
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.3341939806
Short name T427
Test name
Test status
Simulation time 382046863 ps
CPU time 4.47 seconds
Started Aug 19 05:53:41 PM PDT 24
Finished Aug 19 05:53:46 PM PDT 24
Peak memory 217360 kb
Host smart-578acfbf-a4aa-4300-ac3b-a0f24342b2b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341939806 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.3341939806
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2599413936
Short name T886
Test name
Test status
Simulation time 6211988710 ps
CPU time 114.9 seconds
Started Aug 19 05:53:54 PM PDT 24
Finished Aug 19 05:55:49 PM PDT 24
Peak memory 218296 kb
Host smart-7c931970-1dbf-498b-bb51-4a1d88cb13af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599413936 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2599413936
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.2441588797
Short name T131
Test name
Test status
Simulation time 30761294 ps
CPU time 1.29 seconds
Started Aug 19 05:53:39 PM PDT 24
Finished Aug 19 05:53:40 PM PDT 24
Peak memory 220668 kb
Host smart-96faf1a1-2a82-4971-a2e2-acac1615db80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441588797 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.2441588797
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.2603886868
Short name T561
Test name
Test status
Simulation time 65004171 ps
CPU time 0.87 seconds
Started Aug 19 05:53:19 PM PDT 24
Finished Aug 19 05:53:20 PM PDT 24
Peak memory 215052 kb
Host smart-a1b322db-b3bb-44e8-bb0a-236fc50c48f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603886868 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2603886868
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.1527415560
Short name T203
Test name
Test status
Simulation time 9961320 ps
CPU time 0.88 seconds
Started Aug 19 05:53:40 PM PDT 24
Finished Aug 19 05:53:41 PM PDT 24
Peak memory 215508 kb
Host smart-a53511a6-d6c8-486e-a779-28534242c69b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527415560 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.1527415560
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.2139243319
Short name T705
Test name
Test status
Simulation time 78688433 ps
CPU time 1.14 seconds
Started Aug 19 05:53:56 PM PDT 24
Finished Aug 19 05:53:58 PM PDT 24
Peak memory 216972 kb
Host smart-e439f511-3ec4-4c51-8df0-012368ccc9d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139243319 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.2139243319
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3932193726
Short name T79
Test name
Test status
Simulation time 19286464 ps
CPU time 1.06 seconds
Started Aug 19 05:53:29 PM PDT 24
Finished Aug 19 05:53:31 PM PDT 24
Peak memory 218476 kb
Host smart-ada66cfc-bba9-4723-9387-637406199113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932193726 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3932193726
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.2159064007
Short name T747
Test name
Test status
Simulation time 70244788 ps
CPU time 1.36 seconds
Started Aug 19 05:53:35 PM PDT 24
Finished Aug 19 05:53:36 PM PDT 24
Peak memory 218972 kb
Host smart-df26a0fb-83e7-49a8-92ed-9c364003704f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159064007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2159064007
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.3675703300
Short name T706
Test name
Test status
Simulation time 45596686 ps
CPU time 0.99 seconds
Started Aug 19 05:53:31 PM PDT 24
Finished Aug 19 05:53:32 PM PDT 24
Peak memory 224280 kb
Host smart-1310a7c1-b1c6-4f0d-a7ae-24753841fdb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675703300 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.3675703300
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.1227141203
Short name T785
Test name
Test status
Simulation time 26399141 ps
CPU time 0.91 seconds
Started Aug 19 05:53:29 PM PDT 24
Finished Aug 19 05:53:30 PM PDT 24
Peak memory 215284 kb
Host smart-e2d0416f-549d-475c-90ab-f0f980258d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227141203 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.1227141203
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.356747531
Short name T454
Test name
Test status
Simulation time 144211718 ps
CPU time 2.08 seconds
Started Aug 19 05:53:47 PM PDT 24
Finished Aug 19 05:53:54 PM PDT 24
Peak memory 217380 kb
Host smart-f2b474c0-5931-4663-9e89-e11605a9d3a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356747531 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.356747531
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1487766776
Short name T226
Test name
Test status
Simulation time 4969109709 ps
CPU time 128.83 seconds
Started Aug 19 05:53:33 PM PDT 24
Finished Aug 19 05:55:41 PM PDT 24
Peak memory 218744 kb
Host smart-e9220348-2095-48d4-9d02-e12a1ee716ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487766776 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1487766776
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.1040739738
Short name T758
Test name
Test status
Simulation time 52159793 ps
CPU time 1.17 seconds
Started Aug 19 05:53:25 PM PDT 24
Finished Aug 19 05:53:26 PM PDT 24
Peak memory 219928 kb
Host smart-0c8cdb9e-3509-4f1b-9550-2749cb7dec21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040739738 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1040739738
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2370481140
Short name T602
Test name
Test status
Simulation time 133155322 ps
CPU time 0.97 seconds
Started Aug 19 05:53:39 PM PDT 24
Finished Aug 19 05:53:40 PM PDT 24
Peak memory 214988 kb
Host smart-b71763a8-a8be-438b-88a2-c8bcf6980764
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370481140 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2370481140
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.1605487286
Short name T828
Test name
Test status
Simulation time 39245440 ps
CPU time 0.84 seconds
Started Aug 19 05:53:21 PM PDT 24
Finished Aug 19 05:53:22 PM PDT 24
Peak memory 215460 kb
Host smart-d5eb079d-08e0-4176-a2d3-1d242881fb89
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605487286 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1605487286
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.981022149
Short name T475
Test name
Test status
Simulation time 120471137 ps
CPU time 1.13 seconds
Started Aug 19 05:53:33 PM PDT 24
Finished Aug 19 05:53:34 PM PDT 24
Peak memory 215552 kb
Host smart-2843185b-0197-4c94-a318-7479c919de66
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981022149 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_di
sable_auto_req_mode.981022149
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.2963804865
Short name T155
Test name
Test status
Simulation time 40752344 ps
CPU time 1.05 seconds
Started Aug 19 05:53:39 PM PDT 24
Finished Aug 19 05:53:40 PM PDT 24
Peak memory 217440 kb
Host smart-4d6e4620-bcff-4962-8525-7e29fb7320ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963804865 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.2963804865
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.3362989604
Short name T309
Test name
Test status
Simulation time 106891032 ps
CPU time 1.29 seconds
Started Aug 19 05:53:40 PM PDT 24
Finished Aug 19 05:53:41 PM PDT 24
Peak memory 220496 kb
Host smart-51a89feb-efb8-4b90-bee9-01deceeef5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362989604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.3362989604
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.1285687809
Short name T1
Test name
Test status
Simulation time 19878549 ps
CPU time 1.02 seconds
Started Aug 19 05:53:47 PM PDT 24
Finished Aug 19 05:53:48 PM PDT 24
Peak memory 216004 kb
Host smart-a45032b7-92e8-4179-9d92-533104286d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285687809 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.1285687809
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.2070436512
Short name T739
Test name
Test status
Simulation time 47617471 ps
CPU time 0.9 seconds
Started Aug 19 05:53:27 PM PDT 24
Finished Aug 19 05:53:28 PM PDT 24
Peak memory 215388 kb
Host smart-9fcb2170-5dea-4b83-9361-cb7148ef70ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070436512 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.2070436512
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.2181367140
Short name T342
Test name
Test status
Simulation time 97016520 ps
CPU time 1.59 seconds
Started Aug 19 05:53:31 PM PDT 24
Finished Aug 19 05:53:32 PM PDT 24
Peak memory 217284 kb
Host smart-b99430f9-2e65-478e-849b-c8dc8ba57b79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181367140 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2181367140
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_alert.2924896516
Short name T26
Test name
Test status
Simulation time 26042161 ps
CPU time 1.18 seconds
Started Aug 19 05:53:42 PM PDT 24
Finished Aug 19 05:53:44 PM PDT 24
Peak memory 218680 kb
Host smart-45115a77-ca16-4950-9d8e-17cf581fa030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924896516 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2924896516
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.3088022754
Short name T354
Test name
Test status
Simulation time 26452903 ps
CPU time 0.83 seconds
Started Aug 19 05:53:25 PM PDT 24
Finished Aug 19 05:53:26 PM PDT 24
Peak memory 206444 kb
Host smart-ae20e9ee-78f0-473b-8b27-a5e33e726d83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088022754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3088022754
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.3568590293
Short name T577
Test name
Test status
Simulation time 19111401 ps
CPU time 0.9 seconds
Started Aug 19 05:53:33 PM PDT 24
Finished Aug 19 05:53:34 PM PDT 24
Peak memory 207248 kb
Host smart-3553e8fc-5231-4121-bc14-94a702905ca8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568590293 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.3568590293
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.814097577
Short name T134
Test name
Test status
Simulation time 37576080 ps
CPU time 1.21 seconds
Started Aug 19 05:53:38 PM PDT 24
Finished Aug 19 05:53:40 PM PDT 24
Peak memory 217032 kb
Host smart-db76e88c-1ff6-497d-9aab-50f1496ea395
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814097577 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_di
sable_auto_req_mode.814097577
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.2974819718
Short name T875
Test name
Test status
Simulation time 91519546 ps
CPU time 1.16 seconds
Started Aug 19 05:53:42 PM PDT 24
Finished Aug 19 05:53:44 PM PDT 24
Peak memory 219748 kb
Host smart-09f3c127-e007-4600-8114-6b1d96473181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974819718 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.2974819718
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.428961503
Short name T395
Test name
Test status
Simulation time 55422278 ps
CPU time 1.21 seconds
Started Aug 19 05:53:32 PM PDT 24
Finished Aug 19 05:53:34 PM PDT 24
Peak memory 217320 kb
Host smart-df636cbc-f3e9-473f-99e5-51a23255bb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428961503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.428961503
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.1799195851
Short name T813
Test name
Test status
Simulation time 20156391 ps
CPU time 1.04 seconds
Started Aug 19 05:53:37 PM PDT 24
Finished Aug 19 05:53:38 PM PDT 24
Peak memory 216088 kb
Host smart-a0b45c91-793e-4e93-ba55-6e1cb4bcccbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799195851 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.1799195851
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.3654752919
Short name T324
Test name
Test status
Simulation time 25192918 ps
CPU time 0.95 seconds
Started Aug 19 05:53:24 PM PDT 24
Finished Aug 19 05:53:26 PM PDT 24
Peak memory 207204 kb
Host smart-3895fb5d-a705-4da6-a655-6859bda9c6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654752919 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.3654752919
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1921894944
Short name T237
Test name
Test status
Simulation time 1289829395 ps
CPU time 2.53 seconds
Started Aug 19 05:53:41 PM PDT 24
Finished Aug 19 05:53:44 PM PDT 24
Peak memory 217368 kb
Host smart-400f4dad-967f-4d07-b69d-d8a0ec2e543b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921894944 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1921894944
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2919516757
Short name T641
Test name
Test status
Simulation time 4637813487 ps
CPU time 101.19 seconds
Started Aug 19 05:53:21 PM PDT 24
Finished Aug 19 05:55:02 PM PDT 24
Peak memory 220616 kb
Host smart-fa5bbb4d-b6a0-4ca9-aa91-2dd2dec37ada
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919516757 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2919516757
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.908077835
Short name T575
Test name
Test status
Simulation time 69641463 ps
CPU time 1.16 seconds
Started Aug 19 05:53:37 PM PDT 24
Finished Aug 19 05:53:38 PM PDT 24
Peak memory 220408 kb
Host smart-9f5b7a93-e2ea-4229-adf2-85ae910e9520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908077835 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.908077835
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.3456641796
Short name T478
Test name
Test status
Simulation time 37534532 ps
CPU time 0.82 seconds
Started Aug 19 05:53:45 PM PDT 24
Finished Aug 19 05:53:46 PM PDT 24
Peak memory 214896 kb
Host smart-30f7c541-45ff-42a5-bb7c-0e0a9de91ab5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456641796 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3456641796
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.551077972
Short name T162
Test name
Test status
Simulation time 45044470 ps
CPU time 0.8 seconds
Started Aug 19 05:53:30 PM PDT 24
Finished Aug 19 05:53:31 PM PDT 24
Peak memory 207284 kb
Host smart-b5157943-12b4-4542-9e1f-c43cc8cefa9c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551077972 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.551077972
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.3970107192
Short name T804
Test name
Test status
Simulation time 21917822 ps
CPU time 0.98 seconds
Started Aug 19 05:53:41 PM PDT 24
Finished Aug 19 05:53:42 PM PDT 24
Peak memory 218396 kb
Host smart-30cb92b0-2181-430c-8f09-056e8b228b41
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970107192 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.3970107192
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.1218765772
Short name T537
Test name
Test status
Simulation time 24461941 ps
CPU time 1.33 seconds
Started Aug 19 05:53:48 PM PDT 24
Finished Aug 19 05:53:49 PM PDT 24
Peak memory 220232 kb
Host smart-f008d51f-60a5-4351-b52d-28e398acc3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218765772 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.1218765772
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_intr.1432296667
Short name T201
Test name
Test status
Simulation time 22242946 ps
CPU time 1.11 seconds
Started Aug 19 05:53:26 PM PDT 24
Finished Aug 19 05:53:27 PM PDT 24
Peak memory 215504 kb
Host smart-82207162-fee9-4b51-a00f-729c50be1289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432296667 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1432296667
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.3787177165
Short name T386
Test name
Test status
Simulation time 18032180 ps
CPU time 0.94 seconds
Started Aug 19 05:53:24 PM PDT 24
Finished Aug 19 05:53:25 PM PDT 24
Peak memory 215400 kb
Host smart-2dae46c3-965b-4901-8427-da7054c4e6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787177165 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.3787177165
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1396934209
Short name T865
Test name
Test status
Simulation time 139752425 ps
CPU time 1.25 seconds
Started Aug 19 05:53:31 PM PDT 24
Finished Aug 19 05:53:32 PM PDT 24
Peak memory 217392 kb
Host smart-a87d08e9-453b-4b64-a4fd-5c2f781f68af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396934209 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1396934209
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.4065815181
Short name T224
Test name
Test status
Simulation time 15365088676 ps
CPU time 93.34 seconds
Started Aug 19 05:53:38 PM PDT 24
Finished Aug 19 05:55:11 PM PDT 24
Peak memory 218932 kb
Host smart-88964b39-1dfa-458d-ac69-35027c48739a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065815181 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.4065815181
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.1764996160
Short name T771
Test name
Test status
Simulation time 84560248 ps
CPU time 1.19 seconds
Started Aug 19 05:53:23 PM PDT 24
Finished Aug 19 05:53:25 PM PDT 24
Peak memory 218616 kb
Host smart-f9f72a7b-0205-411e-abbb-8b9857cf904f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764996160 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.1764996160
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.2557484674
Short name T903
Test name
Test status
Simulation time 39523219 ps
CPU time 0.92 seconds
Started Aug 19 05:53:34 PM PDT 24
Finished Aug 19 05:53:35 PM PDT 24
Peak memory 206844 kb
Host smart-1f7830ff-61a8-460c-8347-3b5ed5023ab5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557484674 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2557484674
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.1310052983
Short name T183
Test name
Test status
Simulation time 12254700 ps
CPU time 0.9 seconds
Started Aug 19 05:53:47 PM PDT 24
Finished Aug 19 05:53:48 PM PDT 24
Peak memory 215584 kb
Host smart-dec30335-c0ab-4689-b788-c56eb0307256
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310052983 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.1310052983
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1257810883
Short name T660
Test name
Test status
Simulation time 56757788 ps
CPU time 1.22 seconds
Started Aug 19 05:53:48 PM PDT 24
Finished Aug 19 05:53:49 PM PDT 24
Peak memory 216948 kb
Host smart-5a9563a3-b4d4-46ca-8a17-33804e1c1d49
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257810883 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1257810883
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.1733316259
Short name T133
Test name
Test status
Simulation time 24843709 ps
CPU time 1.2 seconds
Started Aug 19 05:53:39 PM PDT 24
Finished Aug 19 05:53:40 PM PDT 24
Peak memory 220532 kb
Host smart-9a5265f0-5030-4731-a3db-36f0d4e7b8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733316259 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1733316259
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.480406941
Short name T402
Test name
Test status
Simulation time 116244171 ps
CPU time 1.37 seconds
Started Aug 19 05:53:47 PM PDT 24
Finished Aug 19 05:53:48 PM PDT 24
Peak memory 219056 kb
Host smart-3c9bc2b9-f1f7-4a71-b11b-464bad47f7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480406941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.480406941
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.2312864712
Short name T29
Test name
Test status
Simulation time 23031877 ps
CPU time 1.03 seconds
Started Aug 19 05:53:31 PM PDT 24
Finished Aug 19 05:53:32 PM PDT 24
Peak memory 215836 kb
Host smart-17175407-ae05-4af4-bba6-358795028c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312864712 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.2312864712
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.1885731670
Short name T383
Test name
Test status
Simulation time 25020229 ps
CPU time 0.99 seconds
Started Aug 19 05:53:30 PM PDT 24
Finished Aug 19 05:53:31 PM PDT 24
Peak memory 215412 kb
Host smart-dfda068b-7277-44f9-b5ff-1679881160be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885731670 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1885731670
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.918795617
Short name T760
Test name
Test status
Simulation time 43548506 ps
CPU time 1.34 seconds
Started Aug 19 05:53:42 PM PDT 24
Finished Aug 19 05:53:43 PM PDT 24
Peak memory 206856 kb
Host smart-d2203b2b-82c9-4f58-aaab-f19f75c4b4ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918795617 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.918795617
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.398617828
Short name T530
Test name
Test status
Simulation time 2805376126 ps
CPU time 74.44 seconds
Started Aug 19 05:53:40 PM PDT 24
Finished Aug 19 05:54:54 PM PDT 24
Peak memory 218520 kb
Host smart-a31df672-da65-44d4-be0b-21710e877078
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398617828 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.398617828
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.3345108233
Short name T796
Test name
Test status
Simulation time 46237754 ps
CPU time 1.13 seconds
Started Aug 19 05:53:27 PM PDT 24
Finished Aug 19 05:53:29 PM PDT 24
Peak memory 219164 kb
Host smart-ce8b9151-8d85-4f2e-8cd5-85d73fc1a233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345108233 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.3345108233
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.3650424610
Short name T780
Test name
Test status
Simulation time 16512503 ps
CPU time 0.91 seconds
Started Aug 19 05:53:33 PM PDT 24
Finished Aug 19 05:53:34 PM PDT 24
Peak memory 206804 kb
Host smart-9cf0b794-475a-44d1-9e39-4cd0e98fa564
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650424610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.3650424610
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.2685840857
Short name T64
Test name
Test status
Simulation time 12804844 ps
CPU time 0.91 seconds
Started Aug 19 05:54:45 PM PDT 24
Finished Aug 19 05:54:46 PM PDT 24
Peak memory 207188 kb
Host smart-23c3f84b-426f-41af-8428-1f3377bc77e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685840857 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.2685840857
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.1229266907
Short name T275
Test name
Test status
Simulation time 82057408 ps
CPU time 1.01 seconds
Started Aug 19 05:53:34 PM PDT 24
Finished Aug 19 05:53:35 PM PDT 24
Peak memory 218800 kb
Host smart-9e9c41de-ebaf-4797-986c-d084761d28dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229266907 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.1229266907
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.1638101063
Short name T177
Test name
Test status
Simulation time 74080197 ps
CPU time 1.15 seconds
Started Aug 19 05:53:23 PM PDT 24
Finished Aug 19 05:53:24 PM PDT 24
Peak memory 219608 kb
Host smart-f538ccaa-f8d3-4e95-aa78-07cf0e668b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638101063 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1638101063
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.970958797
Short name T649
Test name
Test status
Simulation time 73715392 ps
CPU time 1.22 seconds
Started Aug 19 05:53:33 PM PDT 24
Finished Aug 19 05:53:34 PM PDT 24
Peak memory 217332 kb
Host smart-7b935846-fe33-48c5-98ac-02e855e2aa6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970958797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.970958797
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.2080569805
Short name T824
Test name
Test status
Simulation time 22342616 ps
CPU time 1.02 seconds
Started Aug 19 05:53:30 PM PDT 24
Finished Aug 19 05:53:31 PM PDT 24
Peak memory 215864 kb
Host smart-15470204-50a8-486a-8129-6682dced9700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080569805 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.2080569805
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.855917364
Short name T339
Test name
Test status
Simulation time 38742976 ps
CPU time 0.91 seconds
Started Aug 19 05:53:25 PM PDT 24
Finished Aug 19 05:53:26 PM PDT 24
Peak memory 215368 kb
Host smart-78994154-7fa6-4c88-8957-fdd519a90923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855917364 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.855917364
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.1834529289
Short name T576
Test name
Test status
Simulation time 49987473 ps
CPU time 1.55 seconds
Started Aug 19 05:53:34 PM PDT 24
Finished Aug 19 05:53:35 PM PDT 24
Peak memory 215420 kb
Host smart-80877a9d-c69e-4969-becf-72d4099204ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834529289 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1834529289
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.3324717818
Short name T827
Test name
Test status
Simulation time 6643419540 ps
CPU time 44.91 seconds
Started Aug 19 05:53:29 PM PDT 24
Finished Aug 19 05:54:14 PM PDT 24
Peak memory 218916 kb
Host smart-c1a2f7fc-a121-4b8e-9dd5-84c39cd16f09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324717818 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.3324717818
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.153277270
Short name T186
Test name
Test status
Simulation time 43418864 ps
CPU time 1.08 seconds
Started Aug 19 05:53:43 PM PDT 24
Finished Aug 19 05:53:44 PM PDT 24
Peak memory 219672 kb
Host smart-1c5a037a-323f-45e8-97a1-0beaa314f30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153277270 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.153277270
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.3794403516
Short name T447
Test name
Test status
Simulation time 48998512 ps
CPU time 0.92 seconds
Started Aug 19 05:53:36 PM PDT 24
Finished Aug 19 05:53:37 PM PDT 24
Peak memory 206840 kb
Host smart-5a14c9f5-11b6-4f98-aa68-baab786892b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794403516 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3794403516
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.3348922901
Short name T582
Test name
Test status
Simulation time 18615886 ps
CPU time 0.86 seconds
Started Aug 19 05:53:55 PM PDT 24
Finished Aug 19 05:53:56 PM PDT 24
Peak memory 215420 kb
Host smart-2a481d23-378b-4ee0-8daf-b8cb301c9685
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348922901 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3348922901
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1136858604
Short name T510
Test name
Test status
Simulation time 46922615 ps
CPU time 1.52 seconds
Started Aug 19 05:53:49 PM PDT 24
Finished Aug 19 05:53:51 PM PDT 24
Peak memory 219176 kb
Host smart-e7986626-b332-49ce-82ac-0c0890aa6def
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136858604 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1136858604
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.2984911451
Short name T56
Test name
Test status
Simulation time 87331910 ps
CPU time 1 seconds
Started Aug 19 05:53:47 PM PDT 24
Finished Aug 19 05:53:48 PM PDT 24
Peak memory 229664 kb
Host smart-a7a3c693-7367-4a3f-a12d-7e20d73bfa69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984911451 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.2984911451
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.1916942057
Short name T867
Test name
Test status
Simulation time 257774748 ps
CPU time 3.6 seconds
Started Aug 19 05:53:26 PM PDT 24
Finished Aug 19 05:53:30 PM PDT 24
Peak memory 219428 kb
Host smart-c8aae3d7-dace-4c50-bdf9-9eba6b09f4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916942057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1916942057
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1490251510
Short name T30
Test name
Test status
Simulation time 27568235 ps
CPU time 0.88 seconds
Started Aug 19 05:53:34 PM PDT 24
Finished Aug 19 05:53:34 PM PDT 24
Peak memory 215956 kb
Host smart-33d733d1-1683-4c28-8cc6-1b447bd846fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490251510 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1490251510
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.2779329335
Short name T742
Test name
Test status
Simulation time 32043204 ps
CPU time 1 seconds
Started Aug 19 05:53:33 PM PDT 24
Finished Aug 19 05:53:34 PM PDT 24
Peak memory 215400 kb
Host smart-508b7790-8640-4477-8606-9b8f31815be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779329335 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2779329335
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.1232769706
Short name T295
Test name
Test status
Simulation time 187644362 ps
CPU time 4.03 seconds
Started Aug 19 05:54:03 PM PDT 24
Finished Aug 19 05:54:07 PM PDT 24
Peak memory 217288 kb
Host smart-1c5ed6a8-449b-427e-b396-7759c7ae5964
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232769706 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1232769706
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.941115741
Short name T852
Test name
Test status
Simulation time 6107600069 ps
CPU time 51.43 seconds
Started Aug 19 05:53:35 PM PDT 24
Finished Aug 19 05:54:26 PM PDT 24
Peak memory 217936 kb
Host smart-50ef01d1-abc9-4a3f-99c5-30dcc00c5bdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941115741 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.941115741
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.3380933228
Short name T704
Test name
Test status
Simulation time 25093364 ps
CPU time 1.17 seconds
Started Aug 19 05:53:37 PM PDT 24
Finished Aug 19 05:53:38 PM PDT 24
Peak memory 219832 kb
Host smart-7d8b1b28-272f-44f6-990d-0c9eba39464d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380933228 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3380933228
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.647151625
Short name T76
Test name
Test status
Simulation time 36856598 ps
CPU time 0.98 seconds
Started Aug 19 05:53:33 PM PDT 24
Finished Aug 19 05:53:34 PM PDT 24
Peak memory 214924 kb
Host smart-cedb0985-c038-4b30-9f4a-03196673c770
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647151625 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.647151625
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.150739114
Short name T740
Test name
Test status
Simulation time 11275917 ps
CPU time 0.94 seconds
Started Aug 19 05:53:30 PM PDT 24
Finished Aug 19 05:53:31 PM PDT 24
Peak memory 215492 kb
Host smart-c03470b5-2a0f-4d02-8584-f5611a5198b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150739114 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.150739114
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.2163112942
Short name T135
Test name
Test status
Simulation time 499318713 ps
CPU time 1.18 seconds
Started Aug 19 05:53:42 PM PDT 24
Finished Aug 19 05:53:43 PM PDT 24
Peak memory 217028 kb
Host smart-8e758f3d-9ba8-4cc7-8e0f-5b61cae75db8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163112942 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.2163112942
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.1940264698
Short name T415
Test name
Test status
Simulation time 21806898 ps
CPU time 0.91 seconds
Started Aug 19 05:53:37 PM PDT 24
Finished Aug 19 05:53:38 PM PDT 24
Peak memory 218568 kb
Host smart-65745f27-8155-476c-a4e9-1e5285400dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940264698 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.1940264698
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.3856946600
Short name T522
Test name
Test status
Simulation time 103133038 ps
CPU time 1.59 seconds
Started Aug 19 05:53:48 PM PDT 24
Finished Aug 19 05:53:50 PM PDT 24
Peak memory 219048 kb
Host smart-87358f04-f5b1-4564-8ad0-34453d435a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856946600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3856946600
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.4245666885
Short name T105
Test name
Test status
Simulation time 20555610 ps
CPU time 1.16 seconds
Started Aug 19 05:53:36 PM PDT 24
Finished Aug 19 05:53:37 PM PDT 24
Peak memory 216052 kb
Host smart-c72bec4c-532c-49e2-9abb-90f95b8ce5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245666885 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.4245666885
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.1577912117
Short name T67
Test name
Test status
Simulation time 44646915 ps
CPU time 0.92 seconds
Started Aug 19 05:53:42 PM PDT 24
Finished Aug 19 05:53:43 PM PDT 24
Peak memory 215468 kb
Host smart-0d77b751-9b6f-47a8-87b7-2c6c08f6aa2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577912117 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.1577912117
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1047919031
Short name T919
Test name
Test status
Simulation time 194101610 ps
CPU time 2.74 seconds
Started Aug 19 05:53:38 PM PDT 24
Finished Aug 19 05:53:41 PM PDT 24
Peak memory 217376 kb
Host smart-219e3934-de20-424f-9d99-c2e143f1dde6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047919031 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1047919031
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1424693792
Short name T229
Test name
Test status
Simulation time 23777108519 ps
CPU time 59.01 seconds
Started Aug 19 05:53:49 PM PDT 24
Finished Aug 19 05:54:48 PM PDT 24
Peak memory 218828 kb
Host smart-ab1e8499-64aa-436a-8551-086880c26eab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424693792 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1424693792
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.3842595809
Short name T196
Test name
Test status
Simulation time 36096578 ps
CPU time 1.06 seconds
Started Aug 19 05:53:33 PM PDT 24
Finished Aug 19 05:53:34 PM PDT 24
Peak memory 219136 kb
Host smart-3105d4ab-4cda-43b7-b5f6-ef99b9b29bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842595809 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.3842595809
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.226933769
Short name T874
Test name
Test status
Simulation time 19410853 ps
CPU time 1.02 seconds
Started Aug 19 05:53:45 PM PDT 24
Finished Aug 19 05:53:46 PM PDT 24
Peak memory 206852 kb
Host smart-026b2ef8-6cc3-4f6c-948a-169c0db7ff55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226933769 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.226933769
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.2125237564
Short name T675
Test name
Test status
Simulation time 15569910 ps
CPU time 0.92 seconds
Started Aug 19 05:53:44 PM PDT 24
Finished Aug 19 05:53:45 PM PDT 24
Peak memory 215680 kb
Host smart-4618c609-5da9-42e7-a237-d66614d0d8ed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125237564 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2125237564
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.2240091732
Short name T215
Test name
Test status
Simulation time 100797182 ps
CPU time 1.06 seconds
Started Aug 19 05:53:43 PM PDT 24
Finished Aug 19 05:53:45 PM PDT 24
Peak memory 217056 kb
Host smart-45016f83-1b53-494c-b3e4-627678dc98a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240091732 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.2240091732
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.3393188506
Short name T714
Test name
Test status
Simulation time 19568742 ps
CPU time 1.04 seconds
Started Aug 19 05:53:39 PM PDT 24
Finished Aug 19 05:53:41 PM PDT 24
Peak memory 218624 kb
Host smart-04142403-24dc-4d29-8ce6-a0857e9532d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393188506 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3393188506
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.2249423059
Short name T847
Test name
Test status
Simulation time 43105221 ps
CPU time 1.53 seconds
Started Aug 19 05:53:33 PM PDT 24
Finished Aug 19 05:53:34 PM PDT 24
Peak memory 219676 kb
Host smart-ca70928b-8a34-4cd3-8d28-1e6dab6e387a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249423059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2249423059
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.3240226895
Short name T963
Test name
Test status
Simulation time 21962029 ps
CPU time 1.16 seconds
Started Aug 19 05:53:37 PM PDT 24
Finished Aug 19 05:53:38 PM PDT 24
Peak memory 215636 kb
Host smart-59a7e0d1-52de-43fe-9b65-c61592eee5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240226895 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3240226895
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.1130628478
Short name T748
Test name
Test status
Simulation time 14521362 ps
CPU time 1 seconds
Started Aug 19 05:53:36 PM PDT 24
Finished Aug 19 05:53:37 PM PDT 24
Peak memory 215368 kb
Host smart-bf44c0a3-e602-40e9-9857-1de5a978129a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130628478 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.1130628478
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.496086531
Short name T387
Test name
Test status
Simulation time 543876854 ps
CPU time 3.47 seconds
Started Aug 19 05:53:27 PM PDT 24
Finished Aug 19 05:53:31 PM PDT 24
Peak memory 215468 kb
Host smart-692d7aaa-6d64-413c-965f-8db2dc7a553a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496086531 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.496086531
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1218929972
Short name T228
Test name
Test status
Simulation time 6527958817 ps
CPU time 40.2 seconds
Started Aug 19 05:53:40 PM PDT 24
Finished Aug 19 05:54:20 PM PDT 24
Peak memory 218520 kb
Host smart-079a7478-ab18-42b3-96e3-cd14c4a1862c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218929972 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1218929972
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3442585134
Short name T812
Test name
Test status
Simulation time 29334463 ps
CPU time 1.26 seconds
Started Aug 19 05:52:34 PM PDT 24
Finished Aug 19 05:52:35 PM PDT 24
Peak memory 219332 kb
Host smart-6707d2a5-4203-4732-adc3-b9e2df1f56d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442585134 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3442585134
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.2544076146
Short name T344
Test name
Test status
Simulation time 40703011 ps
CPU time 0.88 seconds
Started Aug 19 05:52:40 PM PDT 24
Finished Aug 19 05:52:41 PM PDT 24
Peak memory 206844 kb
Host smart-3732aac2-5efd-4eb7-9d39-cc633e0cd7a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544076146 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2544076146
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.907146063
Short name T483
Test name
Test status
Simulation time 36799057 ps
CPU time 0.9 seconds
Started Aug 19 05:52:32 PM PDT 24
Finished Aug 19 05:52:33 PM PDT 24
Peak memory 215508 kb
Host smart-4ba233ee-8f54-4a7c-8d4b-68a96323bac7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907146063 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.907146063
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.1353072650
Short name T397
Test name
Test status
Simulation time 69333783 ps
CPU time 1.19 seconds
Started Aug 19 05:52:28 PM PDT 24
Finished Aug 19 05:52:30 PM PDT 24
Peak memory 218620 kb
Host smart-97108aa7-0d64-4ddb-88c1-bb3f3e3bcc77
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353072650 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.1353072650
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.1372914004
Short name T208
Test name
Test status
Simulation time 19099840 ps
CPU time 1.15 seconds
Started Aug 19 05:52:46 PM PDT 24
Finished Aug 19 05:52:47 PM PDT 24
Peak memory 224188 kb
Host smart-54cc2dae-1727-48a0-81ae-bccde707e2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372914004 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.1372914004
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.2890146455
Short name T626
Test name
Test status
Simulation time 32491640 ps
CPU time 1.38 seconds
Started Aug 19 05:52:31 PM PDT 24
Finished Aug 19 05:52:32 PM PDT 24
Peak memory 217324 kb
Host smart-8901346f-aa91-4daf-b65d-38a7e9cdc5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890146455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.2890146455
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.2766223961
Short name T101
Test name
Test status
Simulation time 21559466 ps
CPU time 1.1 seconds
Started Aug 19 05:52:47 PM PDT 24
Finished Aug 19 05:52:48 PM PDT 24
Peak memory 216080 kb
Host smart-3edc0617-ba13-4a2b-9477-1919c5072c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766223961 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.2766223961
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.2997960974
Short name T480
Test name
Test status
Simulation time 29510105 ps
CPU time 0.95 seconds
Started Aug 19 05:52:34 PM PDT 24
Finished Aug 19 05:52:36 PM PDT 24
Peak memory 207188 kb
Host smart-6116eeab-a53d-4998-8248-85281d6b7bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997960974 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2997960974
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.921178676
Short name T549
Test name
Test status
Simulation time 23562186 ps
CPU time 0.93 seconds
Started Aug 19 05:52:32 PM PDT 24
Finished Aug 19 05:52:33 PM PDT 24
Peak memory 215408 kb
Host smart-dbc66c00-f584-4306-810f-e1431f10d512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921178676 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.921178676
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.1885274514
Short name T414
Test name
Test status
Simulation time 124466864 ps
CPU time 2.77 seconds
Started Aug 19 05:52:56 PM PDT 24
Finished Aug 19 05:52:59 PM PDT 24
Peak memory 215524 kb
Host smart-08e20f69-115d-43d9-8a1a-ede985289f88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885274514 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1885274514
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.3156483222
Short name T230
Test name
Test status
Simulation time 11297462905 ps
CPU time 129.31 seconds
Started Aug 19 05:52:30 PM PDT 24
Finished Aug 19 05:54:40 PM PDT 24
Peak memory 219296 kb
Host smart-75d847dd-2f8d-4277-b36c-40aa4ad5d794
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156483222 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.3156483222
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.796147077
Short name T906
Test name
Test status
Simulation time 28155671 ps
CPU time 1.27 seconds
Started Aug 19 05:53:28 PM PDT 24
Finished Aug 19 05:53:30 PM PDT 24
Peak memory 220260 kb
Host smart-d0fa0aa6-979a-43ae-9335-b339493c394f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796147077 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.796147077
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.4062448360
Short name T152
Test name
Test status
Simulation time 31497590 ps
CPU time 0.94 seconds
Started Aug 19 05:53:31 PM PDT 24
Finished Aug 19 05:53:32 PM PDT 24
Peak memory 219600 kb
Host smart-500c77a8-c716-4cb7-93ac-e9771c78a15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062448360 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.4062448360
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.707530096
Short name T317
Test name
Test status
Simulation time 37557346 ps
CPU time 1.37 seconds
Started Aug 19 05:53:35 PM PDT 24
Finished Aug 19 05:53:36 PM PDT 24
Peak memory 217400 kb
Host smart-95497bdb-b835-47a5-a1f2-ac067797611c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707530096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.707530096
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.1130627261
Short name T443
Test name
Test status
Simulation time 54339524 ps
CPU time 1.22 seconds
Started Aug 19 05:53:34 PM PDT 24
Finished Aug 19 05:53:36 PM PDT 24
Peak memory 219820 kb
Host smart-755461ac-d786-42b7-b6d8-8ecb8229a03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130627261 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.1130627261
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.3310766881
Short name T756
Test name
Test status
Simulation time 27137128 ps
CPU time 1.23 seconds
Started Aug 19 05:53:48 PM PDT 24
Finished Aug 19 05:53:50 PM PDT 24
Peak memory 217500 kb
Host smart-451f1986-7602-48df-a4d5-b487a068ece4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310766881 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.3310766881
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.89406587
Short name T304
Test name
Test status
Simulation time 219831187 ps
CPU time 1.75 seconds
Started Aug 19 05:53:36 PM PDT 24
Finished Aug 19 05:53:37 PM PDT 24
Peak memory 218780 kb
Host smart-3c21c5f1-ee61-4645-990a-8e750cce64fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89406587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.89406587
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.3309347272
Short name T788
Test name
Test status
Simulation time 33417196 ps
CPU time 1.31 seconds
Started Aug 19 05:53:36 PM PDT 24
Finished Aug 19 05:53:38 PM PDT 24
Peak memory 215904 kb
Host smart-159dab84-d084-471e-91bc-e04a5c189757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309347272 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.3309347272
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.3329735674
Short name T417
Test name
Test status
Simulation time 27887472 ps
CPU time 0.9 seconds
Started Aug 19 05:53:36 PM PDT 24
Finished Aug 19 05:53:37 PM PDT 24
Peak memory 218400 kb
Host smart-cae0db58-e785-48d2-8801-b66340543096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329735674 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3329735674
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.3873664135
Short name T533
Test name
Test status
Simulation time 46576575 ps
CPU time 1.19 seconds
Started Aug 19 05:53:35 PM PDT 24
Finished Aug 19 05:53:37 PM PDT 24
Peak memory 219704 kb
Host smart-3b08764a-e59b-4dfa-b279-650f1a2d27ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873664135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3873664135
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.186702894
Short name T141
Test name
Test status
Simulation time 45198219 ps
CPU time 1.15 seconds
Started Aug 19 05:53:41 PM PDT 24
Finished Aug 19 05:53:42 PM PDT 24
Peak memory 218664 kb
Host smart-eb8e080f-1363-4b1b-95b5-aa6d3cdac32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186702894 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.186702894
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.1490920098
Short name T861
Test name
Test status
Simulation time 84244738 ps
CPU time 1.05 seconds
Started Aug 19 05:53:34 PM PDT 24
Finished Aug 19 05:53:35 PM PDT 24
Peak memory 229880 kb
Host smart-75d9b6ba-f82e-4afc-acd9-5d95ef470bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490920098 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.1490920098
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/54.edn_alert.2781003020
Short name T10
Test name
Test status
Simulation time 24382498 ps
CPU time 1.23 seconds
Started Aug 19 05:53:49 PM PDT 24
Finished Aug 19 05:53:51 PM PDT 24
Peak memory 218812 kb
Host smart-2b2f2791-1a3d-4253-83b5-004b13e858eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781003020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.2781003020
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.1769812083
Short name T879
Test name
Test status
Simulation time 20952923 ps
CPU time 0.95 seconds
Started Aug 19 05:53:26 PM PDT 24
Finished Aug 19 05:53:27 PM PDT 24
Peak memory 218688 kb
Host smart-5d65e88b-ff5f-4e06-aa08-ec2677572458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769812083 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.1769812083
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.556987006
Short name T935
Test name
Test status
Simulation time 87192520 ps
CPU time 3.11 seconds
Started Aug 19 05:53:35 PM PDT 24
Finished Aug 19 05:53:38 PM PDT 24
Peak memory 220784 kb
Host smart-ccea15d6-dec4-4776-99e1-afc6b96ff791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556987006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.556987006
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.2816410758
Short name T151
Test name
Test status
Simulation time 87989033 ps
CPU time 1.16 seconds
Started Aug 19 05:53:42 PM PDT 24
Finished Aug 19 05:53:43 PM PDT 24
Peak memory 218572 kb
Host smart-26df100b-8a25-4e4f-b59f-41935472f072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816410758 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.2816410758
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.1673353569
Short name T123
Test name
Test status
Simulation time 137703738 ps
CPU time 0.96 seconds
Started Aug 19 05:53:41 PM PDT 24
Finished Aug 19 05:53:42 PM PDT 24
Peak memory 220800 kb
Host smart-7b9d8cd5-d269-4863-b75d-3a8585c67916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673353569 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.1673353569
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.3566478086
Short name T816
Test name
Test status
Simulation time 25692551 ps
CPU time 1.19 seconds
Started Aug 19 05:53:57 PM PDT 24
Finished Aug 19 05:53:58 PM PDT 24
Peak memory 217424 kb
Host smart-2ac662ae-3ec3-4fc1-b3a3-05fd24fc47f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566478086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3566478086
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.1352907385
Short name T916
Test name
Test status
Simulation time 22512916 ps
CPU time 1.24 seconds
Started Aug 19 05:53:36 PM PDT 24
Finished Aug 19 05:53:37 PM PDT 24
Peak memory 219696 kb
Host smart-a557d67b-0ba0-4fbf-add6-584a530fdb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352907385 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.1352907385
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.1763578998
Short name T792
Test name
Test status
Simulation time 35736646 ps
CPU time 0.86 seconds
Started Aug 19 05:53:36 PM PDT 24
Finished Aug 19 05:53:37 PM PDT 24
Peak memory 218224 kb
Host smart-6eaa5051-06de-4454-acc9-2dd57b792ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763578998 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1763578998
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.3818414450
Short name T455
Test name
Test status
Simulation time 48878361 ps
CPU time 1.36 seconds
Started Aug 19 05:53:36 PM PDT 24
Finished Aug 19 05:53:38 PM PDT 24
Peak memory 217504 kb
Host smart-f59f98c1-da1e-4d6f-a76d-f8102c02a98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818414450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.3818414450
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.114498381
Short name T956
Test name
Test status
Simulation time 24069445 ps
CPU time 1.19 seconds
Started Aug 19 05:53:53 PM PDT 24
Finished Aug 19 05:53:55 PM PDT 24
Peak memory 219520 kb
Host smart-4c1c16df-0a6f-4a34-b174-af7767d233b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114498381 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.114498381
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.191532916
Short name T161
Test name
Test status
Simulation time 28444795 ps
CPU time 1.32 seconds
Started Aug 19 05:53:46 PM PDT 24
Finished Aug 19 05:53:49 PM PDT 24
Peak memory 225788 kb
Host smart-2809a67a-f138-4cc6-9fd8-ec7a1cb42fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191532916 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.191532916
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.451805906
Short name T901
Test name
Test status
Simulation time 62865578 ps
CPU time 1.06 seconds
Started Aug 19 05:53:34 PM PDT 24
Finished Aug 19 05:53:35 PM PDT 24
Peak memory 217360 kb
Host smart-5850820e-2f81-4b64-b2c6-a80a0928e55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451805906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.451805906
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.85225643
Short name T137
Test name
Test status
Simulation time 31852104 ps
CPU time 1.3 seconds
Started Aug 19 05:53:32 PM PDT 24
Finished Aug 19 05:53:33 PM PDT 24
Peak memory 218812 kb
Host smart-dee140d5-2652-4cd2-86c1-c158d7833670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85225643 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.85225643
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_genbits.2852690732
Short name T604
Test name
Test status
Simulation time 60932657 ps
CPU time 1.37 seconds
Started Aug 19 05:53:23 PM PDT 24
Finished Aug 19 05:53:24 PM PDT 24
Peak memory 218812 kb
Host smart-7f3529bf-9e1d-49dc-80ab-c87aa91f4c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852690732 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.2852690732
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.3082317318
Short name T547
Test name
Test status
Simulation time 84606211 ps
CPU time 1.17 seconds
Started Aug 19 05:53:47 PM PDT 24
Finished Aug 19 05:53:48 PM PDT 24
Peak memory 220812 kb
Host smart-8ceb4e7d-04ba-4219-b431-c0367da7b1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082317318 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.3082317318
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_genbits.1167528806
Short name T42
Test name
Test status
Simulation time 60236607 ps
CPU time 1.27 seconds
Started Aug 19 05:53:42 PM PDT 24
Finished Aug 19 05:53:43 PM PDT 24
Peak memory 217720 kb
Host smart-aaa92474-f51c-4fcd-a2d4-71680cbc6f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167528806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.1167528806
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.1675391771
Short name T165
Test name
Test status
Simulation time 338090223 ps
CPU time 1.31 seconds
Started Aug 19 05:52:38 PM PDT 24
Finished Aug 19 05:52:39 PM PDT 24
Peak memory 220704 kb
Host smart-d2cf2ac9-ca0e-400a-81b8-f7eb3bb3223c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675391771 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.1675391771
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3472443448
Short name T664
Test name
Test status
Simulation time 15571994 ps
CPU time 0.95 seconds
Started Aug 19 05:52:29 PM PDT 24
Finished Aug 19 05:52:31 PM PDT 24
Peak memory 206792 kb
Host smart-bdbe6e25-96e5-45ad-98ca-10757f1d1607
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472443448 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3472443448
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.2124855019
Short name T163
Test name
Test status
Simulation time 33332038 ps
CPU time 0.91 seconds
Started Aug 19 05:52:38 PM PDT 24
Finished Aug 19 05:52:39 PM PDT 24
Peak memory 215408 kb
Host smart-9f18db30-2e8f-4bb4-9444-03ed8f07b2c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124855019 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2124855019
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.1352440369
Short name T90
Test name
Test status
Simulation time 98437442 ps
CPU time 1.21 seconds
Started Aug 19 05:52:36 PM PDT 24
Finished Aug 19 05:52:38 PM PDT 24
Peak memory 217156 kb
Host smart-be5e07ed-6b4d-4269-8c29-9568401c459c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352440369 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.1352440369
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.2756013180
Short name T171
Test name
Test status
Simulation time 21550044 ps
CPU time 0.97 seconds
Started Aug 19 05:52:31 PM PDT 24
Finished Aug 19 05:52:32 PM PDT 24
Peak memory 218692 kb
Host smart-adaf8bb4-a1a8-4ed2-91df-bd18b83f7f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756013180 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.2756013180
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.2639982541
Short name T424
Test name
Test status
Simulation time 124731993 ps
CPU time 2.81 seconds
Started Aug 19 05:52:30 PM PDT 24
Finished Aug 19 05:52:33 PM PDT 24
Peak memory 219584 kb
Host smart-9d277e27-07c9-42d3-b9e6-d35bac5e0f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639982541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.2639982541
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.994591098
Short name T657
Test name
Test status
Simulation time 37884357 ps
CPU time 0.9 seconds
Started Aug 19 05:52:32 PM PDT 24
Finished Aug 19 05:52:33 PM PDT 24
Peak memory 215728 kb
Host smart-39bbf332-c452-4a7c-9625-c268f1c94094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994591098 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.994591098
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.2328485767
Short name T436
Test name
Test status
Simulation time 63305647 ps
CPU time 0.98 seconds
Started Aug 19 05:52:42 PM PDT 24
Finished Aug 19 05:52:44 PM PDT 24
Peak memory 207196 kb
Host smart-7b44f049-9d36-4069-88ec-813d697dcde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328485767 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.2328485767
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.1979468174
Short name T392
Test name
Test status
Simulation time 16708969 ps
CPU time 1 seconds
Started Aug 19 05:52:35 PM PDT 24
Finished Aug 19 05:52:36 PM PDT 24
Peak memory 215396 kb
Host smart-cfb41d8b-8c61-4bbd-acad-ecd61b1f37b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979468174 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.1979468174
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.2737009189
Short name T496
Test name
Test status
Simulation time 70533957 ps
CPU time 0.97 seconds
Started Aug 19 05:52:34 PM PDT 24
Finished Aug 19 05:52:36 PM PDT 24
Peak memory 206608 kb
Host smart-40db74d0-e88e-43de-a441-aad9602eebf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737009189 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2737009189
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1445985780
Short name T110
Test name
Test status
Simulation time 4668610737 ps
CPU time 55.07 seconds
Started Aug 19 05:52:44 PM PDT 24
Finished Aug 19 05:53:39 PM PDT 24
Peak memory 218204 kb
Host smart-6da0a95e-35d7-4d6b-bac9-fe7a9a575bd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445985780 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1445985780
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_alert.428252182
Short name T481
Test name
Test status
Simulation time 59135686 ps
CPU time 1.11 seconds
Started Aug 19 05:53:35 PM PDT 24
Finished Aug 19 05:53:36 PM PDT 24
Peak memory 218856 kb
Host smart-0c84a81c-8378-4c17-88ff-454664961640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428252182 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.428252182
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.1199036981
Short name T144
Test name
Test status
Simulation time 26270126 ps
CPU time 1.25 seconds
Started Aug 19 05:53:28 PM PDT 24
Finished Aug 19 05:53:29 PM PDT 24
Peak memory 220732 kb
Host smart-8312b859-e7f9-4809-bd85-20b470ac6cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199036981 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1199036981
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.1014066807
Short name T80
Test name
Test status
Simulation time 64113368 ps
CPU time 1.66 seconds
Started Aug 19 05:53:40 PM PDT 24
Finished Aug 19 05:53:42 PM PDT 24
Peak memory 220736 kb
Host smart-6e56d083-6679-45ff-8a1d-7ce1286eb2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014066807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1014066807
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.1080289817
Short name T251
Test name
Test status
Simulation time 207383217 ps
CPU time 1.31 seconds
Started Aug 19 05:53:40 PM PDT 24
Finished Aug 19 05:53:42 PM PDT 24
Peak memory 215628 kb
Host smart-c5957326-ca47-49c8-9d5b-d2827fef71bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080289817 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.1080289817
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.3531727261
Short name T472
Test name
Test status
Simulation time 61588795 ps
CPU time 0.99 seconds
Started Aug 19 05:53:58 PM PDT 24
Finished Aug 19 05:53:59 PM PDT 24
Peak memory 223944 kb
Host smart-76848ed3-faab-40c8-92c6-198a906608fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531727261 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.3531727261
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.1649646339
Short name T570
Test name
Test status
Simulation time 226516651 ps
CPU time 1.67 seconds
Started Aug 19 05:53:35 PM PDT 24
Finished Aug 19 05:53:37 PM PDT 24
Peak memory 218984 kb
Host smart-c20e4516-0166-4836-b613-74dafc4875a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649646339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1649646339
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.2288919015
Short name T733
Test name
Test status
Simulation time 40914764 ps
CPU time 1.31 seconds
Started Aug 19 05:53:55 PM PDT 24
Finished Aug 19 05:53:57 PM PDT 24
Peak memory 219740 kb
Host smart-c792fbfc-3e6d-43c9-833d-9a2464e8ce09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288919015 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.2288919015
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.1808930400
Short name T149
Test name
Test status
Simulation time 135092115 ps
CPU time 1.34 seconds
Started Aug 19 05:53:45 PM PDT 24
Finished Aug 19 05:53:46 PM PDT 24
Peak memory 225804 kb
Host smart-9f6f2f30-518c-41f9-9a8e-fda36f061dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808930400 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1808930400
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.340254211
Short name T946
Test name
Test status
Simulation time 49244527 ps
CPU time 1.26 seconds
Started Aug 19 05:53:41 PM PDT 24
Finished Aug 19 05:53:42 PM PDT 24
Peak memory 218900 kb
Host smart-941a271f-c766-4b63-bf98-bcf39df33886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340254211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.340254211
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.3691892432
Short name T892
Test name
Test status
Simulation time 24136288 ps
CPU time 1.3 seconds
Started Aug 19 05:53:46 PM PDT 24
Finished Aug 19 05:53:47 PM PDT 24
Peak memory 220624 kb
Host smart-d340cb1d-04b7-43c0-ae1e-b50ba589abe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691892432 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.3691892432
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.1765810272
Short name T596
Test name
Test status
Simulation time 56788764 ps
CPU time 0.99 seconds
Started Aug 19 05:53:55 PM PDT 24
Finished Aug 19 05:53:56 PM PDT 24
Peak memory 223976 kb
Host smart-81e190f7-bfff-4eb8-a261-1a738d14b338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765810272 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1765810272
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.2040224046
Short name T345
Test name
Test status
Simulation time 37411695 ps
CPU time 1.5 seconds
Started Aug 19 05:53:58 PM PDT 24
Finished Aug 19 05:54:00 PM PDT 24
Peak memory 218516 kb
Host smart-8763b583-44c2-4476-9a7f-c41c061a0226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040224046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2040224046
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.794498222
Short name T169
Test name
Test status
Simulation time 21478486 ps
CPU time 1.05 seconds
Started Aug 19 05:53:57 PM PDT 24
Finished Aug 19 05:53:58 PM PDT 24
Peak memory 218500 kb
Host smart-7566368a-fa2d-4741-90a5-a55292d79e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794498222 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.794498222
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.657698104
Short name T13
Test name
Test status
Simulation time 457045155 ps
CPU time 1.52 seconds
Started Aug 19 05:54:00 PM PDT 24
Finished Aug 19 05:54:02 PM PDT 24
Peak memory 218732 kb
Host smart-5d6bc293-3d07-4c51-a633-4e233965c367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657698104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.657698104
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.4263501502
Short name T587
Test name
Test status
Simulation time 27143298 ps
CPU time 0.99 seconds
Started Aug 19 05:53:53 PM PDT 24
Finished Aug 19 05:53:54 PM PDT 24
Peak memory 223960 kb
Host smart-23d2eab0-b4fb-4956-b0db-94590602539d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263501502 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.4263501502
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.4114889547
Short name T650
Test name
Test status
Simulation time 36972628 ps
CPU time 1.34 seconds
Started Aug 19 05:53:35 PM PDT 24
Finished Aug 19 05:53:36 PM PDT 24
Peak memory 218584 kb
Host smart-2a93ffbd-adcb-4e8c-80bb-56d14ca9f480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114889547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.4114889547
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.1368220628
Short name T595
Test name
Test status
Simulation time 31633411 ps
CPU time 1.32 seconds
Started Aug 19 05:53:58 PM PDT 24
Finished Aug 19 05:54:00 PM PDT 24
Peak memory 215784 kb
Host smart-2a1a2a1a-03b4-49eb-bd79-a9a092031353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368220628 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.1368220628
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.611221283
Short name T320
Test name
Test status
Simulation time 19476290 ps
CPU time 1.14 seconds
Started Aug 19 05:53:40 PM PDT 24
Finished Aug 19 05:53:41 PM PDT 24
Peak memory 224120 kb
Host smart-08068a6f-9aa3-4e76-b900-faca69a16b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611221283 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.611221283
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.1307151953
Short name T952
Test name
Test status
Simulation time 78832691 ps
CPU time 1.14 seconds
Started Aug 19 05:53:59 PM PDT 24
Finished Aug 19 05:54:00 PM PDT 24
Peak memory 219384 kb
Host smart-1eac0aa1-6d02-4083-8999-dc995df49ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307151953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.1307151953
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.3438532032
Short name T724
Test name
Test status
Simulation time 160615354 ps
CPU time 1.25 seconds
Started Aug 19 05:53:45 PM PDT 24
Finished Aug 19 05:53:46 PM PDT 24
Peak memory 225060 kb
Host smart-8190b2e8-c99d-4a64-86b9-bf618dfbb272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438532032 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.3438532032
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.212232780
Short name T880
Test name
Test status
Simulation time 50390726 ps
CPU time 1.25 seconds
Started Aug 19 05:53:47 PM PDT 24
Finished Aug 19 05:53:48 PM PDT 24
Peak memory 219912 kb
Host smart-85ccf33b-08f8-4793-a484-c4663257dec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212232780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.212232780
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.1122372873
Short name T593
Test name
Test status
Simulation time 71307152 ps
CPU time 1.13 seconds
Started Aug 19 05:53:49 PM PDT 24
Finished Aug 19 05:53:51 PM PDT 24
Peak memory 219948 kb
Host smart-d5962e61-9121-42b5-8210-2e4d83d07338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122372873 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.1122372873
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.877890111
Short name T645
Test name
Test status
Simulation time 18238372 ps
CPU time 1.06 seconds
Started Aug 19 05:53:43 PM PDT 24
Finished Aug 19 05:53:44 PM PDT 24
Peak memory 218296 kb
Host smart-84fb0b77-b145-46f7-bd5e-97c75b068019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877890111 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.877890111
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.3355963567
Short name T877
Test name
Test status
Simulation time 66986651 ps
CPU time 1.16 seconds
Started Aug 19 05:53:42 PM PDT 24
Finished Aug 19 05:53:43 PM PDT 24
Peak memory 217688 kb
Host smart-db809507-ab7a-42b5-9810-7671b264fc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355963567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.3355963567
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.854791101
Short name T376
Test name
Test status
Simulation time 23128589 ps
CPU time 1.16 seconds
Started Aug 19 05:53:53 PM PDT 24
Finished Aug 19 05:53:54 PM PDT 24
Peak memory 218632 kb
Host smart-f5713576-a296-4333-b169-920511399a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854791101 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.854791101
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.624139571
Short name T198
Test name
Test status
Simulation time 25179852 ps
CPU time 0.93 seconds
Started Aug 19 05:53:43 PM PDT 24
Finished Aug 19 05:53:44 PM PDT 24
Peak memory 219540 kb
Host smart-1b21d5db-18f8-4c9a-a4b3-1855e3381457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624139571 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.624139571
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.2013496851
Short name T818
Test name
Test status
Simulation time 284937894 ps
CPU time 4.21 seconds
Started Aug 19 05:53:37 PM PDT 24
Finished Aug 19 05:53:41 PM PDT 24
Peak memory 219064 kb
Host smart-08645336-d819-4358-bfb3-80ae7d90c740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013496851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.2013496851
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.1781989869
Short name T638
Test name
Test status
Simulation time 25667610 ps
CPU time 1.25 seconds
Started Aug 19 05:52:42 PM PDT 24
Finished Aug 19 05:52:43 PM PDT 24
Peak memory 220164 kb
Host smart-b6204a2d-cb18-4ee8-9494-10a2ecc217c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781989869 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1781989869
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.972593337
Short name T65
Test name
Test status
Simulation time 15525560 ps
CPU time 0.95 seconds
Started Aug 19 05:52:32 PM PDT 24
Finished Aug 19 05:52:33 PM PDT 24
Peak memory 206772 kb
Host smart-33695b38-2b3d-4163-9600-f02b858f6637
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972593337 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.972593337
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.3942502752
Short name T9
Test name
Test status
Simulation time 31444019 ps
CPU time 1.15 seconds
Started Aug 19 05:52:31 PM PDT 24
Finished Aug 19 05:52:32 PM PDT 24
Peak memory 218220 kb
Host smart-711a341c-27ee-4f44-8043-4d3610429f9d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942502752 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.3942502752
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.2976826427
Short name T209
Test name
Test status
Simulation time 22113235 ps
CPU time 0.95 seconds
Started Aug 19 05:52:36 PM PDT 24
Finished Aug 19 05:52:37 PM PDT 24
Peak memory 218652 kb
Host smart-6e4d1ec4-e4a6-4c93-a5ec-52b3abc9f539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976826427 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.2976826427
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_intr.3190400814
Short name T917
Test name
Test status
Simulation time 28291833 ps
CPU time 0.9 seconds
Started Aug 19 05:52:37 PM PDT 24
Finished Aug 19 05:52:43 PM PDT 24
Peak memory 215940 kb
Host smart-1c0f9c24-decd-457c-af31-0a15be55414a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190400814 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.3190400814
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.2640192805
Short name T364
Test name
Test status
Simulation time 22068449 ps
CPU time 1.01 seconds
Started Aug 19 05:52:31 PM PDT 24
Finished Aug 19 05:52:32 PM PDT 24
Peak memory 207176 kb
Host smart-8fcaeb01-63b6-4b10-8fff-90e355761ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640192805 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.2640192805
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.2350342007
Short name T942
Test name
Test status
Simulation time 33321920 ps
CPU time 0.99 seconds
Started Aug 19 05:52:42 PM PDT 24
Finished Aug 19 05:52:44 PM PDT 24
Peak memory 215408 kb
Host smart-6f3cb716-892e-4615-bf44-ce688d6389f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350342007 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.2350342007
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.3454064812
Short name T545
Test name
Test status
Simulation time 173382530 ps
CPU time 1.07 seconds
Started Aug 19 05:52:30 PM PDT 24
Finished Aug 19 05:52:31 PM PDT 24
Peak memory 217264 kb
Host smart-48878229-e83a-40af-9162-c22081f39314
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454064812 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.3454064812
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/70.edn_alert.1414214065
Short name T612
Test name
Test status
Simulation time 25784118 ps
CPU time 1.22 seconds
Started Aug 19 05:53:44 PM PDT 24
Finished Aug 19 05:53:45 PM PDT 24
Peak memory 218792 kb
Host smart-2cccd378-e650-4963-8204-6b19d035ee52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414214065 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.1414214065
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.833224468
Short name T677
Test name
Test status
Simulation time 22483575 ps
CPU time 0.94 seconds
Started Aug 19 05:53:38 PM PDT 24
Finished Aug 19 05:53:39 PM PDT 24
Peak memory 218460 kb
Host smart-d3fba326-e0ec-4e1c-b21b-c4f01fcc485f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833224468 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.833224468
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.3315570177
Short name T774
Test name
Test status
Simulation time 109937960 ps
CPU time 1.13 seconds
Started Aug 19 05:53:50 PM PDT 24
Finished Aug 19 05:53:51 PM PDT 24
Peak memory 217520 kb
Host smart-ebeb44f0-3c71-4ae7-a4ef-b551a79118cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315570177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3315570177
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.4213734609
Short name T291
Test name
Test status
Simulation time 25329797 ps
CPU time 1.29 seconds
Started Aug 19 05:53:38 PM PDT 24
Finished Aug 19 05:53:40 PM PDT 24
Peak memory 219676 kb
Host smart-5b460d46-17b2-42d4-8759-3c3a52225fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213734609 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.4213734609
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.4132629319
Short name T672
Test name
Test status
Simulation time 23194532 ps
CPU time 1.37 seconds
Started Aug 19 05:54:02 PM PDT 24
Finished Aug 19 05:54:04 PM PDT 24
Peak memory 224184 kb
Host smart-8c09f960-991f-41ab-a5b7-c5769e1e16d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132629319 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.4132629319
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.883740151
Short name T325
Test name
Test status
Simulation time 61275569 ps
CPU time 1.37 seconds
Started Aug 19 05:54:10 PM PDT 24
Finished Aug 19 05:54:11 PM PDT 24
Peak memory 219616 kb
Host smart-782436a6-1a8f-4686-a44b-fdf78b394fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883740151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.883740151
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.826192388
Short name T686
Test name
Test status
Simulation time 194799629 ps
CPU time 1.23 seconds
Started Aug 19 05:53:43 PM PDT 24
Finished Aug 19 05:53:44 PM PDT 24
Peak memory 219812 kb
Host smart-43e74540-9d4c-444f-9bb7-373f5c271c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826192388 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.826192388
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.4268039741
Short name T179
Test name
Test status
Simulation time 35102576 ps
CPU time 0.91 seconds
Started Aug 19 05:53:44 PM PDT 24
Finished Aug 19 05:53:45 PM PDT 24
Peak memory 218404 kb
Host smart-de294690-df8a-48da-a240-1c1b588fcaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268039741 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.4268039741
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.1898386331
Short name T550
Test name
Test status
Simulation time 84896009 ps
CPU time 1.38 seconds
Started Aug 19 05:54:02 PM PDT 24
Finished Aug 19 05:54:03 PM PDT 24
Peak memory 218632 kb
Host smart-fab5bad5-9cc4-4cae-8f36-d312e1a63535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898386331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.1898386331
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.500240067
Short name T634
Test name
Test status
Simulation time 209274595 ps
CPU time 1.17 seconds
Started Aug 19 05:53:44 PM PDT 24
Finished Aug 19 05:53:45 PM PDT 24
Peak memory 219712 kb
Host smart-a4eb4ecd-8232-47f0-bbc8-a7c626a1aff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500240067 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.500240067
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.3128490654
Short name T103
Test name
Test status
Simulation time 25362965 ps
CPU time 1.21 seconds
Started Aug 19 05:53:36 PM PDT 24
Finished Aug 19 05:53:38 PM PDT 24
Peak memory 218516 kb
Host smart-ce6fab81-61b5-4024-8bf8-92302093889b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128490654 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.3128490654
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.3146290642
Short name T297
Test name
Test status
Simulation time 97546528 ps
CPU time 1.59 seconds
Started Aug 19 05:54:01 PM PDT 24
Finished Aug 19 05:54:03 PM PDT 24
Peak memory 218896 kb
Host smart-fe77eaf3-f369-45d0-b3d6-1c772da361d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146290642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.3146290642
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.15757999
Short name T653
Test name
Test status
Simulation time 42157859 ps
CPU time 1.3 seconds
Started Aug 19 05:53:50 PM PDT 24
Finished Aug 19 05:53:51 PM PDT 24
Peak memory 215688 kb
Host smart-ae059833-e99e-4bd1-8a8a-fad6b2a8eb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15757999 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.15757999
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.1971873837
Short name T681
Test name
Test status
Simulation time 48774597 ps
CPU time 1.56 seconds
Started Aug 19 05:53:46 PM PDT 24
Finished Aug 19 05:53:47 PM PDT 24
Peak memory 218696 kb
Host smart-674ebd70-9693-4cad-99b3-8007e26d6cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971873837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.1971873837
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.4153387476
Short name T579
Test name
Test status
Simulation time 102992165 ps
CPU time 1.19 seconds
Started Aug 19 05:53:35 PM PDT 24
Finished Aug 19 05:53:36 PM PDT 24
Peak memory 218608 kb
Host smart-cbc9e991-095a-4ff1-88fc-00ebf161f1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153387476 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.4153387476
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.3789162723
Short name T968
Test name
Test status
Simulation time 111498585 ps
CPU time 0.96 seconds
Started Aug 19 05:53:49 PM PDT 24
Finished Aug 19 05:53:50 PM PDT 24
Peak memory 218712 kb
Host smart-f0cdb9fa-f953-4d97-a88c-b553a8c244f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789162723 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3789162723
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.3162944628
Short name T884
Test name
Test status
Simulation time 47041990 ps
CPU time 1.53 seconds
Started Aug 19 05:53:48 PM PDT 24
Finished Aug 19 05:53:50 PM PDT 24
Peak memory 218816 kb
Host smart-6616dfa7-61f0-4799-9a4d-c262146503fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162944628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.3162944628
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.1582236055
Short name T23
Test name
Test status
Simulation time 46520730 ps
CPU time 1.19 seconds
Started Aug 19 05:53:41 PM PDT 24
Finished Aug 19 05:53:43 PM PDT 24
Peak memory 219180 kb
Host smart-87974d68-e978-4fd4-a19f-3914ddbe3a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582236055 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.1582236055
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.2893258665
Short name T16
Test name
Test status
Simulation time 18990903 ps
CPU time 1.04 seconds
Started Aug 19 05:53:48 PM PDT 24
Finished Aug 19 05:53:49 PM PDT 24
Peak memory 224136 kb
Host smart-9866c024-30c7-4b2e-8054-bd2eac60f41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893258665 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2893258665
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.3271661038
Short name T569
Test name
Test status
Simulation time 42024094 ps
CPU time 1.46 seconds
Started Aug 19 05:53:52 PM PDT 24
Finished Aug 19 05:53:54 PM PDT 24
Peak memory 217652 kb
Host smart-c43e519f-2678-4f9b-b317-1e0e21b7c4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271661038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3271661038
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.2851499331
Short name T513
Test name
Test status
Simulation time 62321765 ps
CPU time 1.06 seconds
Started Aug 19 05:53:53 PM PDT 24
Finished Aug 19 05:53:54 PM PDT 24
Peak memory 218592 kb
Host smart-9c61c8a2-253b-4d80-9729-c6a4864bb5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851499331 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.2851499331
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.506680474
Short name T69
Test name
Test status
Simulation time 22166424 ps
CPU time 0.93 seconds
Started Aug 19 05:53:53 PM PDT 24
Finished Aug 19 05:53:54 PM PDT 24
Peak memory 218176 kb
Host smart-a78e3247-226e-4f9e-8514-0f58327927f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506680474 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.506680474
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.597309390
Short name T977
Test name
Test status
Simulation time 208835667 ps
CPU time 0.98 seconds
Started Aug 19 05:53:46 PM PDT 24
Finished Aug 19 05:53:47 PM PDT 24
Peak memory 217108 kb
Host smart-0aae4373-cda0-4cdd-b6a3-b2dc0f99a3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597309390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.597309390
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.3949308766
Short name T248
Test name
Test status
Simulation time 93196253 ps
CPU time 1.18 seconds
Started Aug 19 05:54:06 PM PDT 24
Finished Aug 19 05:54:07 PM PDT 24
Peak memory 218560 kb
Host smart-c28e1295-5eb6-4d9a-9487-e11a7de8774d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949308766 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.3949308766
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.322636308
Short name T187
Test name
Test status
Simulation time 20577410 ps
CPU time 1.24 seconds
Started Aug 19 05:54:03 PM PDT 24
Finished Aug 19 05:54:04 PM PDT 24
Peak memory 224144 kb
Host smart-c0ae3677-6ef8-413e-ad2e-d41f76861ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322636308 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.322636308
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.1498693064
Short name T372
Test name
Test status
Simulation time 39739954 ps
CPU time 1.77 seconds
Started Aug 19 05:53:59 PM PDT 24
Finished Aug 19 05:54:01 PM PDT 24
Peak memory 218596 kb
Host smart-998d2d63-200c-4b8e-b1cf-a860668c8a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498693064 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.1498693064
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.2907999200
Short name T81
Test name
Test status
Simulation time 73389126 ps
CPU time 1.17 seconds
Started Aug 19 05:53:51 PM PDT 24
Finished Aug 19 05:53:53 PM PDT 24
Peak memory 218852 kb
Host smart-dea6b388-a916-44df-8b7c-eb9ec8e07f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907999200 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.2907999200
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.2340181317
Short name T416
Test name
Test status
Simulation time 26247487 ps
CPU time 0.94 seconds
Started Aug 19 05:53:46 PM PDT 24
Finished Aug 19 05:53:48 PM PDT 24
Peak memory 218256 kb
Host smart-34590830-683f-49ba-8bd2-01549725ca27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340181317 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.2340181317
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.2420114783
Short name T422
Test name
Test status
Simulation time 49094650 ps
CPU time 1.13 seconds
Started Aug 19 05:54:04 PM PDT 24
Finished Aug 19 05:54:05 PM PDT 24
Peak memory 217564 kb
Host smart-c58990d4-7791-4767-8ebc-184b1c9fe387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420114783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.2420114783
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.3864790044
Short name T726
Test name
Test status
Simulation time 264041970 ps
CPU time 1.21 seconds
Started Aug 19 05:52:52 PM PDT 24
Finished Aug 19 05:52:53 PM PDT 24
Peak memory 218572 kb
Host smart-a04cc28f-f7b7-4741-a648-5dde7009411b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864790044 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3864790044
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.3794630158
Short name T394
Test name
Test status
Simulation time 30313385 ps
CPU time 0.8 seconds
Started Aug 19 05:52:39 PM PDT 24
Finished Aug 19 05:52:40 PM PDT 24
Peak memory 206484 kb
Host smart-3c230b64-fdb4-4417-b66e-9da7b3d1a135
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794630158 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3794630158
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.4249492015
Short name T170
Test name
Test status
Simulation time 19270827 ps
CPU time 0.85 seconds
Started Aug 19 05:52:47 PM PDT 24
Finished Aug 19 05:52:48 PM PDT 24
Peak memory 215440 kb
Host smart-de883efc-e2f7-4477-838a-1ca88c9ebf55
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249492015 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.4249492015
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.2008752317
Short name T501
Test name
Test status
Simulation time 34530765 ps
CPU time 1.18 seconds
Started Aug 19 05:52:46 PM PDT 24
Finished Aug 19 05:52:47 PM PDT 24
Peak memory 218716 kb
Host smart-57c6346f-2a2b-4a5b-a909-5c6b70070536
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008752317 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.2008752317
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.1732372227
Short name T34
Test name
Test status
Simulation time 28759933 ps
CPU time 0.88 seconds
Started Aug 19 05:52:50 PM PDT 24
Finished Aug 19 05:52:51 PM PDT 24
Peak memory 219540 kb
Host smart-4478f491-4683-4c11-bf35-80a54f76534d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732372227 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.1732372227
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_intr.1451193513
Short name T98
Test name
Test status
Simulation time 21467843 ps
CPU time 1.07 seconds
Started Aug 19 05:52:35 PM PDT 24
Finished Aug 19 05:52:37 PM PDT 24
Peak memory 215936 kb
Host smart-8c2c2d81-2860-47b8-a56a-8381caa141f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451193513 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.1451193513
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.2561961257
Short name T825
Test name
Test status
Simulation time 84189468 ps
CPU time 0.89 seconds
Started Aug 19 05:52:34 PM PDT 24
Finished Aug 19 05:52:35 PM PDT 24
Peak memory 207212 kb
Host smart-107831a0-b6fc-4d9b-9e64-2e573efc26d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561961257 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.2561961257
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.155449588
Short name T319
Test name
Test status
Simulation time 18252872 ps
CPU time 0.99 seconds
Started Aug 19 05:52:33 PM PDT 24
Finished Aug 19 05:52:34 PM PDT 24
Peak memory 207196 kb
Host smart-11544384-0727-441d-b2a7-af4e4a9be326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155449588 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.155449588
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.1792909312
Short name T651
Test name
Test status
Simulation time 191765224 ps
CPU time 2.32 seconds
Started Aug 19 05:52:33 PM PDT 24
Finished Aug 19 05:52:35 PM PDT 24
Peak memory 219924 kb
Host smart-0e714081-3cb1-46bf-9e60-ca3fd374f527
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792909312 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.1792909312
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/80.edn_alert.2207575346
Short name T527
Test name
Test status
Simulation time 37853442 ps
CPU time 1.08 seconds
Started Aug 19 05:53:52 PM PDT 24
Finished Aug 19 05:53:53 PM PDT 24
Peak memory 219872 kb
Host smart-f01fb93a-abc5-4a31-a1fd-39638f305e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207575346 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.2207575346
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.194253157
Short name T728
Test name
Test status
Simulation time 35849625 ps
CPU time 0.88 seconds
Started Aug 19 05:53:56 PM PDT 24
Finished Aug 19 05:53:57 PM PDT 24
Peak memory 219268 kb
Host smart-f517664e-9798-43c4-81d4-445a71a4ffe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194253157 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.194253157
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.3515907770
Short name T306
Test name
Test status
Simulation time 46228326 ps
CPU time 1.27 seconds
Started Aug 19 05:54:13 PM PDT 24
Finished Aug 19 05:54:14 PM PDT 24
Peak memory 220272 kb
Host smart-14d5f546-a6f4-45a6-a962-984d984fe8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515907770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.3515907770
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.2655380156
Short name T779
Test name
Test status
Simulation time 53238426 ps
CPU time 1.18 seconds
Started Aug 19 05:53:56 PM PDT 24
Finished Aug 19 05:53:57 PM PDT 24
Peak memory 219420 kb
Host smart-3eedf9d0-87d2-4057-8c92-59928786be48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655380156 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.2655380156
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.1737274605
Short name T199
Test name
Test status
Simulation time 19839778 ps
CPU time 1.06 seconds
Started Aug 19 05:53:55 PM PDT 24
Finished Aug 19 05:53:56 PM PDT 24
Peak memory 219492 kb
Host smart-658855b6-2558-4f6c-9486-44a7e0fc9ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737274605 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.1737274605
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.3197912393
Short name T794
Test name
Test status
Simulation time 86470060 ps
CPU time 1.2 seconds
Started Aug 19 05:53:53 PM PDT 24
Finished Aug 19 05:53:54 PM PDT 24
Peak memory 217340 kb
Host smart-50bb4310-0076-4db0-91d1-ea7cde9ad4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197912393 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3197912393
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.3469071197
Short name T145
Test name
Test status
Simulation time 41512491 ps
CPU time 1.19 seconds
Started Aug 19 05:54:03 PM PDT 24
Finished Aug 19 05:54:04 PM PDT 24
Peak memory 219820 kb
Host smart-5e29dc69-0c25-4f8f-9da2-db38f4ba8668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469071197 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.3469071197
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.2920574093
Short name T168
Test name
Test status
Simulation time 21980497 ps
CPU time 0.94 seconds
Started Aug 19 05:53:44 PM PDT 24
Finished Aug 19 05:53:45 PM PDT 24
Peak memory 218600 kb
Host smart-45f5d84d-923d-4497-a10c-f2212ad175c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920574093 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.2920574093
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.203502058
Short name T931
Test name
Test status
Simulation time 217671110 ps
CPU time 1.32 seconds
Started Aug 19 05:53:57 PM PDT 24
Finished Aug 19 05:53:58 PM PDT 24
Peak memory 219056 kb
Host smart-d1a5fde3-32fa-47b6-8c12-bb8a17ae6df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203502058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.203502058
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.1158920757
Short name T548
Test name
Test status
Simulation time 44166965 ps
CPU time 1.2 seconds
Started Aug 19 05:54:02 PM PDT 24
Finished Aug 19 05:54:03 PM PDT 24
Peak memory 219716 kb
Host smart-6b4c799f-7c78-4cbb-9852-18b9e2f5fb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158920757 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.1158920757
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.7361334
Short name T734
Test name
Test status
Simulation time 22129332 ps
CPU time 1.23 seconds
Started Aug 19 05:53:59 PM PDT 24
Finished Aug 19 05:54:00 PM PDT 24
Peak memory 224192 kb
Host smart-de557024-dd02-4f4f-823d-3b0c17ea7878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7361334 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.7361334
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.1295827869
Short name T459
Test name
Test status
Simulation time 62517127 ps
CPU time 1.61 seconds
Started Aug 19 05:53:51 PM PDT 24
Finished Aug 19 05:53:53 PM PDT 24
Peak memory 218852 kb
Host smart-423b72e9-c3ed-4f92-a0e4-5837bce85415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295827869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.1295827869
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.4057127363
Short name T474
Test name
Test status
Simulation time 48259856 ps
CPU time 1.25 seconds
Started Aug 19 05:54:12 PM PDT 24
Finished Aug 19 05:54:14 PM PDT 24
Peak memory 219500 kb
Host smart-320be28a-07cf-4e18-a56b-4384549e6d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057127363 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.4057127363
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.2240998657
Short name T121
Test name
Test status
Simulation time 72669944 ps
CPU time 0.99 seconds
Started Aug 19 05:54:03 PM PDT 24
Finished Aug 19 05:54:04 PM PDT 24
Peak memory 219924 kb
Host smart-692a6b88-548b-49fc-bfd3-1b23dc250d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240998657 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.2240998657
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.334718610
Short name T701
Test name
Test status
Simulation time 34683412 ps
CPU time 1.04 seconds
Started Aug 19 05:54:10 PM PDT 24
Finished Aug 19 05:54:11 PM PDT 24
Peak memory 217408 kb
Host smart-a052c770-b648-49c3-8d77-f4e213bbbd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334718610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.334718610
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.812007450
Short name T159
Test name
Test status
Simulation time 40155010 ps
CPU time 1.18 seconds
Started Aug 19 05:53:54 PM PDT 24
Finished Aug 19 05:53:55 PM PDT 24
Peak memory 218724 kb
Host smart-c5fa3043-34e7-4b7e-bba3-baed5009c846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812007450 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.812007450
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.2686755509
Short name T8
Test name
Test status
Simulation time 239563911 ps
CPU time 1.26 seconds
Started Aug 19 05:53:56 PM PDT 24
Finished Aug 19 05:53:57 PM PDT 24
Peak memory 219752 kb
Host smart-9d035a58-457f-4b20-9646-52cb55106e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686755509 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.2686755509
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.3800896908
Short name T628
Test name
Test status
Simulation time 113458716 ps
CPU time 2.51 seconds
Started Aug 19 05:53:47 PM PDT 24
Finished Aug 19 05:53:50 PM PDT 24
Peak memory 220636 kb
Host smart-76c7a1c9-93b4-40e5-b30e-4e8543768dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800896908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3800896908
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.3032525540
Short name T586
Test name
Test status
Simulation time 78164737 ps
CPU time 1.2 seconds
Started Aug 19 05:53:56 PM PDT 24
Finished Aug 19 05:53:57 PM PDT 24
Peak memory 219536 kb
Host smart-5076ca63-c984-4561-a58e-39c7a6747f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032525540 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.3032525540
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.2646475217
Short name T153
Test name
Test status
Simulation time 52753203 ps
CPU time 1.06 seconds
Started Aug 19 05:53:56 PM PDT 24
Finished Aug 19 05:53:58 PM PDT 24
Peak memory 220876 kb
Host smart-4355460d-efcf-413e-aa6f-c83059367ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646475217 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2646475217
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.3419748222
Short name T688
Test name
Test status
Simulation time 79754458 ps
CPU time 1.17 seconds
Started Aug 19 05:54:06 PM PDT 24
Finished Aug 19 05:54:07 PM PDT 24
Peak memory 219496 kb
Host smart-0cf20d26-7800-44fa-824d-fdbb3c3daf68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419748222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3419748222
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.1611201134
Short name T840
Test name
Test status
Simulation time 31863141 ps
CPU time 1.14 seconds
Started Aug 19 05:54:13 PM PDT 24
Finished Aug 19 05:54:14 PM PDT 24
Peak memory 218448 kb
Host smart-f34b4812-91d1-4ccd-af4e-589e8e6f57e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611201134 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.1611201134
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.3955318124
Short name T885
Test name
Test status
Simulation time 36105697 ps
CPU time 0.97 seconds
Started Aug 19 05:53:54 PM PDT 24
Finished Aug 19 05:53:55 PM PDT 24
Peak memory 229600 kb
Host smart-ba668c94-7c92-4169-97fe-2c46d936bcd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955318124 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3955318124
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.2047819345
Short name T849
Test name
Test status
Simulation time 268458931 ps
CPU time 2.96 seconds
Started Aug 19 05:54:01 PM PDT 24
Finished Aug 19 05:54:04 PM PDT 24
Peak memory 220024 kb
Host smart-70934cf6-936e-45f1-a4d3-17526e9f84d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047819345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2047819345
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.3745444161
Short name T185
Test name
Test status
Simulation time 49218476 ps
CPU time 1.2 seconds
Started Aug 19 05:53:53 PM PDT 24
Finished Aug 19 05:53:54 PM PDT 24
Peak memory 219736 kb
Host smart-2992b072-ef49-4ec0-b1a4-c3c20559d39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745444161 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.3745444161
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.2757571057
Short name T752
Test name
Test status
Simulation time 149186347 ps
CPU time 1.01 seconds
Started Aug 19 05:53:43 PM PDT 24
Finished Aug 19 05:53:44 PM PDT 24
Peak memory 219780 kb
Host smart-0ffc3a11-5d13-49c2-b94f-0995ad4d5569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757571057 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.2757571057
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.257610634
Short name T974
Test name
Test status
Simulation time 34183709 ps
CPU time 1.37 seconds
Started Aug 19 05:53:55 PM PDT 24
Finished Aug 19 05:53:57 PM PDT 24
Peak memory 218752 kb
Host smart-0cd2df44-e969-4685-88ed-69cf5da70dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257610634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.257610634
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.3012835556
Short name T146
Test name
Test status
Simulation time 79696087 ps
CPU time 1.24 seconds
Started Aug 19 05:54:02 PM PDT 24
Finished Aug 19 05:54:03 PM PDT 24
Peak memory 218864 kb
Host smart-62e64393-bb5c-48fb-8a69-fb3f75a5021a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012835556 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.3012835556
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.1879933965
Short name T189
Test name
Test status
Simulation time 18339660 ps
CPU time 1.13 seconds
Started Aug 19 05:54:04 PM PDT 24
Finished Aug 19 05:54:05 PM PDT 24
Peak memory 224148 kb
Host smart-63c74dba-d578-4b09-a247-a251c63de9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879933965 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.1879933965
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.857617654
Short name T385
Test name
Test status
Simulation time 67290624 ps
CPU time 1.61 seconds
Started Aug 19 05:53:53 PM PDT 24
Finished Aug 19 05:53:54 PM PDT 24
Peak memory 218564 kb
Host smart-f3ad04a9-e414-4b3a-a456-d8becfd73a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857617654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.857617654
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.594770555
Short name T113
Test name
Test status
Simulation time 66433362 ps
CPU time 1.16 seconds
Started Aug 19 05:53:14 PM PDT 24
Finished Aug 19 05:53:15 PM PDT 24
Peak memory 220656 kb
Host smart-81860d65-27af-4bbe-96b5-28ce3a1766c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594770555 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.594770555
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.256324829
Short name T926
Test name
Test status
Simulation time 127091179 ps
CPU time 0.86 seconds
Started Aug 19 05:52:55 PM PDT 24
Finished Aug 19 05:52:56 PM PDT 24
Peak memory 206684 kb
Host smart-fbd550ce-eec4-4120-a5fa-b1d15a58c86c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256324829 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.256324829
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.320947579
Short name T178
Test name
Test status
Simulation time 19844263 ps
CPU time 0.88 seconds
Started Aug 19 05:52:53 PM PDT 24
Finished Aug 19 05:52:54 PM PDT 24
Peak memory 215504 kb
Host smart-86acf37c-433c-47bd-a38a-ebcaaeb8790e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320947579 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.320947579
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.4087762887
Short name T449
Test name
Test status
Simulation time 79764793 ps
CPU time 1.08 seconds
Started Aug 19 05:52:51 PM PDT 24
Finished Aug 19 05:52:53 PM PDT 24
Peak memory 215632 kb
Host smart-e77c3406-7ea1-49b1-adfd-b16934f73272
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087762887 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.4087762887
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.2211349697
Short name T850
Test name
Test status
Simulation time 45384989 ps
CPU time 1.12 seconds
Started Aug 19 05:52:47 PM PDT 24
Finished Aug 19 05:52:49 PM PDT 24
Peak memory 219672 kb
Host smart-d382ffb4-8d76-44f4-87d9-db0a5a6161aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211349697 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.2211349697
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.3989293323
Short name T881
Test name
Test status
Simulation time 24282632 ps
CPU time 1.26 seconds
Started Aug 19 05:52:48 PM PDT 24
Finished Aug 19 05:52:50 PM PDT 24
Peak memory 217604 kb
Host smart-6119b486-bbfd-48cc-97fc-ac92769797f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989293323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.3989293323
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.1490877534
Short name T819
Test name
Test status
Simulation time 26617187 ps
CPU time 0.84 seconds
Started Aug 19 05:52:37 PM PDT 24
Finished Aug 19 05:52:38 PM PDT 24
Peak memory 215776 kb
Host smart-ae42d4ae-620e-4bc1-99c5-5e25e699e9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490877534 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.1490877534
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.3710802949
Short name T646
Test name
Test status
Simulation time 30502148 ps
CPU time 0.92 seconds
Started Aug 19 05:52:47 PM PDT 24
Finished Aug 19 05:52:48 PM PDT 24
Peak memory 207208 kb
Host smart-489ab8d8-18d5-44ec-a7de-6b8db205a799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710802949 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.3710802949
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.4074190807
Short name T930
Test name
Test status
Simulation time 66494500 ps
CPU time 0.94 seconds
Started Aug 19 05:52:49 PM PDT 24
Finished Aug 19 05:52:56 PM PDT 24
Peak memory 215396 kb
Host smart-99cf562b-a74a-41f6-9486-ff636297977b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074190807 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.4074190807
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1821285482
Short name T823
Test name
Test status
Simulation time 34987479 ps
CPU time 1.03 seconds
Started Aug 19 05:52:41 PM PDT 24
Finished Aug 19 05:52:42 PM PDT 24
Peak memory 215392 kb
Host smart-941e14f2-f8b3-4581-b19f-c041b21842f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821285482 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1821285482
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/90.edn_alert.2691793714
Short name T835
Test name
Test status
Simulation time 105898276 ps
CPU time 1.21 seconds
Started Aug 19 05:53:55 PM PDT 24
Finished Aug 19 05:53:57 PM PDT 24
Peak memory 218548 kb
Host smart-941d139a-3001-4ed2-8841-5a4441afaef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691793714 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.2691793714
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.3624257730
Short name T175
Test name
Test status
Simulation time 35274275 ps
CPU time 1.34 seconds
Started Aug 19 05:54:10 PM PDT 24
Finished Aug 19 05:54:12 PM PDT 24
Peak memory 225808 kb
Host smart-d44dff02-84c7-4c26-ac23-1c2cbf392e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624257730 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3624257730
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.329336662
Short name T358
Test name
Test status
Simulation time 128902577 ps
CPU time 1.22 seconds
Started Aug 19 05:54:02 PM PDT 24
Finished Aug 19 05:54:03 PM PDT 24
Peak memory 217608 kb
Host smart-3e4445f3-6707-4780-a4a0-f08e7ad83382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329336662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.329336662
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.3386762676
Short name T623
Test name
Test status
Simulation time 37612450 ps
CPU time 1.08 seconds
Started Aug 19 05:53:52 PM PDT 24
Finished Aug 19 05:53:53 PM PDT 24
Peak memory 218856 kb
Host smart-47fda609-2577-4bb2-8d57-35108199c2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386762676 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.3386762676
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.4274458868
Short name T205
Test name
Test status
Simulation time 38255007 ps
CPU time 1.13 seconds
Started Aug 19 05:53:56 PM PDT 24
Finished Aug 19 05:53:57 PM PDT 24
Peak memory 220824 kb
Host smart-7504009a-9688-410d-94ef-cb384ac5f52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274458868 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.4274458868
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.510956225
Short name T859
Test name
Test status
Simulation time 161872504 ps
CPU time 2.21 seconds
Started Aug 19 05:53:59 PM PDT 24
Finished Aug 19 05:54:01 PM PDT 24
Peak memory 217492 kb
Host smart-5b54d298-4484-42c6-bf73-04b24ac73400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510956225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.510956225
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.2492422598
Short name T132
Test name
Test status
Simulation time 78390044 ps
CPU time 1.02 seconds
Started Aug 19 05:53:58 PM PDT 24
Finished Aug 19 05:53:59 PM PDT 24
Peak memory 220836 kb
Host smart-836fb844-d05a-47e7-a49b-3776f734d47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492422598 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.2492422598
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.2891736682
Short name T543
Test name
Test status
Simulation time 75621706 ps
CPU time 1.25 seconds
Started Aug 19 05:54:03 PM PDT 24
Finished Aug 19 05:54:04 PM PDT 24
Peak memory 217460 kb
Host smart-f9346f1d-d6b2-4338-8cca-e02a7dd1877b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891736682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.2891736682
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.101230802
Short name T912
Test name
Test status
Simulation time 18830168 ps
CPU time 1.04 seconds
Started Aug 19 05:54:01 PM PDT 24
Finished Aug 19 05:54:02 PM PDT 24
Peak memory 218552 kb
Host smart-0f95fabb-df27-41d7-bacb-3ebd64b1ee15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101230802 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.101230802
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.3170982035
Short name T642
Test name
Test status
Simulation time 66203415 ps
CPU time 1.45 seconds
Started Aug 19 05:54:02 PM PDT 24
Finished Aug 19 05:54:03 PM PDT 24
Peak memory 217372 kb
Host smart-44c6b723-82e7-4031-a99f-719aec70952e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170982035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.3170982035
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.2387416898
Short name T872
Test name
Test status
Simulation time 51021548 ps
CPU time 1.21 seconds
Started Aug 19 05:54:05 PM PDT 24
Finished Aug 19 05:54:07 PM PDT 24
Peak memory 225776 kb
Host smart-f33c52a1-689f-40e1-8fec-e8e966e09e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387416898 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.2387416898
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.2582931318
Short name T311
Test name
Test status
Simulation time 83765894 ps
CPU time 1.25 seconds
Started Aug 19 05:54:04 PM PDT 24
Finished Aug 19 05:54:05 PM PDT 24
Peak memory 215496 kb
Host smart-976e8e42-7140-4fa1-88fb-310681a21e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582931318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2582931318
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.3333664684
Short name T656
Test name
Test status
Simulation time 110514655 ps
CPU time 1.35 seconds
Started Aug 19 05:54:07 PM PDT 24
Finished Aug 19 05:54:09 PM PDT 24
Peak memory 215788 kb
Host smart-80aae9ea-6705-4e4a-867e-c49126e0c24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333664684 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.3333664684
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.4228710174
Short name T140
Test name
Test status
Simulation time 29278916 ps
CPU time 0.96 seconds
Started Aug 19 05:53:49 PM PDT 24
Finished Aug 19 05:53:50 PM PDT 24
Peak memory 219764 kb
Host smart-e382b7f2-a7af-4224-8ecb-0b3b238a4323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228710174 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.4228710174
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.1660657032
Short name T349
Test name
Test status
Simulation time 46490280 ps
CPU time 1.5 seconds
Started Aug 19 05:53:52 PM PDT 24
Finished Aug 19 05:53:54 PM PDT 24
Peak memory 219672 kb
Host smart-b2d78151-105d-4f13-ae6e-289e37900f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660657032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.1660657032
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.1855231142
Short name T249
Test name
Test status
Simulation time 29949608 ps
CPU time 1.27 seconds
Started Aug 19 05:54:05 PM PDT 24
Finished Aug 19 05:54:06 PM PDT 24
Peak memory 220084 kb
Host smart-c2017113-0890-44d0-a483-31f81a767b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855231142 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.1855231142
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.1374842369
Short name T802
Test name
Test status
Simulation time 28461631 ps
CPU time 0.92 seconds
Started Aug 19 05:54:10 PM PDT 24
Finished Aug 19 05:54:11 PM PDT 24
Peak memory 218224 kb
Host smart-4632ab51-e15d-42f7-ab16-8e76aa067d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374842369 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1374842369
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.1063598864
Short name T403
Test name
Test status
Simulation time 82705786 ps
CPU time 1.45 seconds
Started Aug 19 05:53:59 PM PDT 24
Finished Aug 19 05:54:00 PM PDT 24
Peak memory 218908 kb
Host smart-1a0ac241-af77-44ba-beae-c7a7a25c80d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063598864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.1063598864
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.1187664798
Short name T854
Test name
Test status
Simulation time 94173530 ps
CPU time 1.25 seconds
Started Aug 19 05:54:02 PM PDT 24
Finished Aug 19 05:54:03 PM PDT 24
Peak memory 220860 kb
Host smart-75313198-e747-4ca5-9a2e-311fbc277449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187664798 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.1187664798
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.225358682
Short name T213
Test name
Test status
Simulation time 26610799 ps
CPU time 1.34 seconds
Started Aug 19 05:54:04 PM PDT 24
Finished Aug 19 05:54:05 PM PDT 24
Peak memory 229796 kb
Host smart-adea12b4-4ae8-4ef6-808b-4d346879bdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225358682 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.225358682
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.2345636300
Short name T552
Test name
Test status
Simulation time 370538337 ps
CPU time 3.74 seconds
Started Aug 19 05:54:09 PM PDT 24
Finished Aug 19 05:54:12 PM PDT 24
Peak memory 220156 kb
Host smart-923c5d7a-530c-4b88-9431-efb94d73140e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345636300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2345636300
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.2382506231
Short name T939
Test name
Test status
Simulation time 43853149 ps
CPU time 1.13 seconds
Started Aug 19 05:54:14 PM PDT 24
Finished Aug 19 05:54:15 PM PDT 24
Peak memory 218504 kb
Host smart-e1de07e9-3990-4461-a1b3-4f916c2540fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382506231 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.2382506231
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.1768723789
Short name T514
Test name
Test status
Simulation time 28815067 ps
CPU time 0.98 seconds
Started Aug 19 05:53:57 PM PDT 24
Finished Aug 19 05:53:58 PM PDT 24
Peak memory 223952 kb
Host smart-c98e7b5a-2ccf-41c3-81b4-ee48ac83a047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768723789 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1768723789
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2408124681
Short name T453
Test name
Test status
Simulation time 48079318 ps
CPU time 1.57 seconds
Started Aug 19 05:54:17 PM PDT 24
Finished Aug 19 05:54:18 PM PDT 24
Peak memory 218548 kb
Host smart-06d92c4c-c72e-43f4-85d9-92da390ae7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408124681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2408124681
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.2970166335
Short name T166
Test name
Test status
Simulation time 25770824 ps
CPU time 1.37 seconds
Started Aug 19 05:54:14 PM PDT 24
Finished Aug 19 05:54:16 PM PDT 24
Peak memory 220964 kb
Host smart-fe057423-1f62-43e6-b0f8-fe00c0c1bf3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970166335 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.2970166335
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.3267414441
Short name T691
Test name
Test status
Simulation time 23744140 ps
CPU time 0.95 seconds
Started Aug 19 05:54:12 PM PDT 24
Finished Aug 19 05:54:13 PM PDT 24
Peak memory 219624 kb
Host smart-74d6aa90-ea59-4c68-8c6d-b22505fbaba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267414441 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3267414441
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.3348422451
Short name T541
Test name
Test status
Simulation time 270288465 ps
CPU time 2.2 seconds
Started Aug 19 05:54:09 PM PDT 24
Finished Aug 19 05:54:12 PM PDT 24
Peak memory 219564 kb
Host smart-e04aeb37-8e8d-4a10-9b4e-258c150bb6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348422451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3348422451
Directory /workspace/99.edn_genbits/latest
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