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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.99 98.25 93.97 97.02 93.02 96.37 99.77 93.56


Total test records in report: 1111
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T277 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_rw.3546349746 Aug 21 06:02:55 PM UTC 24 Aug 21 06:02:57 PM UTC 24 16662371 ps
T1006 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.641200103 Aug 21 06:02:54 PM UTC 24 Aug 21 06:02:57 PM UTC 24 32310217 ps
T1007 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_bit_bash.3689720291 Aug 21 06:02:49 PM UTC 24 Aug 21 06:02:57 PM UTC 24 179012254 ps
T1008 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_errors.3437634860 Aug 21 06:02:53 PM UTC 24 Aug 21 06:02:58 PM UTC 24 260170079 ps
T1009 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/7.edn_same_csr_outstanding.1109770580 Aug 21 06:02:56 PM UTC 24 Aug 21 06:02:58 PM UTC 24 84032670 ps
T1010 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3355097827 Aug 21 06:02:56 PM UTC 24 Aug 21 06:02:58 PM UTC 24 38518585 ps
T1011 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_errors.2303191726 Aug 21 06:02:54 PM UTC 24 Aug 21 06:02:58 PM UTC 24 240260664 ps
T304 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_intg_err.1762853970 Aug 21 06:02:54 PM UTC 24 Aug 21 06:02:59 PM UTC 24 85176388 ps
T1012 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/8.edn_intr_test.2567080309 Aug 21 06:02:57 PM UTC 24 Aug 21 06:02:59 PM UTC 24 50208255 ps
T1013 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_rw.1527428691 Aug 21 06:02:57 PM UTC 24 Aug 21 06:02:59 PM UTC 24 25817860 ps
T1014 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_errors.2850602785 Aug 21 06:02:56 PM UTC 24 Aug 21 06:02:59 PM UTC 24 361691161 ps
T302 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_intg_err.996664178 Aug 21 06:02:54 PM UTC 24 Aug 21 06:02:59 PM UTC 24 158853657 ps
T1015 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/9.edn_intr_test.3048195215 Aug 21 06:02:58 PM UTC 24 Aug 21 06:03:00 PM UTC 24 22578660 ps
T1016 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1097802485 Aug 21 06:02:58 PM UTC 24 Aug 21 06:03:00 PM UTC 24 15937074 ps
T1017 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/8.edn_same_csr_outstanding.2242754598 Aug 21 06:02:58 PM UTC 24 Aug 21 06:03:01 PM UTC 24 31543047 ps
T300 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_intg_err.97337573 Aug 21 06:02:57 PM UTC 24 Aug 21 06:03:01 PM UTC 24 315842181 ps
T1018 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/10.edn_intr_test.432330927 Aug 21 06:03:00 PM UTC 24 Aug 21 06:03:02 PM UTC 24 38586780 ps
T1019 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_rw.1973875095 Aug 21 06:02:59 PM UTC 24 Aug 21 06:03:02 PM UTC 24 17195458 ps
T301 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_intg_err.2080770381 Aug 21 06:02:58 PM UTC 24 Aug 21 06:03:02 PM UTC 24 125990530 ps
T1020 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_rw.1949746863 Aug 21 06:03:00 PM UTC 24 Aug 21 06:03:02 PM UTC 24 50563504 ps
T1021 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2575076958 Aug 21 06:03:00 PM UTC 24 Aug 21 06:03:02 PM UTC 24 51321102 ps
T1022 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/9.edn_same_csr_outstanding.1043777593 Aug 21 06:02:59 PM UTC 24 Aug 21 06:03:02 PM UTC 24 18846794 ps
T1023 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/10.edn_same_csr_outstanding.1306048464 Aug 21 06:03:00 PM UTC 24 Aug 21 06:03:02 PM UTC 24 255617140 ps
T1024 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3269166840 Aug 21 06:03:00 PM UTC 24 Aug 21 06:03:03 PM UTC 24 194788117 ps
T1025 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_rw.3770053028 Aug 21 06:03:01 PM UTC 24 Aug 21 06:03:03 PM UTC 24 21500080 ps
T1026 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_errors.3609089158 Aug 21 06:02:58 PM UTC 24 Aug 21 06:03:03 PM UTC 24 206792323 ps
T1027 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/11.edn_intr_test.1986451687 Aug 21 06:03:01 PM UTC 24 Aug 21 06:03:03 PM UTC 24 15197360 ps
T1028 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_intg_err.1409058747 Aug 21 06:03:00 PM UTC 24 Aug 21 06:03:03 PM UTC 24 68677492 ps
T1029 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_intg_err.4019177305 Aug 21 06:03:01 PM UTC 24 Aug 21 06:03:04 PM UTC 24 60209115 ps
T1030 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/12.edn_intr_test.4223183779 Aug 21 06:03:02 PM UTC 24 Aug 21 06:03:05 PM UTC 24 32311241 ps
T1031 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/11.edn_same_csr_outstanding.1448026673 Aug 21 06:03:02 PM UTC 24 Aug 21 06:03:05 PM UTC 24 15921021 ps
T1032 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_errors.983227894 Aug 21 06:03:01 PM UTC 24 Aug 21 06:03:05 PM UTC 24 170922701 ps
T1033 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_rw.1063884069 Aug 21 06:03:02 PM UTC 24 Aug 21 06:03:05 PM UTC 24 12193965 ps
T1034 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_errors.725101235 Aug 21 06:03:00 PM UTC 24 Aug 21 06:03:05 PM UTC 24 480317842 ps
T1035 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/12.edn_same_csr_outstanding.4190537233 Aug 21 06:03:03 PM UTC 24 Aug 21 06:03:05 PM UTC 24 26026360 ps
T1036 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.978284989 Aug 21 06:03:02 PM UTC 24 Aug 21 06:03:05 PM UTC 24 91550183 ps
T1037 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_intg_err.683704946 Aug 21 06:03:02 PM UTC 24 Aug 21 06:03:06 PM UTC 24 45583799 ps
T1038 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_errors.499466502 Aug 21 06:03:02 PM UTC 24 Aug 21 06:03:06 PM UTC 24 230225184 ps
T1039 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_rw.2737796064 Aug 21 06:03:04 PM UTC 24 Aug 21 06:03:06 PM UTC 24 25554016 ps
T1040 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/13.edn_intr_test.4181613118 Aug 21 06:03:04 PM UTC 24 Aug 21 06:03:07 PM UTC 24 16588557 ps
T1041 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.793523200 Aug 21 06:03:04 PM UTC 24 Aug 21 06:03:07 PM UTC 24 18874274 ps
T1042 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2291068397 Aug 21 06:03:04 PM UTC 24 Aug 21 06:03:07 PM UTC 24 88363820 ps
T1043 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/13.edn_same_csr_outstanding.3936828369 Aug 21 06:03:04 PM UTC 24 Aug 21 06:03:07 PM UTC 24 37927051 ps
T1044 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/14.edn_intr_test.1625201105 Aug 21 06:03:06 PM UTC 24 Aug 21 06:03:08 PM UTC 24 13541983 ps
T1045 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_rw.3684332102 Aug 21 06:03:06 PM UTC 24 Aug 21 06:03:08 PM UTC 24 58670402 ps
T1046 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_intg_err.3278045083 Aug 21 06:03:04 PM UTC 24 Aug 21 06:03:08 PM UTC 24 181923703 ps
T1047 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/15.edn_intr_test.1106163444 Aug 21 06:03:06 PM UTC 24 Aug 21 06:03:08 PM UTC 24 83622216 ps
T1048 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_errors.4001034187 Aug 21 06:03:04 PM UTC 24 Aug 21 06:03:08 PM UTC 24 58354926 ps
T1049 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/14.edn_same_csr_outstanding.724306948 Aug 21 06:03:06 PM UTC 24 Aug 21 06:03:08 PM UTC 24 19296675 ps
T1050 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.520009646 Aug 21 06:03:06 PM UTC 24 Aug 21 06:03:08 PM UTC 24 26666875 ps
T1051 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_intg_err.670442228 Aug 21 06:03:06 PM UTC 24 Aug 21 06:03:08 PM UTC 24 176273776 ps
T1052 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_errors.2873708810 Aug 21 06:03:04 PM UTC 24 Aug 21 06:03:09 PM UTC 24 38660009 ps
T1053 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_rw.1514763063 Aug 21 06:03:07 PM UTC 24 Aug 21 06:03:09 PM UTC 24 27522873 ps
T1054 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/15.edn_same_csr_outstanding.4000326280 Aug 21 06:03:07 PM UTC 24 Aug 21 06:03:09 PM UTC 24 61626885 ps
T1055 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_intg_err.1342368264 Aug 21 06:03:06 PM UTC 24 Aug 21 06:03:10 PM UTC 24 470590325 ps
T1056 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2523361262 Aug 21 06:03:07 PM UTC 24 Aug 21 06:03:10 PM UTC 24 241764307 ps
T1057 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_errors.217637117 Aug 21 06:03:07 PM UTC 24 Aug 21 06:03:10 PM UTC 24 58888095 ps
T1058 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_intg_err.2602963232 Aug 21 06:03:07 PM UTC 24 Aug 21 06:03:11 PM UTC 24 944671447 ps
T1059 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/16.edn_intr_test.3168200364 Aug 21 06:03:08 PM UTC 24 Aug 21 06:03:11 PM UTC 24 16731803 ps
T1060 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_rw.609673788 Aug 21 06:03:08 PM UTC 24 Aug 21 06:03:11 PM UTC 24 43814363 ps
T1061 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/17.edn_intr_test.2740068710 Aug 21 06:03:09 PM UTC 24 Aug 21 06:03:11 PM UTC 24 13803639 ps
T1062 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/16.edn_same_csr_outstanding.575718030 Aug 21 06:03:09 PM UTC 24 Aug 21 06:03:11 PM UTC 24 158379471 ps
T1063 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_errors.2413599095 Aug 21 06:03:06 PM UTC 24 Aug 21 06:03:11 PM UTC 24 294268118 ps
T1064 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.269489475 Aug 21 06:03:09 PM UTC 24 Aug 21 06:03:11 PM UTC 24 26710118 ps
T1065 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_intg_err.2698116970 Aug 21 06:03:09 PM UTC 24 Aug 21 06:03:12 PM UTC 24 185086193 ps
T1066 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_rw.2270017069 Aug 21 06:03:10 PM UTC 24 Aug 21 06:03:12 PM UTC 24 19974039 ps
T1067 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_rw.3633561725 Aug 21 06:03:10 PM UTC 24 Aug 21 06:03:13 PM UTC 24 15101041 ps
T1068 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3271675962 Aug 21 06:03:10 PM UTC 24 Aug 21 06:03:13 PM UTC 24 44607630 ps
T1069 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/18.edn_intr_test.3501104097 Aug 21 06:03:10 PM UTC 24 Aug 21 06:03:13 PM UTC 24 260206113 ps
T1070 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/18.edn_same_csr_outstanding.179516474 Aug 21 06:03:10 PM UTC 24 Aug 21 06:03:13 PM UTC 24 22393793 ps
T1071 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/17.edn_same_csr_outstanding.2620017992 Aug 21 06:03:10 PM UTC 24 Aug 21 06:03:13 PM UTC 24 77860114 ps
T1072 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_intg_err.1826710338 Aug 21 06:03:10 PM UTC 24 Aug 21 06:03:14 PM UTC 24 51714510 ps
T1073 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/19.edn_intr_test.3564144087 Aug 21 06:03:12 PM UTC 24 Aug 21 06:03:14 PM UTC 24 38891262 ps
T1074 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_rw.1691963125 Aug 21 06:03:12 PM UTC 24 Aug 21 06:03:14 PM UTC 24 36815205 ps
T1075 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/20.edn_intr_test.643383086 Aug 21 06:03:12 PM UTC 24 Aug 21 06:03:14 PM UTC 24 13815823 ps
T1076 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/21.edn_intr_test.520264235 Aug 21 06:03:12 PM UTC 24 Aug 21 06:03:14 PM UTC 24 19687933 ps
T1077 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3442048998 Aug 21 06:03:12 PM UTC 24 Aug 21 06:03:14 PM UTC 24 61324134 ps
T1078 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_errors.3693547987 Aug 21 06:03:09 PM UTC 24 Aug 21 06:03:14 PM UTC 24 394611774 ps
T1079 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/19.edn_same_csr_outstanding.2606461549 Aug 21 06:03:12 PM UTC 24 Aug 21 06:03:14 PM UTC 24 35489259 ps
T1080 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_errors.217516567 Aug 21 06:03:10 PM UTC 24 Aug 21 06:03:15 PM UTC 24 82456139 ps
T1081 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_intg_err.2048335062 Aug 21 06:03:12 PM UTC 24 Aug 21 06:03:15 PM UTC 24 71395319 ps
T1082 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1649665243 Aug 21 06:03:12 PM UTC 24 Aug 21 06:03:15 PM UTC 24 30899152 ps
T1083 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/22.edn_intr_test.3438986752 Aug 21 06:03:13 PM UTC 24 Aug 21 06:03:15 PM UTC 24 23763853 ps
T1084 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/26.edn_intr_test.4258514573 Aug 21 06:03:13 PM UTC 24 Aug 21 06:03:15 PM UTC 24 40937208 ps
T1085 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/27.edn_intr_test.849476996 Aug 21 06:03:13 PM UTC 24 Aug 21 06:03:15 PM UTC 24 18662511 ps
T1086 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/23.edn_intr_test.3188751202 Aug 21 06:03:13 PM UTC 24 Aug 21 06:03:16 PM UTC 24 26789652 ps
T1087 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/24.edn_intr_test.3608558215 Aug 21 06:03:13 PM UTC 24 Aug 21 06:03:16 PM UTC 24 47960965 ps
T1088 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/25.edn_intr_test.1788018695 Aug 21 06:03:13 PM UTC 24 Aug 21 06:03:16 PM UTC 24 12371603 ps
T1089 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/29.edn_intr_test.2181752154 Aug 21 06:03:15 PM UTC 24 Aug 21 06:03:16 PM UTC 24 13057928 ps
T1090 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_errors.1215908803 Aug 21 06:03:12 PM UTC 24 Aug 21 06:03:16 PM UTC 24 50670448 ps
T1091 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/28.edn_intr_test.3879204948 Aug 21 06:03:15 PM UTC 24 Aug 21 06:03:17 PM UTC 24 24389861 ps
T1092 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/30.edn_intr_test.2016877298 Aug 21 06:03:15 PM UTC 24 Aug 21 06:03:17 PM UTC 24 15991517 ps
T1093 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/31.edn_intr_test.3714508109 Aug 21 06:03:15 PM UTC 24 Aug 21 06:03:17 PM UTC 24 36766228 ps
T1094 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/32.edn_intr_test.4165295010 Aug 21 06:03:16 PM UTC 24 Aug 21 06:03:18 PM UTC 24 16220939 ps
T1095 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/36.edn_intr_test.3987553195 Aug 21 06:03:16 PM UTC 24 Aug 21 06:03:18 PM UTC 24 16047321 ps
T1096 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/33.edn_intr_test.3987726764 Aug 21 06:03:16 PM UTC 24 Aug 21 06:03:19 PM UTC 24 21321707 ps
T1097 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/35.edn_intr_test.1399781447 Aug 21 06:03:16 PM UTC 24 Aug 21 06:03:19 PM UTC 24 33346298 ps
T1098 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/34.edn_intr_test.4104171452 Aug 21 06:03:16 PM UTC 24 Aug 21 06:03:19 PM UTC 24 25412787 ps
T1099 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/42.edn_intr_test.740918656 Aug 21 06:03:17 PM UTC 24 Aug 21 06:03:19 PM UTC 24 31170279 ps
T1100 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/38.edn_intr_test.136661875 Aug 21 06:03:16 PM UTC 24 Aug 21 06:03:19 PM UTC 24 11466391 ps
T1101 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/37.edn_intr_test.1807636142 Aug 21 06:03:16 PM UTC 24 Aug 21 06:03:19 PM UTC 24 162185681 ps
T1102 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/43.edn_intr_test.3774854391 Aug 21 06:03:17 PM UTC 24 Aug 21 06:03:19 PM UTC 24 14434623 ps
T1103 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/44.edn_intr_test.3228500882 Aug 21 06:03:17 PM UTC 24 Aug 21 06:03:19 PM UTC 24 23485895 ps
T1104 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/40.edn_intr_test.1024002030 Aug 21 06:03:17 PM UTC 24 Aug 21 06:03:19 PM UTC 24 16085574 ps
T1105 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/39.edn_intr_test.598237371 Aug 21 06:03:17 PM UTC 24 Aug 21 06:03:19 PM UTC 24 43589563 ps
T1106 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/41.edn_intr_test.2065839545 Aug 21 06:03:17 PM UTC 24 Aug 21 06:03:19 PM UTC 24 29229898 ps
T1107 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/45.edn_intr_test.791039475 Aug 21 06:03:17 PM UTC 24 Aug 21 06:03:19 PM UTC 24 17115354 ps
T1108 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/46.edn_intr_test.3145121229 Aug 21 06:03:18 PM UTC 24 Aug 21 06:03:20 PM UTC 24 38243419 ps
T1109 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/49.edn_intr_test.1089449189 Aug 21 06:03:18 PM UTC 24 Aug 21 06:03:20 PM UTC 24 21520541 ps
T1110 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/48.edn_intr_test.1088196079 Aug 21 06:03:18 PM UTC 24 Aug 21 06:03:20 PM UTC 24 62188680 ps
T1111 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/47.edn_intr_test.1088171122 Aug 21 06:03:18 PM UTC 24 Aug 21 06:03:20 PM UTC 24 15710083 ps

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/0.edn_alert.3373290299
Short name T17
Test name
Test status
Simulation time 150987114 ps
CPU time 1.27 seconds
Started Aug 21 08:50:14 AM UTC 24
Finished Aug 21 08:50:16 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3373290299 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3373290299
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/0.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/4.edn_genbits.1014887424
Short name T13
Test name
Test status
Simulation time 64881757 ps
CPU time 1.8 seconds
Started Aug 21 08:50:24 AM UTC 24
Finished Aug 21 08:50:26 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1014887424 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1014887424
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/4.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/0.edn_sec_cm.1122814226
Short name T18
Test name
Test status
Simulation time 2254806834 ps
CPU time 9.66 seconds
Started Aug 21 08:50:15 AM UTC 24
Finished Aug 21 08:50:26 AM UTC 24
Peak memory 260636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1122814226 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1122814226
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/0.edn_sec_cm/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/0.edn_disable_auto_req_mode.3378617
Short name T10
Test name
Test status
Simulation time 164592511 ps
CPU time 1.4 seconds
Started Aug 21 08:50:15 AM UTC 24
Finished Aug 21 08:50:18 AM UTC 24
Peak memory 226264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3378617 -assert nopo
stproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable
_auto_req_mode.3378617
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/0.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/1.edn_stress_all.2537724416
Short name T59
Test name
Test status
Simulation time 180249502 ps
CPU time 3.66 seconds
Started Aug 21 08:50:17 AM UTC 24
Finished Aug 21 08:50:22 AM UTC 24
Peak memory 229580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2537724416 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2537724416
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/1.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/0.edn_stress_all_with_rand_reset.2294364546
Short name T37
Test name
Test status
Simulation time 3549227526 ps
CPU time 40.51 seconds
Started Aug 21 08:50:14 AM UTC 24
Finished Aug 21 08:50:56 AM UTC 24
Peak memory 234492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2294364546 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2294364546
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/2.edn_alert.2483529324
Short name T30
Test name
Test status
Simulation time 25602869 ps
CPU time 1.59 seconds
Started Aug 21 08:50:20 AM UTC 24
Finished Aug 21 08:50:22 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2483529324 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2483529324
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/2.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/1.edn_regwen.498197780
Short name T27
Test name
Test status
Simulation time 165837223 ps
CPU time 1.2 seconds
Started Aug 21 08:50:15 AM UTC 24
Finished Aug 21 08:50:18 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=498197780 -assert nopostproc +UVM_TESTNAME=ed
n_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.498197780
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/1.edn_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/3.edn_alert.443310421
Short name T109
Test name
Test status
Simulation time 96049619 ps
CPU time 1.41 seconds
Started Aug 21 08:50:22 AM UTC 24
Finished Aug 21 08:50:25 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=443310421 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.443310421
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/3.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/5.edn_genbits.3185236938
Short name T43
Test name
Test status
Simulation time 38271787 ps
CPU time 1.61 seconds
Started Aug 21 08:50:27 AM UTC 24
Finished Aug 21 08:50:30 AM UTC 24
Peak memory 230688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3185236938 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3185236938
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/5.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/0.edn_disable.3822807184
Short name T24
Test name
Test status
Simulation time 14048832 ps
CPU time 1.05 seconds
Started Aug 21 08:50:15 AM UTC 24
Finished Aug 21 08:50:17 AM UTC 24
Peak memory 216136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3822807184 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3822807184
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/0.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/34.edn_alert.3694653957
Short name T172
Test name
Test status
Simulation time 27362107 ps
CPU time 1.71 seconds
Started Aug 21 08:51:52 AM UTC 24
Finished Aug 21 08:51:55 AM UTC 24
Peak memory 228436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3694653957 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.3694653957
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/34.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/7.edn_stress_all.2683610611
Short name T116
Test name
Test status
Simulation time 201202123 ps
CPU time 3.76 seconds
Started Aug 21 08:50:32 AM UTC 24
Finished Aug 21 08:50:37 AM UTC 24
Peak memory 227672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2683610611 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.2683610611
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/7.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/5.edn_stress_all.1600098511
Short name T128
Test name
Test status
Simulation time 335482936 ps
CPU time 4.06 seconds
Started Aug 21 08:50:27 AM UTC 24
Finished Aug 21 08:50:32 AM UTC 24
Peak memory 229584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1600098511 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1600098511
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/5.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/0.edn_err.2823686765
Short name T5
Test name
Test status
Simulation time 27243202 ps
CPU time 1.05 seconds
Started Aug 21 08:50:15 AM UTC 24
Finished Aug 21 08:50:17 AM UTC 24
Peak memory 236964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2823686765 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2823686765
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/0.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/8.edn_alert.4173556271
Short name T58
Test name
Test status
Simulation time 27990174 ps
CPU time 1.69 seconds
Started Aug 21 08:50:35 AM UTC 24
Finished Aug 21 08:50:37 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4173556271 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.4173556271
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/8.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/14.edn_disable_auto_req_mode.3193645302
Short name T115
Test name
Test status
Simulation time 172499031 ps
CPU time 1.35 seconds
Started Aug 21 08:50:47 AM UTC 24
Finished Aug 21 08:50:50 AM UTC 24
Peak memory 226264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3193645302 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_dis
able_auto_req_mode.3193645302
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/14.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/24.edn_disable.351061496
Short name T106
Test name
Test status
Simulation time 38776745 ps
CPU time 1.22 seconds
Started Aug 21 08:51:19 AM UTC 24
Finished Aug 21 08:51:21 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=351061496 -assert no
postproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o
pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.351061496
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/24.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/2.edn_tl_intg_err.2658478997
Short name T289
Test name
Test status
Simulation time 299556419 ps
CPU time 3.26 seconds
Started Aug 21 06:02:41 PM UTC 24
Finished Aug 21 06:02:45 PM UTC 24
Peak memory 217524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2658478997 -
assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.2658478997
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/2.edn_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/5.edn_disable.1874032991
Short name T98
Test name
Test status
Simulation time 16414600 ps
CPU time 1.18 seconds
Started Aug 21 08:50:29 AM UTC 24
Finished Aug 21 08:50:31 AM UTC 24
Peak memory 226360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1874032991 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1874032991
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/5.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_rw.1657452164
Short name T263
Test name
Test status
Simulation time 19503352 ps
CPU time 1.27 seconds
Started Aug 21 06:02:36 PM UTC 24
Finished Aug 21 06:02:38 PM UTC 24
Peak memory 215344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1657452164 -assert no
postproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1657452164
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/0.edn_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/15.edn_disable_auto_req_mode.2613670745
Short name T95
Test name
Test status
Simulation time 149418168 ps
CPU time 1.55 seconds
Started Aug 21 08:50:51 AM UTC 24
Finished Aug 21 08:50:53 AM UTC 24
Peak memory 226264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2613670745 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_dis
able_auto_req_mode.2613670745
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/15.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/3.edn_disable_auto_req_mode.2784738169
Short name T55
Test name
Test status
Simulation time 128432856 ps
CPU time 1.24 seconds
Started Aug 21 08:50:22 AM UTC 24
Finished Aug 21 08:50:25 AM UTC 24
Peak memory 226264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2784738169 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disa
ble_auto_req_mode.2784738169
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/3.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/16.edn_genbits.3148422959
Short name T297
Test name
Test status
Simulation time 155352105 ps
CPU time 1.67 seconds
Started Aug 21 08:50:51 AM UTC 24
Finished Aug 21 08:50:54 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3148422959 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.3148422959
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/16.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/33.edn_genbits.3217556267
Short name T329
Test name
Test status
Simulation time 35104732 ps
CPU time 1.25 seconds
Started Aug 21 08:51:49 AM UTC 24
Finished Aug 21 08:51:51 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3217556267 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3217556267
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/33.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/61.edn_alert.4155793958
Short name T135
Test name
Test status
Simulation time 23181217 ps
CPU time 1.75 seconds
Started Aug 21 08:52:56 AM UTC 24
Finished Aug 21 08:52:59 AM UTC 24
Peak memory 230484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4155793958 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.4155793958
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/61.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/6.edn_disable.3644854715
Short name T99
Test name
Test status
Simulation time 11136210 ps
CPU time 1.14 seconds
Started Aug 21 08:50:32 AM UTC 24
Finished Aug 21 08:50:34 AM UTC 24
Peak memory 216136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3644854715 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.3644854715
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/6.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/13.edn_alert.4170007695
Short name T197
Test name
Test status
Simulation time 48700289 ps
CPU time 1.5 seconds
Started Aug 21 08:50:45 AM UTC 24
Finished Aug 21 08:50:47 AM UTC 24
Peak memory 230484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4170007695 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.4170007695
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/13.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/17.edn_disable_auto_req_mode.2715580830
Short name T150
Test name
Test status
Simulation time 246494422 ps
CPU time 1.66 seconds
Started Aug 21 08:50:56 AM UTC 24
Finished Aug 21 08:50:58 AM UTC 24
Peak memory 226240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2715580830 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_dis
able_auto_req_mode.2715580830
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/17.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/20.edn_intr.1150392057
Short name T33
Test name
Test status
Simulation time 35084725 ps
CPU time 1.13 seconds
Started Aug 21 08:51:02 AM UTC 24
Finished Aug 21 08:51:05 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1150392057 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1150392057
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/20.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/19.edn_disable_auto_req_mode.732472286
Short name T169
Test name
Test status
Simulation time 88553056 ps
CPU time 1.38 seconds
Started Aug 21 08:51:02 AM UTC 24
Finished Aug 21 08:51:04 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=732472286 -assert no
postproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disa
ble_auto_req_mode.732472286
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/19.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/16.edn_disable.139262121
Short name T90
Test name
Test status
Simulation time 11204537 ps
CPU time 0.92 seconds
Started Aug 21 08:50:52 AM UTC 24
Finished Aug 21 08:50:54 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=139262121 -assert no
postproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o
pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.139262121
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/16.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/11.edn_genbits.2894706561
Short name T79
Test name
Test status
Simulation time 66640751 ps
CPU time 1.54 seconds
Started Aug 21 08:50:40 AM UTC 24
Finished Aug 21 08:50:43 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2894706561 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2894706561
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/11.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/33.edn_disable.3764447037
Short name T231
Test name
Test status
Simulation time 10997403 ps
CPU time 1.3 seconds
Started Aug 21 08:51:50 AM UTC 24
Finished Aug 21 08:51:53 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3764447037 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.3764447037
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/33.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/0.edn_alert_test.159279982
Short name T26
Test name
Test status
Simulation time 24622508 ps
CPU time 1.08 seconds
Started Aug 21 08:50:15 AM UTC 24
Finished Aug 21 08:50:18 AM UTC 24
Peak memory 216696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=159279982 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.159279982
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/0.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/5.edn_alert.698891918
Short name T47
Test name
Test status
Simulation time 60952564 ps
CPU time 1.54 seconds
Started Aug 21 08:50:29 AM UTC 24
Finished Aug 21 08:50:31 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=698891918 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.698891918
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/5.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/92.edn_alert.2637779883
Short name T685
Test name
Test status
Simulation time 53346873 ps
CPU time 1.72 seconds
Started Aug 21 08:53:17 AM UTC 24
Finished Aug 21 08:53:19 AM UTC 24
Peak memory 226388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2637779883 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.2637779883
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/92.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/27.edn_stress_all.3955157726
Short name T432
Test name
Test status
Simulation time 235778908 ps
CPU time 4.92 seconds
Started Aug 21 08:51:28 AM UTC 24
Finished Aug 21 08:51:34 AM UTC 24
Peak memory 229520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3955157726 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3955157726
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/27.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/11.edn_intr.533285006
Short name T34
Test name
Test status
Simulation time 20954841 ps
CPU time 1.48 seconds
Started Aug 21 08:50:40 AM UTC 24
Finished Aug 21 08:50:43 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=533285006 -assert nopostproc +UVM_TESTNAME=ed
n_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0
_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.533285006
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/11.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/10.edn_disable.237215975
Short name T77
Test name
Test status
Simulation time 18905895 ps
CPU time 1.07 seconds
Started Aug 21 08:50:39 AM UTC 24
Finished Aug 21 08:50:41 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=237215975 -assert no
postproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o
pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.237215975
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/10.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/10.edn_err.3254207872
Short name T200
Test name
Test status
Simulation time 18781871 ps
CPU time 1.25 seconds
Started Aug 21 08:50:38 AM UTC 24
Finished Aug 21 08:50:40 AM UTC 24
Peak memory 228092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3254207872 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.3254207872
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/10.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/100.edn_alert.4063174879
Short name T705
Test name
Test status
Simulation time 29817867 ps
CPU time 1.57 seconds
Started Aug 21 08:53:22 AM UTC 24
Finished Aug 21 08:53:24 AM UTC 24
Peak memory 226364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4063174879 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.4063174879
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/100.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/106.edn_alert.1192954998
Short name T709
Test name
Test status
Simulation time 38004153 ps
CPU time 1.24 seconds
Started Aug 21 08:53:23 AM UTC 24
Finished Aug 21 08:53:26 AM UTC 24
Peak memory 228404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1192954998 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.1192954998
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/106.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/110.edn_alert.4208519958
Short name T721
Test name
Test status
Simulation time 55746001 ps
CPU time 1.28 seconds
Started Aug 21 08:53:26 AM UTC 24
Finished Aug 21 08:53:28 AM UTC 24
Peak memory 228432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4208519958 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.4208519958
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/110.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/118.edn_alert.3543810965
Short name T157
Test name
Test status
Simulation time 50649270 ps
CPU time 1.63 seconds
Started Aug 21 08:53:29 AM UTC 24
Finished Aug 21 08:53:31 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3543810965 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.3543810965
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/118.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/122.edn_alert.3671276004
Short name T744
Test name
Test status
Simulation time 25931555 ps
CPU time 1.53 seconds
Started Aug 21 08:53:31 AM UTC 24
Finished Aug 21 08:53:34 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3671276004 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.3671276004
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/122.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/148.edn_alert.1793479182
Short name T153
Test name
Test status
Simulation time 28370379 ps
CPU time 1.43 seconds
Started Aug 21 08:53:39 AM UTC 24
Finished Aug 21 08:53:42 AM UTC 24
Peak memory 228404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1793479182 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.1793479182
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/148.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/158.edn_alert.945926651
Short name T806
Test name
Test status
Simulation time 257666530 ps
CPU time 1.55 seconds
Started Aug 21 08:53:42 AM UTC 24
Finished Aug 21 08:53:45 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=945926651 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.945926651
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/158.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/19.edn_disable.3830538408
Short name T94
Test name
Test status
Simulation time 23178638 ps
CPU time 1.19 seconds
Started Aug 21 08:51:01 AM UTC 24
Finished Aug 21 08:51:03 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3830538408 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.3830538408
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/19.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/25.edn_disable.2901659603
Short name T221
Test name
Test status
Simulation time 21898718 ps
CPU time 1.11 seconds
Started Aug 21 08:51:23 AM UTC 24
Finished Aug 21 08:51:25 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2901659603 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2901659603
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/25.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/46.edn_disable.1985969550
Short name T220
Test name
Test status
Simulation time 11261165 ps
CPU time 1.29 seconds
Started Aug 21 08:52:33 AM UTC 24
Finished Aug 21 08:52:35 AM UTC 24
Peak memory 226284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1985969550 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.1985969550
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/46.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/54.edn_err.3566565666
Short name T211
Test name
Test status
Simulation time 30481237 ps
CPU time 1.48 seconds
Started Aug 21 08:52:51 AM UTC 24
Finished Aug 21 08:52:53 AM UTC 24
Peak memory 245732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3566565666 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.3566565666
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/54.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/67.edn_err.2754978443
Short name T209
Test name
Test status
Simulation time 18715828 ps
CPU time 1.48 seconds
Started Aug 21 08:53:01 AM UTC 24
Finished Aug 21 08:53:03 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2754978443 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.2754978443
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/67.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/42.edn_genbits.2487155168
Short name T316
Test name
Test status
Simulation time 46080000 ps
CPU time 2.2 seconds
Started Aug 21 08:52:16 AM UTC 24
Finished Aug 21 08:52:20 AM UTC 24
Peak memory 229516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2487155168 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.2487155168
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/42.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/104.edn_genbits.44085794
Short name T708
Test name
Test status
Simulation time 85401098 ps
CPU time 1.31 seconds
Started Aug 21 08:53:23 AM UTC 24
Finished Aug 21 08:53:25 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=44085794 -assert nopostproc +UVM_TESTNAME=edn
_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_
1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.44085794
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/104.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/158.edn_genbits.3240248339
Short name T335
Test name
Test status
Simulation time 530936009 ps
CPU time 4.2 seconds
Started Aug 21 08:53:42 AM UTC 24
Finished Aug 21 08:53:48 AM UTC 24
Peak memory 231484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3240248339 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.3240248339
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/158.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/48.edn_err.153375286
Short name T110
Test name
Test status
Simulation time 40562358 ps
CPU time 1.62 seconds
Started Aug 21 08:52:39 AM UTC 24
Finished Aug 21 08:52:42 AM UTC 24
Peak memory 233616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=153375286 -assert nopostproc +UVM_TESTNAME=ed
n_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2
024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.153375286
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/48.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/15.edn_genbits.3188420721
Short name T44
Test name
Test status
Simulation time 56070731 ps
CPU time 2.47 seconds
Started Aug 21 08:50:48 AM UTC 24
Finished Aug 21 08:50:52 AM UTC 24
Peak memory 229700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3188420721 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.3188420721
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/15.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_bit_bash.2104825434
Short name T266
Test name
Test status
Simulation time 112980005 ps
CPU time 4.22 seconds
Started Aug 21 06:02:36 PM UTC 24
Finished Aug 21 06:02:41 PM UTC 24
Peak memory 217432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2104825434 -ass
ert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2104825434
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/0.edn_csr_bit_bash/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_intg_err.1342368264
Short name T1055
Test name
Test status
Simulation time 470590325 ps
CPU time 3.07 seconds
Started Aug 21 06:03:06 PM UTC 24
Finished Aug 21 06:03:10 PM UTC 24
Peak memory 227732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1342368264 -
assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1342368264
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/14.edn_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/0.edn_genbits.3067186514
Short name T3
Test name
Test status
Simulation time 25616667 ps
CPU time 1.23 seconds
Started Aug 21 08:50:14 AM UTC 24
Finished Aug 21 08:50:16 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3067186514 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.3067186514
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/0.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/1.edn_genbits.3955440452
Short name T11
Test name
Test status
Simulation time 41645866 ps
CPU time 1.83 seconds
Started Aug 21 08:50:16 AM UTC 24
Finished Aug 21 08:50:19 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3955440452 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.3955440452
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/1.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/10.edn_disable_auto_req_mode.3570795998
Short name T88
Test name
Test status
Simulation time 44947579 ps
CPU time 1.62 seconds
Started Aug 21 08:50:39 AM UTC 24
Finished Aug 21 08:50:42 AM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3570795998 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_dis
able_auto_req_mode.3570795998
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/10.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/106.edn_genbits.2028841837
Short name T345
Test name
Test status
Simulation time 221268734 ps
CPU time 1.4 seconds
Started Aug 21 08:53:23 AM UTC 24
Finished Aug 21 08:53:26 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2028841837 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.2028841837
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/106.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/122.edn_genbits.4168867176
Short name T321
Test name
Test status
Simulation time 316084110 ps
CPU time 2.56 seconds
Started Aug 21 08:53:30 AM UTC 24
Finished Aug 21 08:53:34 AM UTC 24
Peak memory 231764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4168867176 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.4168867176
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/122.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/129.edn_genbits.1798025330
Short name T339
Test name
Test status
Simulation time 53890488 ps
CPU time 1.77 seconds
Started Aug 21 08:53:33 AM UTC 24
Finished Aug 21 08:53:35 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1798025330 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.1798025330
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/129.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/13.edn_genbits.4071659090
Short name T349
Test name
Test status
Simulation time 30297493 ps
CPU time 1.6 seconds
Started Aug 21 08:50:43 AM UTC 24
Finished Aug 21 08:50:46 AM UTC 24
Peak memory 228260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4071659090 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.4071659090
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/13.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/135.edn_genbits.3010830473
Short name T332
Test name
Test status
Simulation time 162474780 ps
CPU time 1.68 seconds
Started Aug 21 08:53:35 AM UTC 24
Finished Aug 21 08:53:38 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3010830473 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.3010830473
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/135.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/153.edn_genbits.1296858083
Short name T342
Test name
Test status
Simulation time 176396620 ps
CPU time 1.46 seconds
Started Aug 21 08:53:41 AM UTC 24
Finished Aug 21 08:53:43 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1296858083 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.1296858083
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/153.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/155.edn_genbits.107664530
Short name T798
Test name
Test status
Simulation time 37006190 ps
CPU time 1.84 seconds
Started Aug 21 08:53:41 AM UTC 24
Finished Aug 21 08:53:44 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=107664530 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.107664530
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/155.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/175.edn_genbits.541700474
Short name T327
Test name
Test status
Simulation time 66778188 ps
CPU time 1.2 seconds
Started Aug 21 08:53:48 AM UTC 24
Finished Aug 21 08:53:51 AM UTC 24
Peak memory 230420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=541700474 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.541700474
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/175.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/176.edn_genbits.1289010460
Short name T336
Test name
Test status
Simulation time 46149348 ps
CPU time 1.85 seconds
Started Aug 21 08:53:49 AM UTC 24
Finished Aug 21 08:53:52 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1289010460 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1289010460
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/176.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/33.edn_disable_auto_req_mode.1038086709
Short name T256
Test name
Test status
Simulation time 24498106 ps
CPU time 1.3 seconds
Started Aug 21 08:51:51 AM UTC 24
Finished Aug 21 08:51:53 AM UTC 24
Peak memory 226212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1038086709 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_dis
able_auto_req_mode.1038086709
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/33.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/37.edn_intr.287192343
Short name T111
Test name
Test status
Simulation time 22170559 ps
CPU time 1.3 seconds
Started Aug 21 08:52:00 AM UTC 24
Finished Aug 21 08:52:03 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=287192343 -assert nopostproc +UVM_TESTNAME=ed
n_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0
_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.287192343
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/37.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/14.edn_intr.3139364956
Short name T137
Test name
Test status
Simulation time 23939855 ps
CPU time 1.35 seconds
Started Aug 21 08:50:46 AM UTC 24
Finished Aug 21 08:50:48 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3139364956 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3139364956
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/14.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/154.edn_alert.3733170650
Short name T139
Test name
Test status
Simulation time 23240585 ps
CPU time 1.57 seconds
Started Aug 21 08:53:41 AM UTC 24
Finished Aug 21 08:53:44 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3733170650 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.3733170650
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/154.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/1.edn_err.2797696188
Short name T7
Test name
Test status
Simulation time 24816655 ps
CPU time 1.26 seconds
Started Aug 21 08:50:17 AM UTC 24
Finished Aug 21 08:50:19 AM UTC 24
Peak memory 244100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2797696188 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.2797696188
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/1.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/246.edn_genbits.4192000959
Short name T924
Test name
Test status
Simulation time 63760120 ps
CPU time 1.33 seconds
Started Aug 21 08:54:12 AM UTC 24
Finished Aug 21 08:54:18 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4192000959 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.4192000959
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/246.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_aliasing.2640756322
Short name T264
Test name
Test status
Simulation time 18785853 ps
CPU time 1.5 seconds
Started Aug 21 06:02:36 PM UTC 24
Finished Aug 21 06:02:38 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2640756322 -ass
ert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2640756322
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/0.edn_csr_aliasing/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_hw_reset.4033441642
Short name T980
Test name
Test status
Simulation time 18476363 ps
CPU time 1.45 seconds
Started Aug 21 06:02:35 PM UTC 24
Finished Aug 21 06:02:38 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4033441642 -ass
ert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.4033441642
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/0.edn_csr_hw_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1473048727
Short name T983
Test name
Test status
Simulation time 137594295 ps
CPU time 1.92 seconds
Started Aug 21 06:02:37 PM UTC 24
Finished Aug 21 06:02:40 PM UTC 24
Peak memory 225692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=1473048727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1473048727
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/0.edn_intr_test.790262599
Short name T979
Test name
Test status
Simulation time 23039150 ps
CPU time 1.23 seconds
Started Aug 21 06:02:35 PM UTC 24
Finished Aug 21 06:02:38 PM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=790262599 -assert nopost
proc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.790262599
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/0.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/0.edn_same_csr_outstanding.1726707899
Short name T278
Test name
Test status
Simulation time 23016703 ps
CPU time 1.7 seconds
Started Aug 21 06:02:37 PM UTC 24
Finished Aug 21 06:02:40 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=172
6707899 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_outs
tanding.1726707899
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/0.edn_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/0.edn_tl_errors.3924320030
Short name T981
Test name
Test status
Simulation time 80709406 ps
CPU time 4.13 seconds
Started Aug 21 06:02:34 PM UTC 24
Finished Aug 21 06:02:39 PM UTC 24
Peak memory 227660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3924320030 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3924320030
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/0.edn_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/0.edn_tl_intg_err.4213091687
Short name T287
Test name
Test status
Simulation time 246711544 ps
CPU time 2.27 seconds
Started Aug 21 06:02:34 PM UTC 24
Finished Aug 21 06:02:38 PM UTC 24
Peak memory 217448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4213091687 -
assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.4213091687
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/0.edn_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_aliasing.1011927883
Short name T267
Test name
Test status
Simulation time 141510181 ps
CPU time 1.73 seconds
Started Aug 21 06:02:39 PM UTC 24
Finished Aug 21 06:02:41 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1011927883 -ass
ert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1011927883
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/1.edn_csr_aliasing/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_bit_bash.2539421496
Short name T986
Test name
Test status
Simulation time 78486601 ps
CPU time 4.37 seconds
Started Aug 21 06:02:39 PM UTC 24
Finished Aug 21 06:02:44 PM UTC 24
Peak memory 217284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2539421496 -ass
ert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2539421496
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/1.edn_csr_bit_bash/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_hw_reset.931974034
Short name T265
Test name
Test status
Simulation time 34946045 ps
CPU time 1.26 seconds
Started Aug 21 06:02:38 PM UTC 24
Finished Aug 21 06:02:41 PM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=931974034 -asse
rt nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.931974034
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/1.edn_csr_hw_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1306436405
Short name T984
Test name
Test status
Simulation time 104194313 ps
CPU time 1.86 seconds
Started Aug 21 06:02:40 PM UTC 24
Finished Aug 21 06:02:43 PM UTC 24
Peak memory 225700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=1306436405 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.1306436405
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_rw.2529654828
Short name T279
Test name
Test status
Simulation time 43543234 ps
CPU time 1.28 seconds
Started Aug 21 06:02:39 PM UTC 24
Finished Aug 21 06:02:41 PM UTC 24
Peak memory 215344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2529654828 -assert no
postproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2529654828
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/1.edn_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/1.edn_intr_test.3079109547
Short name T982
Test name
Test status
Simulation time 25660594 ps
CPU time 1.3 seconds
Started Aug 21 06:02:37 PM UTC 24
Finished Aug 21 06:02:40 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3079109547 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3079109547
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/1.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/1.edn_same_csr_outstanding.4012704976
Short name T280
Test name
Test status
Simulation time 54734738 ps
CPU time 1.49 seconds
Started Aug 21 06:02:40 PM UTC 24
Finished Aug 21 06:02:42 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=401
2704976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_outs
tanding.4012704976
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/1.edn_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/1.edn_tl_errors.1803132931
Short name T988
Test name
Test status
Simulation time 257429894 ps
CPU time 6.06 seconds
Started Aug 21 06:02:37 PM UTC 24
Finished Aug 21 06:02:44 PM UTC 24
Peak memory 228072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1803132931 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.1803132931
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/1.edn_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/1.edn_tl_intg_err.432766407
Short name T288
Test name
Test status
Simulation time 309296748 ps
CPU time 3.28 seconds
Started Aug 21 06:02:37 PM UTC 24
Finished Aug 21 06:02:42 PM UTC 24
Peak memory 227292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=432766407 -a
ssert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri
sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.432766407
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/1.edn_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3269166840
Short name T1024
Test name
Test status
Simulation time 194788117 ps
CPU time 1.88 seconds
Started Aug 21 06:03:00 PM UTC 24
Finished Aug 21 06:03:03 PM UTC 24
Peak memory 225640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=3269166840 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3269166840
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_rw.1949746863
Short name T1020
Test name
Test status
Simulation time 50563504 ps
CPU time 1.14 seconds
Started Aug 21 06:03:00 PM UTC 24
Finished Aug 21 06:03:02 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1949746863 -assert no
postproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1949746863
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/10.edn_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/10.edn_intr_test.432330927
Short name T1018
Test name
Test status
Simulation time 38586780 ps
CPU time 0.89 seconds
Started Aug 21 06:03:00 PM UTC 24
Finished Aug 21 06:03:02 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=432330927 -assert nopost
proc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.432330927
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/10.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/10.edn_same_csr_outstanding.1306048464
Short name T1023
Test name
Test status
Simulation time 255617140 ps
CPU time 1.43 seconds
Started Aug 21 06:03:00 PM UTC 24
Finished Aug 21 06:03:02 PM UTC 24
Peak memory 215384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=130
6048464 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_out
standing.1306048464
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/10.edn_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_errors.725101235
Short name T1034
Test name
Test status
Simulation time 480317842 ps
CPU time 4.43 seconds
Started Aug 21 06:03:00 PM UTC 24
Finished Aug 21 06:03:05 PM UTC 24
Peak memory 227932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=725101235 -assert nopost
proc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.725101235
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/10.edn_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_intg_err.1409058747
Short name T1028
Test name
Test status
Simulation time 68677492 ps
CPU time 2.68 seconds
Started Aug 21 06:03:00 PM UTC 24
Finished Aug 21 06:03:03 PM UTC 24
Peak memory 217684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1409058747 -
assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1409058747
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/10.edn_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.978284989
Short name T1036
Test name
Test status
Simulation time 91550183 ps
CPU time 1.99 seconds
Started Aug 21 06:03:02 PM UTC 24
Finished Aug 21 06:03:05 PM UTC 24
Peak memory 225640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=978284989 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.978284989
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_rw.3770053028
Short name T1025
Test name
Test status
Simulation time 21500080 ps
CPU time 0.97 seconds
Started Aug 21 06:03:01 PM UTC 24
Finished Aug 21 06:03:03 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3770053028 -assert no
postproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3770053028
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/11.edn_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/11.edn_intr_test.1986451687
Short name T1027
Test name
Test status
Simulation time 15197360 ps
CPU time 1.27 seconds
Started Aug 21 06:03:01 PM UTC 24
Finished Aug 21 06:03:03 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1986451687 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1986451687
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/11.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/11.edn_same_csr_outstanding.1448026673
Short name T1031
Test name
Test status
Simulation time 15921021 ps
CPU time 1.43 seconds
Started Aug 21 06:03:02 PM UTC 24
Finished Aug 21 06:03:05 PM UTC 24
Peak memory 225704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=144
8026673 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_out
standing.1448026673
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/11.edn_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_errors.983227894
Short name T1032
Test name
Test status
Simulation time 170922701 ps
CPU time 2.65 seconds
Started Aug 21 06:03:01 PM UTC 24
Finished Aug 21 06:03:05 PM UTC 24
Peak memory 227996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=983227894 -assert nopost
proc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.983227894
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/11.edn_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_intg_err.4019177305
Short name T1029
Test name
Test status
Simulation time 60209115 ps
CPU time 1.75 seconds
Started Aug 21 06:03:01 PM UTC 24
Finished Aug 21 06:03:04 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4019177305 -
assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.4019177305
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/11.edn_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.793523200
Short name T1041
Test name
Test status
Simulation time 18874274 ps
CPU time 1.72 seconds
Started Aug 21 06:03:04 PM UTC 24
Finished Aug 21 06:03:07 PM UTC 24
Peak memory 225640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=793523200 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.793523200
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_rw.1063884069
Short name T1033
Test name
Test status
Simulation time 12193965 ps
CPU time 1.15 seconds
Started Aug 21 06:03:02 PM UTC 24
Finished Aug 21 06:03:05 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1063884069 -assert no
postproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.1063884069
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/12.edn_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/12.edn_intr_test.4223183779
Short name T1030
Test name
Test status
Simulation time 32311241 ps
CPU time 1.18 seconds
Started Aug 21 06:03:02 PM UTC 24
Finished Aug 21 06:03:05 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4223183779 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.4223183779
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/12.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/12.edn_same_csr_outstanding.4190537233
Short name T1035
Test name
Test status
Simulation time 26026360 ps
CPU time 1.41 seconds
Started Aug 21 06:03:03 PM UTC 24
Finished Aug 21 06:03:05 PM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=419
0537233 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_out
standing.4190537233
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/12.edn_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_errors.499466502
Short name T1038
Test name
Test status
Simulation time 230225184 ps
CPU time 2.58 seconds
Started Aug 21 06:03:02 PM UTC 24
Finished Aug 21 06:03:06 PM UTC 24
Peak memory 227996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=499466502 -assert nopost
proc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.499466502
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/12.edn_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_intg_err.683704946
Short name T1037
Test name
Test status
Simulation time 45583799 ps
CPU time 2.31 seconds
Started Aug 21 06:03:02 PM UTC 24
Finished Aug 21 06:03:06 PM UTC 24
Peak memory 217508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=683704946 -a
ssert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri
sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.683704946
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/12.edn_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2291068397
Short name T1042
Test name
Test status
Simulation time 88363820 ps
CPU time 1.73 seconds
Started Aug 21 06:03:04 PM UTC 24
Finished Aug 21 06:03:07 PM UTC 24
Peak memory 225588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=2291068397 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2291068397
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_rw.2737796064
Short name T1039
Test name
Test status
Simulation time 25554016 ps
CPU time 1.29 seconds
Started Aug 21 06:03:04 PM UTC 24
Finished Aug 21 06:03:06 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2737796064 -assert no
postproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.2737796064
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/13.edn_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/13.edn_intr_test.4181613118
Short name T1040
Test name
Test status
Simulation time 16588557 ps
CPU time 1.37 seconds
Started Aug 21 06:03:04 PM UTC 24
Finished Aug 21 06:03:07 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4181613118 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.4181613118
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/13.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/13.edn_same_csr_outstanding.3936828369
Short name T1043
Test name
Test status
Simulation time 37927051 ps
CPU time 1.98 seconds
Started Aug 21 06:03:04 PM UTC 24
Finished Aug 21 06:03:07 PM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=393
6828369 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_out
standing.3936828369
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/13.edn_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_errors.4001034187
Short name T1048
Test name
Test status
Simulation time 58354926 ps
CPU time 3.15 seconds
Started Aug 21 06:03:04 PM UTC 24
Finished Aug 21 06:03:08 PM UTC 24
Peak memory 227988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4001034187 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.4001034187
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/13.edn_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_intg_err.3278045083
Short name T1046
Test name
Test status
Simulation time 181923703 ps
CPU time 2.64 seconds
Started Aug 21 06:03:04 PM UTC 24
Finished Aug 21 06:03:08 PM UTC 24
Peak memory 217580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3278045083 -
assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3278045083
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/13.edn_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.520009646
Short name T1050
Test name
Test status
Simulation time 26666875 ps
CPU time 1.79 seconds
Started Aug 21 06:03:06 PM UTC 24
Finished Aug 21 06:03:08 PM UTC 24
Peak memory 225640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=520009646 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.520009646
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_rw.3684332102
Short name T1045
Test name
Test status
Simulation time 58670402 ps
CPU time 1.2 seconds
Started Aug 21 06:03:06 PM UTC 24
Finished Aug 21 06:03:08 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3684332102 -assert no
postproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.3684332102
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/14.edn_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/14.edn_intr_test.1625201105
Short name T1044
Test name
Test status
Simulation time 13541983 ps
CPU time 1.26 seconds
Started Aug 21 06:03:06 PM UTC 24
Finished Aug 21 06:03:08 PM UTC 24
Peak memory 215248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1625201105 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.1625201105
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/14.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/14.edn_same_csr_outstanding.724306948
Short name T1049
Test name
Test status
Simulation time 19296675 ps
CPU time 1.7 seconds
Started Aug 21 06:03:06 PM UTC 24
Finished Aug 21 06:03:08 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=724
306948 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_outs
tanding.724306948
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/14.edn_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_errors.2873708810
Short name T1052
Test name
Test status
Simulation time 38660009 ps
CPU time 3.11 seconds
Started Aug 21 06:03:04 PM UTC 24
Finished Aug 21 06:03:09 PM UTC 24
Peak memory 227992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2873708810 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2873708810
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/14.edn_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2523361262
Short name T1056
Test name
Test status
Simulation time 241764307 ps
CPU time 1.61 seconds
Started Aug 21 06:03:07 PM UTC 24
Finished Aug 21 06:03:10 PM UTC 24
Peak memory 225708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=2523361262 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2523361262
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_rw.1514763063
Short name T1053
Test name
Test status
Simulation time 27522873 ps
CPU time 1.11 seconds
Started Aug 21 06:03:07 PM UTC 24
Finished Aug 21 06:03:09 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1514763063 -assert no
postproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1514763063
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/15.edn_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/15.edn_intr_test.1106163444
Short name T1047
Test name
Test status
Simulation time 83622216 ps
CPU time 1.23 seconds
Started Aug 21 06:03:06 PM UTC 24
Finished Aug 21 06:03:08 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1106163444 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1106163444
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/15.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/15.edn_same_csr_outstanding.4000326280
Short name T1054
Test name
Test status
Simulation time 61626885 ps
CPU time 1.47 seconds
Started Aug 21 06:03:07 PM UTC 24
Finished Aug 21 06:03:09 PM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=400
0326280 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_out
standing.4000326280
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/15.edn_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_errors.2413599095
Short name T1063
Test name
Test status
Simulation time 294268118 ps
CPU time 4.29 seconds
Started Aug 21 06:03:06 PM UTC 24
Finished Aug 21 06:03:11 PM UTC 24
Peak memory 227800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2413599095 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2413599095
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/15.edn_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_intg_err.670442228
Short name T1051
Test name
Test status
Simulation time 176273776 ps
CPU time 1.68 seconds
Started Aug 21 06:03:06 PM UTC 24
Finished Aug 21 06:03:08 PM UTC 24
Peak memory 215468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=670442228 -a
ssert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri
sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.670442228
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/15.edn_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.269489475
Short name T1064
Test name
Test status
Simulation time 26710118 ps
CPU time 1.59 seconds
Started Aug 21 06:03:09 PM UTC 24
Finished Aug 21 06:03:11 PM UTC 24
Peak memory 225640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=269489475 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.269489475
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_rw.609673788
Short name T1060
Test name
Test status
Simulation time 43814363 ps
CPU time 1.14 seconds
Started Aug 21 06:03:08 PM UTC 24
Finished Aug 21 06:03:11 PM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=609673788 -assert nop
ostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.609673788
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/16.edn_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/16.edn_intr_test.3168200364
Short name T1059
Test name
Test status
Simulation time 16731803 ps
CPU time 1.2 seconds
Started Aug 21 06:03:08 PM UTC 24
Finished Aug 21 06:03:11 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3168200364 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3168200364
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/16.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/16.edn_same_csr_outstanding.575718030
Short name T1062
Test name
Test status
Simulation time 158379471 ps
CPU time 1.48 seconds
Started Aug 21 06:03:09 PM UTC 24
Finished Aug 21 06:03:11 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=575
718030 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_outs
tanding.575718030
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/16.edn_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_errors.217637117
Short name T1057
Test name
Test status
Simulation time 58888095 ps
CPU time 2.28 seconds
Started Aug 21 06:03:07 PM UTC 24
Finished Aug 21 06:03:10 PM UTC 24
Peak memory 227868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=217637117 -assert nopost
proc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.217637117
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/16.edn_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_intg_err.2602963232
Short name T1058
Test name
Test status
Simulation time 944671447 ps
CPU time 2.37 seconds
Started Aug 21 06:03:07 PM UTC 24
Finished Aug 21 06:03:11 PM UTC 24
Peak memory 227732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2602963232 -
assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2602963232
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/16.edn_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3271675962
Short name T1068
Test name
Test status
Simulation time 44607630 ps
CPU time 1.52 seconds
Started Aug 21 06:03:10 PM UTC 24
Finished Aug 21 06:03:13 PM UTC 24
Peak memory 225708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=3271675962 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3271675962
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_rw.2270017069
Short name T1066
Test name
Test status
Simulation time 19974039 ps
CPU time 1.3 seconds
Started Aug 21 06:03:10 PM UTC 24
Finished Aug 21 06:03:12 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2270017069 -assert no
postproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2270017069
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/17.edn_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/17.edn_intr_test.2740068710
Short name T1061
Test name
Test status
Simulation time 13803639 ps
CPU time 1.12 seconds
Started Aug 21 06:03:09 PM UTC 24
Finished Aug 21 06:03:11 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2740068710 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.2740068710
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/17.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/17.edn_same_csr_outstanding.2620017992
Short name T1071
Test name
Test status
Simulation time 77860114 ps
CPU time 1.95 seconds
Started Aug 21 06:03:10 PM UTC 24
Finished Aug 21 06:03:13 PM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=262
0017992 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_out
standing.2620017992
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/17.edn_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_errors.3693547987
Short name T1078
Test name
Test status
Simulation time 394611774 ps
CPU time 4.69 seconds
Started Aug 21 06:03:09 PM UTC 24
Finished Aug 21 06:03:14 PM UTC 24
Peak memory 227800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3693547987 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3693547987
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/17.edn_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_intg_err.2698116970
Short name T1065
Test name
Test status
Simulation time 185086193 ps
CPU time 2.24 seconds
Started Aug 21 06:03:09 PM UTC 24
Finished Aug 21 06:03:12 PM UTC 24
Peak memory 227944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2698116970 -
assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2698116970
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/17.edn_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1649665243
Short name T1082
Test name
Test status
Simulation time 30899152 ps
CPU time 2.59 seconds
Started Aug 21 06:03:12 PM UTC 24
Finished Aug 21 06:03:15 PM UTC 24
Peak memory 227884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=1649665243 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1649665243
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_rw.3633561725
Short name T1067
Test name
Test status
Simulation time 15101041 ps
CPU time 1.26 seconds
Started Aug 21 06:03:10 PM UTC 24
Finished Aug 21 06:03:13 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3633561725 -assert no
postproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.3633561725
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/18.edn_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/18.edn_intr_test.3501104097
Short name T1069
Test name
Test status
Simulation time 260206113 ps
CPU time 1.48 seconds
Started Aug 21 06:03:10 PM UTC 24
Finished Aug 21 06:03:13 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3501104097 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.3501104097
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/18.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/18.edn_same_csr_outstanding.179516474
Short name T1070
Test name
Test status
Simulation time 22393793 ps
CPU time 1.37 seconds
Started Aug 21 06:03:10 PM UTC 24
Finished Aug 21 06:03:13 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=179
516474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_outs
tanding.179516474
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/18.edn_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_errors.217516567
Short name T1080
Test name
Test status
Simulation time 82456139 ps
CPU time 3.7 seconds
Started Aug 21 06:03:10 PM UTC 24
Finished Aug 21 06:03:15 PM UTC 24
Peak memory 227996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=217516567 -assert nopost
proc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.217516567
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/18.edn_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_intg_err.1826710338
Short name T1072
Test name
Test status
Simulation time 51714510 ps
CPU time 2.38 seconds
Started Aug 21 06:03:10 PM UTC 24
Finished Aug 21 06:03:14 PM UTC 24
Peak memory 217552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1826710338 -
assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1826710338
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/18.edn_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3442048998
Short name T1077
Test name
Test status
Simulation time 61324134 ps
CPU time 1.52 seconds
Started Aug 21 06:03:12 PM UTC 24
Finished Aug 21 06:03:14 PM UTC 24
Peak memory 225588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=3442048998 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3442048998
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_rw.1691963125
Short name T1074
Test name
Test status
Simulation time 36815205 ps
CPU time 1.23 seconds
Started Aug 21 06:03:12 PM UTC 24
Finished Aug 21 06:03:14 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1691963125 -assert no
postproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.1691963125
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/19.edn_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/19.edn_intr_test.3564144087
Short name T1073
Test name
Test status
Simulation time 38891262 ps
CPU time 1.23 seconds
Started Aug 21 06:03:12 PM UTC 24
Finished Aug 21 06:03:14 PM UTC 24
Peak memory 215292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3564144087 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.3564144087
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/19.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/19.edn_same_csr_outstanding.2606461549
Short name T1079
Test name
Test status
Simulation time 35489259 ps
CPU time 1.47 seconds
Started Aug 21 06:03:12 PM UTC 24
Finished Aug 21 06:03:14 PM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=260
6461549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_out
standing.2606461549
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/19.edn_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_errors.1215908803
Short name T1090
Test name
Test status
Simulation time 50670448 ps
CPU time 3.79 seconds
Started Aug 21 06:03:12 PM UTC 24
Finished Aug 21 06:03:16 PM UTC 24
Peak memory 227800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1215908803 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1215908803
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/19.edn_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_intg_err.2048335062
Short name T1081
Test name
Test status
Simulation time 71395319 ps
CPU time 2.15 seconds
Started Aug 21 06:03:12 PM UTC 24
Finished Aug 21 06:03:15 PM UTC 24
Peak memory 227732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2048335062 -
assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.2048335062
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/19.edn_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_aliasing.3624502252
Short name T270
Test name
Test status
Simulation time 173798546 ps
CPU time 1.94 seconds
Started Aug 21 06:02:42 PM UTC 24
Finished Aug 21 06:02:45 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3624502252 -ass
ert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.3624502252
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/2.edn_csr_aliasing/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_bit_bash.2114295684
Short name T991
Test name
Test status
Simulation time 59519025 ps
CPU time 4.38 seconds
Started Aug 21 06:02:42 PM UTC 24
Finished Aug 21 06:02:48 PM UTC 24
Peak memory 217520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2114295684 -ass
ert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2114295684
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/2.edn_csr_bit_bash/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_hw_reset.948463427
Short name T268
Test name
Test status
Simulation time 26048962 ps
CPU time 1.32 seconds
Started Aug 21 06:02:42 PM UTC 24
Finished Aug 21 06:02:44 PM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=948463427 -asse
rt nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.948463427
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/2.edn_csr_hw_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1031683541
Short name T989
Test name
Test status
Simulation time 29526356 ps
CPU time 2.11 seconds
Started Aug 21 06:02:43 PM UTC 24
Finished Aug 21 06:02:46 PM UTC 24
Peak memory 227892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=1031683541 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1031683541
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_rw.3809680309
Short name T269
Test name
Test status
Simulation time 146514600 ps
CPU time 1.22 seconds
Started Aug 21 06:02:42 PM UTC 24
Finished Aug 21 06:02:44 PM UTC 24
Peak memory 215344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3809680309 -assert no
postproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3809680309
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/2.edn_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/2.edn_intr_test.3952113794
Short name T985
Test name
Test status
Simulation time 53913056 ps
CPU time 1.24 seconds
Started Aug 21 06:02:41 PM UTC 24
Finished Aug 21 06:02:43 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3952113794 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.3952113794
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/2.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/2.edn_same_csr_outstanding.1106088048
Short name T281
Test name
Test status
Simulation time 46530192 ps
CPU time 1.62 seconds
Started Aug 21 06:02:43 PM UTC 24
Finished Aug 21 06:02:46 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=110
6088048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_outs
tanding.1106088048
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/2.edn_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/2.edn_tl_errors.2623507690
Short name T987
Test name
Test status
Simulation time 292686219 ps
CPU time 2.51 seconds
Started Aug 21 06:02:41 PM UTC 24
Finished Aug 21 06:02:44 PM UTC 24
Peak memory 228072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2623507690 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.2623507690
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/2.edn_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/20.edn_intr_test.643383086
Short name T1075
Test name
Test status
Simulation time 13815823 ps
CPU time 1.32 seconds
Started Aug 21 06:03:12 PM UTC 24
Finished Aug 21 06:03:14 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=643383086 -assert nopost
proc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.643383086
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/20.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/21.edn_intr_test.520264235
Short name T1076
Test name
Test status
Simulation time 19687933 ps
CPU time 1.3 seconds
Started Aug 21 06:03:12 PM UTC 24
Finished Aug 21 06:03:14 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=520264235 -assert nopost
proc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.520264235
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/21.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/22.edn_intr_test.3438986752
Short name T1083
Test name
Test status
Simulation time 23763853 ps
CPU time 1.01 seconds
Started Aug 21 06:03:13 PM UTC 24
Finished Aug 21 06:03:15 PM UTC 24
Peak memory 215004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3438986752 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3438986752
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/22.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/23.edn_intr_test.3188751202
Short name T1086
Test name
Test status
Simulation time 26789652 ps
CPU time 1.17 seconds
Started Aug 21 06:03:13 PM UTC 24
Finished Aug 21 06:03:16 PM UTC 24
Peak memory 215072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3188751202 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3188751202
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/23.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/24.edn_intr_test.3608558215
Short name T1087
Test name
Test status
Simulation time 47960965 ps
CPU time 1.31 seconds
Started Aug 21 06:03:13 PM UTC 24
Finished Aug 21 06:03:16 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3608558215 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3608558215
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/24.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/25.edn_intr_test.1788018695
Short name T1088
Test name
Test status
Simulation time 12371603 ps
CPU time 1.28 seconds
Started Aug 21 06:03:13 PM UTC 24
Finished Aug 21 06:03:16 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1788018695 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1788018695
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/25.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/26.edn_intr_test.4258514573
Short name T1084
Test name
Test status
Simulation time 40937208 ps
CPU time 0.95 seconds
Started Aug 21 06:03:13 PM UTC 24
Finished Aug 21 06:03:15 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4258514573 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.4258514573
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/26.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/27.edn_intr_test.849476996
Short name T1085
Test name
Test status
Simulation time 18662511 ps
CPU time 0.91 seconds
Started Aug 21 06:03:13 PM UTC 24
Finished Aug 21 06:03:15 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=849476996 -assert nopost
proc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.849476996
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/27.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/28.edn_intr_test.3879204948
Short name T1091
Test name
Test status
Simulation time 24389861 ps
CPU time 1.25 seconds
Started Aug 21 06:03:15 PM UTC 24
Finished Aug 21 06:03:17 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3879204948 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.3879204948
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/28.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/29.edn_intr_test.2181752154
Short name T1089
Test name
Test status
Simulation time 13057928 ps
CPU time 0.79 seconds
Started Aug 21 06:03:15 PM UTC 24
Finished Aug 21 06:03:16 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2181752154 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2181752154
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/29.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_aliasing.1612861390
Short name T272
Test name
Test status
Simulation time 34382476 ps
CPU time 1.76 seconds
Started Aug 21 06:02:46 PM UTC 24
Finished Aug 21 06:02:49 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1612861390 -ass
ert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1612861390
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/3.edn_csr_aliasing/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_bit_bash.2172147101
Short name T275
Test name
Test status
Simulation time 219547802 ps
CPU time 8.39 seconds
Started Aug 21 06:02:46 PM UTC 24
Finished Aug 21 06:02:55 PM UTC 24
Peak memory 217492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2172147101 -ass
ert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.2172147101
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/3.edn_csr_bit_bash/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_hw_reset.2242962503
Short name T271
Test name
Test status
Simulation time 16378056 ps
CPU time 1.44 seconds
Started Aug 21 06:02:46 PM UTC 24
Finished Aug 21 06:02:48 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2242962503 -ass
ert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2242962503
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/3.edn_csr_hw_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.143102300
Short name T993
Test name
Test status
Simulation time 37231012 ps
CPU time 1.27 seconds
Started Aug 21 06:02:46 PM UTC 24
Finished Aug 21 06:02:48 PM UTC 24
Peak memory 225700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=143102300 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.143102300
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_rw.3610214307
Short name T992
Test name
Test status
Simulation time 47925336 ps
CPU time 1.33 seconds
Started Aug 21 06:02:46 PM UTC 24
Finished Aug 21 06:02:48 PM UTC 24
Peak memory 215344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3610214307 -assert no
postproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3610214307
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/3.edn_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/3.edn_intr_test.2052889726
Short name T990
Test name
Test status
Simulation time 17630031 ps
CPU time 1.15 seconds
Started Aug 21 06:02:44 PM UTC 24
Finished Aug 21 06:02:47 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2052889726 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.2052889726
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/3.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/3.edn_same_csr_outstanding.903160131
Short name T282
Test name
Test status
Simulation time 81993138 ps
CPU time 1.97 seconds
Started Aug 21 06:02:46 PM UTC 24
Finished Aug 21 06:02:49 PM UTC 24
Peak memory 215348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=903
160131 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_outst
anding.903160131
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/3.edn_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_errors.2531346737
Short name T994
Test name
Test status
Simulation time 110317766 ps
CPU time 5.43 seconds
Started Aug 21 06:02:43 PM UTC 24
Finished Aug 21 06:02:50 PM UTC 24
Peak memory 227992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2531346737 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2531346737
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/3.edn_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_intg_err.4002552354
Short name T299
Test name
Test status
Simulation time 141982590 ps
CPU time 2.14 seconds
Started Aug 21 06:02:44 PM UTC 24
Finished Aug 21 06:02:48 PM UTC 24
Peak memory 227756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4002552354 -
assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.4002552354
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/3.edn_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/30.edn_intr_test.2016877298
Short name T1092
Test name
Test status
Simulation time 15991517 ps
CPU time 1.24 seconds
Started Aug 21 06:03:15 PM UTC 24
Finished Aug 21 06:03:17 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2016877298 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2016877298
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/30.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/31.edn_intr_test.3714508109
Short name T1093
Test name
Test status
Simulation time 36766228 ps
CPU time 1.25 seconds
Started Aug 21 06:03:15 PM UTC 24
Finished Aug 21 06:03:17 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3714508109 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3714508109
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/31.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/32.edn_intr_test.4165295010
Short name T1094
Test name
Test status
Simulation time 16220939 ps
CPU time 0.9 seconds
Started Aug 21 06:03:16 PM UTC 24
Finished Aug 21 06:03:18 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4165295010 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.4165295010
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/32.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/33.edn_intr_test.3987726764
Short name T1096
Test name
Test status
Simulation time 21321707 ps
CPU time 1.21 seconds
Started Aug 21 06:03:16 PM UTC 24
Finished Aug 21 06:03:19 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3987726764 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3987726764
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/33.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/34.edn_intr_test.4104171452
Short name T1098
Test name
Test status
Simulation time 25412787 ps
CPU time 1.29 seconds
Started Aug 21 06:03:16 PM UTC 24
Finished Aug 21 06:03:19 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4104171452 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.4104171452
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/34.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/35.edn_intr_test.1399781447
Short name T1097
Test name
Test status
Simulation time 33346298 ps
CPU time 1.2 seconds
Started Aug 21 06:03:16 PM UTC 24
Finished Aug 21 06:03:19 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1399781447 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1399781447
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/35.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/36.edn_intr_test.3987553195
Short name T1095
Test name
Test status
Simulation time 16047321 ps
CPU time 1.01 seconds
Started Aug 21 06:03:16 PM UTC 24
Finished Aug 21 06:03:18 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3987553195 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3987553195
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/36.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/37.edn_intr_test.1807636142
Short name T1101
Test name
Test status
Simulation time 162185681 ps
CPU time 1.29 seconds
Started Aug 21 06:03:16 PM UTC 24
Finished Aug 21 06:03:19 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1807636142 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1807636142
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/37.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/38.edn_intr_test.136661875
Short name T1100
Test name
Test status
Simulation time 11466391 ps
CPU time 1.27 seconds
Started Aug 21 06:03:16 PM UTC 24
Finished Aug 21 06:03:19 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=136661875 -assert nopost
proc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.136661875
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/38.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/39.edn_intr_test.598237371
Short name T1105
Test name
Test status
Simulation time 43589563 ps
CPU time 1.27 seconds
Started Aug 21 06:03:17 PM UTC 24
Finished Aug 21 06:03:19 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=598237371 -assert nopost
proc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.598237371
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/39.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_aliasing.3970474281
Short name T274
Test name
Test status
Simulation time 39142553 ps
CPU time 2.2 seconds
Started Aug 21 06:02:49 PM UTC 24
Finished Aug 21 06:02:53 PM UTC 24
Peak memory 217452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3970474281 -ass
ert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.3970474281
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/4.edn_csr_aliasing/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_bit_bash.3689720291
Short name T1007
Test name
Test status
Simulation time 179012254 ps
CPU time 7.07 seconds
Started Aug 21 06:02:49 PM UTC 24
Finished Aug 21 06:02:57 PM UTC 24
Peak memory 217492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3689720291 -ass
ert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.3689720291
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/4.edn_csr_bit_bash/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_hw_reset.127703842
Short name T273
Test name
Test status
Simulation time 31383571 ps
CPU time 1.22 seconds
Started Aug 21 06:02:48 PM UTC 24
Finished Aug 21 06:02:50 PM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=127703842 -asse
rt nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.127703842
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/4.edn_csr_hw_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.4086920944
Short name T996
Test name
Test status
Simulation time 23854615 ps
CPU time 2.17 seconds
Started Aug 21 06:02:49 PM UTC 24
Finished Aug 21 06:02:52 PM UTC 24
Peak memory 228084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=4086920944 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.4086920944
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_rw.2201053657
Short name T283
Test name
Test status
Simulation time 22680877 ps
CPU time 1.29 seconds
Started Aug 21 06:02:49 PM UTC 24
Finished Aug 21 06:02:51 PM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2201053657 -assert no
postproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2201053657
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/4.edn_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/4.edn_intr_test.4012475898
Short name T995
Test name
Test status
Simulation time 113953796 ps
CPU time 1.16 seconds
Started Aug 21 06:02:48 PM UTC 24
Finished Aug 21 06:02:50 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4012475898 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.4012475898
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/4.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/4.edn_same_csr_outstanding.2931304370
Short name T284
Test name
Test status
Simulation time 132404974 ps
CPU time 2.05 seconds
Started Aug 21 06:02:49 PM UTC 24
Finished Aug 21 06:02:53 PM UTC 24
Peak memory 217496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=293
1304370 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_outs
tanding.2931304370
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/4.edn_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_errors.726258067
Short name T999
Test name
Test status
Simulation time 1960698300 ps
CPU time 5.56 seconds
Started Aug 21 06:02:47 PM UTC 24
Finished Aug 21 06:02:54 PM UTC 24
Peak memory 227880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=726258067 -assert nopost
proc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.726258067
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/4.edn_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_intg_err.742256913
Short name T303
Test name
Test status
Simulation time 90289072 ps
CPU time 1.66 seconds
Started Aug 21 06:02:47 PM UTC 24
Finished Aug 21 06:02:50 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=742256913 -a
ssert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri
sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.742256913
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/4.edn_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/40.edn_intr_test.1024002030
Short name T1104
Test name
Test status
Simulation time 16085574 ps
CPU time 1.24 seconds
Started Aug 21 06:03:17 PM UTC 24
Finished Aug 21 06:03:19 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1024002030 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1024002030
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/40.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/41.edn_intr_test.2065839545
Short name T1106
Test name
Test status
Simulation time 29229898 ps
CPU time 1.35 seconds
Started Aug 21 06:03:17 PM UTC 24
Finished Aug 21 06:03:19 PM UTC 24
Peak memory 214920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2065839545 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2065839545
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/41.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/42.edn_intr_test.740918656
Short name T1099
Test name
Test status
Simulation time 31170279 ps
CPU time 1.04 seconds
Started Aug 21 06:03:17 PM UTC 24
Finished Aug 21 06:03:19 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=740918656 -assert nopost
proc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.740918656
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/42.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/43.edn_intr_test.3774854391
Short name T1102
Test name
Test status
Simulation time 14434623 ps
CPU time 1.09 seconds
Started Aug 21 06:03:17 PM UTC 24
Finished Aug 21 06:03:19 PM UTC 24
Peak memory 214844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3774854391 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.3774854391
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/43.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/44.edn_intr_test.3228500882
Short name T1103
Test name
Test status
Simulation time 23485895 ps
CPU time 0.94 seconds
Started Aug 21 06:03:17 PM UTC 24
Finished Aug 21 06:03:19 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3228500882 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3228500882
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/44.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/45.edn_intr_test.791039475
Short name T1107
Test name
Test status
Simulation time 17115354 ps
CPU time 1.18 seconds
Started Aug 21 06:03:17 PM UTC 24
Finished Aug 21 06:03:19 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=791039475 -assert nopost
proc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.791039475
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/45.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/46.edn_intr_test.3145121229
Short name T1108
Test name
Test status
Simulation time 38243419 ps
CPU time 0.89 seconds
Started Aug 21 06:03:18 PM UTC 24
Finished Aug 21 06:03:20 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3145121229 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.3145121229
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/46.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/47.edn_intr_test.1088171122
Short name T1111
Test name
Test status
Simulation time 15710083 ps
CPU time 1.28 seconds
Started Aug 21 06:03:18 PM UTC 24
Finished Aug 21 06:03:20 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1088171122 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1088171122
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/47.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/48.edn_intr_test.1088196079
Short name T1110
Test name
Test status
Simulation time 62188680 ps
CPU time 1.24 seconds
Started Aug 21 06:03:18 PM UTC 24
Finished Aug 21 06:03:20 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1088196079 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.1088196079
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/48.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/49.edn_intr_test.1089449189
Short name T1109
Test name
Test status
Simulation time 21520541 ps
CPU time 1.14 seconds
Started Aug 21 06:03:18 PM UTC 24
Finished Aug 21 06:03:20 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1089449189 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1089449189
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/49.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3573961530
Short name T1001
Test name
Test status
Simulation time 60704014 ps
CPU time 2.21 seconds
Started Aug 21 06:02:52 PM UTC 24
Finished Aug 21 06:02:55 PM UTC 24
Peak memory 227752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=3573961530 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3573961530
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_rw.4239863465
Short name T998
Test name
Test status
Simulation time 15548511 ps
CPU time 1.38 seconds
Started Aug 21 06:02:51 PM UTC 24
Finished Aug 21 06:02:53 PM UTC 24
Peak memory 215344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4239863465 -assert no
postproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.4239863465
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/5.edn_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/5.edn_intr_test.891558186
Short name T997
Test name
Test status
Simulation time 202862136 ps
CPU time 1.38 seconds
Started Aug 21 06:02:51 PM UTC 24
Finished Aug 21 06:02:53 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=891558186 -assert nopost
proc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.891558186
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/5.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/5.edn_same_csr_outstanding.3258497664
Short name T285
Test name
Test status
Simulation time 20149015 ps
CPU time 1.65 seconds
Started Aug 21 06:02:52 PM UTC 24
Finished Aug 21 06:02:54 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=325
8497664 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_outs
tanding.3258497664
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/5.edn_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_errors.1101548746
Short name T1002
Test name
Test status
Simulation time 40638990 ps
CPU time 3.68 seconds
Started Aug 21 06:02:50 PM UTC 24
Finished Aug 21 06:02:55 PM UTC 24
Peak memory 227876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1101548746 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.1101548746
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/5.edn_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_intg_err.1153954129
Short name T1000
Test name
Test status
Simulation time 69842970 ps
CPU time 2.14 seconds
Started Aug 21 06:02:51 PM UTC 24
Finished Aug 21 06:02:54 PM UTC 24
Peak memory 217504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1153954129 -
assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1153954129
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/5.edn_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.641200103
Short name T1006
Test name
Test status
Simulation time 32310217 ps
CPU time 1.71 seconds
Started Aug 21 06:02:54 PM UTC 24
Finished Aug 21 06:02:57 PM UTC 24
Peak memory 225700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=641200103 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.641200103
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_rw.149088390
Short name T276
Test name
Test status
Simulation time 22091874 ps
CPU time 1.26 seconds
Started Aug 21 06:02:54 PM UTC 24
Finished Aug 21 06:02:56 PM UTC 24
Peak memory 215468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=149088390 -assert nop
ostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.149088390
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/6.edn_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/6.edn_intr_test.1298432417
Short name T1003
Test name
Test status
Simulation time 12074775 ps
CPU time 1.29 seconds
Started Aug 21 06:02:54 PM UTC 24
Finished Aug 21 06:02:56 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1298432417 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.1298432417
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/6.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/6.edn_same_csr_outstanding.1323250806
Short name T1005
Test name
Test status
Simulation time 21473857 ps
CPU time 1.62 seconds
Started Aug 21 06:02:54 PM UTC 24
Finished Aug 21 06:02:57 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=132
3250806 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_outs
tanding.1323250806
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/6.edn_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_errors.3437634860
Short name T1008
Test name
Test status
Simulation time 260170079 ps
CPU time 4.26 seconds
Started Aug 21 06:02:53 PM UTC 24
Finished Aug 21 06:02:58 PM UTC 24
Peak memory 227992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3437634860 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3437634860
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/6.edn_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_intg_err.996664178
Short name T302
Test name
Test status
Simulation time 158853657 ps
CPU time 4.33 seconds
Started Aug 21 06:02:54 PM UTC 24
Finished Aug 21 06:02:59 PM UTC 24
Peak memory 217556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=996664178 -a
ssert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri
sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.996664178
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/6.edn_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3355097827
Short name T1010
Test name
Test status
Simulation time 38518585 ps
CPU time 1.65 seconds
Started Aug 21 06:02:56 PM UTC 24
Finished Aug 21 06:02:58 PM UTC 24
Peak memory 225700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=3355097827 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3355097827
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_rw.3546349746
Short name T277
Test name
Test status
Simulation time 16662371 ps
CPU time 1.41 seconds
Started Aug 21 06:02:55 PM UTC 24
Finished Aug 21 06:02:57 PM UTC 24
Peak memory 215344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3546349746 -assert no
postproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.3546349746
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/7.edn_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/7.edn_intr_test.1349933072
Short name T1004
Test name
Test status
Simulation time 49723766 ps
CPU time 1.31 seconds
Started Aug 21 06:02:54 PM UTC 24
Finished Aug 21 06:02:57 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1349933072 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.1349933072
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/7.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/7.edn_same_csr_outstanding.1109770580
Short name T1009
Test name
Test status
Simulation time 84032670 ps
CPU time 1.66 seconds
Started Aug 21 06:02:56 PM UTC 24
Finished Aug 21 06:02:58 PM UTC 24
Peak memory 214952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=110
9770580 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_outs
tanding.1109770580
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/7.edn_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_errors.2303191726
Short name T1011
Test name
Test status
Simulation time 240260664 ps
CPU time 3.03 seconds
Started Aug 21 06:02:54 PM UTC 24
Finished Aug 21 06:02:58 PM UTC 24
Peak memory 227864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2303191726 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2303191726
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/7.edn_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_intg_err.1762853970
Short name T304
Test name
Test status
Simulation time 85176388 ps
CPU time 3.25 seconds
Started Aug 21 06:02:54 PM UTC 24
Finished Aug 21 06:02:59 PM UTC 24
Peak memory 217564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1762853970 -
assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1762853970
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/7.edn_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1097802485
Short name T1016
Test name
Test status
Simulation time 15937074 ps
CPU time 1.43 seconds
Started Aug 21 06:02:58 PM UTC 24
Finished Aug 21 06:03:00 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=1097802485 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1097802485
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_rw.1527428691
Short name T1013
Test name
Test status
Simulation time 25817860 ps
CPU time 1.15 seconds
Started Aug 21 06:02:57 PM UTC 24
Finished Aug 21 06:02:59 PM UTC 24
Peak memory 215344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1527428691 -assert no
postproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1527428691
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/8.edn_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/8.edn_intr_test.2567080309
Short name T1012
Test name
Test status
Simulation time 50208255 ps
CPU time 1.23 seconds
Started Aug 21 06:02:57 PM UTC 24
Finished Aug 21 06:02:59 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2567080309 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2567080309
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/8.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/8.edn_same_csr_outstanding.2242754598
Short name T1017
Test name
Test status
Simulation time 31543047 ps
CPU time 1.88 seconds
Started Aug 21 06:02:58 PM UTC 24
Finished Aug 21 06:03:01 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=224
2754598 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_outs
tanding.2242754598
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/8.edn_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_errors.2850602785
Short name T1014
Test name
Test status
Simulation time 361691161 ps
CPU time 2.69 seconds
Started Aug 21 06:02:56 PM UTC 24
Finished Aug 21 06:02:59 PM UTC 24
Peak memory 227992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2850602785 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.2850602785
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/8.edn_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_intg_err.97337573
Short name T300
Test name
Test status
Simulation time 315842181 ps
CPU time 3.11 seconds
Started Aug 21 06:02:57 PM UTC 24
Finished Aug 21 06:03:01 PM UTC 24
Peak memory 227752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=97337573 -as
sert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris
c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.97337573
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/8.edn_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2575076958
Short name T1021
Test name
Test status
Simulation time 51321102 ps
CPU time 1.42 seconds
Started Aug 21 06:03:00 PM UTC 24
Finished Aug 21 06:03:02 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10
000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv
/tools/sim.tcl +ntb_random_seed=2575076958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.2575076958
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_rw.1973875095
Short name T1019
Test name
Test status
Simulation time 17195458 ps
CPU time 1.13 seconds
Started Aug 21 06:02:59 PM UTC 24
Finished Aug 21 06:03:02 PM UTC 24
Peak memory 214916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1973875095 -assert no
postproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.1973875095
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/9.edn_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/9.edn_intr_test.3048195215
Short name T1015
Test name
Test status
Simulation time 22578660 ps
CPU time 1.08 seconds
Started Aug 21 06:02:58 PM UTC 24
Finished Aug 21 06:03:00 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3048195215 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.3048195215
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/9.edn_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/9.edn_same_csr_outstanding.1043777593
Short name T1022
Test name
Test status
Simulation time 18846794 ps
CPU time 1.46 seconds
Started Aug 21 06:02:59 PM UTC 24
Finished Aug 21 06:03:02 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=104
3777593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_outs
tanding.1043777593
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/9.edn_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_errors.3609089158
Short name T1026
Test name
Test status
Simulation time 206792323 ps
CPU time 3.93 seconds
Started Aug 21 06:02:58 PM UTC 24
Finished Aug 21 06:03:03 PM UTC 24
Peak memory 227860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3609089158 -assert nopos
tproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3609089158
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/9.edn_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_intg_err.2080770381
Short name T301
Test name
Test status
Simulation time 125990530 ps
CPU time 2.58 seconds
Started Aug 21 06:02:58 PM UTC 24
Finished Aug 21 06:03:02 PM UTC 24
Peak memory 217568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2080770381 -
assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr
isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2080770381
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/9.edn_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/0.edn_intr.2302987077
Short name T4
Test name
Test status
Simulation time 21601353 ps
CPU time 1.37 seconds
Started Aug 21 08:50:14 AM UTC 24
Finished Aug 21 08:50:16 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2302987077 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.2302987077
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/0.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/0.edn_regwen.2442576281
Short name T1
Test name
Test status
Simulation time 19532889 ps
CPU time 1.12 seconds
Started Aug 21 08:50:13 AM UTC 24
Finished Aug 21 08:50:15 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2442576281 -assert nopostproc +UVM_TESTNAME=e
dn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1
_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2442576281
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/0.edn_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/0.edn_smoke.3510526934
Short name T2
Test name
Test status
Simulation time 15120588 ps
CPU time 1.38 seconds
Started Aug 21 08:50:13 AM UTC 24
Finished Aug 21 08:50:15 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3510526934 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.3510526934
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/0.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/0.edn_stress_all.3094839080
Short name T6
Test name
Test status
Simulation time 116467543 ps
CPU time 2.72 seconds
Started Aug 21 08:50:14 AM UTC 24
Finished Aug 21 08:50:18 AM UTC 24
Peak memory 227484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3094839080 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.3094839080
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/0.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/1.edn_alert.2884587349
Short name T12
Test name
Test status
Simulation time 198275353 ps
CPU time 1.37 seconds
Started Aug 21 08:50:17 AM UTC 24
Finished Aug 21 08:50:19 AM UTC 24
Peak memory 228204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2884587349 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.2884587349
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/1.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/1.edn_alert_test.3823859074
Short name T70
Test name
Test status
Simulation time 85557593 ps
CPU time 1.15 seconds
Started Aug 21 08:50:18 AM UTC 24
Finished Aug 21 08:50:21 AM UTC 24
Peak memory 216512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3823859074 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.3823859074
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/1.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/1.edn_disable.2366597405
Short name T29
Test name
Test status
Simulation time 40953198 ps
CPU time 1.16 seconds
Started Aug 21 08:50:17 AM UTC 24
Finished Aug 21 08:50:19 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2366597405 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2366597405
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/1.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/1.edn_disable_auto_req_mode.3088935744
Short name T21
Test name
Test status
Simulation time 28371038 ps
CPU time 1.36 seconds
Started Aug 21 08:50:18 AM UTC 24
Finished Aug 21 08:50:21 AM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3088935744 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disa
ble_auto_req_mode.3088935744
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/1.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/1.edn_intr.220657871
Short name T16
Test name
Test status
Simulation time 23243234 ps
CPU time 1.5 seconds
Started Aug 21 08:50:17 AM UTC 24
Finished Aug 21 08:50:19 AM UTC 24
Peak memory 237060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=220657871 -assert nopostproc +UVM_TESTNAME=ed
n_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0
_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.220657871
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/1.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/1.edn_sec_cm.1929663310
Short name T19
Test name
Test status
Simulation time 2802918952 ps
CPU time 10.3 seconds
Started Aug 21 08:50:18 AM UTC 24
Finished Aug 21 08:50:30 AM UTC 24
Peak memory 260628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1929663310 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1929663310
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/1.edn_sec_cm/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/1.edn_smoke.9855077
Short name T25
Test name
Test status
Simulation time 53597756 ps
CPU time 1 seconds
Started Aug 21 08:50:15 AM UTC 24
Finished Aug 21 08:50:18 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=9855077 -assert nopostproc +UVM_TESTNAME=edn_
smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0
_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.9855077
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/1.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/1.edn_stress_all_with_rand_reset.109851071
Short name T38
Test name
Test status
Simulation time 13039450131 ps
CPU time 65.74 seconds
Started Aug 21 08:50:17 AM UTC 24
Finished Aug 21 08:51:24 AM UTC 24
Peak memory 229868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=109851071 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.109851071
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/1.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/10.edn_alert.1480503774
Short name T76
Test name
Test status
Simulation time 24243194 ps
CPU time 1.7 seconds
Started Aug 21 08:50:38 AM UTC 24
Finished Aug 21 08:50:41 AM UTC 24
Peak memory 232120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1480503774 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1480503774
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/10.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/10.edn_alert_test.663196188
Short name T368
Test name
Test status
Simulation time 50827583 ps
CPU time 0.99 seconds
Started Aug 21 08:50:39 AM UTC 24
Finished Aug 21 08:50:41 AM UTC 24
Peak memory 216444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=663196188 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.663196188
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/10.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/10.edn_genbits.3440672297
Short name T46
Test name
Test status
Simulation time 64551712 ps
CPU time 1.34 seconds
Started Aug 21 08:50:38 AM UTC 24
Finished Aug 21 08:50:40 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3440672297 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3440672297
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/10.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/10.edn_intr.1452548645
Short name T367
Test name
Test status
Simulation time 35635962 ps
CPU time 1.21 seconds
Started Aug 21 08:50:38 AM UTC 24
Finished Aug 21 08:50:40 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1452548645 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1452548645
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/10.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/10.edn_smoke.1066290280
Short name T366
Test name
Test status
Simulation time 54926430 ps
CPU time 1.26 seconds
Started Aug 21 08:50:38 AM UTC 24
Finished Aug 21 08:50:40 AM UTC 24
Peak memory 225828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1066290280 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1066290280
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/10.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/10.edn_stress_all.2010768992
Short name T118
Test name
Test status
Simulation time 53347206 ps
CPU time 1.7 seconds
Started Aug 21 08:50:38 AM UTC 24
Finished Aug 21 08:50:40 AM UTC 24
Peak memory 228316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2010768992 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.2010768992
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/10.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/100.edn_genbits.2229094345
Short name T702
Test name
Test status
Simulation time 151174390 ps
CPU time 1.37 seconds
Started Aug 21 08:53:22 AM UTC 24
Finished Aug 21 08:53:24 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2229094345 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2229094345
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/100.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/101.edn_alert.46190971
Short name T704
Test name
Test status
Simulation time 23419249 ps
CPU time 1.5 seconds
Started Aug 21 08:53:22 AM UTC 24
Finished Aug 21 08:53:24 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=46190971 -assert nopostproc +UVM_TESTNAME=edn
_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.46190971
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/101.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/101.edn_genbits.2056550281
Short name T713
Test name
Test status
Simulation time 71493531 ps
CPU time 3.64 seconds
Started Aug 21 08:53:22 AM UTC 24
Finished Aug 21 08:53:27 AM UTC 24
Peak memory 231704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2056550281 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.2056550281
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/101.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/102.edn_alert.105095699
Short name T703
Test name
Test status
Simulation time 70764808 ps
CPU time 1.36 seconds
Started Aug 21 08:53:22 AM UTC 24
Finished Aug 21 08:53:24 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=105095699 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.105095699
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/102.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/102.edn_genbits.1911232556
Short name T707
Test name
Test status
Simulation time 71763144 ps
CPU time 2.12 seconds
Started Aug 21 08:53:22 AM UTC 24
Finished Aug 21 08:53:25 AM UTC 24
Peak memory 231464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1911232556 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.1911232556
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/102.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/103.edn_alert.22971110
Short name T706
Test name
Test status
Simulation time 95866209 ps
CPU time 1.44 seconds
Started Aug 21 08:53:22 AM UTC 24
Finished Aug 21 08:53:25 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=22971110 -assert nopostproc +UVM_TESTNAME=edn
_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.22971110
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/103.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/103.edn_genbits.173334030
Short name T711
Test name
Test status
Simulation time 79481269 ps
CPU time 2.59 seconds
Started Aug 21 08:53:22 AM UTC 24
Finished Aug 21 08:53:26 AM UTC 24
Peak memory 229516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=173334030 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.173334030
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/103.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/104.edn_alert.3545017303
Short name T712
Test name
Test status
Simulation time 83727131 ps
CPU time 1.76 seconds
Started Aug 21 08:53:23 AM UTC 24
Finished Aug 21 08:53:26 AM UTC 24
Peak memory 228432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3545017303 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.3545017303
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/104.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/105.edn_alert.3288542349
Short name T710
Test name
Test status
Simulation time 41045901 ps
CPU time 1.29 seconds
Started Aug 21 08:53:23 AM UTC 24
Finished Aug 21 08:53:26 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3288542349 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.3288542349
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/105.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/105.edn_genbits.980918221
Short name T720
Test name
Test status
Simulation time 130604341 ps
CPU time 3.54 seconds
Started Aug 21 08:53:23 AM UTC 24
Finished Aug 21 08:53:28 AM UTC 24
Peak memory 229724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=980918221 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.980918221
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/105.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/107.edn_alert.2402125676
Short name T716
Test name
Test status
Simulation time 81304593 ps
CPU time 1.51 seconds
Started Aug 21 08:53:24 AM UTC 24
Finished Aug 21 08:53:27 AM UTC 24
Peak memory 226364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2402125676 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.2402125676
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/107.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/107.edn_genbits.905834439
Short name T717
Test name
Test status
Simulation time 67596324 ps
CPU time 1.62 seconds
Started Aug 21 08:53:24 AM UTC 24
Finished Aug 21 08:53:27 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=905834439 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.905834439
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/107.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/108.edn_alert.2087616514
Short name T719
Test name
Test status
Simulation time 42222764 ps
CPU time 1.74 seconds
Started Aug 21 08:53:25 AM UTC 24
Finished Aug 21 08:53:27 AM UTC 24
Peak memory 228432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2087616514 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.2087616514
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/108.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/108.edn_genbits.1121780330
Short name T715
Test name
Test status
Simulation time 40614837 ps
CPU time 1.32 seconds
Started Aug 21 08:53:24 AM UTC 24
Finished Aug 21 08:53:27 AM UTC 24
Peak memory 226512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1121780330 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1121780330
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/108.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/109.edn_alert.2507853679
Short name T718
Test name
Test status
Simulation time 87120282 ps
CPU time 1.51 seconds
Started Aug 21 08:53:25 AM UTC 24
Finished Aug 21 08:53:27 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2507853679 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.2507853679
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/109.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/109.edn_genbits.194009932
Short name T714
Test name
Test status
Simulation time 147453781 ps
CPU time 1.06 seconds
Started Aug 21 08:53:25 AM UTC 24
Finished Aug 21 08:53:27 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=194009932 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.194009932
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/109.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/11.edn_alert.2351704906
Short name T132
Test name
Test status
Simulation time 25928937 ps
CPU time 1.35 seconds
Started Aug 21 08:50:40 AM UTC 24
Finished Aug 21 08:50:43 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2351704906 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2351704906
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/11.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/11.edn_alert_test.584953615
Short name T369
Test name
Test status
Simulation time 122788183 ps
CPU time 0.96 seconds
Started Aug 21 08:50:42 AM UTC 24
Finished Aug 21 08:50:44 AM UTC 24
Peak memory 216256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=584953615 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.584953615
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/11.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/11.edn_disable.3399121742
Short name T78
Test name
Test status
Simulation time 19937865 ps
CPU time 1.19 seconds
Started Aug 21 08:50:41 AM UTC 24
Finished Aug 21 08:50:43 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3399121742 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3399121742
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/11.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/11.edn_disable_auto_req_mode.2139499099
Short name T126
Test name
Test status
Simulation time 37652375 ps
CPU time 1.22 seconds
Started Aug 21 08:50:41 AM UTC 24
Finished Aug 21 08:50:43 AM UTC 24
Peak memory 226264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2139499099 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_dis
able_auto_req_mode.2139499099
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/11.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/11.edn_err.2604223168
Short name T228
Test name
Test status
Simulation time 59638494 ps
CPU time 1.32 seconds
Started Aug 21 08:50:40 AM UTC 24
Finished Aug 21 08:50:43 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2604223168 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.2604223168
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/11.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/11.edn_smoke.3925708191
Short name T311
Test name
Test status
Simulation time 31846004 ps
CPU time 1.28 seconds
Started Aug 21 08:50:39 AM UTC 24
Finished Aug 21 08:50:41 AM UTC 24
Peak memory 216028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3925708191 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.3925708191
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/11.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/11.edn_stress_all.351798590
Short name T290
Test name
Test status
Simulation time 116136357 ps
CPU time 1.96 seconds
Started Aug 21 08:50:40 AM UTC 24
Finished Aug 21 08:50:43 AM UTC 24
Peak memory 228320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=351798590 -asser
t nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.351798590
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/11.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/11.edn_stress_all_with_rand_reset.1793879332
Short name T237
Test name
Test status
Simulation time 10566175156 ps
CPU time 68.43 seconds
Started Aug 21 08:50:40 AM UTC 24
Finished Aug 21 08:51:51 AM UTC 24
Peak memory 234364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1793879332 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.1793879332
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/11.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/110.edn_genbits.1381141112
Short name T722
Test name
Test status
Simulation time 49427333 ps
CPU time 1.65 seconds
Started Aug 21 08:53:26 AM UTC 24
Finished Aug 21 08:53:28 AM UTC 24
Peak memory 230336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1381141112 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.1381141112
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/110.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/111.edn_alert.2579827569
Short name T723
Test name
Test status
Simulation time 107675543 ps
CPU time 1.54 seconds
Started Aug 21 08:53:26 AM UTC 24
Finished Aug 21 08:53:28 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2579827569 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.2579827569
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/111.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/111.edn_genbits.2514545002
Short name T734
Test name
Test status
Simulation time 78619387 ps
CPU time 3.64 seconds
Started Aug 21 08:53:26 AM UTC 24
Finished Aug 21 08:53:30 AM UTC 24
Peak memory 231564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2514545002 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.2514545002
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/111.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/112.edn_alert.3929165522
Short name T725
Test name
Test status
Simulation time 45841103 ps
CPU time 1.65 seconds
Started Aug 21 08:53:26 AM UTC 24
Finished Aug 21 08:53:29 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3929165522 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.3929165522
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/112.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/112.edn_genbits.3504411862
Short name T724
Test name
Test status
Simulation time 41663027 ps
CPU time 1.6 seconds
Started Aug 21 08:53:26 AM UTC 24
Finished Aug 21 08:53:29 AM UTC 24
Peak memory 230608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3504411862 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.3504411862
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/112.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/113.edn_alert.3391948009
Short name T729
Test name
Test status
Simulation time 292396347 ps
CPU time 1.65 seconds
Started Aug 21 08:53:27 AM UTC 24
Finished Aug 21 08:53:30 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3391948009 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.3391948009
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/113.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/113.edn_genbits.2683557925
Short name T727
Test name
Test status
Simulation time 33689237 ps
CPU time 1.53 seconds
Started Aug 21 08:53:27 AM UTC 24
Finished Aug 21 08:53:30 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2683557925 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.2683557925
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/113.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/114.edn_alert.3339338031
Short name T728
Test name
Test status
Simulation time 57512027 ps
CPU time 1.48 seconds
Started Aug 21 08:53:27 AM UTC 24
Finished Aug 21 08:53:30 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3339338031 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.3339338031
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/114.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/114.edn_genbits.3263952608
Short name T730
Test name
Test status
Simulation time 107507051 ps
CPU time 1.76 seconds
Started Aug 21 08:53:27 AM UTC 24
Finished Aug 21 08:53:30 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3263952608 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3263952608
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/114.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/115.edn_alert.1937737162
Short name T731
Test name
Test status
Simulation time 189589333 ps
CPU time 1.6 seconds
Started Aug 21 08:53:27 AM UTC 24
Finished Aug 21 08:53:30 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1937737162 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.1937737162
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/115.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/115.edn_genbits.580034292
Short name T726
Test name
Test status
Simulation time 58375644 ps
CPU time 1.29 seconds
Started Aug 21 08:53:27 AM UTC 24
Finished Aug 21 08:53:29 AM UTC 24
Peak memory 230420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=580034292 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.580034292
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/115.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/116.edn_alert.2312502992
Short name T733
Test name
Test status
Simulation time 32136132 ps
CPU time 1.89 seconds
Started Aug 21 08:53:27 AM UTC 24
Finished Aug 21 08:53:30 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2312502992 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.2312502992
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/116.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/116.edn_genbits.3415212907
Short name T732
Test name
Test status
Simulation time 57131619 ps
CPU time 1.79 seconds
Started Aug 21 08:53:27 AM UTC 24
Finished Aug 21 08:53:30 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3415212907 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.3415212907
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/116.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/117.edn_alert.2548539962
Short name T735
Test name
Test status
Simulation time 73913501 ps
CPU time 1.38 seconds
Started Aug 21 08:53:29 AM UTC 24
Finished Aug 21 08:53:31 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2548539962 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.2548539962
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/117.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/117.edn_genbits.1475523989
Short name T328
Test name
Test status
Simulation time 180685670 ps
CPU time 2.74 seconds
Started Aug 21 08:53:28 AM UTC 24
Finished Aug 21 08:53:32 AM UTC 24
Peak memory 231576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1475523989 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.1475523989
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/117.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/118.edn_genbits.1097922395
Short name T736
Test name
Test status
Simulation time 58577442 ps
CPU time 1.48 seconds
Started Aug 21 08:53:29 AM UTC 24
Finished Aug 21 08:53:31 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1097922395 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1097922395
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/118.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/119.edn_alert.1850871858
Short name T737
Test name
Test status
Simulation time 121730561 ps
CPU time 1.71 seconds
Started Aug 21 08:53:29 AM UTC 24
Finished Aug 21 08:53:31 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1850871858 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.1850871858
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/119.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/119.edn_genbits.1486659715
Short name T738
Test name
Test status
Simulation time 62311297 ps
CPU time 2.3 seconds
Started Aug 21 08:53:29 AM UTC 24
Finished Aug 21 08:53:32 AM UTC 24
Peak memory 231748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1486659715 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.1486659715
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/119.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/12.edn_alert.4157937299
Short name T89
Test name
Test status
Simulation time 28097015 ps
CPU time 1.79 seconds
Started Aug 21 08:50:42 AM UTC 24
Finished Aug 21 08:50:45 AM UTC 24
Peak memory 230484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4157937299 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.4157937299
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/12.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/12.edn_alert_test.2494895600
Short name T373
Test name
Test status
Simulation time 81361253 ps
CPU time 1.1 seconds
Started Aug 21 08:50:43 AM UTC 24
Finished Aug 21 08:50:45 AM UTC 24
Peak memory 226732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2494895600 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2494895600
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/12.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/12.edn_disable.3216149527
Short name T101
Test name
Test status
Simulation time 41683694 ps
CPU time 1.23 seconds
Started Aug 21 08:50:43 AM UTC 24
Finished Aug 21 08:50:45 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3216149527 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.3216149527
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/12.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/12.edn_disable_auto_req_mode.3984256893
Short name T149
Test name
Test status
Simulation time 48028694 ps
CPU time 1.62 seconds
Started Aug 21 08:50:43 AM UTC 24
Finished Aug 21 08:50:46 AM UTC 24
Peak memory 226264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3984256893 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_dis
able_auto_req_mode.3984256893
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/12.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/12.edn_err.3677095013
Short name T174
Test name
Test status
Simulation time 28394364 ps
CPU time 1.53 seconds
Started Aug 21 08:50:42 AM UTC 24
Finished Aug 21 08:50:45 AM UTC 24
Peak memory 242248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3677095013 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3677095013
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/12.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/12.edn_genbits.958309919
Short name T52
Test name
Test status
Simulation time 59169564 ps
CPU time 1.99 seconds
Started Aug 21 08:50:42 AM UTC 24
Finished Aug 21 08:50:45 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=958309919 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.958309919
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/12.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/12.edn_intr.4157320737
Short name T372
Test name
Test status
Simulation time 23250069 ps
CPU time 1.63 seconds
Started Aug 21 08:50:42 AM UTC 24
Finished Aug 21 08:50:45 AM UTC 24
Peak memory 237820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4157320737 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.4157320737
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/12.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/12.edn_smoke.2750093491
Short name T370
Test name
Test status
Simulation time 53261096 ps
CPU time 1.26 seconds
Started Aug 21 08:50:42 AM UTC 24
Finished Aug 21 08:50:44 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2750093491 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2750093491
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/12.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/12.edn_stress_all.236710679
Short name T371
Test name
Test status
Simulation time 78947752 ps
CPU time 1.59 seconds
Started Aug 21 08:50:42 AM UTC 24
Finished Aug 21 08:50:44 AM UTC 24
Peak memory 216684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=236710679 -asser
t nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.236710679
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/12.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/12.edn_stress_all_with_rand_reset.624791544
Short name T236
Test name
Test status
Simulation time 2801860726 ps
CPU time 63.61 seconds
Started Aug 21 08:50:42 AM UTC 24
Finished Aug 21 08:51:47 AM UTC 24
Peak memory 229984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=624791544 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.624791544
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/12.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/120.edn_alert.335332169
Short name T741
Test name
Test status
Simulation time 27279951 ps
CPU time 1.57 seconds
Started Aug 21 08:53:30 AM UTC 24
Finished Aug 21 08:53:32 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=335332169 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.335332169
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/120.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/120.edn_genbits.3145653660
Short name T742
Test name
Test status
Simulation time 63024944 ps
CPU time 1.67 seconds
Started Aug 21 08:53:30 AM UTC 24
Finished Aug 21 08:53:32 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3145653660 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3145653660
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/120.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/121.edn_alert.3195026067
Short name T740
Test name
Test status
Simulation time 41389549 ps
CPU time 1.43 seconds
Started Aug 21 08:53:30 AM UTC 24
Finished Aug 21 08:53:32 AM UTC 24
Peak memory 228432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3195026067 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.3195026067
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/121.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/121.edn_genbits.3687681524
Short name T739
Test name
Test status
Simulation time 40449362 ps
CPU time 1.14 seconds
Started Aug 21 08:53:30 AM UTC 24
Finished Aug 21 08:53:32 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3687681524 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.3687681524
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/121.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/123.edn_alert.228877890
Short name T746
Test name
Test status
Simulation time 46176846 ps
CPU time 1.49 seconds
Started Aug 21 08:53:31 AM UTC 24
Finished Aug 21 08:53:34 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=228877890 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.228877890
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/123.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/123.edn_genbits.1003213818
Short name T334
Test name
Test status
Simulation time 39195209 ps
CPU time 1.44 seconds
Started Aug 21 08:53:31 AM UTC 24
Finished Aug 21 08:53:34 AM UTC 24
Peak memory 230608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1003213818 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1003213818
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/123.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/124.edn_alert.1138063370
Short name T745
Test name
Test status
Simulation time 56658860 ps
CPU time 1.37 seconds
Started Aug 21 08:53:31 AM UTC 24
Finished Aug 21 08:53:34 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1138063370 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.1138063370
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/124.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/124.edn_genbits.4035218926
Short name T747
Test name
Test status
Simulation time 95006665 ps
CPU time 1.51 seconds
Started Aug 21 08:53:31 AM UTC 24
Finished Aug 21 08:53:34 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4035218926 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.4035218926
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/124.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/125.edn_alert.3570300546
Short name T749
Test name
Test status
Simulation time 43143891 ps
CPU time 1.55 seconds
Started Aug 21 08:53:31 AM UTC 24
Finished Aug 21 08:53:34 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3570300546 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.3570300546
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/125.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/125.edn_genbits.3159427979
Short name T748
Test name
Test status
Simulation time 47564015 ps
CPU time 1.6 seconds
Started Aug 21 08:53:31 AM UTC 24
Finished Aug 21 08:53:34 AM UTC 24
Peak memory 228560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3159427979 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.3159427979
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/125.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/126.edn_alert.3973029957
Short name T751
Test name
Test status
Simulation time 42796717 ps
CPU time 1.23 seconds
Started Aug 21 08:53:32 AM UTC 24
Finished Aug 21 08:53:35 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3973029957 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.3973029957
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/126.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/126.edn_genbits.54979618
Short name T750
Test name
Test status
Simulation time 49200752 ps
CPU time 1.48 seconds
Started Aug 21 08:53:31 AM UTC 24
Finished Aug 21 08:53:34 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=54979618 -assert nopostproc +UVM_TESTNAME=edn
_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_
1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.54979618
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/126.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/127.edn_alert.270681904
Short name T260
Test name
Test status
Simulation time 111585036 ps
CPU time 1.46 seconds
Started Aug 21 08:53:33 AM UTC 24
Finished Aug 21 08:53:35 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=270681904 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.270681904
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/127.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/127.edn_genbits.2098153324
Short name T752
Test name
Test status
Simulation time 66989199 ps
CPU time 1.37 seconds
Started Aug 21 08:53:32 AM UTC 24
Finished Aug 21 08:53:35 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2098153324 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2098153324
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/127.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/128.edn_alert.862218274
Short name T754
Test name
Test status
Simulation time 50435058 ps
CPU time 1.35 seconds
Started Aug 21 08:53:33 AM UTC 24
Finished Aug 21 08:53:35 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=862218274 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.862218274
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/128.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/128.edn_genbits.2635654189
Short name T756
Test name
Test status
Simulation time 87865803 ps
CPU time 1.97 seconds
Started Aug 21 08:53:33 AM UTC 24
Finished Aug 21 08:53:36 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2635654189 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.2635654189
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/128.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/129.edn_alert.3870008014
Short name T753
Test name
Test status
Simulation time 24114758 ps
CPU time 1.26 seconds
Started Aug 21 08:53:33 AM UTC 24
Finished Aug 21 08:53:35 AM UTC 24
Peak memory 228432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3870008014 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.3870008014
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/129.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/13.edn_alert_test.1518392212
Short name T376
Test name
Test status
Simulation time 12100944 ps
CPU time 1.09 seconds
Started Aug 21 08:50:46 AM UTC 24
Finished Aug 21 08:50:48 AM UTC 24
Peak memory 216376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1518392212 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.1518392212
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/13.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/13.edn_disable.3871067086
Short name T230
Test name
Test status
Simulation time 35682814 ps
CPU time 1 seconds
Started Aug 21 08:50:45 AM UTC 24
Finished Aug 21 08:50:47 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3871067086 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.3871067086
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/13.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/13.edn_disable_auto_req_mode.690706198
Short name T124
Test name
Test status
Simulation time 60226948 ps
CPU time 2.4 seconds
Started Aug 21 08:50:46 AM UTC 24
Finished Aug 21 08:50:49 AM UTC 24
Peak memory 232172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=690706198 -assert no
postproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disa
ble_auto_req_mode.690706198
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/13.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/13.edn_err.3505806843
Short name T177
Test name
Test status
Simulation time 74740956 ps
CPU time 1.6 seconds
Started Aug 21 08:50:45 AM UTC 24
Finished Aug 21 08:50:47 AM UTC 24
Peak memory 242076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3505806843 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3505806843
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/13.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/13.edn_intr.283892682
Short name T35
Test name
Test status
Simulation time 66376806 ps
CPU time 1.04 seconds
Started Aug 21 08:50:45 AM UTC 24
Finished Aug 21 08:50:47 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=283892682 -assert nopostproc +UVM_TESTNAME=ed
n_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0
_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.283892682
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/13.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/13.edn_smoke.3439074434
Short name T374
Test name
Test status
Simulation time 20696998 ps
CPU time 1.28 seconds
Started Aug 21 08:50:43 AM UTC 24
Finished Aug 21 08:50:46 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3439074434 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.3439074434
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/13.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/13.edn_stress_all.736690500
Short name T375
Test name
Test status
Simulation time 222120400 ps
CPU time 1.74 seconds
Started Aug 21 08:50:43 AM UTC 24
Finished Aug 21 08:50:46 AM UTC 24
Peak memory 226272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=736690500 -asser
t nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.736690500
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/13.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/13.edn_stress_all_with_rand_reset.4208583856
Short name T39
Test name
Test status
Simulation time 1897945037 ps
CPU time 45.24 seconds
Started Aug 21 08:50:44 AM UTC 24
Finished Aug 21 08:51:31 AM UTC 24
Peak memory 229792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4208583856 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.4208583856
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/13.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/130.edn_alert.3946782951
Short name T759
Test name
Test status
Simulation time 71373014 ps
CPU time 1.61 seconds
Started Aug 21 08:53:34 AM UTC 24
Finished Aug 21 08:53:36 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3946782951 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.3946782951
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/130.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/130.edn_genbits.1097786405
Short name T755
Test name
Test status
Simulation time 48760552 ps
CPU time 1.58 seconds
Started Aug 21 08:53:33 AM UTC 24
Finished Aug 21 08:53:35 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1097786405 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1097786405
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/130.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/131.edn_alert.531803670
Short name T758
Test name
Test status
Simulation time 35491021 ps
CPU time 1.39 seconds
Started Aug 21 08:53:34 AM UTC 24
Finished Aug 21 08:53:36 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=531803670 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.531803670
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/131.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/131.edn_genbits.852077184
Short name T764
Test name
Test status
Simulation time 140094517 ps
CPU time 2.73 seconds
Started Aug 21 08:53:34 AM UTC 24
Finished Aug 21 08:53:38 AM UTC 24
Peak memory 231964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=852077184 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.852077184
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/131.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/132.edn_alert.897388891
Short name T261
Test name
Test status
Simulation time 26673834 ps
CPU time 1.43 seconds
Started Aug 21 08:53:34 AM UTC 24
Finished Aug 21 08:53:36 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=897388891 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.897388891
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/132.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/132.edn_genbits.86214158
Short name T757
Test name
Test status
Simulation time 205107666 ps
CPU time 1.14 seconds
Started Aug 21 08:53:34 AM UTC 24
Finished Aug 21 08:53:36 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=86214158 -assert nopostproc +UVM_TESTNAME=edn
_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_
1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.86214158
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/132.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/133.edn_alert.3297176689
Short name T198
Test name
Test status
Simulation time 67184536 ps
CPU time 1.37 seconds
Started Aug 21 08:53:34 AM UTC 24
Finished Aug 21 08:53:36 AM UTC 24
Peak memory 228432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3297176689 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.3297176689
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/133.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/133.edn_genbits.4134095128
Short name T761
Test name
Test status
Simulation time 50971774 ps
CPU time 1.78 seconds
Started Aug 21 08:53:34 AM UTC 24
Finished Aug 21 08:53:37 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4134095128 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.4134095128
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/133.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/134.edn_alert.1945023077
Short name T768
Test name
Test status
Simulation time 128893051 ps
CPU time 1.89 seconds
Started Aug 21 08:53:35 AM UTC 24
Finished Aug 21 08:53:38 AM UTC 24
Peak memory 228432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1945023077 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.1945023077
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/134.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/134.edn_genbits.2702791777
Short name T760
Test name
Test status
Simulation time 40824408 ps
CPU time 1.39 seconds
Started Aug 21 08:53:34 AM UTC 24
Finished Aug 21 08:53:37 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2702791777 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2702791777
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/134.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/135.edn_alert.1095242361
Short name T763
Test name
Test status
Simulation time 103288215 ps
CPU time 1.41 seconds
Started Aug 21 08:53:35 AM UTC 24
Finished Aug 21 08:53:38 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1095242361 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.1095242361
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/135.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/136.edn_alert.2758694623
Short name T765
Test name
Test status
Simulation time 76409599 ps
CPU time 1.34 seconds
Started Aug 21 08:53:35 AM UTC 24
Finished Aug 21 08:53:38 AM UTC 24
Peak memory 228432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2758694623 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.2758694623
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/136.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/136.edn_genbits.3751141379
Short name T762
Test name
Test status
Simulation time 24952997 ps
CPU time 1.2 seconds
Started Aug 21 08:53:35 AM UTC 24
Finished Aug 21 08:53:37 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3751141379 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3751141379
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/136.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/137.edn_alert.3216040375
Short name T767
Test name
Test status
Simulation time 210133394 ps
CPU time 1.58 seconds
Started Aug 21 08:53:35 AM UTC 24
Finished Aug 21 08:53:38 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3216040375 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.3216040375
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/137.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/137.edn_genbits.268163562
Short name T769
Test name
Test status
Simulation time 40140531 ps
CPU time 1.73 seconds
Started Aug 21 08:53:35 AM UTC 24
Finished Aug 21 08:53:38 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=268163562 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.268163562
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/137.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/138.edn_alert.3679023387
Short name T771
Test name
Test status
Simulation time 28851414 ps
CPU time 1.39 seconds
Started Aug 21 08:53:37 AM UTC 24
Finished Aug 21 08:53:39 AM UTC 24
Peak memory 228432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3679023387 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.3679023387
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/138.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/138.edn_genbits.2237328867
Short name T766
Test name
Test status
Simulation time 34895476 ps
CPU time 1.46 seconds
Started Aug 21 08:53:36 AM UTC 24
Finished Aug 21 08:53:38 AM UTC 24
Peak memory 230608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2237328867 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.2237328867
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/138.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/139.edn_alert.3748775499
Short name T773
Test name
Test status
Simulation time 32335970 ps
CPU time 1.48 seconds
Started Aug 21 08:53:37 AM UTC 24
Finished Aug 21 08:53:39 AM UTC 24
Peak memory 226384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3748775499 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.3748775499
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/139.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/139.edn_genbits.3495585073
Short name T770
Test name
Test status
Simulation time 52819784 ps
CPU time 1.28 seconds
Started Aug 21 08:53:37 AM UTC 24
Finished Aug 21 08:53:39 AM UTC 24
Peak memory 230608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3495585073 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3495585073
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/139.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/14.edn_alert.1215530891
Short name T86
Test name
Test status
Simulation time 30096950 ps
CPU time 1.78 seconds
Started Aug 21 08:50:47 AM UTC 24
Finished Aug 21 08:50:50 AM UTC 24
Peak memory 230484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1215530891 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.1215530891
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/14.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/14.edn_alert_test.2777568657
Short name T379
Test name
Test status
Simulation time 270406926 ps
CPU time 1.43 seconds
Started Aug 21 08:50:47 AM UTC 24
Finished Aug 21 08:50:50 AM UTC 24
Peak memory 226932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2777568657 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.2777568657
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/14.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/14.edn_disable.278748499
Short name T102
Test name
Test status
Simulation time 23125276 ps
CPU time 1.2 seconds
Started Aug 21 08:50:47 AM UTC 24
Finished Aug 21 08:50:49 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=278748499 -assert no
postproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o
pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.278748499
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/14.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/14.edn_err.3517934057
Short name T215
Test name
Test status
Simulation time 132446326 ps
CPU time 1.62 seconds
Started Aug 21 08:50:47 AM UTC 24
Finished Aug 21 08:50:50 AM UTC 24
Peak memory 242188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3517934057 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.3517934057
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/14.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/14.edn_genbits.2691835835
Short name T80
Test name
Test status
Simulation time 83596010 ps
CPU time 1.75 seconds
Started Aug 21 08:50:46 AM UTC 24
Finished Aug 21 08:50:49 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2691835835 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2691835835
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/14.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/14.edn_smoke.3551047205
Short name T377
Test name
Test status
Simulation time 29291546 ps
CPU time 1.37 seconds
Started Aug 21 08:50:46 AM UTC 24
Finished Aug 21 08:50:48 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3551047205 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.3551047205
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/14.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/14.edn_stress_all.1398515353
Short name T129
Test name
Test status
Simulation time 217227820 ps
CPU time 4.73 seconds
Started Aug 21 08:50:46 AM UTC 24
Finished Aug 21 08:50:52 AM UTC 24
Peak memory 227472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1398515353 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1398515353
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/14.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/14.edn_stress_all_with_rand_reset.971617898
Short name T246
Test name
Test status
Simulation time 36480000370 ps
CPU time 97.2 seconds
Started Aug 21 08:50:46 AM UTC 24
Finished Aug 21 08:52:25 AM UTC 24
Peak memory 234212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=971617898 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.971617898
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/14.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/140.edn_alert.3091137031
Short name T774
Test name
Test status
Simulation time 46269102 ps
CPU time 1.4 seconds
Started Aug 21 08:53:37 AM UTC 24
Finished Aug 21 08:53:39 AM UTC 24
Peak memory 228432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3091137031 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.3091137031
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/140.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/140.edn_genbits.193468745
Short name T778
Test name
Test status
Simulation time 104333282 ps
CPU time 1.85 seconds
Started Aug 21 08:53:37 AM UTC 24
Finished Aug 21 08:53:40 AM UTC 24
Peak memory 230420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=193468745 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.193468745
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/140.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/141.edn_alert.1775633547
Short name T777
Test name
Test status
Simulation time 85935045 ps
CPU time 1.62 seconds
Started Aug 21 08:53:37 AM UTC 24
Finished Aug 21 08:53:40 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1775633547 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.1775633547
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/141.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/141.edn_genbits.1133170997
Short name T776
Test name
Test status
Simulation time 90017695 ps
CPU time 1.51 seconds
Started Aug 21 08:53:37 AM UTC 24
Finished Aug 21 08:53:39 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1133170997 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1133170997
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/141.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/142.edn_alert.3677385197
Short name T781
Test name
Test status
Simulation time 30954897 ps
CPU time 1.5 seconds
Started Aug 21 08:53:38 AM UTC 24
Finished Aug 21 08:53:40 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3677385197 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.3677385197
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/142.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/142.edn_genbits.2412898794
Short name T772
Test name
Test status
Simulation time 197748174 ps
CPU time 1.15 seconds
Started Aug 21 08:53:37 AM UTC 24
Finished Aug 21 08:53:39 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2412898794 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2412898794
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/142.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/143.edn_alert.3101896370
Short name T199
Test name
Test status
Simulation time 254940576 ps
CPU time 1.29 seconds
Started Aug 21 08:53:38 AM UTC 24
Finished Aug 21 08:53:40 AM UTC 24
Peak memory 228432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3101896370 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.3101896370
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/143.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/143.edn_genbits.2752545715
Short name T779
Test name
Test status
Simulation time 54756053 ps
CPU time 1.36 seconds
Started Aug 21 08:53:38 AM UTC 24
Finished Aug 21 08:53:40 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2752545715 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2752545715
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/143.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/144.edn_alert.458573883
Short name T780
Test name
Test status
Simulation time 33869293 ps
CPU time 1.22 seconds
Started Aug 21 08:53:38 AM UTC 24
Finished Aug 21 08:53:40 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=458573883 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.458573883
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/144.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/144.edn_genbits.3960078438
Short name T786
Test name
Test status
Simulation time 43127830 ps
CPU time 1.93 seconds
Started Aug 21 08:53:38 AM UTC 24
Finished Aug 21 08:53:41 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3960078438 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.3960078438
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/144.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/145.edn_alert.2921613238
Short name T784
Test name
Test status
Simulation time 53732520 ps
CPU time 1.38 seconds
Started Aug 21 08:53:38 AM UTC 24
Finished Aug 21 08:53:41 AM UTC 24
Peak memory 228432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2921613238 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.2921613238
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/145.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/145.edn_genbits.2879316414
Short name T783
Test name
Test status
Simulation time 57493867 ps
CPU time 1.32 seconds
Started Aug 21 08:53:38 AM UTC 24
Finished Aug 21 08:53:41 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2879316414 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2879316414
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/145.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/146.edn_alert.3424885038
Short name T785
Test name
Test status
Simulation time 42511412 ps
CPU time 1.46 seconds
Started Aug 21 08:53:38 AM UTC 24
Finished Aug 21 08:53:41 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3424885038 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.3424885038
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/146.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/146.edn_genbits.426520203
Short name T782
Test name
Test status
Simulation time 206854640 ps
CPU time 1.2 seconds
Started Aug 21 08:53:38 AM UTC 24
Finished Aug 21 08:53:41 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=426520203 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.426520203
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/146.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/147.edn_alert.1050561270
Short name T788
Test name
Test status
Simulation time 23797871 ps
CPU time 1.2 seconds
Started Aug 21 08:53:39 AM UTC 24
Finished Aug 21 08:53:42 AM UTC 24
Peak memory 228432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1050561270 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.1050561270
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/147.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/147.edn_genbits.3858514090
Short name T787
Test name
Test status
Simulation time 67134049 ps
CPU time 1.1 seconds
Started Aug 21 08:53:39 AM UTC 24
Finished Aug 21 08:53:41 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3858514090 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3858514090
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/147.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/148.edn_genbits.1828405741
Short name T799
Test name
Test status
Simulation time 140360323 ps
CPU time 3.59 seconds
Started Aug 21 08:53:39 AM UTC 24
Finished Aug 21 08:53:44 AM UTC 24
Peak memory 231548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1828405741 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.1828405741
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/148.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/149.edn_alert.1581854629
Short name T792
Test name
Test status
Simulation time 94548045 ps
CPU time 1.51 seconds
Started Aug 21 08:53:40 AM UTC 24
Finished Aug 21 08:53:42 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1581854629 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.1581854629
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/149.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/149.edn_genbits.1922373150
Short name T791
Test name
Test status
Simulation time 49154073 ps
CPU time 1.41 seconds
Started Aug 21 08:53:39 AM UTC 24
Finished Aug 21 08:53:42 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1922373150 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1922373150
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/149.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/15.edn_alert.733528336
Short name T185
Test name
Test status
Simulation time 23388952 ps
CPU time 1.26 seconds
Started Aug 21 08:50:50 AM UTC 24
Finished Aug 21 08:50:52 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=733528336 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.733528336
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/15.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/15.edn_alert_test.119075391
Short name T380
Test name
Test status
Simulation time 15171664 ps
CPU time 1.21 seconds
Started Aug 21 08:50:51 AM UTC 24
Finished Aug 21 08:50:53 AM UTC 24
Peak memory 217044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=119075391 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.119075391
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/15.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/15.edn_disable.2331065620
Short name T127
Test name
Test status
Simulation time 16582796 ps
CPU time 1.36 seconds
Started Aug 21 08:50:50 AM UTC 24
Finished Aug 21 08:50:52 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2331065620 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.2331065620
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/15.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/15.edn_err.1285123917
Short name T175
Test name
Test status
Simulation time 28655121 ps
CPU time 1.24 seconds
Started Aug 21 08:50:50 AM UTC 24
Finished Aug 21 08:50:52 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1285123917 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1285123917
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/15.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/15.edn_intr.2081577738
Short name T119
Test name
Test status
Simulation time 22394212 ps
CPU time 1.57 seconds
Started Aug 21 08:50:50 AM UTC 24
Finished Aug 21 08:50:52 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2081577738 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2081577738
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/15.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/15.edn_smoke.2227047988
Short name T378
Test name
Test status
Simulation time 181097618 ps
CPU time 1.31 seconds
Started Aug 21 08:50:47 AM UTC 24
Finished Aug 21 08:50:50 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2227047988 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2227047988
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/15.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/15.edn_stress_all.1818524501
Short name T130
Test name
Test status
Simulation time 391212136 ps
CPU time 3.07 seconds
Started Aug 21 08:50:49 AM UTC 24
Finished Aug 21 08:50:53 AM UTC 24
Peak memory 229712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1818524501 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1818524501
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/15.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/150.edn_alert.3375959711
Short name T790
Test name
Test status
Simulation time 40023211 ps
CPU time 1.23 seconds
Started Aug 21 08:53:40 AM UTC 24
Finished Aug 21 08:53:42 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3375959711 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.3375959711
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/150.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/150.edn_genbits.3162283371
Short name T789
Test name
Test status
Simulation time 27504222 ps
CPU time 1.33 seconds
Started Aug 21 08:53:40 AM UTC 24
Finished Aug 21 08:53:42 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3162283371 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3162283371
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/150.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/151.edn_alert.97923783
Short name T795
Test name
Test status
Simulation time 48336642 ps
CPU time 1.39 seconds
Started Aug 21 08:53:41 AM UTC 24
Finished Aug 21 08:53:43 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=97923783 -assert nopostproc +UVM_TESTNAME=edn
_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.97923783
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/151.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/151.edn_genbits.4037450726
Short name T797
Test name
Test status
Simulation time 40736256 ps
CPU time 1.96 seconds
Started Aug 21 08:53:41 AM UTC 24
Finished Aug 21 08:53:44 AM UTC 24
Peak memory 227904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4037450726 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.4037450726
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/151.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/152.edn_alert.1342399036
Short name T796
Test name
Test status
Simulation time 25055312 ps
CPU time 1.43 seconds
Started Aug 21 08:53:41 AM UTC 24
Finished Aug 21 08:53:43 AM UTC 24
Peak memory 228432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1342399036 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.1342399036
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/152.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/152.edn_genbits.1918578527
Short name T794
Test name
Test status
Simulation time 176185178 ps
CPU time 1.31 seconds
Started Aug 21 08:53:41 AM UTC 24
Finished Aug 21 08:53:43 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1918578527 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.1918578527
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/152.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/153.edn_alert.2590686257
Short name T793
Test name
Test status
Simulation time 93358136 ps
CPU time 1.2 seconds
Started Aug 21 08:53:41 AM UTC 24
Finished Aug 21 08:53:43 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2590686257 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.2590686257
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/153.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/154.edn_genbits.2910564728
Short name T346
Test name
Test status
Simulation time 170365192 ps
CPU time 1.45 seconds
Started Aug 21 08:53:41 AM UTC 24
Finished Aug 21 08:53:43 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2910564728 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2910564728
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/154.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/155.edn_alert.2285261727
Short name T800
Test name
Test status
Simulation time 128969163 ps
CPU time 1.21 seconds
Started Aug 21 08:53:42 AM UTC 24
Finished Aug 21 08:53:44 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2285261727 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.2285261727
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/155.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/156.edn_alert.4246131761
Short name T805
Test name
Test status
Simulation time 40072853 ps
CPU time 1.48 seconds
Started Aug 21 08:53:42 AM UTC 24
Finished Aug 21 08:53:45 AM UTC 24
Peak memory 228432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4246131761 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.4246131761
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/156.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/156.edn_genbits.861446154
Short name T802
Test name
Test status
Simulation time 64081398 ps
CPU time 1.35 seconds
Started Aug 21 08:53:42 AM UTC 24
Finished Aug 21 08:53:44 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=861446154 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.861446154
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/156.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/157.edn_alert.2559282851
Short name T801
Test name
Test status
Simulation time 36390065 ps
CPU time 1.14 seconds
Started Aug 21 08:53:42 AM UTC 24
Finished Aug 21 08:53:44 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2559282851 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.2559282851
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/157.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/157.edn_genbits.1257983833
Short name T803
Test name
Test status
Simulation time 99266561 ps
CPU time 1.32 seconds
Started Aug 21 08:53:42 AM UTC 24
Finished Aug 21 08:53:45 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1257983833 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.1257983833
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/157.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/159.edn_alert.3778477361
Short name T812
Test name
Test status
Simulation time 73354891 ps
CPU time 1.72 seconds
Started Aug 21 08:53:43 AM UTC 24
Finished Aug 21 08:53:46 AM UTC 24
Peak memory 228432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3778477361 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.3778477361
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/159.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/159.edn_genbits.4012914387
Short name T804
Test name
Test status
Simulation time 33101962 ps
CPU time 1.22 seconds
Started Aug 21 08:53:42 AM UTC 24
Finished Aug 21 08:53:45 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4012914387 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.4012914387
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/159.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/16.edn_alert.2340502970
Short name T134
Test name
Test status
Simulation time 99091855 ps
CPU time 1.8 seconds
Started Aug 21 08:50:52 AM UTC 24
Finished Aug 21 08:50:55 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2340502970 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2340502970
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/16.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/16.edn_alert_test.3215844792
Short name T383
Test name
Test status
Simulation time 15443427 ps
CPU time 1.29 seconds
Started Aug 21 08:50:53 AM UTC 24
Finished Aug 21 08:50:56 AM UTC 24
Peak memory 216248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3215844792 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3215844792
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/16.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/16.edn_disable_auto_req_mode.8451145
Short name T144
Test name
Test status
Simulation time 26460740 ps
CPU time 1.49 seconds
Started Aug 21 08:50:52 AM UTC 24
Finished Aug 21 08:50:55 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=8451145 -assert nopo
stproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disabl
e_auto_req_mode.8451145
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/16.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/16.edn_err.3315667126
Short name T205
Test name
Test status
Simulation time 19570768 ps
CPU time 1.22 seconds
Started Aug 21 08:50:52 AM UTC 24
Finished Aug 21 08:50:55 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3315667126 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.3315667126
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/16.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/16.edn_intr.1147787751
Short name T382
Test name
Test status
Simulation time 20749013 ps
CPU time 1.6 seconds
Started Aug 21 08:50:52 AM UTC 24
Finished Aug 21 08:50:55 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1147787751 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.1147787751
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/16.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/16.edn_smoke.3881433879
Short name T381
Test name
Test status
Simulation time 25952408 ps
CPU time 1.15 seconds
Started Aug 21 08:50:51 AM UTC 24
Finished Aug 21 08:50:53 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3881433879 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.3881433879
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/16.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/16.edn_stress_all.430120549
Short name T350
Test name
Test status
Simulation time 633916130 ps
CPU time 7.59 seconds
Started Aug 21 08:50:51 AM UTC 24
Finished Aug 21 08:51:00 AM UTC 24
Peak memory 227420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=430120549 -asser
t nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.430120549
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/16.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/160.edn_alert.3100995760
Short name T808
Test name
Test status
Simulation time 50267119 ps
CPU time 1.32 seconds
Started Aug 21 08:53:43 AM UTC 24
Finished Aug 21 08:53:46 AM UTC 24
Peak memory 228308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3100995760 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.3100995760
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/160.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/160.edn_genbits.1574976128
Short name T343
Test name
Test status
Simulation time 60631872 ps
CPU time 1.57 seconds
Started Aug 21 08:53:43 AM UTC 24
Finished Aug 21 08:53:46 AM UTC 24
Peak memory 230320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1574976128 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1574976128
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/160.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/161.edn_alert.4028899913
Short name T807
Test name
Test status
Simulation time 36366621 ps
CPU time 1.18 seconds
Started Aug 21 08:53:44 AM UTC 24
Finished Aug 21 08:53:46 AM UTC 24
Peak memory 228432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4028899913 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.4028899913
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/161.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/161.edn_genbits.192715410
Short name T809
Test name
Test status
Simulation time 144739407 ps
CPU time 1.41 seconds
Started Aug 21 08:53:44 AM UTC 24
Finished Aug 21 08:53:46 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=192715410 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.192715410
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/161.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/162.edn_alert.1426958527
Short name T810
Test name
Test status
Simulation time 246452713 ps
CPU time 1.31 seconds
Started Aug 21 08:53:44 AM UTC 24
Finished Aug 21 08:53:46 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1426958527 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.1426958527
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/162.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/162.edn_genbits.2580238934
Short name T811
Test name
Test status
Simulation time 50054039 ps
CPU time 1.42 seconds
Started Aug 21 08:53:44 AM UTC 24
Finished Aug 21 08:53:46 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2580238934 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.2580238934
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/162.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/163.edn_alert.3559149150
Short name T814
Test name
Test status
Simulation time 83141558 ps
CPU time 1.26 seconds
Started Aug 21 08:53:45 AM UTC 24
Finished Aug 21 08:53:47 AM UTC 24
Peak memory 228432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3559149150 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.3559149150
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/163.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/163.edn_genbits.223771112
Short name T813
Test name
Test status
Simulation time 47796476 ps
CPU time 1.55 seconds
Started Aug 21 08:53:44 AM UTC 24
Finished Aug 21 08:53:46 AM UTC 24
Peak memory 230612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=223771112 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.223771112
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/163.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/164.edn_alert.1936444720
Short name T818
Test name
Test status
Simulation time 54094672 ps
CPU time 1.39 seconds
Started Aug 21 08:53:45 AM UTC 24
Finished Aug 21 08:53:47 AM UTC 24
Peak memory 228432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1936444720 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.1936444720
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/164.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/164.edn_genbits.748074365
Short name T816
Test name
Test status
Simulation time 50206258 ps
CPU time 1.32 seconds
Started Aug 21 08:53:45 AM UTC 24
Finished Aug 21 08:53:47 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=748074365 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.748074365
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/164.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/165.edn_alert.3687199641
Short name T822
Test name
Test status
Simulation time 27466238 ps
CPU time 1.64 seconds
Started Aug 21 08:53:45 AM UTC 24
Finished Aug 21 08:53:48 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3687199641 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.3687199641
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/165.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/165.edn_genbits.1950959835
Short name T815
Test name
Test status
Simulation time 103850131 ps
CPU time 1.2 seconds
Started Aug 21 08:53:45 AM UTC 24
Finished Aug 21 08:53:47 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1950959835 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1950959835
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/165.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/166.edn_alert.4111945338
Short name T819
Test name
Test status
Simulation time 79353755 ps
CPU time 1.34 seconds
Started Aug 21 08:53:45 AM UTC 24
Finished Aug 21 08:53:47 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4111945338 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.4111945338
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/166.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/166.edn_genbits.3457509281
Short name T817
Test name
Test status
Simulation time 26801618 ps
CPU time 1.31 seconds
Started Aug 21 08:53:45 AM UTC 24
Finished Aug 21 08:53:47 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3457509281 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.3457509281
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/166.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/167.edn_alert.1835740419
Short name T824
Test name
Test status
Simulation time 69611486 ps
CPU time 1.62 seconds
Started Aug 21 08:53:45 AM UTC 24
Finished Aug 21 08:53:48 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1835740419 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.1835740419
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/167.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/167.edn_genbits.586946519
Short name T823
Test name
Test status
Simulation time 104631829 ps
CPU time 1.65 seconds
Started Aug 21 08:53:45 AM UTC 24
Finished Aug 21 08:53:48 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=586946519 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.586946519
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/167.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/168.edn_alert.3705287671
Short name T262
Test name
Test status
Simulation time 30235100 ps
CPU time 1.51 seconds
Started Aug 21 08:53:46 AM UTC 24
Finished Aug 21 08:53:49 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3705287671 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.3705287671
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/168.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/168.edn_genbits.4072062215
Short name T821
Test name
Test status
Simulation time 38883793 ps
CPU time 1.24 seconds
Started Aug 21 08:53:45 AM UTC 24
Finished Aug 21 08:53:47 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4072062215 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.4072062215
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/168.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/169.edn_alert.2237234909
Short name T827
Test name
Test status
Simulation time 162609978 ps
CPU time 1.27 seconds
Started Aug 21 08:53:46 AM UTC 24
Finished Aug 21 08:53:48 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2237234909 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.2237234909
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/169.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/169.edn_genbits.3988014778
Short name T829
Test name
Test status
Simulation time 89211339 ps
CPU time 1.58 seconds
Started Aug 21 08:53:46 AM UTC 24
Finished Aug 21 08:53:49 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3988014778 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.3988014778
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/169.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/17.edn_alert.2540912527
Short name T96
Test name
Test status
Simulation time 65002780 ps
CPU time 1.86 seconds
Started Aug 21 08:50:55 AM UTC 24
Finished Aug 21 08:50:58 AM UTC 24
Peak memory 228436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2540912527 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.2540912527
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/17.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/17.edn_alert_test.2901939062
Short name T242
Test name
Test status
Simulation time 31876061 ps
CPU time 1.19 seconds
Started Aug 21 08:50:56 AM UTC 24
Finished Aug 21 08:50:58 AM UTC 24
Peak memory 216472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2901939062 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2901939062
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/17.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/17.edn_disable.1448609834
Short name T233
Test name
Test status
Simulation time 26142383 ps
CPU time 1.02 seconds
Started Aug 21 08:50:56 AM UTC 24
Finished Aug 21 08:50:58 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1448609834 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.1448609834
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/17.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/17.edn_err.3453457911
Short name T164
Test name
Test status
Simulation time 19347568 ps
CPU time 1.36 seconds
Started Aug 21 08:50:55 AM UTC 24
Finished Aug 21 08:50:57 AM UTC 24
Peak memory 228488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3453457911 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.3453457911
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/17.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/17.edn_genbits.1171679335
Short name T120
Test name
Test status
Simulation time 87550040 ps
CPU time 2 seconds
Started Aug 21 08:50:54 AM UTC 24
Finished Aug 21 08:50:57 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1171679335 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1171679335
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/17.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/17.edn_intr.2110407178
Short name T138
Test name
Test status
Simulation time 22995451 ps
CPU time 1.09 seconds
Started Aug 21 08:50:55 AM UTC 24
Finished Aug 21 08:50:57 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2110407178 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.2110407178
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/17.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/17.edn_smoke.1992097333
Short name T240
Test name
Test status
Simulation time 58888061 ps
CPU time 1.28 seconds
Started Aug 21 08:50:54 AM UTC 24
Finished Aug 21 08:50:56 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1992097333 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.1992097333
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/17.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/17.edn_stress_all.4004160309
Short name T241
Test name
Test status
Simulation time 404746531 ps
CPU time 3.12 seconds
Started Aug 21 08:50:54 AM UTC 24
Finished Aug 21 08:50:58 AM UTC 24
Peak memory 229456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4004160309 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.4004160309
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/17.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/17.edn_stress_all_with_rand_reset.3099345733
Short name T248
Test name
Test status
Simulation time 14321317457 ps
CPU time 118.82 seconds
Started Aug 21 08:50:54 AM UTC 24
Finished Aug 21 08:52:55 AM UTC 24
Peak memory 229716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3099345733 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.3099345733
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/17.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/170.edn_alert.572572087
Short name T826
Test name
Test status
Simulation time 23675328 ps
CPU time 1.11 seconds
Started Aug 21 08:53:46 AM UTC 24
Finished Aug 21 08:53:48 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=572572087 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.572572087
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/170.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/170.edn_genbits.1808861154
Short name T830
Test name
Test status
Simulation time 220992759 ps
CPU time 1.96 seconds
Started Aug 21 08:53:46 AM UTC 24
Finished Aug 21 08:53:49 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1808861154 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1808861154
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/170.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/171.edn_alert.816641081
Short name T833
Test name
Test status
Simulation time 41912494 ps
CPU time 1.53 seconds
Started Aug 21 08:53:47 AM UTC 24
Finished Aug 21 08:53:50 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=816641081 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.816641081
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/171.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/171.edn_genbits.4166685268
Short name T828
Test name
Test status
Simulation time 96355719 ps
CPU time 1.21 seconds
Started Aug 21 08:53:46 AM UTC 24
Finished Aug 21 08:53:49 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4166685268 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.4166685268
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/171.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/172.edn_alert.3371608356
Short name T831
Test name
Test status
Simulation time 28179864 ps
CPU time 1.33 seconds
Started Aug 21 08:53:47 AM UTC 24
Finished Aug 21 08:53:50 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3371608356 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.3371608356
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/172.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/172.edn_genbits.1503950560
Short name T832
Test name
Test status
Simulation time 39989688 ps
CPU time 1.42 seconds
Started Aug 21 08:53:47 AM UTC 24
Finished Aug 21 08:53:50 AM UTC 24
Peak memory 228556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1503950560 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.1503950560
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/172.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/173.edn_alert.971708562
Short name T835
Test name
Test status
Simulation time 49543490 ps
CPU time 1.36 seconds
Started Aug 21 08:53:48 AM UTC 24
Finished Aug 21 08:53:50 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=971708562 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.971708562
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/173.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/173.edn_genbits.937016319
Short name T836
Test name
Test status
Simulation time 122494171 ps
CPU time 1.19 seconds
Started Aug 21 08:53:48 AM UTC 24
Finished Aug 21 08:53:51 AM UTC 24
Peak memory 228340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=937016319 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.937016319
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/173.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/174.edn_alert.3958639415
Short name T834
Test name
Test status
Simulation time 82054831 ps
CPU time 1.37 seconds
Started Aug 21 08:53:48 AM UTC 24
Finished Aug 21 08:53:50 AM UTC 24
Peak memory 228432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3958639415 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.3958639415
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/174.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/174.edn_genbits.3343724536
Short name T846
Test name
Test status
Simulation time 64711433 ps
CPU time 2.03 seconds
Started Aug 21 08:53:48 AM UTC 24
Finished Aug 21 08:53:52 AM UTC 24
Peak memory 231636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3343724536 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3343724536
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/174.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/175.edn_alert.1775852120
Short name T839
Test name
Test status
Simulation time 43787889 ps
CPU time 1.26 seconds
Started Aug 21 08:53:48 AM UTC 24
Finished Aug 21 08:53:51 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1775852120 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.1775852120
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/175.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/176.edn_alert.4275896445
Short name T838
Test name
Test status
Simulation time 37108101 ps
CPU time 1.11 seconds
Started Aug 21 08:53:49 AM UTC 24
Finished Aug 21 08:53:51 AM UTC 24
Peak memory 228432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4275896445 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.4275896445
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/176.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/177.edn_alert.1720304899
Short name T837
Test name
Test status
Simulation time 70413731 ps
CPU time 1.04 seconds
Started Aug 21 08:53:49 AM UTC 24
Finished Aug 21 08:53:51 AM UTC 24
Peak memory 228432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1720304899 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.1720304899
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/177.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/177.edn_genbits.2885033961
Short name T840
Test name
Test status
Simulation time 58203945 ps
CPU time 1.29 seconds
Started Aug 21 08:53:49 AM UTC 24
Finished Aug 21 08:53:51 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2885033961 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2885033961
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/177.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/178.edn_alert.146897963
Short name T842
Test name
Test status
Simulation time 95482669 ps
CPU time 1.41 seconds
Started Aug 21 08:53:49 AM UTC 24
Finished Aug 21 08:53:52 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=146897963 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.146897963
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/178.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/178.edn_genbits.646511645
Short name T844
Test name
Test status
Simulation time 21312229 ps
CPU time 1.42 seconds
Started Aug 21 08:53:49 AM UTC 24
Finished Aug 21 08:53:52 AM UTC 24
Peak memory 230372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=646511645 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.646511645
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/178.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/179.edn_alert.749340702
Short name T845
Test name
Test status
Simulation time 30438974 ps
CPU time 1.48 seconds
Started Aug 21 08:53:49 AM UTC 24
Finished Aug 21 08:53:52 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=749340702 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.749340702
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/179.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/179.edn_genbits.455421219
Short name T849
Test name
Test status
Simulation time 259646917 ps
CPU time 1.81 seconds
Started Aug 21 08:53:49 AM UTC 24
Finished Aug 21 08:53:52 AM UTC 24
Peak memory 230600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=455421219 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.455421219
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/179.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/18.edn_alert.2640785873
Short name T305
Test name
Test status
Simulation time 26658107 ps
CPU time 1.85 seconds
Started Aug 21 08:50:57 AM UTC 24
Finished Aug 21 08:51:00 AM UTC 24
Peak memory 228436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2640785873 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.2640785873
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/18.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/18.edn_alert_test.2298121173
Short name T385
Test name
Test status
Simulation time 11929038 ps
CPU time 1.21 seconds
Started Aug 21 08:50:59 AM UTC 24
Finished Aug 21 08:51:01 AM UTC 24
Peak memory 216436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2298121173 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2298121173
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/18.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/18.edn_disable.3144123599
Short name T56
Test name
Test status
Simulation time 22310260 ps
CPU time 1.31 seconds
Started Aug 21 08:50:58 AM UTC 24
Finished Aug 21 08:51:01 AM UTC 24
Peak memory 225956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3144123599 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3144123599
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/18.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/18.edn_disable_auto_req_mode.635458914
Short name T226
Test name
Test status
Simulation time 68288195 ps
CPU time 1.56 seconds
Started Aug 21 08:50:58 AM UTC 24
Finished Aug 21 08:51:01 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=635458914 -assert no
postproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disa
ble_auto_req_mode.635458914
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/18.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/18.edn_err.2398581779
Short name T192
Test name
Test status
Simulation time 19547707 ps
CPU time 1.47 seconds
Started Aug 21 08:50:58 AM UTC 24
Finished Aug 21 08:51:01 AM UTC 24
Peak memory 236888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2398581779 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2398581779
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/18.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/18.edn_genbits.1747940217
Short name T298
Test name
Test status
Simulation time 74605406 ps
CPU time 1.82 seconds
Started Aug 21 08:50:57 AM UTC 24
Finished Aug 21 08:51:00 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1747940217 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1747940217
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/18.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/18.edn_intr.820171475
Short name T384
Test name
Test status
Simulation time 34080509 ps
CPU time 1.16 seconds
Started Aug 21 08:50:57 AM UTC 24
Finished Aug 21 08:50:59 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=820171475 -assert nopostproc +UVM_TESTNAME=ed
n_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0
_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.820171475
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/18.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/18.edn_smoke.2405280944
Short name T243
Test name
Test status
Simulation time 16739270 ps
CPU time 1.15 seconds
Started Aug 21 08:50:56 AM UTC 24
Finished Aug 21 08:50:58 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2405280944 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2405280944
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/18.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/18.edn_stress_all.4215437080
Short name T387
Test name
Test status
Simulation time 157377655 ps
CPU time 3.04 seconds
Started Aug 21 08:50:57 AM UTC 24
Finished Aug 21 08:51:01 AM UTC 24
Peak memory 231756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4215437080 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.4215437080
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/18.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/180.edn_alert.1302752785
Short name T848
Test name
Test status
Simulation time 39043181 ps
CPU time 1.62 seconds
Started Aug 21 08:53:49 AM UTC 24
Finished Aug 21 08:53:52 AM UTC 24
Peak memory 226348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1302752785 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.1302752785
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/180.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/180.edn_genbits.3373226898
Short name T841
Test name
Test status
Simulation time 71125089 ps
CPU time 1.21 seconds
Started Aug 21 08:53:49 AM UTC 24
Finished Aug 21 08:53:52 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3373226898 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3373226898
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/180.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/181.edn_alert.2369999037
Short name T843
Test name
Test status
Simulation time 39071214 ps
CPU time 1.32 seconds
Started Aug 21 08:53:49 AM UTC 24
Finished Aug 21 08:53:52 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2369999037 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.2369999037
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/181.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/181.edn_genbits.1594925031
Short name T847
Test name
Test status
Simulation time 64202252 ps
CPU time 1.61 seconds
Started Aug 21 08:53:49 AM UTC 24
Finished Aug 21 08:53:52 AM UTC 24
Peak memory 230608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1594925031 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.1594925031
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/181.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/182.edn_alert.2755598282
Short name T858
Test name
Test status
Simulation time 104264313 ps
CPU time 1.27 seconds
Started Aug 21 08:53:50 AM UTC 24
Finished Aug 21 08:53:56 AM UTC 24
Peak memory 228432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2755598282 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.2755598282
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/182.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/182.edn_genbits.699045478
Short name T867
Test name
Test status
Simulation time 52736618 ps
CPU time 2.35 seconds
Started Aug 21 08:53:50 AM UTC 24
Finished Aug 21 08:53:57 AM UTC 24
Peak memory 231924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=699045478 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.699045478
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/182.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/183.edn_alert.1695363202
Short name T853
Test name
Test status
Simulation time 22171109 ps
CPU time 1.08 seconds
Started Aug 21 08:53:50 AM UTC 24
Finished Aug 21 08:53:56 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1695363202 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.1695363202
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/183.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/183.edn_genbits.2720884273
Short name T860
Test name
Test status
Simulation time 47682674 ps
CPU time 1.52 seconds
Started Aug 21 08:53:50 AM UTC 24
Finished Aug 21 08:53:56 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2720884273 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.2720884273
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/183.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/184.edn_alert.1378800939
Short name T873
Test name
Test status
Simulation time 88985212 ps
CPU time 1.27 seconds
Started Aug 21 08:53:51 AM UTC 24
Finished Aug 21 08:53:57 AM UTC 24
Peak memory 228432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1378800939 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.1378800939
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/184.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/184.edn_genbits.3562938947
Short name T337
Test name
Test status
Simulation time 376087094 ps
CPU time 1.8 seconds
Started Aug 21 08:53:51 AM UTC 24
Finished Aug 21 08:53:55 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3562938947 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3562938947
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/184.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/185.edn_alert.3174416973
Short name T872
Test name
Test status
Simulation time 98641799 ps
CPU time 1.19 seconds
Started Aug 21 08:53:52 AM UTC 24
Finished Aug 21 08:53:57 AM UTC 24
Peak memory 228432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3174416973 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.3174416973
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/185.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/185.edn_genbits.2368603473
Short name T871
Test name
Test status
Simulation time 37358364 ps
CPU time 1.24 seconds
Started Aug 21 08:53:52 AM UTC 24
Finished Aug 21 08:53:57 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2368603473 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2368603473
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/185.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/186.edn_alert.18271652
Short name T850
Test name
Test status
Simulation time 44551020 ps
CPU time 1.16 seconds
Started Aug 21 08:53:52 AM UTC 24
Finished Aug 21 08:53:55 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=18271652 -assert nopostproc +UVM_TESTNAME=edn
_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.18271652
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/186.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/186.edn_genbits.982719952
Short name T874
Test name
Test status
Simulation time 34115795 ps
CPU time 1.42 seconds
Started Aug 21 08:53:52 AM UTC 24
Finished Aug 21 08:53:58 AM UTC 24
Peak memory 228268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=982719952 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.982719952
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/186.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/187.edn_alert.3631889931
Short name T866
Test name
Test status
Simulation time 121313965 ps
CPU time 1.64 seconds
Started Aug 21 08:53:53 AM UTC 24
Finished Aug 21 08:53:57 AM UTC 24
Peak memory 228344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3631889931 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.3631889931
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/187.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/187.edn_genbits.2786616777
Short name T861
Test name
Test status
Simulation time 109020472 ps
CPU time 1.34 seconds
Started Aug 21 08:53:53 AM UTC 24
Finished Aug 21 08:53:57 AM UTC 24
Peak memory 230608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2786616777 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2786616777
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/187.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/188.edn_alert.4217214216
Short name T862
Test name
Test status
Simulation time 89305631 ps
CPU time 1.25 seconds
Started Aug 21 08:53:53 AM UTC 24
Finished Aug 21 08:53:57 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4217214216 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.4217214216
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/188.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/188.edn_genbits.2177134266
Short name T863
Test name
Test status
Simulation time 28667483 ps
CPU time 1.4 seconds
Started Aug 21 08:53:53 AM UTC 24
Finished Aug 21 08:53:57 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2177134266 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.2177134266
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/188.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/189.edn_alert.1205813485
Short name T864
Test name
Test status
Simulation time 53791689 ps
CPU time 1.26 seconds
Started Aug 21 08:53:53 AM UTC 24
Finished Aug 21 08:53:57 AM UTC 24
Peak memory 230436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1205813485 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.1205813485
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/189.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/189.edn_genbits.3288028904
Short name T868
Test name
Test status
Simulation time 33403237 ps
CPU time 1.65 seconds
Started Aug 21 08:53:53 AM UTC 24
Finished Aug 21 08:53:57 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3288028904 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.3288028904
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/189.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/19.edn_alert.3125742961
Short name T100
Test name
Test status
Simulation time 96500127 ps
CPU time 1.42 seconds
Started Aug 21 08:51:01 AM UTC 24
Finished Aug 21 08:51:03 AM UTC 24
Peak memory 228436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3125742961 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.3125742961
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/19.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/19.edn_alert_test.2602810431
Short name T390
Test name
Test status
Simulation time 14524486 ps
CPU time 1.1 seconds
Started Aug 21 08:51:02 AM UTC 24
Finished Aug 21 08:51:04 AM UTC 24
Peak memory 216632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2602810431 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2602810431
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/19.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/19.edn_err.1278982025
Short name T389
Test name
Test status
Simulation time 44652617 ps
CPU time 1.29 seconds
Started Aug 21 08:51:01 AM UTC 24
Finished Aug 21 08:51:03 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1278982025 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1278982025
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/19.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/19.edn_genbits.575168134
Short name T45
Test name
Test status
Simulation time 93453162 ps
CPU time 1.87 seconds
Started Aug 21 08:50:59 AM UTC 24
Finished Aug 21 08:51:02 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=575168134 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.575168134
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/19.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/19.edn_intr.3917918526
Short name T388
Test name
Test status
Simulation time 24063415 ps
CPU time 1.61 seconds
Started Aug 21 08:51:00 AM UTC 24
Finished Aug 21 08:51:03 AM UTC 24
Peak memory 237160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3917918526 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3917918526
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/19.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/19.edn_smoke.1428479341
Short name T386
Test name
Test status
Simulation time 30572686 ps
CPU time 1.4 seconds
Started Aug 21 08:50:59 AM UTC 24
Finished Aug 21 08:51:01 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1428479341 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.1428479341
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/19.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/19.edn_stress_all.1960087183
Short name T393
Test name
Test status
Simulation time 682353133 ps
CPU time 5.04 seconds
Started Aug 21 08:51:00 AM UTC 24
Finished Aug 21 08:51:06 AM UTC 24
Peak memory 227768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1960087183 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1960087183
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/19.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/19.edn_stress_all_with_rand_reset.3506362296
Short name T530
Test name
Test status
Simulation time 6108440264 ps
CPU time 77.85 seconds
Started Aug 21 08:51:00 AM UTC 24
Finished Aug 21 08:52:20 AM UTC 24
Peak memory 231896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3506362296 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.3506362296
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/19.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/190.edn_alert.3400493788
Short name T865
Test name
Test status
Simulation time 32566466 ps
CPU time 1.31 seconds
Started Aug 21 08:53:53 AM UTC 24
Finished Aug 21 08:53:57 AM UTC 24
Peak memory 226364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3400493788 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.3400493788
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/190.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/190.edn_genbits.1823695457
Short name T869
Test name
Test status
Simulation time 154370842 ps
CPU time 1.88 seconds
Started Aug 21 08:53:53 AM UTC 24
Finished Aug 21 08:53:57 AM UTC 24
Peak memory 230396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1823695457 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1823695457
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/190.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/191.edn_alert.818333920
Short name T856
Test name
Test status
Simulation time 31922115 ps
CPU time 1.5 seconds
Started Aug 21 08:53:53 AM UTC 24
Finished Aug 21 08:53:56 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=818333920 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.818333920
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/191.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/191.edn_genbits.2519563704
Short name T870
Test name
Test status
Simulation time 36810329 ps
CPU time 1.73 seconds
Started Aug 21 08:53:53 AM UTC 24
Finished Aug 21 08:53:57 AM UTC 24
Peak memory 230540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2519563704 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2519563704
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/191.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/192.edn_alert.3210787176
Short name T851
Test name
Test status
Simulation time 51996215 ps
CPU time 1.07 seconds
Started Aug 21 08:53:53 AM UTC 24
Finished Aug 21 08:53:56 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3210787176 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.3210787176
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/192.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/192.edn_genbits.1010977370
Short name T852
Test name
Test status
Simulation time 70206535 ps
CPU time 1.18 seconds
Started Aug 21 08:53:53 AM UTC 24
Finished Aug 21 08:53:56 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1010977370 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1010977370
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/192.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/193.edn_alert.483931954
Short name T854
Test name
Test status
Simulation time 51612408 ps
CPU time 1.34 seconds
Started Aug 21 08:53:53 AM UTC 24
Finished Aug 21 08:53:56 AM UTC 24
Peak memory 228336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=483931954 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.483931954
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/193.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/193.edn_genbits.303265769
Short name T859
Test name
Test status
Simulation time 44047168 ps
CPU time 1.51 seconds
Started Aug 21 08:53:53 AM UTC 24
Finished Aug 21 08:53:56 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=303265769 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.303265769
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/193.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/194.edn_alert.4165673716
Short name T875
Test name
Test status
Simulation time 70796778 ps
CPU time 1.15 seconds
Started Aug 21 08:53:55 AM UTC 24
Finished Aug 21 08:53:58 AM UTC 24
Peak memory 228432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4165673716 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.4165673716
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/194.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/194.edn_genbits.2505129775
Short name T857
Test name
Test status
Simulation time 34223041 ps
CPU time 1.42 seconds
Started Aug 21 08:53:53 AM UTC 24
Finished Aug 21 08:53:56 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2505129775 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2505129775
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/194.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/195.edn_alert.3492551613
Short name T877
Test name
Test status
Simulation time 76879971 ps
CPU time 1.19 seconds
Started Aug 21 08:53:56 AM UTC 24
Finished Aug 21 08:53:59 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3492551613 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.3492551613
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/195.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/195.edn_genbits.24620646
Short name T880
Test name
Test status
Simulation time 76602274 ps
CPU time 1.24 seconds
Started Aug 21 08:53:56 AM UTC 24
Finished Aug 21 08:53:59 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=24620646 -assert nopostproc +UVM_TESTNAME=edn
_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_
1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.24620646
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/195.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/196.edn_alert.4006701092
Short name T878
Test name
Test status
Simulation time 81884152 ps
CPU time 1.15 seconds
Started Aug 21 08:53:56 AM UTC 24
Finished Aug 21 08:53:59 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4006701092 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.4006701092
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/196.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/196.edn_genbits.108097704
Short name T879
Test name
Test status
Simulation time 68059295 ps
CPU time 1.17 seconds
Started Aug 21 08:53:56 AM UTC 24
Finished Aug 21 08:53:59 AM UTC 24
Peak memory 230420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=108097704 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.108097704
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/196.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/197.edn_alert.3389608580
Short name T888
Test name
Test status
Simulation time 25822214 ps
CPU time 1.25 seconds
Started Aug 21 08:53:58 AM UTC 24
Finished Aug 21 08:54:01 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3389608580 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.3389608580
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/197.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/197.edn_genbits.3256705299
Short name T881
Test name
Test status
Simulation time 56902658 ps
CPU time 1.98 seconds
Started Aug 21 08:53:56 AM UTC 24
Finished Aug 21 08:54:00 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3256705299 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3256705299
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/197.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/198.edn_alert.2294224642
Short name T889
Test name
Test status
Simulation time 31286046 ps
CPU time 1.3 seconds
Started Aug 21 08:53:58 AM UTC 24
Finished Aug 21 08:54:01 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2294224642 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.2294224642
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/198.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/198.edn_genbits.4219120039
Short name T943
Test name
Test status
Simulation time 131828011 ps
CPU time 1.68 seconds
Started Aug 21 08:53:58 AM UTC 24
Finished Aug 21 08:54:22 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4219120039 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.4219120039
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/198.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/199.edn_alert.3762573
Short name T940
Test name
Test status
Simulation time 25549071 ps
CPU time 1.31 seconds
Started Aug 21 08:53:58 AM UTC 24
Finished Aug 21 08:54:21 AM UTC 24
Peak memory 230480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3762573 -assert nopostproc +UVM_TESTNAME=edn_
alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0
_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.3762573
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/199.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/199.edn_genbits.119006747
Short name T890
Test name
Test status
Simulation time 266177624 ps
CPU time 3.53 seconds
Started Aug 21 08:53:58 AM UTC 24
Finished Aug 21 08:54:04 AM UTC 24
Peak memory 231780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=119006747 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.119006747
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/199.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/2.edn_alert_test.2643766001
Short name T71
Test name
Test status
Simulation time 24096736 ps
CPU time 1.13 seconds
Started Aug 21 08:50:20 AM UTC 24
Finished Aug 21 08:50:22 AM UTC 24
Peak memory 216112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2643766001 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2643766001
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/2.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/2.edn_disable.1536654623
Short name T42
Test name
Test status
Simulation time 13478081 ps
CPU time 1.12 seconds
Started Aug 21 08:50:20 AM UTC 24
Finished Aug 21 08:50:22 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1536654623 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1536654623
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/2.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/2.edn_disable_auto_req_mode.1047336564
Short name T22
Test name
Test status
Simulation time 208573957 ps
CPU time 1.21 seconds
Started Aug 21 08:50:20 AM UTC 24
Finished Aug 21 08:50:22 AM UTC 24
Peak memory 230360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1047336564 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disa
ble_auto_req_mode.1047336564
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/2.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/2.edn_err.1020465766
Short name T75
Test name
Test status
Simulation time 28124325 ps
CPU time 1.29 seconds
Started Aug 21 08:50:20 AM UTC 24
Finished Aug 21 08:50:22 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1020465766 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.1020465766
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/2.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/2.edn_genbits.3175730099
Short name T57
Test name
Test status
Simulation time 20289084 ps
CPU time 1.67 seconds
Started Aug 21 08:50:18 AM UTC 24
Finished Aug 21 08:50:21 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3175730099 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3175730099
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/2.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/2.edn_intr.609410746
Short name T74
Test name
Test status
Simulation time 21028014 ps
CPU time 1.15 seconds
Started Aug 21 08:50:18 AM UTC 24
Finished Aug 21 08:50:21 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=609410746 -assert nopostproc +UVM_TESTNAME=ed
n_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0
_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.609410746
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/2.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/2.edn_regwen.1407604220
Short name T28
Test name
Test status
Simulation time 41543592 ps
CPU time 0.95 seconds
Started Aug 21 08:50:18 AM UTC 24
Finished Aug 21 08:50:20 AM UTC 24
Peak memory 216016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1407604220 -assert nopostproc +UVM_TESTNAME=e
dn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1
_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.1407604220
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/2.edn_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/2.edn_sec_cm.3039213893
Short name T20
Test name
Test status
Simulation time 908400251 ps
CPU time 10.02 seconds
Started Aug 21 08:50:20 AM UTC 24
Finished Aug 21 08:50:31 AM UTC 24
Peak memory 260604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3039213893 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.3039213893
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/2.edn_sec_cm/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/2.edn_smoke.2758398795
Short name T73
Test name
Test status
Simulation time 26196554 ps
CPU time 1.01 seconds
Started Aug 21 08:50:18 AM UTC 24
Finished Aug 21 08:50:20 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2758398795 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.2758398795
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/2.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/2.edn_stress_all.1242772099
Short name T60
Test name
Test status
Simulation time 1059125531 ps
CPU time 4.67 seconds
Started Aug 21 08:50:18 AM UTC 24
Finished Aug 21 08:50:24 AM UTC 24
Peak memory 229736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1242772099 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1242772099
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/2.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/2.edn_stress_all_with_rand_reset.1608631829
Short name T520
Test name
Test status
Simulation time 19019089077 ps
CPU time 114.31 seconds
Started Aug 21 08:50:18 AM UTC 24
Finished Aug 21 08:52:15 AM UTC 24
Peak memory 229788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1608631829 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1608631829
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/2.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/20.edn_alert.544655339
Short name T394
Test name
Test status
Simulation time 27752161 ps
CPU time 1.8 seconds
Started Aug 21 08:51:03 AM UTC 24
Finished Aug 21 08:51:06 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=544655339 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.544655339
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/20.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/20.edn_alert_test.2989359964
Short name T395
Test name
Test status
Simulation time 67117584 ps
CPU time 1.18 seconds
Started Aug 21 08:51:05 AM UTC 24
Finished Aug 21 08:51:07 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2989359964 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2989359964
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/20.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/20.edn_disable.3561192106
Short name T392
Test name
Test status
Simulation time 16841851 ps
CPU time 0.86 seconds
Started Aug 21 08:51:04 AM UTC 24
Finished Aug 21 08:51:05 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3561192106 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3561192106
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/20.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/20.edn_disable_auto_req_mode.340511895
Short name T396
Test name
Test status
Simulation time 42473021 ps
CPU time 1.39 seconds
Started Aug 21 08:51:05 AM UTC 24
Finished Aug 21 08:51:07 AM UTC 24
Peak memory 228308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=340511895 -assert no
postproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disa
ble_auto_req_mode.340511895
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/20.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/20.edn_err.2661260813
Short name T250
Test name
Test status
Simulation time 35967261 ps
CPU time 1.31 seconds
Started Aug 21 08:51:04 AM UTC 24
Finished Aug 21 08:51:06 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2661260813 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2661260813
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/20.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/20.edn_genbits.2466574687
Short name T104
Test name
Test status
Simulation time 71196135 ps
CPU time 1.88 seconds
Started Aug 21 08:51:02 AM UTC 24
Finished Aug 21 08:51:05 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2466574687 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.2466574687
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/20.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/20.edn_smoke.3352598685
Short name T391
Test name
Test status
Simulation time 18642552 ps
CPU time 1.42 seconds
Started Aug 21 08:51:02 AM UTC 24
Finished Aug 21 08:51:05 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3352598685 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.3352598685
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/20.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/20.edn_stress_all.1092915868
Short name T399
Test name
Test status
Simulation time 328325774 ps
CPU time 6.03 seconds
Started Aug 21 08:51:02 AM UTC 24
Finished Aug 21 08:51:09 AM UTC 24
Peak memory 227548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1092915868 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1092915868
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/20.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/20.edn_stress_all_with_rand_reset.4086949557
Short name T775
Test name
Test status
Simulation time 21778585962 ps
CPU time 154.35 seconds
Started Aug 21 08:51:02 AM UTC 24
Finished Aug 21 08:53:39 AM UTC 24
Peak memory 233876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4086949557 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.4086949557
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/20.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/203.edn_genbits.930701754
Short name T914
Test name
Test status
Simulation time 80240534 ps
CPU time 1.58 seconds
Started Aug 21 08:53:58 AM UTC 24
Finished Aug 21 08:54:12 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=930701754 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.930701754
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/203.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/204.edn_genbits.1805201819
Short name T883
Test name
Test status
Simulation time 48098916 ps
CPU time 1.45 seconds
Started Aug 21 08:53:58 AM UTC 24
Finished Aug 21 08:54:00 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1805201819 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.1805201819
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/204.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/205.edn_genbits.2153242983
Short name T913
Test name
Test status
Simulation time 57148010 ps
CPU time 1.21 seconds
Started Aug 21 08:53:58 AM UTC 24
Finished Aug 21 08:54:12 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2153242983 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.2153242983
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/205.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/206.edn_genbits.3752849341
Short name T884
Test name
Test status
Simulation time 40806521 ps
CPU time 1.37 seconds
Started Aug 21 08:53:58 AM UTC 24
Finished Aug 21 08:54:01 AM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3752849341 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.3752849341
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/206.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/207.edn_genbits.2739587917
Short name T885
Test name
Test status
Simulation time 42485133 ps
CPU time 1.39 seconds
Started Aug 21 08:53:58 AM UTC 24
Finished Aug 21 08:54:01 AM UTC 24
Peak memory 228316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2739587917 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.2739587917
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/207.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/208.edn_genbits.1683900142
Short name T887
Test name
Test status
Simulation time 74547630 ps
CPU time 1.67 seconds
Started Aug 21 08:53:58 AM UTC 24
Finished Aug 21 08:54:01 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1683900142 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.1683900142
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/208.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/209.edn_genbits.3778318677
Short name T882
Test name
Test status
Simulation time 95901173 ps
CPU time 1.06 seconds
Started Aug 21 08:53:58 AM UTC 24
Finished Aug 21 08:54:00 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3778318677 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.3778318677
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/209.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/21.edn_alert.1608411571
Short name T166
Test name
Test status
Simulation time 25801695 ps
CPU time 1.58 seconds
Started Aug 21 08:51:07 AM UTC 24
Finished Aug 21 08:51:10 AM UTC 24
Peak memory 230484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1608411571 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.1608411571
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/21.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/21.edn_alert_test.1459008471
Short name T401
Test name
Test status
Simulation time 20532772 ps
CPU time 1.47 seconds
Started Aug 21 08:51:08 AM UTC 24
Finished Aug 21 08:51:11 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1459008471 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.1459008471
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/21.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/21.edn_disable.464448928
Short name T92
Test name
Test status
Simulation time 38665676 ps
CPU time 1.3 seconds
Started Aug 21 08:51:07 AM UTC 24
Finished Aug 21 08:51:09 AM UTC 24
Peak memory 216136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=464448928 -assert no
postproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o
pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.464448928
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/21.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/21.edn_disable_auto_req_mode.782542265
Short name T402
Test name
Test status
Simulation time 110405251 ps
CPU time 1.62 seconds
Started Aug 21 08:51:08 AM UTC 24
Finished Aug 21 08:51:11 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=782542265 -assert no
postproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disa
ble_auto_req_mode.782542265
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/21.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/21.edn_err.490946635
Short name T400
Test name
Test status
Simulation time 19338004 ps
CPU time 1.53 seconds
Started Aug 21 08:51:07 AM UTC 24
Finished Aug 21 08:51:10 AM UTC 24
Peak memory 228316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=490946635 -assert nopostproc +UVM_TESTNAME=ed
n_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2
024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.490946635
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/21.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/21.edn_genbits.2685106826
Short name T91
Test name
Test status
Simulation time 99335379 ps
CPU time 2.03 seconds
Started Aug 21 08:51:06 AM UTC 24
Finished Aug 21 08:51:09 AM UTC 24
Peak memory 229568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2685106826 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2685106826
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/21.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/21.edn_intr.560498197
Short name T398
Test name
Test status
Simulation time 33843588 ps
CPU time 1.57 seconds
Started Aug 21 08:51:06 AM UTC 24
Finished Aug 21 08:51:09 AM UTC 24
Peak memory 236704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=560498197 -assert nopostproc +UVM_TESTNAME=ed
n_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0
_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.560498197
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/21.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/21.edn_smoke.2295345816
Short name T397
Test name
Test status
Simulation time 17345861 ps
CPU time 1.41 seconds
Started Aug 21 08:51:06 AM UTC 24
Finished Aug 21 08:51:08 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2295345816 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.2295345816
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/21.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/21.edn_stress_all.1350705326
Short name T291
Test name
Test status
Simulation time 640996886 ps
CPU time 8.32 seconds
Started Aug 21 08:51:06 AM UTC 24
Finished Aug 21 08:51:15 AM UTC 24
Peak memory 231208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1350705326 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.1350705326
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/21.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/21.edn_stress_all_with_rand_reset.3500283283
Short name T249
Test name
Test status
Simulation time 5249635906 ps
CPU time 115.13 seconds
Started Aug 21 08:51:06 AM UTC 24
Finished Aug 21 08:53:03 AM UTC 24
Peak memory 229760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3500283283 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.3500283283
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/21.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/210.edn_genbits.3939125951
Short name T886
Test name
Test status
Simulation time 45339889 ps
CPU time 1.34 seconds
Started Aug 21 08:53:58 AM UTC 24
Finished Aug 21 08:54:01 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3939125951 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.3939125951
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/210.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/211.edn_genbits.4008050765
Short name T946
Test name
Test status
Simulation time 52869007 ps
CPU time 1.64 seconds
Started Aug 21 08:53:59 AM UTC 24
Finished Aug 21 08:54:25 AM UTC 24
Peak memory 228584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4008050765 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.4008050765
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/211.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/212.edn_genbits.920286685
Short name T333
Test name
Test status
Simulation time 82335825 ps
CPU time 1.29 seconds
Started Aug 21 08:53:59 AM UTC 24
Finished Aug 21 08:54:12 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=920286685 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.920286685
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/212.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/213.edn_genbits.3654854273
Short name T945
Test name
Test status
Simulation time 48273332 ps
CPU time 1.52 seconds
Started Aug 21 08:53:59 AM UTC 24
Finished Aug 21 08:54:25 AM UTC 24
Peak memory 228544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3654854273 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3654854273
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/213.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/214.edn_genbits.3304191550
Short name T891
Test name
Test status
Simulation time 119478127 ps
CPU time 1.11 seconds
Started Aug 21 08:53:59 AM UTC 24
Finished Aug 21 08:54:05 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3304191550 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.3304191550
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/214.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/215.edn_genbits.3212244791
Short name T972
Test name
Test status
Simulation time 130776082 ps
CPU time 2.39 seconds
Started Aug 21 08:53:59 AM UTC 24
Finished Aug 21 08:54:31 AM UTC 24
Peak memory 231512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3212244791 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.3212244791
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/215.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/216.edn_genbits.3093610135
Short name T970
Test name
Test status
Simulation time 41046926 ps
CPU time 1.38 seconds
Started Aug 21 08:53:59 AM UTC 24
Finished Aug 21 08:54:30 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3093610135 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.3093610135
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/216.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/217.edn_genbits.2844435195
Short name T978
Test name
Test status
Simulation time 4460163112 ps
CPU time 79.27 seconds
Started Aug 21 08:53:59 AM UTC 24
Finished Aug 21 08:56:01 AM UTC 24
Peak memory 231884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2844435195 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.2844435195
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/217.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/218.edn_genbits.1755882827
Short name T977
Test name
Test status
Simulation time 96764920 ps
CPU time 2.02 seconds
Started Aug 21 08:53:59 AM UTC 24
Finished Aug 21 08:54:43 AM UTC 24
Peak memory 231656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1755882827 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1755882827
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/218.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/219.edn_genbits.831893066
Short name T896
Test name
Test status
Simulation time 166118699 ps
CPU time 2.33 seconds
Started Aug 21 08:54:01 AM UTC 24
Finished Aug 21 08:54:07 AM UTC 24
Peak memory 229520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=831893066 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.831893066
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/219.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/22.edn_alert.2421628047
Short name T105
Test name
Test status
Simulation time 24566854 ps
CPU time 1.77 seconds
Started Aug 21 08:51:11 AM UTC 24
Finished Aug 21 08:51:13 AM UTC 24
Peak memory 230484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2421628047 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2421628047
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/22.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/22.edn_alert_test.2664820185
Short name T406
Test name
Test status
Simulation time 38639715 ps
CPU time 1.27 seconds
Started Aug 21 08:51:12 AM UTC 24
Finished Aug 21 08:51:14 AM UTC 24
Peak memory 216248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2664820185 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2664820185
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/22.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/22.edn_disable.4065065808
Short name T189
Test name
Test status
Simulation time 30336688 ps
CPU time 1.06 seconds
Started Aug 21 08:51:11 AM UTC 24
Finished Aug 21 08:51:13 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4065065808 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.4065065808
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/22.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/22.edn_disable_auto_req_mode.3621313963
Short name T407
Test name
Test status
Simulation time 39447776 ps
CPU time 1.93 seconds
Started Aug 21 08:51:12 AM UTC 24
Finished Aug 21 08:51:15 AM UTC 24
Peak memory 226264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3621313963 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_dis
able_auto_req_mode.3621313963
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/22.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/22.edn_err.3836415124
Short name T405
Test name
Test status
Simulation time 24050133 ps
CPU time 1.33 seconds
Started Aug 21 08:51:11 AM UTC 24
Finished Aug 21 08:51:13 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3836415124 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3836415124
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/22.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/22.edn_genbits.1195599452
Short name T54
Test name
Test status
Simulation time 71132006 ps
CPU time 2.04 seconds
Started Aug 21 08:51:09 AM UTC 24
Finished Aug 21 08:51:12 AM UTC 24
Peak memory 229676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1195599452 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.1195599452
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/22.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/22.edn_intr.3734007434
Short name T404
Test name
Test status
Simulation time 29459050 ps
CPU time 1.38 seconds
Started Aug 21 08:51:11 AM UTC 24
Finished Aug 21 08:51:13 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3734007434 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3734007434
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/22.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/22.edn_smoke.2727846127
Short name T403
Test name
Test status
Simulation time 98990236 ps
CPU time 1.29 seconds
Started Aug 21 08:51:09 AM UTC 24
Finished Aug 21 08:51:12 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2727846127 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2727846127
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/22.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/22.edn_stress_all.3758497052
Short name T252
Test name
Test status
Simulation time 228323279 ps
CPU time 3.69 seconds
Started Aug 21 08:51:09 AM UTC 24
Finished Aug 21 08:51:14 AM UTC 24
Peak memory 229712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3758497052 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.3758497052
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/22.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/220.edn_genbits.3567038959
Short name T894
Test name
Test status
Simulation time 113867040 ps
CPU time 1.61 seconds
Started Aug 21 08:54:01 AM UTC 24
Finished Aug 21 08:54:06 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3567038959 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.3567038959
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/220.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/221.edn_genbits.1006408238
Short name T892
Test name
Test status
Simulation time 39940972 ps
CPU time 1.28 seconds
Started Aug 21 08:54:01 AM UTC 24
Finished Aug 21 08:54:06 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1006408238 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1006408238
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/221.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/222.edn_genbits.2567524450
Short name T897
Test name
Test status
Simulation time 66638733 ps
CPU time 1.11 seconds
Started Aug 21 08:54:02 AM UTC 24
Finished Aug 21 08:54:07 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2567524450 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.2567524450
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/222.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/223.edn_genbits.2378620263
Short name T899
Test name
Test status
Simulation time 76494627 ps
CPU time 1.47 seconds
Started Aug 21 08:54:02 AM UTC 24
Finished Aug 21 08:54:07 AM UTC 24
Peak memory 230268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2378620263 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2378620263
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/223.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/224.edn_genbits.2818146913
Short name T900
Test name
Test status
Simulation time 43634129 ps
CPU time 1.54 seconds
Started Aug 21 08:54:02 AM UTC 24
Finished Aug 21 08:54:08 AM UTC 24
Peak memory 228296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2818146913 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2818146913
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/224.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/225.edn_genbits.3057465493
Short name T340
Test name
Test status
Simulation time 207714830 ps
CPU time 1.28 seconds
Started Aug 21 08:54:02 AM UTC 24
Finished Aug 21 08:54:11 AM UTC 24
Peak memory 230368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3057465493 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3057465493
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/225.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/226.edn_genbits.59075015
Short name T907
Test name
Test status
Simulation time 56903796 ps
CPU time 1.55 seconds
Started Aug 21 08:54:02 AM UTC 24
Finished Aug 21 08:54:11 AM UTC 24
Peak memory 228336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=59075015 -assert nopostproc +UVM_TESTNAME=edn
_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_
1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.59075015
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/226.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/227.edn_genbits.1978052543
Short name T901
Test name
Test status
Simulation time 293665396 ps
CPU time 2.25 seconds
Started Aug 21 08:54:02 AM UTC 24
Finished Aug 21 08:54:08 AM UTC 24
Peak memory 231576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1978052543 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1978052543
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/227.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/228.edn_genbits.3716091429
Short name T338
Test name
Test status
Simulation time 57612220 ps
CPU time 1.18 seconds
Started Aug 21 08:54:02 AM UTC 24
Finished Aug 21 08:54:11 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3716091429 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.3716091429
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/228.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/229.edn_genbits.2357490158
Short name T898
Test name
Test status
Simulation time 141309186 ps
CPU time 1 seconds
Started Aug 21 08:54:02 AM UTC 24
Finished Aug 21 08:54:07 AM UTC 24
Peak memory 228316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2357490158 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.2357490158
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/229.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/23.edn_alert.3464147827
Short name T410
Test name
Test status
Simulation time 53687730 ps
CPU time 1.53 seconds
Started Aug 21 08:51:14 AM UTC 24
Finished Aug 21 08:51:17 AM UTC 24
Peak memory 228436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3464147827 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.3464147827
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/23.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/23.edn_alert_test.1301418367
Short name T413
Test name
Test status
Simulation time 138940645 ps
CPU time 1.49 seconds
Started Aug 21 08:51:16 AM UTC 24
Finished Aug 21 08:51:18 AM UTC 24
Peak memory 226912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1301418367 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1301418367
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/23.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/23.edn_disable.73581777
Short name T412
Test name
Test status
Simulation time 13509639 ps
CPU time 1.35 seconds
Started Aug 21 08:51:16 AM UTC 24
Finished Aug 21 08:51:18 AM UTC 24
Peak memory 226384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=73581777 -assert nop
ostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op
entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.73581777
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/23.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/23.edn_disable_auto_req_mode.3424045235
Short name T414
Test name
Test status
Simulation time 41617975 ps
CPU time 1.69 seconds
Started Aug 21 08:51:16 AM UTC 24
Finished Aug 21 08:51:18 AM UTC 24
Peak memory 226264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3424045235 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_dis
able_auto_req_mode.3424045235
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/23.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/23.edn_err.488715025
Short name T141
Test name
Test status
Simulation time 90969436 ps
CPU time 1.54 seconds
Started Aug 21 08:51:15 AM UTC 24
Finished Aug 21 08:51:18 AM UTC 24
Peak memory 246404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=488715025 -assert nopostproc +UVM_TESTNAME=ed
n_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2
024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.488715025
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/23.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/23.edn_genbits.585006648
Short name T411
Test name
Test status
Simulation time 396813465 ps
CPU time 3.2 seconds
Started Aug 21 08:51:13 AM UTC 24
Finished Aug 21 08:51:18 AM UTC 24
Peak memory 229816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=585006648 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.585006648
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/23.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/23.edn_intr.1831288089
Short name T409
Test name
Test status
Simulation time 38439961 ps
CPU time 1.49 seconds
Started Aug 21 08:51:14 AM UTC 24
Finished Aug 21 08:51:17 AM UTC 24
Peak memory 236700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1831288089 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1831288089
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/23.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/23.edn_smoke.2992962951
Short name T408
Test name
Test status
Simulation time 38195873 ps
CPU time 1.36 seconds
Started Aug 21 08:51:13 AM UTC 24
Finished Aug 21 08:51:16 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2992962951 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.2992962951
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/23.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/23.edn_stress_all.4065858838
Short name T292
Test name
Test status
Simulation time 243833775 ps
CPU time 6.08 seconds
Started Aug 21 08:51:14 AM UTC 24
Finished Aug 21 08:51:21 AM UTC 24
Peak memory 231516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4065858838 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.4065858838
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/23.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/230.edn_genbits.305908152
Short name T903
Test name
Test status
Simulation time 44426205 ps
CPU time 1.07 seconds
Started Aug 21 08:54:02 AM UTC 24
Finished Aug 21 08:54:11 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=305908152 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.305908152
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/230.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/231.edn_genbits.3342927657
Short name T893
Test name
Test status
Simulation time 33469859 ps
CPU time 1.04 seconds
Started Aug 21 08:54:04 AM UTC 24
Finished Aug 21 08:54:06 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3342927657 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3342927657
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/231.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/232.edn_genbits.2261610724
Short name T905
Test name
Test status
Simulation time 108153022 ps
CPU time 1.49 seconds
Started Aug 21 08:54:05 AM UTC 24
Finished Aug 21 08:54:11 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2261610724 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2261610724
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/232.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/233.edn_genbits.127372579
Short name T908
Test name
Test status
Simulation time 48424666 ps
CPU time 1.45 seconds
Started Aug 21 08:54:07 AM UTC 24
Finished Aug 21 08:54:11 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=127372579 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.127372579
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/233.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/234.edn_genbits.2813642732
Short name T904
Test name
Test status
Simulation time 42739002 ps
CPU time 1.18 seconds
Started Aug 21 08:54:07 AM UTC 24
Finished Aug 21 08:54:11 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2813642732 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2813642732
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/234.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/235.edn_genbits.2015429146
Short name T912
Test name
Test status
Simulation time 66836506 ps
CPU time 1.5 seconds
Started Aug 21 08:54:07 AM UTC 24
Finished Aug 21 08:54:11 AM UTC 24
Peak memory 226512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2015429146 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2015429146
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/235.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/236.edn_genbits.2912774886
Short name T909
Test name
Test status
Simulation time 29892198 ps
CPU time 1.41 seconds
Started Aug 21 08:54:07 AM UTC 24
Finished Aug 21 08:54:11 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2912774886 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.2912774886
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/236.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/237.edn_genbits.910972054
Short name T911
Test name
Test status
Simulation time 62304479 ps
CPU time 1.42 seconds
Started Aug 21 08:54:07 AM UTC 24
Finished Aug 21 08:54:11 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=910972054 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.910972054
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/237.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/238.edn_genbits.1307543578
Short name T906
Test name
Test status
Simulation time 35546055 ps
CPU time 1.17 seconds
Started Aug 21 08:54:08 AM UTC 24
Finished Aug 21 08:54:11 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1307543578 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.1307543578
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/238.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/239.edn_genbits.971987055
Short name T322
Test name
Test status
Simulation time 68350129 ps
CPU time 1.17 seconds
Started Aug 21 08:54:08 AM UTC 24
Finished Aug 21 08:54:11 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=971987055 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.971987055
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/239.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/24.edn_alert.1563503299
Short name T190
Test name
Test status
Simulation time 80940005 ps
CPU time 1.65 seconds
Started Aug 21 08:51:19 AM UTC 24
Finished Aug 21 08:51:22 AM UTC 24
Peak memory 230484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1563503299 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1563503299
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/24.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/24.edn_alert_test.3127116900
Short name T420
Test name
Test status
Simulation time 110357345 ps
CPU time 2.12 seconds
Started Aug 21 08:51:20 AM UTC 24
Finished Aug 21 08:51:24 AM UTC 24
Peak memory 217308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3127116900 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3127116900
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/24.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/24.edn_disable_auto_req_mode.2591993952
Short name T418
Test name
Test status
Simulation time 78549637 ps
CPU time 1.57 seconds
Started Aug 21 08:51:19 AM UTC 24
Finished Aug 21 08:51:22 AM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2591993952 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_dis
able_auto_req_mode.2591993952
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/24.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/24.edn_err.2677513378
Short name T181
Test name
Test status
Simulation time 32480580 ps
CPU time 1.32 seconds
Started Aug 21 08:51:19 AM UTC 24
Finished Aug 21 08:51:21 AM UTC 24
Peak memory 236968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2677513378 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.2677513378
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/24.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/24.edn_genbits.2507975564
Short name T416
Test name
Test status
Simulation time 59643825 ps
CPU time 2.22 seconds
Started Aug 21 08:51:17 AM UTC 24
Finished Aug 21 08:51:20 AM UTC 24
Peak memory 231828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2507975564 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.2507975564
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/24.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/24.edn_intr.1939124060
Short name T417
Test name
Test status
Simulation time 27570885 ps
CPU time 1.37 seconds
Started Aug 21 08:51:18 AM UTC 24
Finished Aug 21 08:51:20 AM UTC 24
Peak memory 226436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1939124060 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.1939124060
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/24.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/24.edn_smoke.109445170
Short name T415
Test name
Test status
Simulation time 19305861 ps
CPU time 1.55 seconds
Started Aug 21 08:51:17 AM UTC 24
Finished Aug 21 08:51:19 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=109445170 -assert nopostproc +UVM_TESTNAME=ed
n_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.109445170
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/24.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/24.edn_stress_all.3044394927
Short name T253
Test name
Test status
Simulation time 179161352 ps
CPU time 4.52 seconds
Started Aug 21 08:51:18 AM UTC 24
Finished Aug 21 08:51:23 AM UTC 24
Peak memory 229712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3044394927 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3044394927
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/24.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/240.edn_genbits.3317442176
Short name T910
Test name
Test status
Simulation time 34679008 ps
CPU time 1.28 seconds
Started Aug 21 08:54:08 AM UTC 24
Finished Aug 21 08:54:11 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3317442176 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3317442176
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/240.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/241.edn_genbits.2753274019
Short name T344
Test name
Test status
Simulation time 56837680 ps
CPU time 1.2 seconds
Started Aug 21 08:54:08 AM UTC 24
Finished Aug 21 08:54:11 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2753274019 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.2753274019
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/241.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/242.edn_genbits.73288003
Short name T976
Test name
Test status
Simulation time 29301112 ps
CPU time 1.44 seconds
Started Aug 21 08:54:09 AM UTC 24
Finished Aug 21 08:54:42 AM UTC 24
Peak memory 228700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=73288003 -assert nopostproc +UVM_TESTNAME=edn
_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_
1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.73288003
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/242.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/243.edn_genbits.2191401324
Short name T341
Test name
Test status
Simulation time 45789990 ps
CPU time 1.34 seconds
Started Aug 21 08:54:12 AM UTC 24
Finished Aug 21 08:54:15 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2191401324 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.2191401324
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/243.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/244.edn_genbits.941829697
Short name T923
Test name
Test status
Simulation time 66711470 ps
CPU time 1.16 seconds
Started Aug 21 08:54:12 AM UTC 24
Finished Aug 21 08:54:17 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=941829697 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.941829697
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/244.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/245.edn_genbits.1982522752
Short name T922
Test name
Test status
Simulation time 66088613 ps
CPU time 1.1 seconds
Started Aug 21 08:54:12 AM UTC 24
Finished Aug 21 08:54:17 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1982522752 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.1982522752
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/245.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/247.edn_genbits.3452676824
Short name T938
Test name
Test status
Simulation time 576126032 ps
CPU time 4.86 seconds
Started Aug 21 08:54:12 AM UTC 24
Finished Aug 21 08:54:21 AM UTC 24
Peak memory 231756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3452676824 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.3452676824
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/247.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/248.edn_genbits.1191332126
Short name T927
Test name
Test status
Simulation time 83496484 ps
CPU time 1.38 seconds
Started Aug 21 08:54:12 AM UTC 24
Finished Aug 21 08:54:18 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1191332126 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1191332126
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/248.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/249.edn_genbits.2183014671
Short name T930
Test name
Test status
Simulation time 82285822 ps
CPU time 1.6 seconds
Started Aug 21 08:54:12 AM UTC 24
Finished Aug 21 08:54:18 AM UTC 24
Peak memory 230688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2183014671 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.2183014671
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/249.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/25.edn_alert.1210304208
Short name T191
Test name
Test status
Simulation time 27086726 ps
CPU time 1.83 seconds
Started Aug 21 08:51:22 AM UTC 24
Finished Aug 21 08:51:25 AM UTC 24
Peak memory 228436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1210304208 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.1210304208
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/25.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/25.edn_alert_test.1589736527
Short name T425
Test name
Test status
Simulation time 26233321 ps
CPU time 1.48 seconds
Started Aug 21 08:51:24 AM UTC 24
Finished Aug 21 08:51:27 AM UTC 24
Peak memory 217052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1589736527 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1589736527
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/25.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/25.edn_disable_auto_req_mode.3607298527
Short name T423
Test name
Test status
Simulation time 56472569 ps
CPU time 1.62 seconds
Started Aug 21 08:51:23 AM UTC 24
Finished Aug 21 08:51:26 AM UTC 24
Peak memory 226264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3607298527 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_dis
able_auto_req_mode.3607298527
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/25.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/25.edn_err.2605882182
Short name T186
Test name
Test status
Simulation time 24266403 ps
CPU time 1.5 seconds
Started Aug 21 08:51:22 AM UTC 24
Finished Aug 21 08:51:24 AM UTC 24
Peak memory 236968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2605882182 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.2605882182
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/25.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/25.edn_genbits.1617736395
Short name T295
Test name
Test status
Simulation time 232567767 ps
CPU time 1.69 seconds
Started Aug 21 08:51:21 AM UTC 24
Finished Aug 21 08:51:23 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1617736395 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1617736395
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/25.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/25.edn_intr.46369919
Short name T422
Test name
Test status
Simulation time 26847247 ps
CPU time 1.46 seconds
Started Aug 21 08:51:22 AM UTC 24
Finished Aug 21 08:51:24 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=46369919 -assert nopostproc +UVM_TESTNAME=edn
_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.46369919
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/25.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/25.edn_smoke.3101766892
Short name T419
Test name
Test status
Simulation time 22345334 ps
CPU time 1.36 seconds
Started Aug 21 08:51:20 AM UTC 24
Finished Aug 21 08:51:23 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3101766892 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.3101766892
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/25.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/25.edn_stress_all.3793197876
Short name T421
Test name
Test status
Simulation time 86028926 ps
CPU time 2.38 seconds
Started Aug 21 08:51:21 AM UTC 24
Finished Aug 21 08:51:24 AM UTC 24
Peak memory 229520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3793197876 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.3793197876
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/25.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/250.edn_genbits.1837021861
Short name T966
Test name
Test status
Simulation time 91459790 ps
CPU time 1.19 seconds
Started Aug 21 08:54:12 AM UTC 24
Finished Aug 21 08:54:28 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1837021861 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.1837021861
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/250.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/251.edn_genbits.756504165
Short name T929
Test name
Test status
Simulation time 72656747 ps
CPU time 1.43 seconds
Started Aug 21 08:54:12 AM UTC 24
Finished Aug 21 08:54:18 AM UTC 24
Peak memory 230616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=756504165 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.756504165
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/251.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/252.edn_genbits.2097611293
Short name T916
Test name
Test status
Simulation time 58359204 ps
CPU time 1 seconds
Started Aug 21 08:54:12 AM UTC 24
Finished Aug 21 08:54:15 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2097611293 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2097611293
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/252.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/253.edn_genbits.2931861473
Short name T928
Test name
Test status
Simulation time 38831649 ps
CPU time 1.38 seconds
Started Aug 21 08:54:12 AM UTC 24
Finished Aug 21 08:54:18 AM UTC 24
Peak memory 228560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2931861473 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.2931861473
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/253.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/254.edn_genbits.2224844978
Short name T925
Test name
Test status
Simulation time 47078887 ps
CPU time 1.13 seconds
Started Aug 21 08:54:12 AM UTC 24
Finished Aug 21 08:54:18 AM UTC 24
Peak memory 230608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2224844978 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2224844978
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/254.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/255.edn_genbits.2896650037
Short name T926
Test name
Test status
Simulation time 40520353 ps
CPU time 1.14 seconds
Started Aug 21 08:54:12 AM UTC 24
Finished Aug 21 08:54:18 AM UTC 24
Peak memory 228560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2896650037 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2896650037
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/255.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/256.edn_genbits.1895435341
Short name T918
Test name
Test status
Simulation time 34772125 ps
CPU time 1.22 seconds
Started Aug 21 08:54:12 AM UTC 24
Finished Aug 21 08:54:16 AM UTC 24
Peak memory 230608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1895435341 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1895435341
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/256.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/257.edn_genbits.1927568437
Short name T917
Test name
Test status
Simulation time 41289243 ps
CPU time 1 seconds
Started Aug 21 08:54:12 AM UTC 24
Finished Aug 21 08:54:15 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1927568437 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1927568437
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/257.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/258.edn_genbits.1111035
Short name T915
Test name
Test status
Simulation time 54361582 ps
CPU time 1.22 seconds
Started Aug 21 08:54:12 AM UTC 24
Finished Aug 21 08:54:15 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1111035 -assert nopostproc +UVM_TESTNAME=edn_
genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1
_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1111035
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/258.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/259.edn_genbits.2927368911
Short name T919
Test name
Test status
Simulation time 35612112 ps
CPU time 1.36 seconds
Started Aug 21 08:54:13 AM UTC 24
Finished Aug 21 08:54:16 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2927368911 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.2927368911
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/259.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/26.edn_alert.3321393512
Short name T146
Test name
Test status
Simulation time 24923839 ps
CPU time 1.88 seconds
Started Aug 21 08:51:25 AM UTC 24
Finished Aug 21 08:51:28 AM UTC 24
Peak memory 228436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3321393512 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3321393512
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/26.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/26.edn_alert_test.2177943819
Short name T427
Test name
Test status
Simulation time 38281127 ps
CPU time 1.32 seconds
Started Aug 21 08:51:27 AM UTC 24
Finished Aug 21 08:51:29 AM UTC 24
Peak memory 226832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2177943819 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2177943819
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/26.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/26.edn_disable.2359134345
Short name T195
Test name
Test status
Simulation time 12669836 ps
CPU time 1.39 seconds
Started Aug 21 08:51:25 AM UTC 24
Finished Aug 21 08:51:28 AM UTC 24
Peak memory 226384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2359134345 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2359134345
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/26.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/26.edn_disable_auto_req_mode.2877160769
Short name T428
Test name
Test status
Simulation time 31336565 ps
CPU time 1.75 seconds
Started Aug 21 08:51:27 AM UTC 24
Finished Aug 21 08:51:29 AM UTC 24
Peak memory 226240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2877160769 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_dis
able_auto_req_mode.2877160769
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/26.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/26.edn_err.4135508685
Short name T219
Test name
Test status
Simulation time 70954112 ps
CPU time 1.6 seconds
Started Aug 21 08:51:25 AM UTC 24
Finished Aug 21 08:51:28 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4135508685 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.4135508685
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/26.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/26.edn_genbits.3734469516
Short name T426
Test name
Test status
Simulation time 62012884 ps
CPU time 1.46 seconds
Started Aug 21 08:51:24 AM UTC 24
Finished Aug 21 08:51:27 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3734469516 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3734469516
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/26.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/26.edn_intr.271179751
Short name T113
Test name
Test status
Simulation time 40311671 ps
CPU time 1.37 seconds
Started Aug 21 08:51:25 AM UTC 24
Finished Aug 21 08:51:28 AM UTC 24
Peak memory 228248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=271179751 -assert nopostproc +UVM_TESTNAME=ed
n_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0
_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.271179751
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/26.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/26.edn_smoke.3789687368
Short name T424
Test name
Test status
Simulation time 16789564 ps
CPU time 1.43 seconds
Started Aug 21 08:51:24 AM UTC 24
Finished Aug 21 08:51:26 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3789687368 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3789687368
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/26.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/26.edn_stress_all.3353109639
Short name T293
Test name
Test status
Simulation time 496907735 ps
CPU time 5.4 seconds
Started Aug 21 08:51:24 AM UTC 24
Finished Aug 21 08:51:31 AM UTC 24
Peak memory 229508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3353109639 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3353109639
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/26.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/26.edn_stress_all_with_rand_reset.1697929690
Short name T235
Test name
Test status
Simulation time 3240012247 ps
CPU time 18.31 seconds
Started Aug 21 08:51:25 AM UTC 24
Finished Aug 21 08:51:45 AM UTC 24
Peak memory 229404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1697929690 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1697929690
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/26.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/260.edn_genbits.1337536793
Short name T920
Test name
Test status
Simulation time 76262137 ps
CPU time 1.41 seconds
Started Aug 21 08:54:13 AM UTC 24
Finished Aug 21 08:54:16 AM UTC 24
Peak memory 230608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1337536793 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.1337536793
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/260.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/261.edn_genbits.3072560473
Short name T921
Test name
Test status
Simulation time 199804308 ps
CPU time 2.39 seconds
Started Aug 21 08:54:13 AM UTC 24
Finished Aug 21 08:54:17 AM UTC 24
Peak memory 231484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3072560473 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3072560473
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/261.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/262.edn_genbits.3569111656
Short name T939
Test name
Test status
Simulation time 44418038 ps
CPU time 1.63 seconds
Started Aug 21 08:54:15 AM UTC 24
Finished Aug 21 08:54:21 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3569111656 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3569111656
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/262.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/263.edn_genbits.526214302
Short name T956
Test name
Test status
Simulation time 61964594 ps
CPU time 1.25 seconds
Started Aug 21 08:54:16 AM UTC 24
Finished Aug 21 08:54:26 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=526214302 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.526214302
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/263.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/264.edn_genbits.391266253
Short name T957
Test name
Test status
Simulation time 77203606 ps
CPU time 1.31 seconds
Started Aug 21 08:54:16 AM UTC 24
Finished Aug 21 08:54:26 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=391266253 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.391266253
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/264.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/265.edn_genbits.1128305294
Short name T961
Test name
Test status
Simulation time 184964706 ps
CPU time 1.3 seconds
Started Aug 21 08:54:16 AM UTC 24
Finished Aug 21 08:54:26 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1128305294 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.1128305294
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/265.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/266.edn_genbits.3985593510
Short name T959
Test name
Test status
Simulation time 106000311 ps
CPU time 1.31 seconds
Started Aug 21 08:54:16 AM UTC 24
Finished Aug 21 08:54:26 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3985593510 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.3985593510
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/266.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/267.edn_genbits.2418989557
Short name T958
Test name
Test status
Simulation time 52707528 ps
CPU time 1.1 seconds
Started Aug 21 08:54:16 AM UTC 24
Finished Aug 21 08:54:26 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2418989557 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2418989557
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/267.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/268.edn_genbits.3498205782
Short name T962
Test name
Test status
Simulation time 272797536 ps
CPU time 1.4 seconds
Started Aug 21 08:54:16 AM UTC 24
Finished Aug 21 08:54:26 AM UTC 24
Peak memory 230628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3498205782 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.3498205782
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/268.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/269.edn_genbits.2111556311
Short name T937
Test name
Test status
Simulation time 72912864 ps
CPU time 1.5 seconds
Started Aug 21 08:54:17 AM UTC 24
Finished Aug 21 08:54:21 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2111556311 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.2111556311
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/269.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/27.edn_alert.3673058046
Short name T431
Test name
Test status
Simulation time 27163552 ps
CPU time 1.86 seconds
Started Aug 21 08:51:29 AM UTC 24
Finished Aug 21 08:51:32 AM UTC 24
Peak memory 230484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3673058046 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.3673058046
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/27.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/27.edn_alert_test.2153346108
Short name T434
Test name
Test status
Simulation time 29490049 ps
CPU time 1.31 seconds
Started Aug 21 08:51:31 AM UTC 24
Finished Aug 21 08:51:34 AM UTC 24
Peak memory 216632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2153346108 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2153346108
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/27.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/27.edn_disable.3988986117
Short name T232
Test name
Test status
Simulation time 34111888 ps
CPU time 1.26 seconds
Started Aug 21 08:51:30 AM UTC 24
Finished Aug 21 08:51:33 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3988986117 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3988986117
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/27.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/27.edn_disable_auto_req_mode.1059128958
Short name T145
Test name
Test status
Simulation time 34599299 ps
CPU time 1.76 seconds
Started Aug 21 08:51:30 AM UTC 24
Finished Aug 21 08:51:33 AM UTC 24
Peak memory 226264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1059128958 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_dis
able_auto_req_mode.1059128958
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/27.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/27.edn_err.2608238335
Short name T217
Test name
Test status
Simulation time 20395684 ps
CPU time 1.56 seconds
Started Aug 21 08:51:29 AM UTC 24
Finished Aug 21 08:51:32 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2608238335 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2608238335
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/27.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/27.edn_genbits.741646589
Short name T14
Test name
Test status
Simulation time 68835260 ps
CPU time 2.1 seconds
Started Aug 21 08:51:28 AM UTC 24
Finished Aug 21 08:51:31 AM UTC 24
Peak memory 231764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=741646589 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.741646589
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/27.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/27.edn_intr.1626826698
Short name T430
Test name
Test status
Simulation time 36856458 ps
CPU time 1.41 seconds
Started Aug 21 08:51:29 AM UTC 24
Finished Aug 21 08:51:31 AM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1626826698 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1626826698
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/27.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/27.edn_smoke.2392667342
Short name T429
Test name
Test status
Simulation time 87702330 ps
CPU time 1.42 seconds
Started Aug 21 08:51:28 AM UTC 24
Finished Aug 21 08:51:30 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2392667342 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2392667342
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/27.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/270.edn_genbits.2796630439
Short name T944
Test name
Test status
Simulation time 58107558 ps
CPU time 2.12 seconds
Started Aug 21 08:54:17 AM UTC 24
Finished Aug 21 08:54:22 AM UTC 24
Peak memory 229756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2796630439 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2796630439
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/270.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/271.edn_genbits.657503602
Short name T931
Test name
Test status
Simulation time 40387070 ps
CPU time 1.06 seconds
Started Aug 21 08:54:19 AM UTC 24
Finished Aug 21 08:54:21 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=657503602 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.657503602
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/271.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/272.edn_genbits.3958712729
Short name T941
Test name
Test status
Simulation time 42840511 ps
CPU time 1.7 seconds
Started Aug 21 08:54:19 AM UTC 24
Finished Aug 21 08:54:21 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3958712729 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.3958712729
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/272.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/273.edn_genbits.1536918456
Short name T932
Test name
Test status
Simulation time 42391606 ps
CPU time 1.21 seconds
Started Aug 21 08:54:19 AM UTC 24
Finished Aug 21 08:54:21 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1536918456 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.1536918456
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/273.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/274.edn_genbits.3008190527
Short name T936
Test name
Test status
Simulation time 46736164 ps
CPU time 1.33 seconds
Started Aug 21 08:54:19 AM UTC 24
Finished Aug 21 08:54:21 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3008190527 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3008190527
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/274.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/275.edn_genbits.2536406813
Short name T934
Test name
Test status
Simulation time 36316057 ps
CPU time 1.15 seconds
Started Aug 21 08:54:19 AM UTC 24
Finished Aug 21 08:54:21 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2536406813 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2536406813
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/275.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/276.edn_genbits.2896134762
Short name T933
Test name
Test status
Simulation time 27901527 ps
CPU time 1.1 seconds
Started Aug 21 08:54:19 AM UTC 24
Finished Aug 21 08:54:21 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2896134762 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.2896134762
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/276.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/277.edn_genbits.2827725096
Short name T935
Test name
Test status
Simulation time 185551746 ps
CPU time 1.16 seconds
Started Aug 21 08:54:19 AM UTC 24
Finished Aug 21 08:54:21 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2827725096 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2827725096
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/277.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/278.edn_genbits.3658336490
Short name T942
Test name
Test status
Simulation time 47586785 ps
CPU time 1.43 seconds
Started Aug 21 08:54:19 AM UTC 24
Finished Aug 21 08:54:21 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3658336490 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3658336490
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/278.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/279.edn_genbits.4239637348
Short name T964
Test name
Test status
Simulation time 73381773 ps
CPU time 1.07 seconds
Started Aug 21 08:54:22 AM UTC 24
Finished Aug 21 08:54:27 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4239637348 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.4239637348
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/279.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/28.edn_alert.1821311576
Short name T210
Test name
Test status
Simulation time 67911295 ps
CPU time 1.49 seconds
Started Aug 21 08:51:33 AM UTC 24
Finished Aug 21 08:51:35 AM UTC 24
Peak memory 228436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1821311576 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.1821311576
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/28.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/28.edn_alert_test.2794535811
Short name T439
Test name
Test status
Simulation time 26682928 ps
CPU time 1.47 seconds
Started Aug 21 08:51:35 AM UTC 24
Finished Aug 21 08:51:37 AM UTC 24
Peak memory 217052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2794535811 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2794535811
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/28.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/28.edn_disable.39264806
Short name T216
Test name
Test status
Simulation time 33958274 ps
CPU time 1.28 seconds
Started Aug 21 08:51:34 AM UTC 24
Finished Aug 21 08:51:36 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=39264806 -assert nop
ostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op
entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.39264806
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/28.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/28.edn_disable_auto_req_mode.263869002
Short name T436
Test name
Test status
Simulation time 69125119 ps
CPU time 1.3 seconds
Started Aug 21 08:51:34 AM UTC 24
Finished Aug 21 08:51:36 AM UTC 24
Peak memory 228032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=263869002 -assert no
postproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disa
ble_auto_req_mode.263869002
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/28.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/28.edn_err.788484719
Short name T176
Test name
Test status
Simulation time 18922103 ps
CPU time 1.53 seconds
Started Aug 21 08:51:34 AM UTC 24
Finished Aug 21 08:51:36 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=788484719 -assert nopostproc +UVM_TESTNAME=ed
n_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2
024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.788484719
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/28.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/28.edn_genbits.1189313974
Short name T315
Test name
Test status
Simulation time 43188508 ps
CPU time 1.65 seconds
Started Aug 21 08:51:31 AM UTC 24
Finished Aug 21 08:51:34 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1189313974 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.1189313974
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/28.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/28.edn_intr.2303453566
Short name T435
Test name
Test status
Simulation time 26517813 ps
CPU time 1.3 seconds
Started Aug 21 08:51:33 AM UTC 24
Finished Aug 21 08:51:35 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2303453566 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2303453566
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/28.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/28.edn_smoke.2353826793
Short name T433
Test name
Test status
Simulation time 45917061 ps
CPU time 1.3 seconds
Started Aug 21 08:51:31 AM UTC 24
Finished Aug 21 08:51:34 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2353826793 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2353826793
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/28.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/28.edn_stress_all.3047669888
Short name T437
Test name
Test status
Simulation time 245927623 ps
CPU time 2.97 seconds
Started Aug 21 08:51:32 AM UTC 24
Finished Aug 21 08:51:37 AM UTC 24
Peak memory 231580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3047669888 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3047669888
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/28.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/28.edn_stress_all_with_rand_reset.3653060096
Short name T509
Test name
Test status
Simulation time 1654941954 ps
CPU time 36.06 seconds
Started Aug 21 08:51:32 AM UTC 24
Finished Aug 21 08:52:10 AM UTC 24
Peak memory 231636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3653060096 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.3653060096
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/28.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/280.edn_genbits.1006052279
Short name T965
Test name
Test status
Simulation time 66502982 ps
CPU time 1.29 seconds
Started Aug 21 08:54:22 AM UTC 24
Finished Aug 21 08:54:27 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1006052279 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1006052279
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/280.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/281.edn_genbits.1799971484
Short name T963
Test name
Test status
Simulation time 296845159 ps
CPU time 0.98 seconds
Started Aug 21 08:54:22 AM UTC 24
Finished Aug 21 08:54:27 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1799971484 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1799971484
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/281.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/282.edn_genbits.1557918984
Short name T953
Test name
Test status
Simulation time 38085504 ps
CPU time 1.59 seconds
Started Aug 21 08:54:22 AM UTC 24
Finished Aug 21 08:54:26 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1557918984 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.1557918984
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/282.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/283.edn_genbits.3379032165
Short name T950
Test name
Test status
Simulation time 52307844 ps
CPU time 1.42 seconds
Started Aug 21 08:54:22 AM UTC 24
Finished Aug 21 08:54:25 AM UTC 24
Peak memory 228104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3379032165 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.3379032165
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/283.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/284.edn_genbits.1265349181
Short name T949
Test name
Test status
Simulation time 56017205 ps
CPU time 1.33 seconds
Started Aug 21 08:54:22 AM UTC 24
Finished Aug 21 08:54:25 AM UTC 24
Peak memory 228144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1265349181 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1265349181
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/284.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/285.edn_genbits.4256880354
Short name T947
Test name
Test status
Simulation time 57773382 ps
CPU time 1.2 seconds
Started Aug 21 08:54:22 AM UTC 24
Finished Aug 21 08:54:25 AM UTC 24
Peak memory 230292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4256880354 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.4256880354
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/285.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/286.edn_genbits.973700616
Short name T347
Test name
Test status
Simulation time 23865838 ps
CPU time 1.22 seconds
Started Aug 21 08:54:22 AM UTC 24
Finished Aug 21 08:54:25 AM UTC 24
Peak memory 228216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=973700616 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.973700616
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/286.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/287.edn_genbits.1812033896
Short name T951
Test name
Test status
Simulation time 61297029 ps
CPU time 1.38 seconds
Started Aug 21 08:54:22 AM UTC 24
Finished Aug 21 08:54:26 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1812033896 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1812033896
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/287.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/288.edn_genbits.1613838164
Short name T960
Test name
Test status
Simulation time 67433773 ps
CPU time 1.48 seconds
Started Aug 21 08:54:22 AM UTC 24
Finished Aug 21 08:54:26 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1613838164 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.1613838164
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/288.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/289.edn_genbits.98032567
Short name T954
Test name
Test status
Simulation time 103324315 ps
CPU time 1.41 seconds
Started Aug 21 08:54:22 AM UTC 24
Finished Aug 21 08:54:26 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=98032567 -assert nopostproc +UVM_TESTNAME=edn
_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_
1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.98032567
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/289.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/29.edn_alert.2917762671
Short name T444
Test name
Test status
Simulation time 63181966 ps
CPU time 1.76 seconds
Started Aug 21 08:51:37 AM UTC 24
Finished Aug 21 08:51:40 AM UTC 24
Peak memory 230484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2917762671 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.2917762671
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/29.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/29.edn_alert_test.2035785082
Short name T446
Test name
Test status
Simulation time 38506327 ps
CPU time 1.21 seconds
Started Aug 21 08:51:38 AM UTC 24
Finished Aug 21 08:51:41 AM UTC 24
Peak memory 216388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2035785082 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.2035785082
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/29.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/29.edn_disable.1610376576
Short name T442
Test name
Test status
Simulation time 29326473 ps
CPU time 1.17 seconds
Started Aug 21 08:51:37 AM UTC 24
Finished Aug 21 08:51:39 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1610376576 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1610376576
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/29.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/29.edn_disable_auto_req_mode.298307272
Short name T445
Test name
Test status
Simulation time 38763809 ps
CPU time 2.04 seconds
Started Aug 21 08:51:37 AM UTC 24
Finished Aug 21 08:51:40 AM UTC 24
Peak memory 228064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=298307272 -assert no
postproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disa
ble_auto_req_mode.298307272
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/29.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/29.edn_err.2998927045
Short name T443
Test name
Test status
Simulation time 22316373 ps
CPU time 1.31 seconds
Started Aug 21 08:51:37 AM UTC 24
Finished Aug 21 08:51:40 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2998927045 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2998927045
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/29.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/29.edn_genbits.4291012846
Short name T440
Test name
Test status
Simulation time 297827300 ps
CPU time 1.83 seconds
Started Aug 21 08:51:35 AM UTC 24
Finished Aug 21 08:51:38 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4291012846 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.4291012846
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/29.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/29.edn_intr.1214180729
Short name T441
Test name
Test status
Simulation time 29171720 ps
CPU time 1.37 seconds
Started Aug 21 08:51:36 AM UTC 24
Finished Aug 21 08:51:39 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1214180729 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.1214180729
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/29.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/29.edn_smoke.1103265597
Short name T438
Test name
Test status
Simulation time 135950908 ps
CPU time 1.14 seconds
Started Aug 21 08:51:35 AM UTC 24
Finished Aug 21 08:51:37 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1103265597 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.1103265597
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/29.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/29.edn_stress_all.3754107572
Short name T448
Test name
Test status
Simulation time 237569350 ps
CPU time 6.77 seconds
Started Aug 21 08:51:35 AM UTC 24
Finished Aug 21 08:51:43 AM UTC 24
Peak memory 227400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3754107572 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3754107572
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/29.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/29.edn_stress_all_with_rand_reset.2487837881
Short name T323
Test name
Test status
Simulation time 5896984139 ps
CPU time 22.6 seconds
Started Aug 21 08:51:36 AM UTC 24
Finished Aug 21 08:52:00 AM UTC 24
Peak memory 229720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2487837881 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2487837881
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/29.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/290.edn_genbits.2519917656
Short name T948
Test name
Test status
Simulation time 103577847 ps
CPU time 1.1 seconds
Started Aug 21 08:54:22 AM UTC 24
Finished Aug 21 08:54:25 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2519917656 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2519917656
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/290.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/291.edn_genbits.3651589979
Short name T952
Test name
Test status
Simulation time 47554373 ps
CPU time 1.37 seconds
Started Aug 21 08:54:23 AM UTC 24
Finished Aug 21 08:54:26 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3651589979 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.3651589979
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/291.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/292.edn_genbits.3205813155
Short name T955
Test name
Test status
Simulation time 88257865 ps
CPU time 1.32 seconds
Started Aug 21 08:54:23 AM UTC 24
Finished Aug 21 08:54:26 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3205813155 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3205813155
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/292.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/293.edn_genbits.1082914649
Short name T973
Test name
Test status
Simulation time 41511168 ps
CPU time 1.01 seconds
Started Aug 21 08:54:26 AM UTC 24
Finished Aug 21 08:54:36 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1082914649 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1082914649
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/293.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/294.edn_genbits.4053802793
Short name T974
Test name
Test status
Simulation time 37382806 ps
CPU time 1.3 seconds
Started Aug 21 08:54:26 AM UTC 24
Finished Aug 21 08:54:36 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4053802793 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.4053802793
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/294.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/295.edn_genbits.3510010655
Short name T967
Test name
Test status
Simulation time 87950367 ps
CPU time 1.09 seconds
Started Aug 21 08:54:26 AM UTC 24
Finished Aug 21 08:54:30 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3510010655 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.3510010655
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/295.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/296.edn_genbits.601733590
Short name T969
Test name
Test status
Simulation time 96331222 ps
CPU time 1.1 seconds
Started Aug 21 08:54:26 AM UTC 24
Finished Aug 21 08:54:30 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=601733590 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.601733590
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/296.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/297.edn_genbits.1875708169
Short name T971
Test name
Test status
Simulation time 45277379 ps
CPU time 1.41 seconds
Started Aug 21 08:54:26 AM UTC 24
Finished Aug 21 08:54:30 AM UTC 24
Peak memory 228552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1875708169 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1875708169
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/297.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/298.edn_genbits.398187056
Short name T975
Test name
Test status
Simulation time 106888281 ps
CPU time 1.1 seconds
Started Aug 21 08:54:26 AM UTC 24
Finished Aug 21 08:54:36 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=398187056 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.398187056
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/298.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/299.edn_genbits.3484377969
Short name T968
Test name
Test status
Simulation time 41046661 ps
CPU time 1.11 seconds
Started Aug 21 08:54:26 AM UTC 24
Finished Aug 21 08:54:30 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3484377969 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3484377969
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/299.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/3.edn_alert_test.2717377721
Short name T72
Test name
Test status
Simulation time 16296135 ps
CPU time 1.27 seconds
Started Aug 21 08:50:23 AM UTC 24
Finished Aug 21 08:50:26 AM UTC 24
Peak memory 226912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2717377721 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2717377721
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/3.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/3.edn_disable.3578801350
Short name T41
Test name
Test status
Simulation time 37567545 ps
CPU time 1.35 seconds
Started Aug 21 08:50:22 AM UTC 24
Finished Aug 21 08:50:25 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3578801350 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.3578801350
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/3.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/3.edn_err.2037946332
Short name T8
Test name
Test status
Simulation time 26521774 ps
CPU time 2.02 seconds
Started Aug 21 08:50:22 AM UTC 24
Finished Aug 21 08:50:25 AM UTC 24
Peak memory 245740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2037946332 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2037946332
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/3.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/3.edn_genbits.3405534479
Short name T40
Test name
Test status
Simulation time 50458933 ps
CPU time 2.37 seconds
Started Aug 21 08:50:21 AM UTC 24
Finished Aug 21 08:50:25 AM UTC 24
Peak memory 229772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3405534479 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3405534479
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/3.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/3.edn_intr.4063511631
Short name T31
Test name
Test status
Simulation time 25732142 ps
CPU time 1.47 seconds
Started Aug 21 08:50:22 AM UTC 24
Finished Aug 21 08:50:25 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4063511631 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.4063511631
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/3.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/3.edn_regwen.256376869
Short name T308
Test name
Test status
Simulation time 19310877 ps
CPU time 1.38 seconds
Started Aug 21 08:50:21 AM UTC 24
Finished Aug 21 08:50:23 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=256376869 -assert nopostproc +UVM_TESTNAME=ed
n_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.256376869
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/3.edn_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/3.edn_sec_cm.1536919348
Short name T63
Test name
Test status
Simulation time 1429260282 ps
CPU time 12.33 seconds
Started Aug 21 08:50:23 AM UTC 24
Finished Aug 21 08:50:37 AM UTC 24
Peak memory 260560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1536919348 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.1536919348
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/3.edn_sec_cm/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/3.edn_smoke.1199314207
Short name T125
Test name
Test status
Simulation time 188786341 ps
CPU time 1.09 seconds
Started Aug 21 08:50:21 AM UTC 24
Finished Aug 21 08:50:23 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1199314207 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.1199314207
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/3.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/3.edn_stress_all.2916376614
Short name T65
Test name
Test status
Simulation time 225217221 ps
CPU time 4.95 seconds
Started Aug 21 08:50:21 AM UTC 24
Finished Aug 21 08:50:27 AM UTC 24
Peak memory 227412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2916376614 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2916376614
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/3.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/3.edn_stress_all_with_rand_reset.4076975504
Short name T214
Test name
Test status
Simulation time 2503892903 ps
CPU time 69.43 seconds
Started Aug 21 08:50:21 AM UTC 24
Finished Aug 21 08:51:33 AM UTC 24
Peak memory 231836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4076975504 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.4076975504
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/3.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/30.edn_alert.1264427394
Short name T451
Test name
Test status
Simulation time 97481504 ps
CPU time 1.52 seconds
Started Aug 21 08:51:41 AM UTC 24
Finished Aug 21 08:51:43 AM UTC 24
Peak memory 228436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1264427394 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1264427394
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/30.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/30.edn_alert_test.481968321
Short name T454
Test name
Test status
Simulation time 33854584 ps
CPU time 1.31 seconds
Started Aug 21 08:51:42 AM UTC 24
Finished Aug 21 08:51:45 AM UTC 24
Peak memory 215696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=481968321 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.481968321
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/30.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/30.edn_disable.2044291332
Short name T449
Test name
Test status
Simulation time 22934814 ps
CPU time 1.31 seconds
Started Aug 21 08:51:41 AM UTC 24
Finished Aug 21 08:51:43 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2044291332 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.2044291332
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/30.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/30.edn_disable_auto_req_mode.1377022016
Short name T452
Test name
Test status
Simulation time 29314625 ps
CPU time 1.37 seconds
Started Aug 21 08:51:42 AM UTC 24
Finished Aug 21 08:51:45 AM UTC 24
Peak memory 228104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1377022016 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_dis
able_auto_req_mode.1377022016
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/30.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/30.edn_err.515647274
Short name T140
Test name
Test status
Simulation time 52392635 ps
CPU time 1.5 seconds
Started Aug 21 08:51:41 AM UTC 24
Finished Aug 21 08:51:43 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=515647274 -assert nopostproc +UVM_TESTNAME=ed
n_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2
024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.515647274
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/30.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/30.edn_genbits.1833417138
Short name T107
Test name
Test status
Simulation time 45875816 ps
CPU time 1.96 seconds
Started Aug 21 08:51:39 AM UTC 24
Finished Aug 21 08:51:42 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1833417138 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1833417138
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/30.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/30.edn_intr.1011334730
Short name T450
Test name
Test status
Simulation time 26574054 ps
CPU time 1.54 seconds
Started Aug 21 08:51:41 AM UTC 24
Finished Aug 21 08:51:43 AM UTC 24
Peak memory 237896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1011334730 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.1011334730
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/30.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/30.edn_smoke.2917373785
Short name T447
Test name
Test status
Simulation time 83565236 ps
CPU time 1.33 seconds
Started Aug 21 08:51:39 AM UTC 24
Finished Aug 21 08:51:41 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2917373785 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2917373785
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/30.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/30.edn_stress_all.3856479032
Short name T251
Test name
Test status
Simulation time 570420659 ps
CPU time 1.72 seconds
Started Aug 21 08:51:39 AM UTC 24
Finished Aug 21 08:51:41 AM UTC 24
Peak memory 226684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3856479032 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.3856479032
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/30.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/31.edn_alert.3066384614
Short name T206
Test name
Test status
Simulation time 36830594 ps
CPU time 1.88 seconds
Started Aug 21 08:51:45 AM UTC 24
Finished Aug 21 08:51:47 AM UTC 24
Peak memory 226388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3066384614 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.3066384614
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/31.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/31.edn_alert_test.3590958016
Short name T459
Test name
Test status
Simulation time 33685715 ps
CPU time 1.07 seconds
Started Aug 21 08:51:46 AM UTC 24
Finished Aug 21 08:51:48 AM UTC 24
Peak memory 217292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3590958016 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3590958016
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/31.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/31.edn_disable.2230825065
Short name T456
Test name
Test status
Simulation time 45225937 ps
CPU time 1.13 seconds
Started Aug 21 08:51:45 AM UTC 24
Finished Aug 21 08:51:47 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2230825065 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2230825065
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/31.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/31.edn_disable_auto_req_mode.1504738314
Short name T457
Test name
Test status
Simulation time 101356750 ps
CPU time 1.66 seconds
Started Aug 21 08:51:45 AM UTC 24
Finished Aug 21 08:51:47 AM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1504738314 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_dis
able_auto_req_mode.1504738314
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/31.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/31.edn_err.1474197394
Short name T227
Test name
Test status
Simulation time 23848965 ps
CPU time 1.41 seconds
Started Aug 21 08:51:45 AM UTC 24
Finished Aug 21 08:51:47 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1474197394 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1474197394
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/31.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/31.edn_genbits.3825825362
Short name T314
Test name
Test status
Simulation time 84483423 ps
CPU time 1.92 seconds
Started Aug 21 08:51:42 AM UTC 24
Finished Aug 21 08:51:45 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3825825362 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.3825825362
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/31.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/31.edn_intr.1768844063
Short name T455
Test name
Test status
Simulation time 27273514 ps
CPU time 1.42 seconds
Started Aug 21 08:51:43 AM UTC 24
Finished Aug 21 08:51:46 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1768844063 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.1768844063
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/31.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/31.edn_smoke.1114420169
Short name T453
Test name
Test status
Simulation time 43736828 ps
CPU time 1.39 seconds
Started Aug 21 08:51:42 AM UTC 24
Finished Aug 21 08:51:45 AM UTC 24
Peak memory 226208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1114420169 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1114420169
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/31.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/31.edn_stress_all.2890901744
Short name T458
Test name
Test status
Simulation time 136534444 ps
CPU time 4.13 seconds
Started Aug 21 08:51:42 AM UTC 24
Finished Aug 21 08:51:48 AM UTC 24
Peak memory 229536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2890901744 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.2890901744
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/31.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/31.edn_stress_all_with_rand_reset.822422353
Short name T590
Test name
Test status
Simulation time 10779337300 ps
CPU time 65.94 seconds
Started Aug 21 08:51:43 AM UTC 24
Finished Aug 21 08:52:51 AM UTC 24
Peak memory 229844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=822422353 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.822422353
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/31.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/32.edn_alert.4282760814
Short name T161
Test name
Test status
Simulation time 38151313 ps
CPU time 1.45 seconds
Started Aug 21 08:51:47 AM UTC 24
Finished Aug 21 08:51:50 AM UTC 24
Peak memory 228436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4282760814 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.4282760814
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/32.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/32.edn_alert_test.799274353
Short name T464
Test name
Test status
Simulation time 35821630 ps
CPU time 1.43 seconds
Started Aug 21 08:51:48 AM UTC 24
Finished Aug 21 08:51:51 AM UTC 24
Peak memory 216220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=799274353 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.799274353
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/32.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/32.edn_disable.3468849154
Short name T463
Test name
Test status
Simulation time 54007423 ps
CPU time 1.15 seconds
Started Aug 21 08:51:48 AM UTC 24
Finished Aug 21 08:51:51 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3468849154 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3468849154
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/32.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/32.edn_disable_auto_req_mode.3415038345
Short name T466
Test name
Test status
Simulation time 68977055 ps
CPU time 1.62 seconds
Started Aug 21 08:51:48 AM UTC 24
Finished Aug 21 08:51:51 AM UTC 24
Peak memory 226264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3415038345 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_dis
able_auto_req_mode.3415038345
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/32.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/32.edn_err.73887734
Short name T184
Test name
Test status
Simulation time 24533933 ps
CPU time 1.51 seconds
Started Aug 21 08:51:48 AM UTC 24
Finished Aug 21 08:51:51 AM UTC 24
Peak memory 237220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=73887734 -assert nopostproc +UVM_TESTNAME=edn
_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_20
24_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.73887734
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/32.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/32.edn_genbits.3595726964
Short name T460
Test name
Test status
Simulation time 60029301 ps
CPU time 1.35 seconds
Started Aug 21 08:51:46 AM UTC 24
Finished Aug 21 08:51:48 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3595726964 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3595726964
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/32.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/32.edn_intr.377015644
Short name T462
Test name
Test status
Simulation time 37283196 ps
CPU time 0.98 seconds
Started Aug 21 08:51:47 AM UTC 24
Finished Aug 21 08:51:49 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=377015644 -assert nopostproc +UVM_TESTNAME=ed
n_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0
_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.377015644
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/32.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/32.edn_smoke.3461867255
Short name T461
Test name
Test status
Simulation time 25352589 ps
CPU time 1.44 seconds
Started Aug 21 08:51:46 AM UTC 24
Finished Aug 21 08:51:48 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3461867255 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.3461867255
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/32.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/32.edn_stress_all.2419379884
Short name T468
Test name
Test status
Simulation time 644458816 ps
CPU time 5.91 seconds
Started Aug 21 08:51:46 AM UTC 24
Finished Aug 21 08:51:53 AM UTC 24
Peak memory 229468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2419379884 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.2419379884
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/32.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/33.edn_alert.3724374891
Short name T178
Test name
Test status
Simulation time 27539993 ps
CPU time 1.52 seconds
Started Aug 21 08:51:50 AM UTC 24
Finished Aug 21 08:51:53 AM UTC 24
Peak memory 228436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3724374891 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3724374891
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/33.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/33.edn_alert_test.3855881496
Short name T469
Test name
Test status
Simulation time 46583219 ps
CPU time 1.32 seconds
Started Aug 21 08:51:51 AM UTC 24
Finished Aug 21 08:51:53 AM UTC 24
Peak memory 226880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3855881496 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.3855881496
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/33.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/33.edn_err.491611401
Short name T158
Test name
Test status
Simulation time 25341732 ps
CPU time 1.4 seconds
Started Aug 21 08:51:50 AM UTC 24
Finished Aug 21 08:51:53 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=491611401 -assert nopostproc +UVM_TESTNAME=ed
n_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2
024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.491611401
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/33.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/33.edn_intr.3612402508
Short name T36
Test name
Test status
Simulation time 45526093 ps
CPU time 1.32 seconds
Started Aug 21 08:51:50 AM UTC 24
Finished Aug 21 08:51:53 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3612402508 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3612402508
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/33.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/33.edn_smoke.2990753648
Short name T465
Test name
Test status
Simulation time 30566949 ps
CPU time 1.48 seconds
Started Aug 21 08:51:49 AM UTC 24
Finished Aug 21 08:51:51 AM UTC 24
Peak memory 226248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2990753648 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.2990753648
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/33.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/33.edn_stress_all.814243388
Short name T473
Test name
Test status
Simulation time 861003974 ps
CPU time 5.34 seconds
Started Aug 21 08:51:49 AM UTC 24
Finished Aug 21 08:51:55 AM UTC 24
Peak memory 229528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=814243388 -asser
t nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.814243388
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/33.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/33.edn_stress_all_with_rand_reset.3616889178
Short name T587
Test name
Test status
Simulation time 3092731858 ps
CPU time 59.34 seconds
Started Aug 21 08:51:49 AM UTC 24
Finished Aug 21 08:52:50 AM UTC 24
Peak memory 229724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3616889178 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3616889178
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/33.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/34.edn_alert_test.1456864153
Short name T475
Test name
Test status
Simulation time 21722893 ps
CPU time 0.93 seconds
Started Aug 21 08:51:54 AM UTC 24
Finished Aug 21 08:51:56 AM UTC 24
Peak memory 226912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1456864153 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1456864153
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/34.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/34.edn_disable.172062408
Short name T476
Test name
Test status
Simulation time 12285350 ps
CPU time 1.24 seconds
Started Aug 21 08:51:54 AM UTC 24
Finished Aug 21 08:51:56 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=172062408 -assert no
postproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o
pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.172062408
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/34.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/34.edn_disable_auto_req_mode.4000354326
Short name T480
Test name
Test status
Simulation time 145396545 ps
CPU time 1.79 seconds
Started Aug 21 08:51:54 AM UTC 24
Finished Aug 21 08:51:57 AM UTC 24
Peak memory 226264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4000354326 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_dis
able_auto_req_mode.4000354326
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/34.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/34.edn_err.2125264794
Short name T474
Test name
Test status
Simulation time 56089643 ps
CPU time 1.74 seconds
Started Aug 21 08:51:52 AM UTC 24
Finished Aug 21 08:51:55 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2125264794 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.2125264794
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/34.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/34.edn_genbits.1004093544
Short name T472
Test name
Test status
Simulation time 52324913 ps
CPU time 1.5 seconds
Started Aug 21 08:51:52 AM UTC 24
Finished Aug 21 08:51:55 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1004093544 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1004093544
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/34.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/34.edn_intr.1148743283
Short name T471
Test name
Test status
Simulation time 47082934 ps
CPU time 1.24 seconds
Started Aug 21 08:51:52 AM UTC 24
Finished Aug 21 08:51:55 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1148743283 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1148743283
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/34.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/34.edn_smoke.1959088870
Short name T470
Test name
Test status
Simulation time 16698941 ps
CPU time 1.39 seconds
Started Aug 21 08:51:51 AM UTC 24
Finished Aug 21 08:51:54 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1959088870 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1959088870
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/34.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/34.edn_stress_all.2756995011
Short name T486
Test name
Test status
Simulation time 626387241 ps
CPU time 6.27 seconds
Started Aug 21 08:51:52 AM UTC 24
Finished Aug 21 08:52:00 AM UTC 24
Peak memory 227484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2756995011 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.2756995011
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/34.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/34.edn_stress_all_with_rand_reset.4000859907
Short name T580
Test name
Test status
Simulation time 21150905688 ps
CPU time 53.41 seconds
Started Aug 21 08:51:52 AM UTC 24
Finished Aug 21 08:52:47 AM UTC 24
Peak memory 230068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4000859907 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.4000859907
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/34.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/35.edn_alert.3575384222
Short name T155
Test name
Test status
Simulation time 214951061 ps
CPU time 1.81 seconds
Started Aug 21 08:51:55 AM UTC 24
Finished Aug 21 08:51:58 AM UTC 24
Peak memory 228436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3575384222 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.3575384222
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/35.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/35.edn_alert_test.348196680
Short name T484
Test name
Test status
Simulation time 37268070 ps
CPU time 1.42 seconds
Started Aug 21 08:51:56 AM UTC 24
Finished Aug 21 08:51:59 AM UTC 24
Peak memory 226752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=348196680 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.348196680
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/35.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/35.edn_disable.3194526581
Short name T482
Test name
Test status
Simulation time 12598420 ps
CPU time 1.23 seconds
Started Aug 21 08:51:56 AM UTC 24
Finished Aug 21 08:51:59 AM UTC 24
Peak memory 226364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3194526581 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.3194526581
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/35.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/35.edn_disable_auto_req_mode.1166759316
Short name T485
Test name
Test status
Simulation time 55413988 ps
CPU time 1.7 seconds
Started Aug 21 08:51:56 AM UTC 24
Finished Aug 21 08:51:59 AM UTC 24
Peak memory 226264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1166759316 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_dis
able_auto_req_mode.1166759316
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/35.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/35.edn_err.2950923694
Short name T170
Test name
Test status
Simulation time 36995124 ps
CPU time 1.3 seconds
Started Aug 21 08:51:56 AM UTC 24
Finished Aug 21 08:51:59 AM UTC 24
Peak memory 230288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2950923694 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.2950923694
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/35.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/35.edn_genbits.1905526331
Short name T477
Test name
Test status
Simulation time 50408397 ps
CPU time 1.33 seconds
Started Aug 21 08:51:54 AM UTC 24
Finished Aug 21 08:51:56 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1905526331 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1905526331
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/35.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/35.edn_intr.1116511480
Short name T481
Test name
Test status
Simulation time 24653658 ps
CPU time 1.17 seconds
Started Aug 21 08:51:55 AM UTC 24
Finished Aug 21 08:51:58 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1116511480 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1116511480
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/35.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/35.edn_smoke.1175565943
Short name T478
Test name
Test status
Simulation time 18895422 ps
CPU time 1.32 seconds
Started Aug 21 08:51:54 AM UTC 24
Finished Aug 21 08:51:56 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1175565943 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.1175565943
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/35.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/35.edn_stress_all.619224885
Short name T479
Test name
Test status
Simulation time 71273326 ps
CPU time 1.32 seconds
Started Aug 21 08:51:54 AM UTC 24
Finished Aug 21 08:51:56 AM UTC 24
Peak memory 216708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=619224885 -asser
t nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.619224885
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/35.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/35.edn_stress_all_with_rand_reset.4225628797
Short name T247
Test name
Test status
Simulation time 10624811007 ps
CPU time 28.74 seconds
Started Aug 21 08:51:55 AM UTC 24
Finished Aug 21 08:52:25 AM UTC 24
Peak memory 229868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4225628797 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.4225628797
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/35.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/36.edn_alert.1582910925
Short name T487
Test name
Test status
Simulation time 48760759 ps
CPU time 1.59 seconds
Started Aug 21 08:51:58 AM UTC 24
Finished Aug 21 08:52:00 AM UTC 24
Peak memory 230484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1582910925 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.1582910925
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/36.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/36.edn_alert_test.2953549060
Short name T490
Test name
Test status
Simulation time 80331277 ps
CPU time 1.17 seconds
Started Aug 21 08:51:59 AM UTC 24
Finished Aug 21 08:52:01 AM UTC 24
Peak memory 226912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2953549060 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2953549060
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/36.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/36.edn_disable.2795482268
Short name T489
Test name
Test status
Simulation time 16806682 ps
CPU time 1.01 seconds
Started Aug 21 08:51:59 AM UTC 24
Finished Aug 21 08:52:01 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2795482268 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2795482268
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/36.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/36.edn_disable_auto_req_mode.3501806244
Short name T491
Test name
Test status
Simulation time 83472505 ps
CPU time 1.53 seconds
Started Aug 21 08:51:59 AM UTC 24
Finished Aug 21 08:52:01 AM UTC 24
Peak memory 230360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3501806244 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_dis
able_auto_req_mode.3501806244
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/36.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/36.edn_err.1403977796
Short name T148
Test name
Test status
Simulation time 27839972 ps
CPU time 1.81 seconds
Started Aug 21 08:51:58 AM UTC 24
Finished Aug 21 08:52:01 AM UTC 24
Peak memory 243984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1403977796 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1403977796
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/36.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/36.edn_genbits.3504914510
Short name T108
Test name
Test status
Simulation time 42035876 ps
CPU time 2.05 seconds
Started Aug 21 08:51:57 AM UTC 24
Finished Aug 21 08:52:01 AM UTC 24
Peak memory 229524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3504914510 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3504914510
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/36.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/36.edn_intr.3646626515
Short name T488
Test name
Test status
Simulation time 23739055 ps
CPU time 1.75 seconds
Started Aug 21 08:51:57 AM UTC 24
Finished Aug 21 08:52:00 AM UTC 24
Peak memory 237280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3646626515 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.3646626515
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/36.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/36.edn_smoke.1693682978
Short name T483
Test name
Test status
Simulation time 17382507 ps
CPU time 1.18 seconds
Started Aug 21 08:51:56 AM UTC 24
Finished Aug 21 08:51:59 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1693682978 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1693682978
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/36.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/36.edn_stress_all.197766646
Short name T330
Test name
Test status
Simulation time 772287783 ps
CPU time 6.52 seconds
Started Aug 21 08:51:57 AM UTC 24
Finished Aug 21 08:52:05 AM UTC 24
Peak memory 229476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=197766646 -asser
t nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.197766646
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/36.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/36.edn_stress_all_with_rand_reset.2949061964
Short name T245
Test name
Test status
Simulation time 799740299 ps
CPU time 16.71 seconds
Started Aug 21 08:51:57 AM UTC 24
Finished Aug 21 08:52:16 AM UTC 24
Peak memory 229592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2949061964 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.2949061964
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/36.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/37.edn_alert.384200453
Short name T207
Test name
Test status
Simulation time 90932706 ps
CPU time 1.49 seconds
Started Aug 21 08:52:01 AM UTC 24
Finished Aug 21 08:52:04 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=384200453 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.384200453
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/37.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/37.edn_alert_test.2635041798
Short name T495
Test name
Test status
Simulation time 18292186 ps
CPU time 1.26 seconds
Started Aug 21 08:52:02 AM UTC 24
Finished Aug 21 08:52:05 AM UTC 24
Peak memory 216248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2635041798 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2635041798
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/37.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/37.edn_disable.3204430058
Short name T493
Test name
Test status
Simulation time 12794154 ps
CPU time 1.35 seconds
Started Aug 21 08:52:01 AM UTC 24
Finished Aug 21 08:52:04 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3204430058 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.3204430058
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/37.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/37.edn_disable_auto_req_mode.291470286
Short name T494
Test name
Test status
Simulation time 44490360 ps
CPU time 1.45 seconds
Started Aug 21 08:52:01 AM UTC 24
Finished Aug 21 08:52:04 AM UTC 24
Peak memory 228308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=291470286 -assert no
postproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disa
ble_auto_req_mode.291470286
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/37.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/37.edn_err.2161351246
Short name T142
Test name
Test status
Simulation time 24768963 ps
CPU time 1.63 seconds
Started Aug 21 08:52:01 AM UTC 24
Finished Aug 21 08:52:04 AM UTC 24
Peak memory 243864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2161351246 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2161351246
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/37.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/37.edn_genbits.584697132
Short name T324
Test name
Test status
Simulation time 63565523 ps
CPU time 1.79 seconds
Started Aug 21 08:52:00 AM UTC 24
Finished Aug 21 08:52:03 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=584697132 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.584697132
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/37.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/37.edn_smoke.2547293416
Short name T492
Test name
Test status
Simulation time 49914846 ps
CPU time 1.36 seconds
Started Aug 21 08:52:00 AM UTC 24
Finished Aug 21 08:52:03 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2547293416 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.2547293416
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/37.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/37.edn_stress_all.2492364848
Short name T497
Test name
Test status
Simulation time 844603520 ps
CPU time 4.6 seconds
Started Aug 21 08:52:00 AM UTC 24
Finished Aug 21 08:52:06 AM UTC 24
Peak memory 229448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2492364848 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2492364848
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/37.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/37.edn_stress_all_with_rand_reset.2647293180
Short name T603
Test name
Test status
Simulation time 2288751251 ps
CPU time 54.83 seconds
Started Aug 21 08:52:00 AM UTC 24
Finished Aug 21 08:52:57 AM UTC 24
Peak memory 231768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2647293180 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.2647293180
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/37.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/38.edn_alert.878089662
Short name T499
Test name
Test status
Simulation time 27841935 ps
CPU time 1.83 seconds
Started Aug 21 08:52:04 AM UTC 24
Finished Aug 21 08:52:07 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=878089662 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.878089662
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/38.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/38.edn_alert_test.821333898
Short name T501
Test name
Test status
Simulation time 29918637 ps
CPU time 1.26 seconds
Started Aug 21 08:52:05 AM UTC 24
Finished Aug 21 08:52:07 AM UTC 24
Peak memory 215880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=821333898 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.821333898
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/38.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/38.edn_disable.619311585
Short name T500
Test name
Test status
Simulation time 45979950 ps
CPU time 1.16 seconds
Started Aug 21 08:52:05 AM UTC 24
Finished Aug 21 08:52:07 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=619311585 -assert no
postproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o
pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.619311585
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/38.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/38.edn_disable_auto_req_mode.2896397743
Short name T502
Test name
Test status
Simulation time 103431216 ps
CPU time 1.46 seconds
Started Aug 21 08:52:05 AM UTC 24
Finished Aug 21 08:52:08 AM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2896397743 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_dis
able_auto_req_mode.2896397743
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/38.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/38.edn_err.2975706752
Short name T201
Test name
Test status
Simulation time 19320339 ps
CPU time 1.39 seconds
Started Aug 21 08:52:04 AM UTC 24
Finished Aug 21 08:52:06 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2975706752 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.2975706752
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/38.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/38.edn_genbits.18090221
Short name T325
Test name
Test status
Simulation time 54167941 ps
CPU time 1.57 seconds
Started Aug 21 08:52:03 AM UTC 24
Finished Aug 21 08:52:05 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=18090221 -assert nopostproc +UVM_TESTNAME=edn
_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_
1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.18090221
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/38.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/38.edn_intr.1883707537
Short name T498
Test name
Test status
Simulation time 33992811 ps
CPU time 1.21 seconds
Started Aug 21 08:52:04 AM UTC 24
Finished Aug 21 08:52:06 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1883707537 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1883707537
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/38.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/38.edn_smoke.3647984749
Short name T496
Test name
Test status
Simulation time 27090345 ps
CPU time 1.41 seconds
Started Aug 21 08:52:02 AM UTC 24
Finished Aug 21 08:52:05 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3647984749 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3647984749
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/38.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/38.edn_stress_all.1354931743
Short name T506
Test name
Test status
Simulation time 2200316030 ps
CPU time 4.98 seconds
Started Aug 21 08:52:03 AM UTC 24
Finished Aug 21 08:52:09 AM UTC 24
Peak memory 229596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1354931743 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.1354931743
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/38.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/38.edn_stress_all_with_rand_reset.120364236
Short name T743
Test name
Test status
Simulation time 7682388340 ps
CPU time 88.02 seconds
Started Aug 21 08:52:03 AM UTC 24
Finished Aug 21 08:53:33 AM UTC 24
Peak memory 229804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=120364236 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.120364236
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/38.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/39.edn_alert.2858537224
Short name T151
Test name
Test status
Simulation time 272499296 ps
CPU time 2.16 seconds
Started Aug 21 08:52:07 AM UTC 24
Finished Aug 21 08:52:11 AM UTC 24
Peak memory 228232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2858537224 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2858537224
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/39.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/39.edn_alert_test.289965788
Short name T511
Test name
Test status
Simulation time 21099335 ps
CPU time 1.35 seconds
Started Aug 21 08:52:09 AM UTC 24
Finished Aug 21 08:52:11 AM UTC 24
Peak memory 217060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=289965788 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.289965788
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/39.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/39.edn_disable.1538814478
Short name T507
Test name
Test status
Simulation time 10516781 ps
CPU time 1.35 seconds
Started Aug 21 08:52:07 AM UTC 24
Finished Aug 21 08:52:10 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1538814478 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1538814478
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/39.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/39.edn_disable_auto_req_mode.3250214212
Short name T467
Test name
Test status
Simulation time 45542001 ps
CPU time 1.29 seconds
Started Aug 21 08:52:07 AM UTC 24
Finished Aug 21 08:52:10 AM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3250214212 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_dis
able_auto_req_mode.3250214212
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/39.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/39.edn_err.550410289
Short name T508
Test name
Test status
Simulation time 50166846 ps
CPU time 1.46 seconds
Started Aug 21 08:52:07 AM UTC 24
Finished Aug 21 08:52:10 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=550410289 -assert nopostproc +UVM_TESTNAME=ed
n_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2
024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.550410289
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/39.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/39.edn_genbits.1152705061
Short name T504
Test name
Test status
Simulation time 91828669 ps
CPU time 1.28 seconds
Started Aug 21 08:52:06 AM UTC 24
Finished Aug 21 08:52:08 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1152705061 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1152705061
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/39.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/39.edn_intr.3161016482
Short name T505
Test name
Test status
Simulation time 21590758 ps
CPU time 1.19 seconds
Started Aug 21 08:52:06 AM UTC 24
Finished Aug 21 08:52:08 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3161016482 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.3161016482
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/39.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/39.edn_smoke.290606615
Short name T503
Test name
Test status
Simulation time 37975973 ps
CPU time 1.3 seconds
Started Aug 21 08:52:05 AM UTC 24
Finished Aug 21 08:52:08 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=290606615 -assert nopostproc +UVM_TESTNAME=ed
n_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.290606615
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/39.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/39.edn_stress_all.1328049191
Short name T510
Test name
Test status
Simulation time 703930134 ps
CPU time 3.63 seconds
Started Aug 21 08:52:06 AM UTC 24
Finished Aug 21 08:52:11 AM UTC 24
Peak memory 227480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1328049191 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.1328049191
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/39.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/4.edn_alert.1156009415
Short name T67
Test name
Test status
Simulation time 26866447 ps
CPU time 1.35 seconds
Started Aug 21 08:50:26 AM UTC 24
Finished Aug 21 08:50:28 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1156009415 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1156009415
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/4.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/4.edn_alert_test.2748308989
Short name T68
Test name
Test status
Simulation time 22646464 ps
CPU time 1.25 seconds
Started Aug 21 08:50:26 AM UTC 24
Finished Aug 21 08:50:28 AM UTC 24
Peak memory 216736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2748308989 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2748308989
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/4.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/4.edn_disable.48842604
Short name T50
Test name
Test status
Simulation time 50568051 ps
CPU time 1.22 seconds
Started Aug 21 08:50:26 AM UTC 24
Finished Aug 21 08:50:28 AM UTC 24
Peak memory 226384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=48842604 -assert nop
ostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op
entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.48842604
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/4.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/4.edn_disable_auto_req_mode.3103563483
Short name T23
Test name
Test status
Simulation time 51737626 ps
CPU time 1.7 seconds
Started Aug 21 08:50:26 AM UTC 24
Finished Aug 21 08:50:29 AM UTC 24
Peak memory 226264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3103563483 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disa
ble_auto_req_mode.3103563483
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/4.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/4.edn_err.4224284167
Short name T66
Test name
Test status
Simulation time 22506042 ps
CPU time 1.11 seconds
Started Aug 21 08:50:26 AM UTC 24
Finished Aug 21 08:50:28 AM UTC 24
Peak memory 228344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4224284167 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.4224284167
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/4.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/4.edn_intr.3173595958
Short name T64
Test name
Test status
Simulation time 99365069 ps
CPU time 1.24 seconds
Started Aug 21 08:50:25 AM UTC 24
Finished Aug 21 08:50:27 AM UTC 24
Peak memory 226324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3173595958 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3173595958
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/4.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/4.edn_regwen.3868083343
Short name T255
Test name
Test status
Simulation time 47243469 ps
CPU time 1.25 seconds
Started Aug 21 08:50:24 AM UTC 24
Finished Aug 21 08:50:26 AM UTC 24
Peak memory 215972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3868083343 -assert nopostproc +UVM_TESTNAME=e
dn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1
_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.3868083343
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/4.edn_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/4.edn_sec_cm.99963195
Short name T61
Test name
Test status
Simulation time 1030815709 ps
CPU time 5.32 seconds
Started Aug 21 08:50:26 AM UTC 24
Finished Aug 21 08:50:32 AM UTC 24
Peak memory 258372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=99963195 -assert nop
ostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.99963195
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/4.edn_sec_cm/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/4.edn_smoke.1855195224
Short name T254
Test name
Test status
Simulation time 43247450 ps
CPU time 1.14 seconds
Started Aug 21 08:50:23 AM UTC 24
Finished Aug 21 08:50:26 AM UTC 24
Peak memory 226220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1855195224 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.1855195224
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/4.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/4.edn_stress_all.947354754
Short name T69
Test name
Test status
Simulation time 107431792 ps
CPU time 3.21 seconds
Started Aug 21 08:50:25 AM UTC 24
Finished Aug 21 08:50:29 AM UTC 24
Peak memory 229716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=947354754 -asser
t nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.947354754
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/4.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/40.edn_alert.3680690914
Short name T173
Test name
Test status
Simulation time 34417399 ps
CPU time 2.02 seconds
Started Aug 21 08:52:11 AM UTC 24
Finished Aug 21 08:52:15 AM UTC 24
Peak memory 232200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3680690914 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.3680690914
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/40.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/40.edn_alert_test.3610926134
Short name T516
Test name
Test status
Simulation time 127049447 ps
CPU time 1.18 seconds
Started Aug 21 08:52:12 AM UTC 24
Finished Aug 21 08:52:14 AM UTC 24
Peak memory 215876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3610926134 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3610926134
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/40.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/40.edn_disable.2914957095
Short name T515
Test name
Test status
Simulation time 29169585 ps
CPU time 1.14 seconds
Started Aug 21 08:52:12 AM UTC 24
Finished Aug 21 08:52:14 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2914957095 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2914957095
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/40.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/40.edn_disable_auto_req_mode.1438359010
Short name T519
Test name
Test status
Simulation time 106188467 ps
CPU time 1.77 seconds
Started Aug 21 08:52:12 AM UTC 24
Finished Aug 21 08:52:15 AM UTC 24
Peak memory 226212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1438359010 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_dis
able_auto_req_mode.1438359010
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/40.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/40.edn_err.3401549207
Short name T143
Test name
Test status
Simulation time 24679506 ps
CPU time 1.63 seconds
Started Aug 21 08:52:11 AM UTC 24
Finished Aug 21 08:52:14 AM UTC 24
Peak memory 243984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3401549207 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.3401549207
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/40.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/40.edn_genbits.921423259
Short name T514
Test name
Test status
Simulation time 106516910 ps
CPU time 1.64 seconds
Started Aug 21 08:52:10 AM UTC 24
Finished Aug 21 08:52:13 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=921423259 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.921423259
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/40.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/40.edn_intr.1335010720
Short name T513
Test name
Test status
Simulation time 36684758 ps
CPU time 1.14 seconds
Started Aug 21 08:52:10 AM UTC 24
Finished Aug 21 08:52:13 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1335010720 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.1335010720
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/40.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/40.edn_smoke.1175702713
Short name T512
Test name
Test status
Simulation time 17533601 ps
CPU time 1.13 seconds
Started Aug 21 08:52:10 AM UTC 24
Finished Aug 21 08:52:13 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1175702713 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1175702713
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/40.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/40.edn_stress_all.332243822
Short name T518
Test name
Test status
Simulation time 408549677 ps
CPU time 3.17 seconds
Started Aug 21 08:52:10 AM UTC 24
Finished Aug 21 08:52:15 AM UTC 24
Peak memory 227680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=332243822 -asser
t nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.332243822
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/40.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/41.edn_alert.1406080202
Short name T524
Test name
Test status
Simulation time 27329430 ps
CPU time 1.68 seconds
Started Aug 21 08:52:14 AM UTC 24
Finished Aug 21 08:52:17 AM UTC 24
Peak memory 230484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1406080202 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1406080202
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/41.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/41.edn_alert_test.525363363
Short name T526
Test name
Test status
Simulation time 37299992 ps
CPU time 1.58 seconds
Started Aug 21 08:52:16 AM UTC 24
Finished Aug 21 08:52:19 AM UTC 24
Peak memory 217056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=525363363 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.525363363
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/41.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/41.edn_disable.3343557853
Short name T196
Test name
Test status
Simulation time 31754947 ps
CPU time 1.22 seconds
Started Aug 21 08:52:16 AM UTC 24
Finished Aug 21 08:52:18 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3343557853 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3343557853
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/41.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/41.edn_disable_auto_req_mode.4230652470
Short name T527
Test name
Test status
Simulation time 55728397 ps
CPU time 1.67 seconds
Started Aug 21 08:52:16 AM UTC 24
Finished Aug 21 08:52:19 AM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4230652470 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_dis
able_auto_req_mode.4230652470
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/41.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/41.edn_err.3815549904
Short name T523
Test name
Test status
Simulation time 55009253 ps
CPU time 1.57 seconds
Started Aug 21 08:52:14 AM UTC 24
Finished Aug 21 08:52:17 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3815549904 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3815549904
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/41.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/41.edn_genbits.43407083
Short name T353
Test name
Test status
Simulation time 95558202 ps
CPU time 2.78 seconds
Started Aug 21 08:52:12 AM UTC 24
Finished Aug 21 08:52:16 AM UTC 24
Peak memory 231580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=43407083 -assert nopostproc +UVM_TESTNAME=edn
_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_
1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.43407083
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/41.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/41.edn_intr.1605415726
Short name T521
Test name
Test status
Simulation time 113364634 ps
CPU time 1.56 seconds
Started Aug 21 08:52:14 AM UTC 24
Finished Aug 21 08:52:17 AM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1605415726 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1605415726
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/41.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/41.edn_smoke.316682814
Short name T517
Test name
Test status
Simulation time 45142177 ps
CPU time 1.23 seconds
Started Aug 21 08:52:12 AM UTC 24
Finished Aug 21 08:52:14 AM UTC 24
Peak memory 226212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=316682814 -assert nopostproc +UVM_TESTNAME=ed
n_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.316682814
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/41.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/41.edn_stress_all.2345381700
Short name T522
Test name
Test status
Simulation time 1047654893 ps
CPU time 3.69 seconds
Started Aug 21 08:52:12 AM UTC 24
Finished Aug 21 08:52:17 AM UTC 24
Peak memory 229448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2345381700 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.2345381700
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/41.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/41.edn_stress_all_with_rand_reset.288415280
Short name T624
Test name
Test status
Simulation time 2095438918 ps
CPU time 47.76 seconds
Started Aug 21 08:52:14 AM UTC 24
Finished Aug 21 08:53:03 AM UTC 24
Peak memory 229588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=288415280 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.288415280
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/41.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/42.edn_alert.562685195
Short name T529
Test name
Test status
Simulation time 27118137 ps
CPU time 1.69 seconds
Started Aug 21 08:52:17 AM UTC 24
Finished Aug 21 08:52:19 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=562685195 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.562685195
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/42.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/42.edn_alert_test.4144622565
Short name T531
Test name
Test status
Simulation time 16024181 ps
CPU time 1.1 seconds
Started Aug 21 08:52:19 AM UTC 24
Finished Aug 21 08:52:21 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4144622565 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.4144622565
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/42.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/42.edn_disable.2573479077
Short name T532
Test name
Test status
Simulation time 11051077 ps
CPU time 1.31 seconds
Started Aug 21 08:52:19 AM UTC 24
Finished Aug 21 08:52:21 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2573479077 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.2573479077
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/42.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/42.edn_disable_auto_req_mode.480333213
Short name T222
Test name
Test status
Simulation time 99030482 ps
CPU time 1.61 seconds
Started Aug 21 08:52:19 AM UTC 24
Finished Aug 21 08:52:21 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=480333213 -assert no
postproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disa
ble_auto_req_mode.480333213
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/42.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/42.edn_err.1162882092
Short name T187
Test name
Test status
Simulation time 18580300 ps
CPU time 1.42 seconds
Started Aug 21 08:52:19 AM UTC 24
Finished Aug 21 08:52:21 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1162882092 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1162882092
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/42.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/42.edn_intr.1085064061
Short name T528
Test name
Test status
Simulation time 21069571 ps
CPU time 1.74 seconds
Started Aug 21 08:52:16 AM UTC 24
Finished Aug 21 08:52:19 AM UTC 24
Peak memory 237160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1085064061 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.1085064061
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/42.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/42.edn_smoke.3681194427
Short name T525
Test name
Test status
Simulation time 16947946 ps
CPU time 1.43 seconds
Started Aug 21 08:52:16 AM UTC 24
Finished Aug 21 08:52:19 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3681194427 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3681194427
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/42.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/42.edn_stress_all.2023023666
Short name T317
Test name
Test status
Simulation time 941231621 ps
CPU time 4.56 seconds
Started Aug 21 08:52:16 AM UTC 24
Finished Aug 21 08:52:22 AM UTC 24
Peak memory 229520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2023023666 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2023023666
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/42.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/42.edn_stress_all_with_rand_reset.4139586570
Short name T895
Test name
Test status
Simulation time 21454934527 ps
CPU time 108.1 seconds
Started Aug 21 08:52:16 AM UTC 24
Finished Aug 21 08:54:07 AM UTC 24
Peak memory 229724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4139586570 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.4139586570
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/42.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/43.edn_alert.3859547131
Short name T536
Test name
Test status
Simulation time 24969569 ps
CPU time 1.63 seconds
Started Aug 21 08:52:21 AM UTC 24
Finished Aug 21 08:52:24 AM UTC 24
Peak memory 230484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3859547131 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.3859547131
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/43.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/43.edn_alert_test.3919568680
Short name T540
Test name
Test status
Simulation time 34318002 ps
CPU time 1.31 seconds
Started Aug 21 08:52:23 AM UTC 24
Finished Aug 21 08:52:26 AM UTC 24
Peak memory 217052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3919568680 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3919568680
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/43.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/43.edn_disable.2795414633
Short name T534
Test name
Test status
Simulation time 13163022 ps
CPU time 1.4 seconds
Started Aug 21 08:52:21 AM UTC 24
Finished Aug 21 08:52:24 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2795414633 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2795414633
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/43.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/43.edn_disable_auto_req_mode.977484019
Short name T225
Test name
Test status
Simulation time 101617731 ps
CPU time 1.62 seconds
Started Aug 21 08:52:21 AM UTC 24
Finished Aug 21 08:52:24 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=977484019 -assert no
postproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disa
ble_auto_req_mode.977484019
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/43.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/43.edn_err.2571277703
Short name T165
Test name
Test status
Simulation time 20870548 ps
CPU time 1.22 seconds
Started Aug 21 08:52:21 AM UTC 24
Finished Aug 21 08:52:23 AM UTC 24
Peak memory 236968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2571277703 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.2571277703
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/43.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/43.edn_genbits.4162928839
Short name T351
Test name
Test status
Simulation time 71206198 ps
CPU time 2.59 seconds
Started Aug 21 08:52:21 AM UTC 24
Finished Aug 21 08:52:24 AM UTC 24
Peak memory 231308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4162928839 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.4162928839
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/43.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/43.edn_intr.2883238804
Short name T535
Test name
Test status
Simulation time 21577081 ps
CPU time 1.68 seconds
Started Aug 21 08:52:21 AM UTC 24
Finished Aug 21 08:52:24 AM UTC 24
Peak memory 236700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2883238804 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2883238804
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/43.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/43.edn_smoke.1392929041
Short name T533
Test name
Test status
Simulation time 23134828 ps
CPU time 1.32 seconds
Started Aug 21 08:52:19 AM UTC 24
Finished Aug 21 08:52:21 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1392929041 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.1392929041
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/43.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/43.edn_stress_all.3602980772
Short name T537
Test name
Test status
Simulation time 195978978 ps
CPU time 2.16 seconds
Started Aug 21 08:52:21 AM UTC 24
Finished Aug 21 08:52:24 AM UTC 24
Peak memory 229812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3602980772 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3602980772
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/43.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/43.edn_stress_all_with_rand_reset.3168343889
Short name T902
Test name
Test status
Simulation time 4616256297 ps
CPU time 107.3 seconds
Started Aug 21 08:52:21 AM UTC 24
Finished Aug 21 08:54:10 AM UTC 24
Peak memory 229812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3168343889 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.3168343889
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/43.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/44.edn_alert.1865303448
Short name T167
Test name
Test status
Simulation time 25571848 ps
CPU time 1.63 seconds
Started Aug 21 08:52:26 AM UTC 24
Finished Aug 21 08:52:29 AM UTC 24
Peak memory 228036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1865303448 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.1865303448
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/44.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/44.edn_alert_test.1617601957
Short name T544
Test name
Test status
Simulation time 65292318 ps
CPU time 1.42 seconds
Started Aug 21 08:52:26 AM UTC 24
Finished Aug 21 08:52:28 AM UTC 24
Peak memory 216648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1617601957 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.1617601957
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/44.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/44.edn_disable.1738953029
Short name T542
Test name
Test status
Simulation time 31629445 ps
CPU time 1.33 seconds
Started Aug 21 08:52:26 AM UTC 24
Finished Aug 21 08:52:28 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1738953029 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1738953029
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/44.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/44.edn_disable_auto_req_mode.3483164681
Short name T545
Test name
Test status
Simulation time 26010001 ps
CPU time 1.46 seconds
Started Aug 21 08:52:26 AM UTC 24
Finished Aug 21 08:52:28 AM UTC 24
Peak memory 226264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3483164681 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_dis
able_auto_req_mode.3483164681
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/44.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/44.edn_err.1982557408
Short name T193
Test name
Test status
Simulation time 20069908 ps
CPU time 1.27 seconds
Started Aug 21 08:52:26 AM UTC 24
Finished Aug 21 08:52:28 AM UTC 24
Peak memory 227912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1982557408 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.1982557408
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/44.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/44.edn_genbits.1087991777
Short name T15
Test name
Test status
Simulation time 96708733 ps
CPU time 1.61 seconds
Started Aug 21 08:52:23 AM UTC 24
Finished Aug 21 08:52:26 AM UTC 24
Peak memory 230608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1087991777 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1087991777
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/44.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/44.edn_intr.1145687474
Short name T539
Test name
Test status
Simulation time 24622729 ps
CPU time 1.12 seconds
Started Aug 21 08:52:24 AM UTC 24
Finished Aug 21 08:52:26 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1145687474 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1145687474
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/44.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/44.edn_smoke.2895196389
Short name T538
Test name
Test status
Simulation time 29482687 ps
CPU time 1.23 seconds
Started Aug 21 08:52:23 AM UTC 24
Finished Aug 21 08:52:26 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2895196389 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.2895196389
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/44.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/44.edn_stress_all.3088175756
Short name T541
Test name
Test status
Simulation time 147975426 ps
CPU time 3.61 seconds
Started Aug 21 08:52:24 AM UTC 24
Finished Aug 21 08:52:28 AM UTC 24
Peak memory 229448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3088175756 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3088175756
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/44.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/44.edn_stress_all_with_rand_reset.455835467
Short name T876
Test name
Test status
Simulation time 6917871108 ps
CPU time 93.19 seconds
Started Aug 21 08:52:24 AM UTC 24
Finished Aug 21 08:53:59 AM UTC 24
Peak memory 234036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=455835467 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.455835467
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/44.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/45.edn_alert.1538485313
Short name T550
Test name
Test status
Simulation time 80190509 ps
CPU time 1.63 seconds
Started Aug 21 08:52:28 AM UTC 24
Finished Aug 21 08:52:31 AM UTC 24
Peak memory 228436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1538485313 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.1538485313
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/45.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/45.edn_alert_test.1890088857
Short name T558
Test name
Test status
Simulation time 160368149 ps
CPU time 2.56 seconds
Started Aug 21 08:52:30 AM UTC 24
Finished Aug 21 08:52:34 AM UTC 24
Peak memory 217196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1890088857 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.1890088857
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/45.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/45.edn_disable.3004567176
Short name T548
Test name
Test status
Simulation time 11736441 ps
CPU time 1.24 seconds
Started Aug 21 08:52:28 AM UTC 24
Finished Aug 21 08:52:31 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3004567176 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3004567176
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/45.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/45.edn_disable_auto_req_mode.2387754531
Short name T554
Test name
Test status
Simulation time 61943803 ps
CPU time 1.82 seconds
Started Aug 21 08:52:30 AM UTC 24
Finished Aug 21 08:52:33 AM UTC 24
Peak memory 226264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2387754531 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_dis
able_auto_req_mode.2387754531
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/45.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/45.edn_err.260799178
Short name T551
Test name
Test status
Simulation time 38148372 ps
CPU time 1.54 seconds
Started Aug 21 08:52:28 AM UTC 24
Finished Aug 21 08:52:31 AM UTC 24
Peak memory 242240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=260799178 -assert nopostproc +UVM_TESTNAME=ed
n_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2
024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.260799178
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/45.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/45.edn_genbits.281823288
Short name T547
Test name
Test status
Simulation time 67781523 ps
CPU time 2 seconds
Started Aug 21 08:52:26 AM UTC 24
Finished Aug 21 08:52:29 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=281823288 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.281823288
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/45.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/45.edn_intr.3558701636
Short name T549
Test name
Test status
Simulation time 24377968 ps
CPU time 1.4 seconds
Started Aug 21 08:52:28 AM UTC 24
Finished Aug 21 08:52:31 AM UTC 24
Peak memory 236700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3558701636 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3558701636
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/45.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/45.edn_smoke.3798985537
Short name T543
Test name
Test status
Simulation time 26127502 ps
CPU time 1.24 seconds
Started Aug 21 08:52:26 AM UTC 24
Finished Aug 21 08:52:28 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3798985537 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.3798985537
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/45.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/45.edn_stress_all.425116134
Short name T546
Test name
Test status
Simulation time 59339653 ps
CPU time 1.47 seconds
Started Aug 21 08:52:26 AM UTC 24
Finished Aug 21 08:52:29 AM UTC 24
Peak memory 216120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=425116134 -asser
t nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.425116134
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/45.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/45.edn_stress_all_with_rand_reset.3703021303
Short name T855
Test name
Test status
Simulation time 3334241943 ps
CPU time 85.61 seconds
Started Aug 21 08:52:28 AM UTC 24
Finished Aug 21 08:53:56 AM UTC 24
Peak memory 229772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3703021303 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3703021303
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/45.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/46.edn_alert.3551897926
Short name T557
Test name
Test status
Simulation time 38368689 ps
CPU time 1.66 seconds
Started Aug 21 08:52:31 AM UTC 24
Finished Aug 21 08:52:34 AM UTC 24
Peak memory 230440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3551897926 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.3551897926
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/46.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/46.edn_alert_test.3673195003
Short name T559
Test name
Test status
Simulation time 37487864 ps
CPU time 1.28 seconds
Started Aug 21 08:52:33 AM UTC 24
Finished Aug 21 08:52:35 AM UTC 24
Peak memory 226912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3673195003 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.3673195003
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/46.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/46.edn_disable_auto_req_mode.1220528247
Short name T223
Test name
Test status
Simulation time 42722572 ps
CPU time 1.86 seconds
Started Aug 21 08:52:33 AM UTC 24
Finished Aug 21 08:52:36 AM UTC 24
Peak memory 226264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1220528247 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_dis
able_auto_req_mode.1220528247
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/46.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/46.edn_err.922083542
Short name T555
Test name
Test status
Simulation time 51598286 ps
CPU time 1.4 seconds
Started Aug 21 08:52:31 AM UTC 24
Finished Aug 21 08:52:33 AM UTC 24
Peak memory 230364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=922083542 -assert nopostproc +UVM_TESTNAME=ed
n_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2
024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.922083542
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/46.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/46.edn_genbits.1614433185
Short name T553
Test name
Test status
Simulation time 86605120 ps
CPU time 1.52 seconds
Started Aug 21 08:52:31 AM UTC 24
Finished Aug 21 08:52:33 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1614433185 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1614433185
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/46.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/46.edn_intr.3131550241
Short name T556
Test name
Test status
Simulation time 30815003 ps
CPU time 1.48 seconds
Started Aug 21 08:52:31 AM UTC 24
Finished Aug 21 08:52:33 AM UTC 24
Peak memory 237160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3131550241 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3131550241
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/46.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/46.edn_smoke.1979495338
Short name T552
Test name
Test status
Simulation time 41203726 ps
CPU time 1.19 seconds
Started Aug 21 08:52:31 AM UTC 24
Finished Aug 21 08:52:33 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1979495338 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.1979495338
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/46.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/46.edn_stress_all.2454361970
Short name T318
Test name
Test status
Simulation time 485260698 ps
CPU time 4.99 seconds
Started Aug 21 08:52:31 AM UTC 24
Finished Aug 21 08:52:37 AM UTC 24
Peak memory 227536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2454361970 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2454361970
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/46.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/47.edn_alert.3938432327
Short name T564
Test name
Test status
Simulation time 27434698 ps
CPU time 1.87 seconds
Started Aug 21 08:52:35 AM UTC 24
Finished Aug 21 08:52:38 AM UTC 24
Peak memory 230484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3938432327 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.3938432327
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/47.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/47.edn_alert_test.3393639658
Short name T565
Test name
Test status
Simulation time 22945270 ps
CPU time 1.11 seconds
Started Aug 21 08:52:38 AM UTC 24
Finished Aug 21 08:52:40 AM UTC 24
Peak memory 216360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3393639658 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3393639658
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/47.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/47.edn_disable.3765987218
Short name T218
Test name
Test status
Simulation time 17939296 ps
CPU time 1.29 seconds
Started Aug 21 08:52:35 AM UTC 24
Finished Aug 21 08:52:38 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3765987218 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3765987218
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/47.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/47.edn_disable_auto_req_mode.3250685298
Short name T566
Test name
Test status
Simulation time 23451332 ps
CPU time 1.46 seconds
Started Aug 21 08:52:38 AM UTC 24
Finished Aug 21 08:52:40 AM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3250685298 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_dis
able_auto_req_mode.3250685298
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/47.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/47.edn_err.1484720439
Short name T563
Test name
Test status
Simulation time 22957933 ps
CPU time 1.57 seconds
Started Aug 21 08:52:35 AM UTC 24
Finished Aug 21 08:52:38 AM UTC 24
Peak memory 244224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1484720439 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.1484720439
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/47.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/47.edn_genbits.3850000631
Short name T562
Test name
Test status
Simulation time 43550457 ps
CPU time 1.52 seconds
Started Aug 21 08:52:35 AM UTC 24
Finished Aug 21 08:52:38 AM UTC 24
Peak memory 228136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3850000631 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3850000631
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/47.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/47.edn_intr.2193353560
Short name T561
Test name
Test status
Simulation time 31520012 ps
CPU time 1.23 seconds
Started Aug 21 08:52:35 AM UTC 24
Finished Aug 21 08:52:38 AM UTC 24
Peak memory 228484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2193353560 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.2193353560
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/47.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/47.edn_smoke.1365068084
Short name T560
Test name
Test status
Simulation time 45069315 ps
CPU time 1.37 seconds
Started Aug 21 08:52:33 AM UTC 24
Finished Aug 21 08:52:36 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1365068084 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.1365068084
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/47.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/47.edn_stress_all.2796150738
Short name T577
Test name
Test status
Simulation time 418813344 ps
CPU time 9.85 seconds
Started Aug 21 08:52:35 AM UTC 24
Finished Aug 21 08:52:46 AM UTC 24
Peak memory 227260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2796150738 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.2796150738
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/47.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/47.edn_stress_all_with_rand_reset.2955105834
Short name T820
Test name
Test status
Simulation time 2904285192 ps
CPU time 70.15 seconds
Started Aug 21 08:52:35 AM UTC 24
Finished Aug 21 08:53:47 AM UTC 24
Peak memory 229924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2955105834 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2955105834
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/47.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/48.edn_alert.3593132375
Short name T152
Test name
Test status
Simulation time 29786310 ps
CPU time 1.62 seconds
Started Aug 21 08:52:39 AM UTC 24
Finished Aug 21 08:52:42 AM UTC 24
Peak memory 228436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3593132375 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3593132375
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/48.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/48.edn_alert_test.3361378699
Short name T571
Test name
Test status
Simulation time 28393604 ps
CPU time 1.34 seconds
Started Aug 21 08:52:41 AM UTC 24
Finished Aug 21 08:52:44 AM UTC 24
Peak memory 216248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3361378699 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.3361378699
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/48.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/48.edn_disable.3901483406
Short name T568
Test name
Test status
Simulation time 23542608 ps
CPU time 1.34 seconds
Started Aug 21 08:52:39 AM UTC 24
Finished Aug 21 08:52:41 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3901483406 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3901483406
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/48.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/48.edn_disable_auto_req_mode.3678182966
Short name T573
Test name
Test status
Simulation time 29269404 ps
CPU time 1.75 seconds
Started Aug 21 08:52:41 AM UTC 24
Finished Aug 21 08:52:44 AM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3678182966 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_dis
able_auto_req_mode.3678182966
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/48.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/48.edn_genbits.276486137
Short name T570
Test name
Test status
Simulation time 125188506 ps
CPU time 2.86 seconds
Started Aug 21 08:52:38 AM UTC 24
Finished Aug 21 08:52:42 AM UTC 24
Peak memory 231520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=276486137 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.276486137
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/48.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/48.edn_intr.2795766320
Short name T112
Test name
Test status
Simulation time 21736659 ps
CPU time 1.62 seconds
Started Aug 21 08:52:39 AM UTC 24
Finished Aug 21 08:52:42 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2795766320 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2795766320
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/48.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/48.edn_smoke.2491881848
Short name T567
Test name
Test status
Simulation time 16147806 ps
CPU time 1.45 seconds
Started Aug 21 08:52:38 AM UTC 24
Finished Aug 21 08:52:40 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2491881848 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.2491881848
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/48.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/48.edn_stress_all.548841366
Short name T569
Test name
Test status
Simulation time 105357709 ps
CPU time 1.75 seconds
Started Aug 21 08:52:39 AM UTC 24
Finished Aug 21 08:52:42 AM UTC 24
Peak memory 226040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=548841366 -asser
t nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.548841366
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/48.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/48.edn_stress_all_with_rand_reset.2351924074
Short name T825
Test name
Test status
Simulation time 11399573523 ps
CPU time 67.47 seconds
Started Aug 21 08:52:39 AM UTC 24
Finished Aug 21 08:53:48 AM UTC 24
Peak memory 229708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2351924074 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.2351924074
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/48.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/49.edn_alert.2823642150
Short name T306
Test name
Test status
Simulation time 65039506 ps
CPU time 1.67 seconds
Started Aug 21 08:52:44 AM UTC 24
Finished Aug 21 08:52:46 AM UTC 24
Peak memory 230484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2823642150 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2823642150
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/49.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/49.edn_alert_test.3131395621
Short name T579
Test name
Test status
Simulation time 48241442 ps
CPU time 1.33 seconds
Started Aug 21 08:52:45 AM UTC 24
Finished Aug 21 08:52:47 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3131395621 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3131395621
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/49.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/49.edn_disable.3937883161
Short name T578
Test name
Test status
Simulation time 58765678 ps
CPU time 1.27 seconds
Started Aug 21 08:52:45 AM UTC 24
Finished Aug 21 08:52:47 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3937883161 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3937883161
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/49.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/49.edn_disable_auto_req_mode.1839319875
Short name T581
Test name
Test status
Simulation time 40367584 ps
CPU time 1.86 seconds
Started Aug 21 08:52:45 AM UTC 24
Finished Aug 21 08:52:48 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1839319875 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_dis
able_auto_req_mode.1839319875
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/49.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/49.edn_err.1311327212
Short name T575
Test name
Test status
Simulation time 22474569 ps
CPU time 1.35 seconds
Started Aug 21 08:52:44 AM UTC 24
Finished Aug 21 08:52:46 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1311327212 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.1311327212
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/49.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/49.edn_genbits.3965842690
Short name T574
Test name
Test status
Simulation time 74693573 ps
CPU time 1.53 seconds
Started Aug 21 08:52:43 AM UTC 24
Finished Aug 21 08:52:46 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3965842690 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3965842690
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/49.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/49.edn_intr.2699860592
Short name T576
Test name
Test status
Simulation time 24849541 ps
CPU time 1.54 seconds
Started Aug 21 08:52:44 AM UTC 24
Finished Aug 21 08:52:46 AM UTC 24
Peak memory 237160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2699860592 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2699860592
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/49.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/49.edn_smoke.4227865981
Short name T572
Test name
Test status
Simulation time 28097639 ps
CPU time 1.33 seconds
Started Aug 21 08:52:41 AM UTC 24
Finished Aug 21 08:52:44 AM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4227865981 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.4227865981
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/49.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/49.edn_stress_all.2178098095
Short name T584
Test name
Test status
Simulation time 188768330 ps
CPU time 5.13 seconds
Started Aug 21 08:52:43 AM UTC 24
Finished Aug 21 08:52:50 AM UTC 24
Peak memory 229468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2178098095 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2178098095
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/49.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/49.edn_stress_all_with_rand_reset.3256310849
Short name T684
Test name
Test status
Simulation time 1292589861 ps
CPU time 34.47 seconds
Started Aug 21 08:52:43 AM UTC 24
Finished Aug 21 08:53:19 AM UTC 24
Peak memory 229664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3256310849 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3256310849
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/49.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/5.edn_alert_test.2891962177
Short name T355
Test name
Test status
Simulation time 33062607 ps
CPU time 1.23 seconds
Started Aug 21 08:50:29 AM UTC 24
Finished Aug 21 08:50:31 AM UTC 24
Peak memory 226808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2891962177 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2891962177
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/5.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/5.edn_disable_auto_req_mode.2468466637
Short name T97
Test name
Test status
Simulation time 20223907 ps
CPU time 0.98 seconds
Started Aug 21 08:50:29 AM UTC 24
Finished Aug 21 08:50:31 AM UTC 24
Peak memory 226264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2468466637 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disa
ble_auto_req_mode.2468466637
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/5.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/5.edn_err.2727735587
Short name T9
Test name
Test status
Simulation time 95269136 ps
CPU time 1.59 seconds
Started Aug 21 08:50:29 AM UTC 24
Finished Aug 21 08:50:31 AM UTC 24
Peak memory 242388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2727735587 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.2727735587
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/5.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/5.edn_intr.231607719
Short name T32
Test name
Test status
Simulation time 25172530 ps
CPU time 1.13 seconds
Started Aug 21 08:50:29 AM UTC 24
Finished Aug 21 08:50:31 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=231607719 -assert nopostproc +UVM_TESTNAME=ed
n_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0
_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.231607719
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/5.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/5.edn_regwen.2034689188
Short name T85
Test name
Test status
Simulation time 94768946 ps
CPU time 1.26 seconds
Started Aug 21 08:50:27 AM UTC 24
Finished Aug 21 08:50:30 AM UTC 24
Peak memory 215912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2034689188 -assert nopostproc +UVM_TESTNAME=e
dn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1
_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2034689188
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/5.edn_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/5.edn_smoke.355106400
Short name T121
Test name
Test status
Simulation time 59105387 ps
CPU time 1.34 seconds
Started Aug 21 08:50:27 AM UTC 24
Finished Aug 21 08:50:30 AM UTC 24
Peak memory 216016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=355106400 -assert nopostproc +UVM_TESTNAME=ed
n_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.355106400
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/5.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/5.edn_stress_all_with_rand_reset.3697238177
Short name T244
Test name
Test status
Simulation time 4374784161 ps
CPU time 100.18 seconds
Started Aug 21 08:50:27 AM UTC 24
Finished Aug 21 08:52:10 AM UTC 24
Peak memory 233896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3697238177 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.3697238177
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/5.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/50.edn_alert.3140810601
Short name T586
Test name
Test status
Simulation time 28082923 ps
CPU time 1.77 seconds
Started Aug 21 08:52:47 AM UTC 24
Finished Aug 21 08:52:50 AM UTC 24
Peak memory 226388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3140810601 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.3140810601
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/50.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/50.edn_err.449775841
Short name T583
Test name
Test status
Simulation time 22846422 ps
CPU time 1.43 seconds
Started Aug 21 08:52:47 AM UTC 24
Finished Aug 21 08:52:49 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=449775841 -assert nopostproc +UVM_TESTNAME=ed
n_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2
024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.449775841
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/50.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/50.edn_genbits.2184650891
Short name T582
Test name
Test status
Simulation time 145319649 ps
CPU time 1.82 seconds
Started Aug 21 08:52:45 AM UTC 24
Finished Aug 21 08:52:48 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2184650891 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2184650891
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/50.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/51.edn_alert.4034317662
Short name T286
Test name
Test status
Simulation time 52461965 ps
CPU time 1.87 seconds
Started Aug 21 08:52:47 AM UTC 24
Finished Aug 21 08:52:50 AM UTC 24
Peak memory 226388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4034317662 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.4034317662
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/51.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/51.edn_err.185439628
Short name T585
Test name
Test status
Simulation time 19091799 ps
CPU time 1.44 seconds
Started Aug 21 08:52:47 AM UTC 24
Finished Aug 21 08:52:50 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=185439628 -assert nopostproc +UVM_TESTNAME=ed
n_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2
024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.185439628
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/51.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/51.edn_genbits.1390470631
Short name T588
Test name
Test status
Simulation time 42455432 ps
CPU time 2.26 seconds
Started Aug 21 08:52:47 AM UTC 24
Finished Aug 21 08:52:50 AM UTC 24
Peak memory 229508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1390470631 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.1390470631
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/51.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/52.edn_alert.335061993
Short name T162
Test name
Test status
Simulation time 33424139 ps
CPU time 1.99 seconds
Started Aug 21 08:52:48 AM UTC 24
Finished Aug 21 08:52:51 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=335061993 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.335061993
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/52.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/52.edn_err.2520850141
Short name T589
Test name
Test status
Simulation time 35114631 ps
CPU time 1.3 seconds
Started Aug 21 08:52:48 AM UTC 24
Finished Aug 21 08:52:51 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2520850141 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2520850141
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/52.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/52.edn_genbits.542214524
Short name T331
Test name
Test status
Simulation time 94856355 ps
CPU time 2.22 seconds
Started Aug 21 08:52:48 AM UTC 24
Finished Aug 21 08:52:51 AM UTC 24
Peak memory 229468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=542214524 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.542214524
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/52.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/53.edn_alert.3552498840
Short name T183
Test name
Test status
Simulation time 41254091 ps
CPU time 1.97 seconds
Started Aug 21 08:52:48 AM UTC 24
Finished Aug 21 08:52:51 AM UTC 24
Peak memory 232532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3552498840 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.3552498840
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/53.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/53.edn_err.1051315067
Short name T591
Test name
Test status
Simulation time 30976254 ps
CPU time 1.18 seconds
Started Aug 21 08:52:51 AM UTC 24
Finished Aug 21 08:52:53 AM UTC 24
Peak memory 237300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1051315067 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.1051315067
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/53.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/53.edn_genbits.3361215221
Short name T594
Test name
Test status
Simulation time 95252653 ps
CPU time 4.04 seconds
Started Aug 21 08:52:48 AM UTC 24
Finished Aug 21 08:52:53 AM UTC 24
Peak memory 229452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3361215221 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.3361215221
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/53.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/54.edn_alert.3586737613
Short name T592
Test name
Test status
Simulation time 79178294 ps
CPU time 1.45 seconds
Started Aug 21 08:52:51 AM UTC 24
Finished Aug 21 08:52:53 AM UTC 24
Peak memory 228436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3586737613 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.3586737613
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/54.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/54.edn_genbits.987926929
Short name T593
Test name
Test status
Simulation time 42209064 ps
CPU time 1.61 seconds
Started Aug 21 08:52:51 AM UTC 24
Finished Aug 21 08:52:53 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=987926929 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.987926929
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/54.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/55.edn_alert.4046956783
Short name T179
Test name
Test status
Simulation time 43539119 ps
CPU time 1.69 seconds
Started Aug 21 08:52:51 AM UTC 24
Finished Aug 21 08:52:53 AM UTC 24
Peak memory 230484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4046956783 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.4046956783
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/55.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/55.edn_err.1528361407
Short name T212
Test name
Test status
Simulation time 81181960 ps
CPU time 1.34 seconds
Started Aug 21 08:52:52 AM UTC 24
Finished Aug 21 08:52:54 AM UTC 24
Peak memory 246032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1528361407 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.1528361407
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/55.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/55.edn_genbits.3442896226
Short name T595
Test name
Test status
Simulation time 63041658 ps
CPU time 1.81 seconds
Started Aug 21 08:52:51 AM UTC 24
Finished Aug 21 08:52:54 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3442896226 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3442896226
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/55.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/56.edn_alert.3530024923
Short name T208
Test name
Test status
Simulation time 63022201 ps
CPU time 1.82 seconds
Started Aug 21 08:52:52 AM UTC 24
Finished Aug 21 08:52:55 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3530024923 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.3530024923
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/56.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/56.edn_err.3182976193
Short name T596
Test name
Test status
Simulation time 27850261 ps
CPU time 1.25 seconds
Started Aug 21 08:52:52 AM UTC 24
Finished Aug 21 08:52:54 AM UTC 24
Peak memory 228308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3182976193 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3182976193
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/56.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/56.edn_genbits.2116201930
Short name T296
Test name
Test status
Simulation time 119422553 ps
CPU time 1.49 seconds
Started Aug 21 08:52:52 AM UTC 24
Finished Aug 21 08:52:54 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2116201930 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2116201930
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/56.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/57.edn_alert.668417495
Short name T597
Test name
Test status
Simulation time 26402143 ps
CPU time 1.79 seconds
Started Aug 21 08:52:52 AM UTC 24
Finished Aug 21 08:52:55 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=668417495 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.668417495
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/57.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/57.edn_err.3251001065
Short name T599
Test name
Test status
Simulation time 20627897 ps
CPU time 1.13 seconds
Started Aug 21 08:52:53 AM UTC 24
Finished Aug 21 08:52:55 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3251001065 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.3251001065
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/57.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/57.edn_genbits.1721260922
Short name T598
Test name
Test status
Simulation time 76052519 ps
CPU time 1.98 seconds
Started Aug 21 08:52:52 AM UTC 24
Finished Aug 21 08:52:55 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1721260922 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.1721260922
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/57.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/58.edn_alert.1725871720
Short name T600
Test name
Test status
Simulation time 30923116 ps
CPU time 1.48 seconds
Started Aug 21 08:52:54 AM UTC 24
Finished Aug 21 08:52:57 AM UTC 24
Peak memory 228436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1725871720 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.1725871720
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/58.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/58.edn_err.2442787755
Short name T601
Test name
Test status
Simulation time 24399574 ps
CPU time 1.34 seconds
Started Aug 21 08:52:54 AM UTC 24
Finished Aug 21 08:52:57 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2442787755 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2442787755
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/58.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/58.edn_genbits.1898527949
Short name T604
Test name
Test status
Simulation time 70873075 ps
CPU time 1.67 seconds
Started Aug 21 08:52:54 AM UTC 24
Finished Aug 21 08:52:57 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1898527949 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1898527949
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/58.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/59.edn_alert.1940643263
Short name T606
Test name
Test status
Simulation time 27010027 ps
CPU time 1.62 seconds
Started Aug 21 08:52:55 AM UTC 24
Finished Aug 21 08:52:57 AM UTC 24
Peak memory 228436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1940643263 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.1940643263
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/59.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/59.edn_err.176714006
Short name T605
Test name
Test status
Simulation time 68712017 ps
CPU time 1.44 seconds
Started Aug 21 08:52:55 AM UTC 24
Finished Aug 21 08:52:57 AM UTC 24
Peak memory 242128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=176714006 -assert nopostproc +UVM_TESTNAME=ed
n_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2
024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.176714006
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/59.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/59.edn_genbits.548224128
Short name T602
Test name
Test status
Simulation time 41538239 ps
CPU time 1.41 seconds
Started Aug 21 08:52:54 AM UTC 24
Finished Aug 21 08:52:57 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=548224128 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.548224128
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/59.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/6.edn_alert.1033013785
Short name T133
Test name
Test status
Simulation time 23753347 ps
CPU time 1.4 seconds
Started Aug 21 08:50:30 AM UTC 24
Finished Aug 21 08:50:33 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1033013785 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.1033013785
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/6.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/6.edn_alert_test.998294058
Short name T357
Test name
Test status
Simulation time 24194673 ps
CPU time 0.92 seconds
Started Aug 21 08:50:32 AM UTC 24
Finished Aug 21 08:50:34 AM UTC 24
Peak memory 216696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=998294058 -assert n
opostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.998294058
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/6.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/6.edn_disable_auto_req_mode.226556548
Short name T48
Test name
Test status
Simulation time 29593926 ps
CPU time 1.56 seconds
Started Aug 21 08:50:32 AM UTC 24
Finished Aug 21 08:50:34 AM UTC 24
Peak memory 227848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=226556548 -assert no
postproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disab
le_auto_req_mode.226556548
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/6.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/6.edn_err.1418790680
Short name T224
Test name
Test status
Simulation time 44308008 ps
CPU time 1.31 seconds
Started Aug 21 08:50:30 AM UTC 24
Finished Aug 21 08:50:33 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1418790680 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1418790680
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/6.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/6.edn_genbits.4005636435
Short name T53
Test name
Test status
Simulation time 47264208 ps
CPU time 1.86 seconds
Started Aug 21 08:50:30 AM UTC 24
Finished Aug 21 08:50:33 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4005636435 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.4005636435
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/6.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/6.edn_intr.2872104849
Short name T87
Test name
Test status
Simulation time 21772987 ps
CPU time 1.41 seconds
Started Aug 21 08:50:30 AM UTC 24
Finished Aug 21 08:50:33 AM UTC 24
Peak memory 226324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2872104849 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.2872104849
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/6.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/6.edn_regwen.577281247
Short name T309
Test name
Test status
Simulation time 23774876 ps
CPU time 1.33 seconds
Started Aug 21 08:50:30 AM UTC 24
Finished Aug 21 08:50:32 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=577281247 -assert nopostproc +UVM_TESTNAME=ed
n_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.577281247
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/6.edn_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/6.edn_smoke.3815210435
Short name T356
Test name
Test status
Simulation time 63238506 ps
CPU time 1.12 seconds
Started Aug 21 08:50:29 AM UTC 24
Finished Aug 21 08:50:31 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3815210435 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.3815210435
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/6.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/6.edn_stress_all.1133084455
Short name T123
Test name
Test status
Simulation time 398080407 ps
CPU time 3.28 seconds
Started Aug 21 08:50:30 AM UTC 24
Finished Aug 21 08:50:34 AM UTC 24
Peak memory 229448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1133084455 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.1133084455
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/6.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/60.edn_alert.1540745893
Short name T163
Test name
Test status
Simulation time 32737443 ps
CPU time 1.38 seconds
Started Aug 21 08:52:56 AM UTC 24
Finished Aug 21 08:52:58 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1540745893 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.1540745893
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/60.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/60.edn_err.1684058782
Short name T171
Test name
Test status
Simulation time 21962765 ps
CPU time 1.23 seconds
Started Aug 21 08:52:56 AM UTC 24
Finished Aug 21 08:52:58 AM UTC 24
Peak memory 230356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1684058782 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1684058782
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/60.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/60.edn_genbits.3490103434
Short name T609
Test name
Test status
Simulation time 47736936 ps
CPU time 2.15 seconds
Started Aug 21 08:52:56 AM UTC 24
Finished Aug 21 08:52:59 AM UTC 24
Peak memory 229636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3490103434 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3490103434
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/60.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/61.edn_err.217525851
Short name T607
Test name
Test status
Simulation time 30125500 ps
CPU time 1.4 seconds
Started Aug 21 08:52:56 AM UTC 24
Finished Aug 21 08:52:58 AM UTC 24
Peak memory 237140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=217525851 -assert nopostproc +UVM_TESTNAME=ed
n_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2
024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.217525851
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/61.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/61.edn_genbits.611231544
Short name T610
Test name
Test status
Simulation time 70235752 ps
CPU time 2.63 seconds
Started Aug 21 08:52:56 AM UTC 24
Finished Aug 21 08:52:59 AM UTC 24
Peak memory 231448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=611231544 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.611231544
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/61.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/62.edn_alert.3603010252
Short name T156
Test name
Test status
Simulation time 42556866 ps
CPU time 1.42 seconds
Started Aug 21 08:52:56 AM UTC 24
Finished Aug 21 08:52:58 AM UTC 24
Peak memory 226388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3603010252 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.3603010252
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/62.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/62.edn_err.781634870
Short name T613
Test name
Test status
Simulation time 21897565 ps
CPU time 1.51 seconds
Started Aug 21 08:52:58 AM UTC 24
Finished Aug 21 08:53:01 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=781634870 -assert nopostproc +UVM_TESTNAME=ed
n_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2
024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.781634870
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/62.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/62.edn_genbits.131368437
Short name T608
Test name
Test status
Simulation time 57473678 ps
CPU time 1.6 seconds
Started Aug 21 08:52:56 AM UTC 24
Finished Aug 21 08:52:58 AM UTC 24
Peak memory 230612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=131368437 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.131368437
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/62.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/63.edn_alert.3871818287
Short name T611
Test name
Test status
Simulation time 45644314 ps
CPU time 1.25 seconds
Started Aug 21 08:52:58 AM UTC 24
Finished Aug 21 08:53:00 AM UTC 24
Peak memory 230484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3871818287 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.3871818287
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/63.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/63.edn_err.1730828561
Short name T202
Test name
Test status
Simulation time 21808437 ps
CPU time 1.61 seconds
Started Aug 21 08:52:58 AM UTC 24
Finished Aug 21 08:53:01 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1730828561 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1730828561
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/63.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/63.edn_genbits.630220677
Short name T320
Test name
Test status
Simulation time 197803870 ps
CPU time 1.45 seconds
Started Aug 21 08:52:58 AM UTC 24
Finished Aug 21 08:53:01 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=630220677 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.630220677
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/63.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/64.edn_alert.264552429
Short name T203
Test name
Test status
Simulation time 24388501 ps
CPU time 1.72 seconds
Started Aug 21 08:52:58 AM UTC 24
Finished Aug 21 08:53:01 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=264552429 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.264552429
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/64.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/64.edn_err.1470620186
Short name T612
Test name
Test status
Simulation time 45239603 ps
CPU time 1.28 seconds
Started Aug 21 08:52:58 AM UTC 24
Finished Aug 21 08:53:01 AM UTC 24
Peak memory 228308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1470620186 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.1470620186
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/64.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/64.edn_genbits.2179619597
Short name T614
Test name
Test status
Simulation time 53134334 ps
CPU time 1.67 seconds
Started Aug 21 08:52:58 AM UTC 24
Finished Aug 21 08:53:01 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2179619597 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2179619597
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/64.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/65.edn_alert.2356651054
Short name T617
Test name
Test status
Simulation time 24622023 ps
CPU time 1.5 seconds
Started Aug 21 08:52:59 AM UTC 24
Finished Aug 21 08:53:02 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2356651054 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.2356651054
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/65.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/65.edn_err.2655222115
Short name T615
Test name
Test status
Simulation time 36542185 ps
CPU time 1.01 seconds
Started Aug 21 08:52:59 AM UTC 24
Finished Aug 21 08:53:02 AM UTC 24
Peak memory 236968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2655222115 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.2655222115
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/65.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/65.edn_genbits.699209502
Short name T618
Test name
Test status
Simulation time 255975128 ps
CPU time 1.67 seconds
Started Aug 21 08:52:59 AM UTC 24
Finished Aug 21 08:53:02 AM UTC 24
Peak memory 228088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=699209502 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.699209502
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/65.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/66.edn_alert.3916343971
Short name T620
Test name
Test status
Simulation time 60323889 ps
CPU time 1.77 seconds
Started Aug 21 08:53:00 AM UTC 24
Finished Aug 21 08:53:03 AM UTC 24
Peak memory 228436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3916343971 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.3916343971
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/66.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/66.edn_err.3125743978
Short name T619
Test name
Test status
Simulation time 18994320 ps
CPU time 1.56 seconds
Started Aug 21 08:53:00 AM UTC 24
Finished Aug 21 08:53:02 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3125743978 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.3125743978
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/66.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/66.edn_genbits.1195241642
Short name T616
Test name
Test status
Simulation time 227125095 ps
CPU time 1.41 seconds
Started Aug 21 08:53:00 AM UTC 24
Finished Aug 21 08:53:02 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1195241642 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.1195241642
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/66.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/67.edn_alert.709626458
Short name T622
Test name
Test status
Simulation time 37324154 ps
CPU time 1.44 seconds
Started Aug 21 08:53:01 AM UTC 24
Finished Aug 21 08:53:03 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=709626458 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.709626458
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/67.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/67.edn_genbits.911837027
Short name T621
Test name
Test status
Simulation time 50280497 ps
CPU time 1.87 seconds
Started Aug 21 08:53:00 AM UTC 24
Finished Aug 21 08:53:03 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=911837027 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.911837027
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/67.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/68.edn_alert.4232772938
Short name T628
Test name
Test status
Simulation time 48752535 ps
CPU time 1.76 seconds
Started Aug 21 08:53:02 AM UTC 24
Finished Aug 21 08:53:05 AM UTC 24
Peak memory 230484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4232772938 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.4232772938
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/68.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/68.edn_err.3962074411
Short name T625
Test name
Test status
Simulation time 22518685 ps
CPU time 1.25 seconds
Started Aug 21 08:53:02 AM UTC 24
Finished Aug 21 08:53:04 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3962074411 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.3962074411
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/68.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/68.edn_genbits.90876002
Short name T623
Test name
Test status
Simulation time 67165453 ps
CPU time 1.57 seconds
Started Aug 21 08:53:01 AM UTC 24
Finished Aug 21 08:53:03 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=90876002 -assert nopostproc +UVM_TESTNAME=edn
_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_
1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.90876002
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/68.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/69.edn_alert.232126303
Short name T627
Test name
Test status
Simulation time 97984538 ps
CPU time 1.6 seconds
Started Aug 21 08:53:02 AM UTC 24
Finished Aug 21 08:53:05 AM UTC 24
Peak memory 226360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=232126303 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.232126303
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/69.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/69.edn_err.1470605191
Short name T626
Test name
Test status
Simulation time 36910922 ps
CPU time 1.26 seconds
Started Aug 21 08:53:02 AM UTC 24
Finished Aug 21 08:53:04 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1470605191 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.1470605191
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/69.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/69.edn_genbits.630280921
Short name T326
Test name
Test status
Simulation time 73793056 ps
CPU time 1.34 seconds
Started Aug 21 08:53:02 AM UTC 24
Finished Aug 21 08:53:04 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=630280921 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.630280921
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/69.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/7.edn_alert.38906809
Short name T82
Test name
Test status
Simulation time 37200354 ps
CPU time 1.32 seconds
Started Aug 21 08:50:32 AM UTC 24
Finished Aug 21 08:50:35 AM UTC 24
Peak memory 228432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=38906809 -assert nopostproc +UVM_TESTNAME=edn
_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.38906809
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/7.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/7.edn_alert_test.3383984250
Short name T359
Test name
Test status
Simulation time 29995808 ps
CPU time 1.04 seconds
Started Aug 21 08:50:33 AM UTC 24
Finished Aug 21 08:50:35 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3383984250 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3383984250
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/7.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/7.edn_disable.3032922999
Short name T81
Test name
Test status
Simulation time 100450932 ps
CPU time 1.13 seconds
Started Aug 21 08:50:32 AM UTC 24
Finished Aug 21 08:50:34 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3032922999 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3032922999
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/7.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/7.edn_disable_auto_req_mode.4261367470
Short name T103
Test name
Test status
Simulation time 49806253 ps
CPU time 1.37 seconds
Started Aug 21 08:50:33 AM UTC 24
Finished Aug 21 08:50:36 AM UTC 24
Peak memory 226264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4261367470 -assert n
opostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disa
ble_auto_req_mode.4261367470
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/7.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/7.edn_err.319380384
Short name T117
Test name
Test status
Simulation time 18348757 ps
CPU time 1.24 seconds
Started Aug 21 08:50:32 AM UTC 24
Finished Aug 21 08:50:34 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=319380384 -assert nopostproc +UVM_TESTNAME=ed
n_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2
024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.319380384
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/7.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/7.edn_genbits.4111393651
Short name T348
Test name
Test status
Simulation time 72266238 ps
CPU time 1.43 seconds
Started Aug 21 08:50:32 AM UTC 24
Finished Aug 21 08:50:34 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4111393651 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.4111393651
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/7.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/7.edn_intr.3897395226
Short name T62
Test name
Test status
Simulation time 22785884 ps
CPU time 1.78 seconds
Started Aug 21 08:50:32 AM UTC 24
Finished Aug 21 08:50:35 AM UTC 24
Peak memory 236708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3897395226 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.3897395226
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/7.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/7.edn_regwen.3801710874
Short name T122
Test name
Test status
Simulation time 31340756 ps
CPU time 1.21 seconds
Started Aug 21 08:50:32 AM UTC 24
Finished Aug 21 08:50:34 AM UTC 24
Peak memory 216016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3801710874 -assert nopostproc +UVM_TESTNAME=e
dn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1
_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3801710874
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/7.edn_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/7.edn_smoke.2794605436
Short name T358
Test name
Test status
Simulation time 17693623 ps
CPU time 1.21 seconds
Started Aug 21 08:50:32 AM UTC 24
Finished Aug 21 08:50:34 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2794605436 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.2794605436
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/7.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/7.edn_stress_all_with_rand_reset.820934115
Short name T238
Test name
Test status
Simulation time 24907836578 ps
CPU time 78.73 seconds
Started Aug 21 08:50:32 AM UTC 24
Finished Aug 21 08:51:53 AM UTC 24
Peak memory 229780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=820934115 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.820934115
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/7.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/70.edn_alert.3573122059
Short name T180
Test name
Test status
Simulation time 33193442 ps
CPU time 1.83 seconds
Started Aug 21 08:53:03 AM UTC 24
Finished Aug 21 08:53:06 AM UTC 24
Peak memory 226368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3573122059 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.3573122059
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/70.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/70.edn_err.3688786816
Short name T630
Test name
Test status
Simulation time 38850423 ps
CPU time 1.33 seconds
Started Aug 21 08:53:03 AM UTC 24
Finished Aug 21 08:53:06 AM UTC 24
Peak memory 236968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3688786816 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.3688786816
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/70.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/70.edn_genbits.4208335746
Short name T629
Test name
Test status
Simulation time 71394452 ps
CPU time 2.33 seconds
Started Aug 21 08:53:02 AM UTC 24
Finished Aug 21 08:53:06 AM UTC 24
Peak memory 229524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4208335746 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.4208335746
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/70.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/71.edn_alert.3305331780
Short name T632
Test name
Test status
Simulation time 27555734 ps
CPU time 1.48 seconds
Started Aug 21 08:53:03 AM UTC 24
Finished Aug 21 08:53:06 AM UTC 24
Peak memory 230484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3305331780 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.3305331780
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/71.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/71.edn_err.549489197
Short name T182
Test name
Test status
Simulation time 19127889 ps
CPU time 1.45 seconds
Started Aug 21 08:53:03 AM UTC 24
Finished Aug 21 08:53:06 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=549489197 -assert nopostproc +UVM_TESTNAME=ed
n_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2
024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.549489197
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/71.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/71.edn_genbits.3052438620
Short name T634
Test name
Test status
Simulation time 64363661 ps
CPU time 2.18 seconds
Started Aug 21 08:53:03 AM UTC 24
Finished Aug 21 08:53:07 AM UTC 24
Peak memory 231368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3052438620 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.3052438620
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/71.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/72.edn_alert.941738822
Short name T633
Test name
Test status
Simulation time 27705993 ps
CPU time 1.7 seconds
Started Aug 21 08:53:04 AM UTC 24
Finished Aug 21 08:53:06 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=941738822 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.941738822
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/72.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/72.edn_err.1197670599
Short name T229
Test name
Test status
Simulation time 19010263 ps
CPU time 1.3 seconds
Started Aug 21 08:53:05 AM UTC 24
Finished Aug 21 08:53:07 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1197670599 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.1197670599
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/72.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/72.edn_genbits.225686152
Short name T631
Test name
Test status
Simulation time 71974936 ps
CPU time 1.39 seconds
Started Aug 21 08:53:03 AM UTC 24
Finished Aug 21 08:53:06 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=225686152 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.225686152
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/72.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/73.edn_alert.557110502
Short name T635
Test name
Test status
Simulation time 60957719 ps
CPU time 1.31 seconds
Started Aug 21 08:53:05 AM UTC 24
Finished Aug 21 08:53:07 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=557110502 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.557110502
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/73.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/73.edn_err.1124971470
Short name T636
Test name
Test status
Simulation time 19564726 ps
CPU time 1.45 seconds
Started Aug 21 08:53:05 AM UTC 24
Finished Aug 21 08:53:07 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1124971470 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1124971470
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/73.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/73.edn_genbits.2276445367
Short name T648
Test name
Test status
Simulation time 340938956 ps
CPU time 4.85 seconds
Started Aug 21 08:53:05 AM UTC 24
Finished Aug 21 08:53:11 AM UTC 24
Peak memory 231500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2276445367 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.2276445367
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/73.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/74.edn_alert.540791997
Short name T637
Test name
Test status
Simulation time 48344211 ps
CPU time 1.79 seconds
Started Aug 21 08:53:05 AM UTC 24
Finished Aug 21 08:53:08 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=540791997 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.540791997
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/74.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/74.edn_err.3224935900
Short name T154
Test name
Test status
Simulation time 80104145 ps
CPU time 1.29 seconds
Started Aug 21 08:53:05 AM UTC 24
Finished Aug 21 08:53:07 AM UTC 24
Peak memory 243744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3224935900 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3224935900
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/74.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/74.edn_genbits.1684139966
Short name T638
Test name
Test status
Simulation time 76396794 ps
CPU time 1.89 seconds
Started Aug 21 08:53:05 AM UTC 24
Finished Aug 21 08:53:08 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1684139966 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.1684139966
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/74.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/75.edn_alert.392733323
Short name T643
Test name
Test status
Simulation time 164477762 ps
CPU time 1.82 seconds
Started Aug 21 08:53:06 AM UTC 24
Finished Aug 21 08:53:09 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=392733323 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.392733323
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/75.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/75.edn_err.1741374078
Short name T639
Test name
Test status
Simulation time 134753115 ps
CPU time 1.43 seconds
Started Aug 21 08:53:06 AM UTC 24
Finished Aug 21 08:53:08 AM UTC 24
Peak memory 242076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1741374078 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.1741374078
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/75.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/75.edn_genbits.457131682
Short name T641
Test name
Test status
Simulation time 43700656 ps
CPU time 1.68 seconds
Started Aug 21 08:53:06 AM UTC 24
Finished Aug 21 08:53:09 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=457131682 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.457131682
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/75.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/76.edn_alert.3575095981
Short name T642
Test name
Test status
Simulation time 113727138 ps
CPU time 1.54 seconds
Started Aug 21 08:53:06 AM UTC 24
Finished Aug 21 08:53:09 AM UTC 24
Peak memory 228436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3575095981 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.3575095981
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/76.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/76.edn_err.1585592438
Short name T644
Test name
Test status
Simulation time 38395209 ps
CPU time 1.13 seconds
Started Aug 21 08:53:07 AM UTC 24
Finished Aug 21 08:53:09 AM UTC 24
Peak memory 244164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1585592438 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.1585592438
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/76.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/76.edn_genbits.3675330110
Short name T640
Test name
Test status
Simulation time 274782756 ps
CPU time 1.43 seconds
Started Aug 21 08:53:06 AM UTC 24
Finished Aug 21 08:53:09 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3675330110 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3675330110
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/76.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/77.edn_alert.4080341193
Short name T646
Test name
Test status
Simulation time 22637053 ps
CPU time 1.42 seconds
Started Aug 21 08:53:07 AM UTC 24
Finished Aug 21 08:53:10 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4080341193 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.4080341193
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/77.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/77.edn_err.3068698459
Short name T194
Test name
Test status
Simulation time 21368544 ps
CPU time 1.47 seconds
Started Aug 21 08:53:07 AM UTC 24
Finished Aug 21 08:53:10 AM UTC 24
Peak memory 236968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3068698459 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.3068698459
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/77.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/77.edn_genbits.1619374899
Short name T647
Test name
Test status
Simulation time 40306621 ps
CPU time 1.88 seconds
Started Aug 21 08:53:07 AM UTC 24
Finished Aug 21 08:53:10 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1619374899 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.1619374899
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/77.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/78.edn_alert.2963373887
Short name T645
Test name
Test status
Simulation time 45399323 ps
CPU time 1.29 seconds
Started Aug 21 08:53:07 AM UTC 24
Finished Aug 21 08:53:10 AM UTC 24
Peak memory 228436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2963373887 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.2963373887
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/78.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/78.edn_err.1549878838
Short name T188
Test name
Test status
Simulation time 32804451 ps
CPU time 1.19 seconds
Started Aug 21 08:53:07 AM UTC 24
Finished Aug 21 08:53:10 AM UTC 24
Peak memory 236968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1549878838 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.1549878838
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/78.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/78.edn_genbits.3384292632
Short name T650
Test name
Test status
Simulation time 46893168 ps
CPU time 2.27 seconds
Started Aug 21 08:53:07 AM UTC 24
Finished Aug 21 08:53:11 AM UTC 24
Peak memory 229708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3384292632 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.3384292632
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/78.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/79.edn_alert.1166632877
Short name T651
Test name
Test status
Simulation time 75157547 ps
CPU time 1.54 seconds
Started Aug 21 08:53:09 AM UTC 24
Finished Aug 21 08:53:11 AM UTC 24
Peak memory 230484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1166632877 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.1166632877
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/79.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/79.edn_err.4028665097
Short name T649
Test name
Test status
Simulation time 23137553 ps
CPU time 1 seconds
Started Aug 21 08:53:09 AM UTC 24
Finished Aug 21 08:53:11 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4028665097 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.4028665097
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/79.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/79.edn_genbits.4126422850
Short name T653
Test name
Test status
Simulation time 27026095 ps
CPU time 1.66 seconds
Started Aug 21 08:53:09 AM UTC 24
Finished Aug 21 08:53:11 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4126422850 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.4126422850
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/79.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/8.edn_alert_test.3018480491
Short name T360
Test name
Test status
Simulation time 37106441 ps
CPU time 0.98 seconds
Started Aug 21 08:50:35 AM UTC 24
Finished Aug 21 08:50:37 AM UTC 24
Peak memory 216376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3018480491 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3018480491
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/8.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/8.edn_disable.1657401458
Short name T83
Test name
Test status
Simulation time 14553820 ps
CPU time 1.24 seconds
Started Aug 21 08:50:35 AM UTC 24
Finished Aug 21 08:50:37 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1657401458 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.1657401458
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/8.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/8.edn_disable_auto_req_mode.742156170
Short name T84
Test name
Test status
Simulation time 99890680 ps
CPU time 1.32 seconds
Started Aug 21 08:50:35 AM UTC 24
Finished Aug 21 08:50:37 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=742156170 -assert no
postproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disab
le_auto_req_mode.742156170
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/8.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/8.edn_err.3023176215
Short name T361
Test name
Test status
Simulation time 27209177 ps
CPU time 1.31 seconds
Started Aug 21 08:50:35 AM UTC 24
Finished Aug 21 08:50:37 AM UTC 24
Peak memory 228168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3023176215 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3023176215
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/8.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/8.edn_genbits.1881863091
Short name T49
Test name
Test status
Simulation time 305495757 ps
CPU time 4.3 seconds
Started Aug 21 08:50:34 AM UTC 24
Finished Aug 21 08:50:39 AM UTC 24
Peak memory 231564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1881863091 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1881863091
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/8.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/8.edn_intr.1636229079
Short name T51
Test name
Test status
Simulation time 38066522 ps
CPU time 1.12 seconds
Started Aug 21 08:50:35 AM UTC 24
Finished Aug 21 08:50:37 AM UTC 24
Peak memory 228320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1636229079 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.1636229079
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/8.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/8.edn_regwen.3703301358
Short name T312
Test name
Test status
Simulation time 49972553 ps
CPU time 1.03 seconds
Started Aug 21 08:50:33 AM UTC 24
Finished Aug 21 08:50:35 AM UTC 24
Peak memory 216016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3703301358 -assert nopostproc +UVM_TESTNAME=e
dn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1
_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3703301358
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/8.edn_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/8.edn_smoke.4069902200
Short name T310
Test name
Test status
Simulation time 22573349 ps
CPU time 1.38 seconds
Started Aug 21 08:50:33 AM UTC 24
Finished Aug 21 08:50:36 AM UTC 24
Peak memory 216016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4069902200 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.4069902200
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/8.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/8.edn_stress_all.2098422778
Short name T114
Test name
Test status
Simulation time 303676294 ps
CPU time 5.04 seconds
Started Aug 21 08:50:34 AM UTC 24
Finished Aug 21 08:50:40 AM UTC 24
Peak memory 231260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2098422778 -asse
rt nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2098422778
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/8.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/8.edn_stress_all_with_rand_reset.669634127
Short name T234
Test name
Test status
Simulation time 39148983356 ps
CPU time 65.95 seconds
Started Aug 21 08:50:34 AM UTC 24
Finished Aug 21 08:51:41 AM UTC 24
Peak memory 227692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=669634127 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.669634127
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/8.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/80.edn_alert.1583226359
Short name T307
Test name
Test status
Simulation time 48884075 ps
CPU time 1.29 seconds
Started Aug 21 08:53:09 AM UTC 24
Finished Aug 21 08:53:11 AM UTC 24
Peak memory 230484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1583226359 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.1583226359
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/80.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/80.edn_err.15156955
Short name T655
Test name
Test status
Simulation time 24580696 ps
CPU time 1.67 seconds
Started Aug 21 08:53:10 AM UTC 24
Finished Aug 21 08:53:12 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=15156955 -assert nopostproc +UVM_TESTNAME=edn
_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_20
24_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.15156955
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/80.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/80.edn_genbits.2439164281
Short name T652
Test name
Test status
Simulation time 64327035 ps
CPU time 1.5 seconds
Started Aug 21 08:53:09 AM UTC 24
Finished Aug 21 08:53:11 AM UTC 24
Peak memory 230628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2439164281 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2439164281
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/80.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/81.edn_alert.1842164781
Short name T654
Test name
Test status
Simulation time 336939291 ps
CPU time 1.33 seconds
Started Aug 21 08:53:10 AM UTC 24
Finished Aug 21 08:53:12 AM UTC 24
Peak memory 228436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1842164781 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.1842164781
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/81.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/81.edn_err.805492196
Short name T213
Test name
Test status
Simulation time 19881317 ps
CPU time 1.31 seconds
Started Aug 21 08:53:10 AM UTC 24
Finished Aug 21 08:53:12 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=805492196 -assert nopostproc +UVM_TESTNAME=ed
n_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2
024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.805492196
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/81.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/81.edn_genbits.892296929
Short name T352
Test name
Test status
Simulation time 313115999 ps
CPU time 3.99 seconds
Started Aug 21 08:53:10 AM UTC 24
Finished Aug 21 08:53:15 AM UTC 24
Peak memory 231572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=892296929 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.892296929
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/81.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/82.edn_alert.937056990
Short name T656
Test name
Test status
Simulation time 63516814 ps
CPU time 1.58 seconds
Started Aug 21 08:53:10 AM UTC 24
Finished Aug 21 08:53:13 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=937056990 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.937056990
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/82.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/82.edn_err.2882154372
Short name T658
Test name
Test status
Simulation time 32110346 ps
CPU time 1.23 seconds
Started Aug 21 08:53:11 AM UTC 24
Finished Aug 21 08:53:13 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2882154372 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.2882154372
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/82.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/82.edn_genbits.217893843
Short name T657
Test name
Test status
Simulation time 51058917 ps
CPU time 1.69 seconds
Started Aug 21 08:53:10 AM UTC 24
Finished Aug 21 08:53:13 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=217893843 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.217893843
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/82.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/83.edn_alert.1672925128
Short name T662
Test name
Test status
Simulation time 49238746 ps
CPU time 1.71 seconds
Started Aug 21 08:53:11 AM UTC 24
Finished Aug 21 08:53:14 AM UTC 24
Peak memory 230484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1672925128 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.1672925128
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/83.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/83.edn_err.3931384045
Short name T660
Test name
Test status
Simulation time 33472867 ps
CPU time 1.54 seconds
Started Aug 21 08:53:11 AM UTC 24
Finished Aug 21 08:53:14 AM UTC 24
Peak memory 228308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3931384045 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.3931384045
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/83.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/83.edn_genbits.930923411
Short name T319
Test name
Test status
Simulation time 86349117 ps
CPU time 1.25 seconds
Started Aug 21 08:53:11 AM UTC 24
Finished Aug 21 08:53:13 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=930923411 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.930923411
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/83.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/84.edn_alert.1609023586
Short name T204
Test name
Test status
Simulation time 43132644 ps
CPU time 1.64 seconds
Started Aug 21 08:53:11 AM UTC 24
Finished Aug 21 08:53:14 AM UTC 24
Peak memory 230484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1609023586 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.1609023586
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/84.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/84.edn_err.3634477817
Short name T659
Test name
Test status
Simulation time 33379003 ps
CPU time 1.24 seconds
Started Aug 21 08:53:11 AM UTC 24
Finished Aug 21 08:53:14 AM UTC 24
Peak memory 230400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3634477817 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3634477817
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/84.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/84.edn_genbits.3525547711
Short name T661
Test name
Test status
Simulation time 216279340 ps
CPU time 1.53 seconds
Started Aug 21 08:53:11 AM UTC 24
Finished Aug 21 08:53:14 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3525547711 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3525547711
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/84.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/85.edn_alert.2663643818
Short name T664
Test name
Test status
Simulation time 91783742 ps
CPU time 1.37 seconds
Started Aug 21 08:53:12 AM UTC 24
Finished Aug 21 08:53:15 AM UTC 24
Peak memory 228436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2663643818 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.2663643818
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/85.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/85.edn_err.1742553258
Short name T665
Test name
Test status
Simulation time 43828459 ps
CPU time 1.45 seconds
Started Aug 21 08:53:13 AM UTC 24
Finished Aug 21 08:53:15 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1742553258 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1742553258
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/85.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/85.edn_genbits.1802012701
Short name T663
Test name
Test status
Simulation time 45397100 ps
CPU time 2.33 seconds
Started Aug 21 08:53:11 AM UTC 24
Finished Aug 21 08:53:15 AM UTC 24
Peak memory 231584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1802012701 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1802012701
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/85.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/86.edn_alert.1650350190
Short name T667
Test name
Test status
Simulation time 112849059 ps
CPU time 1.56 seconds
Started Aug 21 08:53:13 AM UTC 24
Finished Aug 21 08:53:15 AM UTC 24
Peak memory 228436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1650350190 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.1650350190
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/86.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/86.edn_err.1208153857
Short name T668
Test name
Test status
Simulation time 29050222 ps
CPU time 1.23 seconds
Started Aug 21 08:53:14 AM UTC 24
Finished Aug 21 08:53:16 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1208153857 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1208153857
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/86.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/86.edn_genbits.2551010449
Short name T666
Test name
Test status
Simulation time 51433107 ps
CPU time 1.38 seconds
Started Aug 21 08:53:13 AM UTC 24
Finished Aug 21 08:53:15 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2551010449 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.2551010449
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/86.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/87.edn_alert.4281260670
Short name T257
Test name
Test status
Simulation time 30891276 ps
CPU time 1.36 seconds
Started Aug 21 08:53:14 AM UTC 24
Finished Aug 21 08:53:16 AM UTC 24
Peak memory 230484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4281260670 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.4281260670
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/87.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/87.edn_err.76843364
Short name T669
Test name
Test status
Simulation time 108892318 ps
CPU time 1.48 seconds
Started Aug 21 08:53:14 AM UTC 24
Finished Aug 21 08:53:16 AM UTC 24
Peak memory 242392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=76843364 -assert nopostproc +UVM_TESTNAME=edn
_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_20
24_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.76843364
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/87.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/87.edn_genbits.3851378451
Short name T673
Test name
Test status
Simulation time 106366251 ps
CPU time 2.07 seconds
Started Aug 21 08:53:14 AM UTC 24
Finished Aug 21 08:53:17 AM UTC 24
Peak memory 231496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3851378451 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3851378451
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/87.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/88.edn_alert.2458651837
Short name T670
Test name
Test status
Simulation time 138417804 ps
CPU time 1.39 seconds
Started Aug 21 08:53:14 AM UTC 24
Finished Aug 21 08:53:16 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2458651837 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.2458651837
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/88.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/88.edn_err.3978714006
Short name T672
Test name
Test status
Simulation time 96498978 ps
CPU time 1.67 seconds
Started Aug 21 08:53:14 AM UTC 24
Finished Aug 21 08:53:17 AM UTC 24
Peak memory 230356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3978714006 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.3978714006
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/88.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/88.edn_genbits.2183886960
Short name T671
Test name
Test status
Simulation time 43777443 ps
CPU time 1.61 seconds
Started Aug 21 08:53:14 AM UTC 24
Finished Aug 21 08:53:17 AM UTC 24
Peak memory 228560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2183886960 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.2183886960
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/88.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/89.edn_alert.2357977030
Short name T677
Test name
Test status
Simulation time 40940438 ps
CPU time 1.63 seconds
Started Aug 21 08:53:15 AM UTC 24
Finished Aug 21 08:53:18 AM UTC 24
Peak memory 228436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2357977030 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.2357977030
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/89.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/89.edn_err.4270252755
Short name T674
Test name
Test status
Simulation time 101929900 ps
CPU time 1.09 seconds
Started Aug 21 08:53:15 AM UTC 24
Finished Aug 21 08:53:17 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4270252755 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.4270252755
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/89.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/89.edn_genbits.2657780893
Short name T676
Test name
Test status
Simulation time 42386857 ps
CPU time 1.48 seconds
Started Aug 21 08:53:15 AM UTC 24
Finished Aug 21 08:53:18 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2657780893 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.2657780893
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/89.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/9.edn_alert.2693490019
Short name T131
Test name
Test status
Simulation time 27891022 ps
CPU time 1.81 seconds
Started Aug 21 08:50:36 AM UTC 24
Finished Aug 21 08:50:39 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2693490019 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.2693490019
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/9.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/9.edn_alert_test.3423310859
Short name T365
Test name
Test status
Simulation time 15508579 ps
CPU time 1.21 seconds
Started Aug 21 08:50:38 AM UTC 24
Finished Aug 21 08:50:40 AM UTC 24
Peak memory 215792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3423310859 -assert
nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.3423310859
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/9.edn_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/9.edn_disable.3953573430
Short name T93
Test name
Test status
Simulation time 17389459 ps
CPU time 1.08 seconds
Started Aug 21 08:50:36 AM UTC 24
Finished Aug 21 08:50:38 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3953573430 -assert n
opostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.3953573430
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/9.edn_disable/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/9.edn_disable_auto_req_mode.350869518
Short name T160
Test name
Test status
Simulation time 39041151 ps
CPU time 1.38 seconds
Started Aug 21 08:50:36 AM UTC 24
Finished Aug 21 08:50:39 AM UTC 24
Peak memory 228308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=350869518 -assert no
postproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disab
le_auto_req_mode.350869518
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/9.edn_disable_auto_req_mode/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/9.edn_err.2432506662
Short name T147
Test name
Test status
Simulation time 28288251 ps
CPU time 1.5 seconds
Started Aug 21 08:50:36 AM UTC 24
Finished Aug 21 08:50:39 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2432506662 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.2432506662
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/9.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/9.edn_genbits.1508409586
Short name T364
Test name
Test status
Simulation time 57732950 ps
CPU time 1.62 seconds
Started Aug 21 08:50:36 AM UTC 24
Finished Aug 21 08:50:39 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1508409586 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1508409586
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/9.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/9.edn_intr.1616731138
Short name T363
Test name
Test status
Simulation time 38972427 ps
CPU time 1.25 seconds
Started Aug 21 08:50:36 AM UTC 24
Finished Aug 21 08:50:38 AM UTC 24
Peak memory 226324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1616731138 -assert nopostproc +UVM_TESTNAME=e
dn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_
0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.1616731138
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/9.edn_intr/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/9.edn_regwen.522295310
Short name T313
Test name
Test status
Simulation time 44356911 ps
CPU time 1.23 seconds
Started Aug 21 08:50:35 AM UTC 24
Finished Aug 21 08:50:37 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=522295310 -assert nopostproc +UVM_TESTNAME=ed
n_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.522295310
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/9.edn_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/9.edn_smoke.2309997660
Short name T362
Test name
Test status
Simulation time 19410564 ps
CPU time 1.31 seconds
Started Aug 21 08:50:35 AM UTC 24
Finished Aug 21 08:50:37 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2309997660 -assert nopostproc +UVM_TESTNAME=e
dn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2309997660
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/9.edn_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/9.edn_stress_all.792240592
Short name T294
Test name
Test status
Simulation time 421337232 ps
CPU time 3.52 seconds
Started Aug 21 08:50:36 AM UTC 24
Finished Aug 21 08:50:41 AM UTC 24
Peak memory 227352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=792240592 -asser
t nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.792240592
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/9.edn_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/9.edn_stress_all_with_rand_reset.2179907728
Short name T239
Test name
Test status
Simulation time 2881668971 ps
CPU time 79.44 seconds
Started Aug 21 08:50:36 AM UTC 24
Finished Aug 21 08:51:58 AM UTC 24
Peak memory 229800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000
000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc
/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2179907728 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.2179907728
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/9.edn_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/90.edn_alert.353477811
Short name T678
Test name
Test status
Simulation time 77000376 ps
CPU time 1.62 seconds
Started Aug 21 08:53:15 AM UTC 24
Finished Aug 21 08:53:18 AM UTC 24
Peak memory 232524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=353477811 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.353477811
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/90.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/90.edn_err.2158790160
Short name T675
Test name
Test status
Simulation time 19885374 ps
CPU time 1.08 seconds
Started Aug 21 08:53:15 AM UTC 24
Finished Aug 21 08:53:17 AM UTC 24
Peak memory 228308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2158790160 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.2158790160
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/90.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/90.edn_genbits.3122484955
Short name T687
Test name
Test status
Simulation time 94513245 ps
CPU time 3.64 seconds
Started Aug 21 08:53:15 AM UTC 24
Finished Aug 21 08:53:20 AM UTC 24
Peak memory 231760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3122484955 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3122484955
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/90.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/91.edn_alert.622390989
Short name T681
Test name
Test status
Simulation time 27294469 ps
CPU time 1.64 seconds
Started Aug 21 08:53:16 AM UTC 24
Finished Aug 21 08:53:19 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=622390989 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.622390989
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/91.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/91.edn_err.3994716117
Short name T682
Test name
Test status
Simulation time 18686141 ps
CPU time 1.64 seconds
Started Aug 21 08:53:17 AM UTC 24
Finished Aug 21 08:53:19 AM UTC 24
Peak memory 237344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3994716117 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3994716117
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/91.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/91.edn_genbits.705212988
Short name T680
Test name
Test status
Simulation time 86835559 ps
CPU time 1.33 seconds
Started Aug 21 08:53:16 AM UTC 24
Finished Aug 21 08:53:19 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=705212988 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.705212988
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/91.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/92.edn_err.4016917793
Short name T679
Test name
Test status
Simulation time 30567077 ps
CPU time 0.95 seconds
Started Aug 21 08:53:17 AM UTC 24
Finished Aug 21 08:53:19 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4016917793 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.4016917793
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/92.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/92.edn_genbits.1297333528
Short name T683
Test name
Test status
Simulation time 38629623 ps
CPU time 1.66 seconds
Started Aug 21 08:53:17 AM UTC 24
Finished Aug 21 08:53:19 AM UTC 24
Peak memory 228152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1297333528 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1297333528
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/92.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/93.edn_alert.3406275566
Short name T690
Test name
Test status
Simulation time 25188591 ps
CPU time 1.69 seconds
Started Aug 21 08:53:18 AM UTC 24
Finished Aug 21 08:53:20 AM UTC 24
Peak memory 230484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3406275566 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.3406275566
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/93.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/93.edn_err.3200884609
Short name T688
Test name
Test status
Simulation time 25046619 ps
CPU time 1.12 seconds
Started Aug 21 08:53:18 AM UTC 24
Finished Aug 21 08:53:20 AM UTC 24
Peak memory 236968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3200884609 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3200884609
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/93.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/93.edn_genbits.4154666846
Short name T686
Test name
Test status
Simulation time 38367503 ps
CPU time 1.76 seconds
Started Aug 21 08:53:17 AM UTC 24
Finished Aug 21 08:53:19 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4154666846 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.4154666846
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/93.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/94.edn_alert.230356568
Short name T258
Test name
Test status
Simulation time 35599646 ps
CPU time 1.38 seconds
Started Aug 21 08:53:18 AM UTC 24
Finished Aug 21 08:53:20 AM UTC 24
Peak memory 226360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=230356568 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.230356568
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/94.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/94.edn_err.2560668152
Short name T691
Test name
Test status
Simulation time 44278828 ps
CPU time 1.44 seconds
Started Aug 21 08:53:18 AM UTC 24
Finished Aug 21 08:53:20 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2560668152 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.2560668152
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/94.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/94.edn_genbits.136302726
Short name T694
Test name
Test status
Simulation time 97693812 ps
CPU time 2.38 seconds
Started Aug 21 08:53:18 AM UTC 24
Finished Aug 21 08:53:21 AM UTC 24
Peak memory 231512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=136302726 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.136302726
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/94.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/95.edn_alert.517103498
Short name T689
Test name
Test status
Simulation time 80256785 ps
CPU time 1.3 seconds
Started Aug 21 08:53:18 AM UTC 24
Finished Aug 21 08:53:20 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=517103498 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.517103498
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/95.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/95.edn_err.1429686483
Short name T695
Test name
Test status
Simulation time 78257670 ps
CPU time 1.19 seconds
Started Aug 21 08:53:19 AM UTC 24
Finished Aug 21 08:53:21 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1429686483 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1429686483
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/95.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/95.edn_genbits.2743300488
Short name T692
Test name
Test status
Simulation time 31140563 ps
CPU time 1.67 seconds
Started Aug 21 08:53:18 AM UTC 24
Finished Aug 21 08:53:21 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2743300488 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2743300488
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/95.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/96.edn_alert.1644036758
Short name T168
Test name
Test status
Simulation time 100407788 ps
CPU time 1.76 seconds
Started Aug 21 08:53:19 AM UTC 24
Finished Aug 21 08:53:22 AM UTC 24
Peak memory 225856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1644036758 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.1644036758
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/96.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/96.edn_err.1005744052
Short name T693
Test name
Test status
Simulation time 40114308 ps
CPU time 0.94 seconds
Started Aug 21 08:53:19 AM UTC 24
Finished Aug 21 08:53:21 AM UTC 24
Peak memory 236968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1005744052 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1005744052
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/96.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/96.edn_genbits.208883641
Short name T696
Test name
Test status
Simulation time 63908873 ps
CPU time 1.43 seconds
Started Aug 21 08:53:19 AM UTC 24
Finished Aug 21 08:53:22 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=208883641 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.208883641
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/96.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/97.edn_alert.503908829
Short name T698
Test name
Test status
Simulation time 51757020 ps
CPU time 1.42 seconds
Started Aug 21 08:53:20 AM UTC 24
Finished Aug 21 08:53:23 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=503908829 -assert nopostproc +UVM_TESTNAME=ed
n_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0
_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.503908829
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/97.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/97.edn_err.1187528949
Short name T697
Test name
Test status
Simulation time 23467901 ps
CPU time 1.25 seconds
Started Aug 21 08:53:20 AM UTC 24
Finished Aug 21 08:53:23 AM UTC 24
Peak memory 236968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1187528949 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.1187528949
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/97.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/97.edn_genbits.3439068309
Short name T354
Test name
Test status
Simulation time 33472020 ps
CPU time 1.93 seconds
Started Aug 21 08:53:19 AM UTC 24
Finished Aug 21 08:53:22 AM UTC 24
Peak memory 230744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3439068309 -assert nopostproc +UVM_TESTNAME=e
dn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgre
y_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3439068309
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/97.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/98.edn_alert.1553867606
Short name T699
Test name
Test status
Simulation time 73827549 ps
CPU time 1.36 seconds
Started Aug 21 08:53:20 AM UTC 24
Finished Aug 21 08:53:23 AM UTC 24
Peak memory 228436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1553867606 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.1553867606
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/98.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/98.edn_err.3852884683
Short name T159
Test name
Test status
Simulation time 20579514 ps
CPU time 1.58 seconds
Started Aug 21 08:53:21 AM UTC 24
Finished Aug 21 08:53:23 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3852884683 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.3852884683
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/98.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/98.edn_genbits.51807038
Short name T701
Test name
Test status
Simulation time 77549099 ps
CPU time 2.13 seconds
Started Aug 21 08:53:20 AM UTC 24
Finished Aug 21 08:53:24 AM UTC 24
Peak memory 229776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=51807038 -assert nopostproc +UVM_TESTNAME=edn
_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_
1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.51807038
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/98.edn_genbits/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/99.edn_alert.2793109059
Short name T259
Test name
Test status
Simulation time 70598876 ps
CPU time 1.45 seconds
Started Aug 21 08:53:21 AM UTC 24
Finished Aug 21 08:53:23 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2793109059 -assert nopostproc +UVM_TESTNAME=e
dn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_
0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.2793109059
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/99.edn_alert/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/99.edn_err.1748884472
Short name T136
Test name
Test status
Simulation time 33991260 ps
CPU time 1.49 seconds
Started Aug 21 08:53:21 AM UTC 24
Finished Aug 21 08:53:23 AM UTC 24
Peak memory 244104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1748884472 -assert nopostproc +UVM_TESTNAME=e
dn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_
2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1748884472
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/99.edn_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default/99.edn_genbits.727777278
Short name T700
Test name
Test status
Simulation time 35914782 ps
CPU time 1.75 seconds
Started Aug 21 08:53:21 AM UTC 24
Finished Aug 21 08:53:23 AM UTC 24
Peak memory 230668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=727777278 -assert nopostproc +UVM_TESTNAME=ed
n_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey
_1_0_0_2024_08_20_RC0/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.727777278
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/99.edn_genbits/latest
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