Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 12 0 12 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 2 0 2 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 12 0 12 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 5006 1 T4 18 T56 14 T57 4
all_values[1] 5006 1 T4 18 T56 14 T57 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5145 1 T4 23 T56 11 T57 5
auto[1] 4867 1 T4 13 T56 17 T57 3


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3927 1 T4 18 T56 11 T57 5
auto[1] 6085 1 T4 18 T56 17 T57 3


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5967 1 T4 23 T56 20 T57 6
auto[1] 4045 1 T4 13 T56 8 T57 2


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 12 0 12 100.00
Automatically Generated Cross Bins 12 0 12 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 1020 1 T4 6 T56 4 T110 5
all_values[0] auto[0] auto[0] auto[1] 513 1 T4 1 T57 1 T110 8
all_values[0] auto[0] auto[1] auto[0] 945 1 T4 5 T56 5 T57 2
all_values[0] auto[0] auto[1] auto[1] 517 1 T4 1 T56 3 T110 2
all_values[0] auto[1] auto[0] auto[1] 1043 1 T4 4 T56 2 T110 11
all_values[0] auto[1] auto[1] auto[1] 968 1 T4 1 T57 1 T110 6
all_values[1] auto[0] auto[0] auto[0] 1036 1 T4 4 T57 3 T110 6
all_values[1] auto[0] auto[0] auto[1] 508 1 T4 2 T56 3 T110 4
all_values[1] auto[0] auto[1] auto[0] 926 1 T4 3 T56 2 T110 3
all_values[1] auto[0] auto[1] auto[1] 502 1 T4 1 T56 3 T110 3
all_values[1] auto[1] auto[0] auto[1] 1025 1 T4 6 T56 2 T57 1
all_values[1] auto[1] auto[1] auto[1] 1009 1 T4 2 T56 4 T110 11


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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