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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.63 98.25 93.91 97.02 91.28 96.37 99.77 92.80


Total test records in report: 1117
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T317 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_intg_err.112355309 Aug 23 05:50:28 PM UTC 24 Aug 23 05:50:31 PM UTC 24 76305240 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/4.edn_same_csr_outstanding.2818574837 Aug 23 05:50:26 PM UTC 24 Aug 23 05:50:31 PM UTC 24 52327536 ps
T1007 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_intg_err.2656713864 Aug 23 05:50:26 PM UTC 24 Aug 23 05:50:32 PM UTC 24 51127087 ps
T1008 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2876526616 Aug 23 05:50:26 PM UTC 24 Aug 23 05:50:32 PM UTC 24 33349695 ps
T1009 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_errors.2336811051 Aug 23 05:50:22 PM UTC 24 Aug 23 05:50:32 PM UTC 24 131994074 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_rw.1017692755 Aug 23 05:50:30 PM UTC 24 Aug 23 05:50:32 PM UTC 24 14302355 ps
T1010 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_errors.2990281245 Aug 23 05:50:26 PM UTC 24 Aug 23 05:50:32 PM UTC 24 36135586 ps
T1011 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/6.edn_same_csr_outstanding.887835860 Aug 23 05:50:30 PM UTC 24 Aug 23 05:50:32 PM UTC 24 72743242 ps
T1012 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_bit_bash.448797615 Aug 23 05:50:26 PM UTC 24 Aug 23 05:50:33 PM UTC 24 93864331 ps
T1013 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_rw.3029785438 Aug 23 05:50:33 PM UTC 24 Aug 23 05:50:35 PM UTC 24 42873314 ps
T1014 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/9.edn_intr_test.727315958 Aug 23 05:50:33 PM UTC 24 Aug 23 05:50:35 PM UTC 24 14634777 ps
T1015 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1662012782 Aug 23 05:50:32 PM UTC 24 Aug 23 05:50:35 PM UTC 24 30382534 ps
T1016 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/9.edn_same_csr_outstanding.3234283284 Aug 23 05:50:33 PM UTC 24 Aug 23 05:50:35 PM UTC 24 19327461 ps
T1017 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3419080658 Aug 23 05:50:33 PM UTC 24 Aug 23 05:50:35 PM UTC 24 26225366 ps
T1018 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/8.edn_intr_test.1668466752 Aug 23 05:50:33 PM UTC 24 Aug 23 05:50:36 PM UTC 24 14312116 ps
T1019 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_errors.3889159345 Aug 23 05:50:33 PM UTC 24 Aug 23 05:50:36 PM UTC 24 46509659 ps
T1020 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/8.edn_same_csr_outstanding.54767613 Aug 23 05:50:33 PM UTC 24 Aug 23 05:50:36 PM UTC 24 61478508 ps
T1021 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_rw.3466645508 Aug 23 05:50:33 PM UTC 24 Aug 23 05:50:36 PM UTC 24 27331716 ps
T1022 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_intg_err.2446495611 Aug 23 05:50:33 PM UTC 24 Aug 23 05:50:36 PM UTC 24 385026196 ps
T1023 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_errors.1298816150 Aug 23 05:50:32 PM UTC 24 Aug 23 05:50:37 PM UTC 24 111134785 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_rw.1344965784 Aug 23 05:50:37 PM UTC 24 Aug 23 05:50:40 PM UTC 24 22244765 ps
T1024 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/11.edn_same_csr_outstanding.2598564426 Aug 23 05:50:38 PM UTC 24 Aug 23 05:50:41 PM UTC 24 81568952 ps
T1025 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_rw.3650329037 Aug 23 05:50:32 PM UTC 24 Aug 23 05:50:41 PM UTC 24 14752687 ps
T1026 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/7.edn_intr_test.3891339068 Aug 23 05:50:32 PM UTC 24 Aug 23 05:50:41 PM UTC 24 14064605 ps
T1027 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_errors.4093512693 Aug 23 05:50:35 PM UTC 24 Aug 23 05:50:41 PM UTC 24 186788185 ps
T1028 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/7.edn_same_csr_outstanding.3987961177 Aug 23 05:50:32 PM UTC 24 Aug 23 05:50:41 PM UTC 24 52790552 ps
T1029 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3547067991 Aug 23 05:50:32 PM UTC 24 Aug 23 05:50:41 PM UTC 24 56955412 ps
T1030 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_intg_err.1225601344 Aug 23 05:50:32 PM UTC 24 Aug 23 05:50:42 PM UTC 24 95167456 ps
T1031 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_intg_err.2726048378 Aug 23 05:50:32 PM UTC 24 Aug 23 05:50:42 PM UTC 24 536867115 ps
T1032 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_errors.1708893823 Aug 23 05:50:32 PM UTC 24 Aug 23 05:50:43 PM UTC 24 101384944 ps
T1033 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/10.edn_intr_test.1504099794 Aug 23 05:50:36 PM UTC 24 Aug 23 05:50:44 PM UTC 24 23970463 ps
T1034 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_rw.3141294694 Aug 23 05:50:36 PM UTC 24 Aug 23 05:50:44 PM UTC 24 20430750 ps
T1035 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2573559813 Aug 23 05:50:36 PM UTC 24 Aug 23 05:50:45 PM UTC 24 44760954 ps
T1036 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/10.edn_same_csr_outstanding.3580221262 Aug 23 05:50:36 PM UTC 24 Aug 23 05:50:45 PM UTC 24 144781217 ps
T1037 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/13.edn_intr_test.1277846142 Aug 23 05:50:43 PM UTC 24 Aug 23 05:50:45 PM UTC 24 19731589 ps
T1038 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/11.edn_intr_test.818511564 Aug 23 05:50:36 PM UTC 24 Aug 23 05:50:45 PM UTC 24 19582116 ps
T1039 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_errors.618197655 Aug 23 05:50:36 PM UTC 24 Aug 23 05:50:46 PM UTC 24 111965435 ps
T1040 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3583822382 Aug 23 05:50:41 PM UTC 24 Aug 23 05:50:46 PM UTC 24 104129672 ps
T1041 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_rw.1529738388 Aug 23 05:50:44 PM UTC 24 Aug 23 05:50:46 PM UTC 24 34523934 ps
T1042 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_intg_err.2698450355 Aug 23 05:50:36 PM UTC 24 Aug 23 05:50:46 PM UTC 24 183960599 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_rw.2089693407 Aug 23 05:50:42 PM UTC 24 Aug 23 05:50:50 PM UTC 24 40903907 ps
T1043 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2863243092 Aug 23 05:50:07 PM UTC 24 Aug 23 05:50:46 PM UTC 24 17836400 ps
T1044 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.227991961 Aug 23 05:50:34 PM UTC 24 Aug 23 05:50:46 PM UTC 24 45766246 ps
T1045 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_intg_err.1493605282 Aug 23 05:50:43 PM UTC 24 Aug 23 05:50:47 PM UTC 24 146048893 ps
T1046 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/12.edn_intr_test.2530606525 Aug 23 05:50:42 PM UTC 24 Aug 23 05:50:50 PM UTC 24 12091711 ps
T1047 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/12.edn_same_csr_outstanding.4167720065 Aug 23 05:50:42 PM UTC 24 Aug 23 05:50:50 PM UTC 24 15158467 ps
T1048 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/14.edn_intr_test.3998744174 Aug 23 05:50:45 PM UTC 24 Aug 23 05:50:50 PM UTC 24 25569862 ps
T1049 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/13.edn_same_csr_outstanding.36938486 Aug 23 05:50:45 PM UTC 24 Aug 23 05:50:50 PM UTC 24 105247560 ps
T1050 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_rw.3774524096 Aug 23 05:50:47 PM UTC 24 Aug 23 05:50:50 PM UTC 24 24951105 ps
T1051 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/15.edn_intr_test.2507231305 Aug 23 05:50:47 PM UTC 24 Aug 23 05:50:50 PM UTC 24 41753548 ps
T1052 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_intg_err.3927690153 Aug 23 05:50:42 PM UTC 24 Aug 23 05:50:50 PM UTC 24 45328858 ps
T1053 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2463202595 Aug 23 05:50:45 PM UTC 24 Aug 23 05:50:50 PM UTC 24 90564073 ps
T1054 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.138283889 Aug 23 05:50:42 PM UTC 24 Aug 23 05:50:50 PM UTC 24 27586788 ps
T1055 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/15.edn_same_csr_outstanding.2800101735 Aug 23 05:50:47 PM UTC 24 Aug 23 05:50:50 PM UTC 24 19243824 ps
T1056 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_errors.674567681 Aug 23 05:50:42 PM UTC 24 Aug 23 05:50:51 PM UTC 24 40612261 ps
T1057 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_rw.147237539 Aug 23 05:50:46 PM UTC 24 Aug 23 05:50:51 PM UTC 24 27959887 ps
T1058 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.97026966 Aug 23 05:50:48 PM UTC 24 Aug 23 05:50:51 PM UTC 24 52971175 ps
T1059 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/14.edn_same_csr_outstanding.3953203809 Aug 23 05:50:46 PM UTC 24 Aug 23 05:50:51 PM UTC 24 44384522 ps
T1060 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_intg_err.1504437935 Aug 23 05:50:47 PM UTC 24 Aug 23 05:50:52 PM UTC 24 102478407 ps
T1061 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_intg_err.1467230321 Aug 23 05:50:45 PM UTC 24 Aug 23 05:50:52 PM UTC 24 187403284 ps
T1062 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_errors.2985005159 Aug 23 05:50:45 PM UTC 24 Aug 23 05:50:53 PM UTC 24 129858048 ps
T1063 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3076109784 Aug 23 05:50:52 PM UTC 24 Aug 23 05:50:55 PM UTC 24 35515733 ps
T1064 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/18.edn_intr_test.717976004 Aug 23 05:50:52 PM UTC 24 Aug 23 05:50:55 PM UTC 24 34792959 ps
T1065 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/17.edn_same_csr_outstanding.668051946 Aug 23 05:50:52 PM UTC 24 Aug 23 05:50:55 PM UTC 24 44436406 ps
T1066 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_rw.3427763833 Aug 23 05:50:52 PM UTC 24 Aug 23 05:50:55 PM UTC 24 15310250 ps
T1067 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.130107014 Aug 23 05:50:53 PM UTC 24 Aug 23 05:50:55 PM UTC 24 31950993 ps
T1068 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/18.edn_same_csr_outstanding.1025398492 Aug 23 05:50:53 PM UTC 24 Aug 23 05:50:56 PM UTC 24 73899267 ps
T1069 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_intg_err.1247172090 Aug 23 05:50:52 PM UTC 24 Aug 23 05:50:56 PM UTC 24 175750829 ps
T1070 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_errors.3691613896 Aug 23 05:50:52 PM UTC 24 Aug 23 05:50:56 PM UTC 24 42734190 ps
T1071 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_errors.2290918249 Aug 23 05:50:46 PM UTC 24 Aug 23 05:50:56 PM UTC 24 400408423 ps
T1072 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_errors.854691315 Aug 23 05:50:51 PM UTC 24 Aug 23 05:50:57 PM UTC 24 340951415 ps
T1073 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/20.edn_intr_test.3676458582 Aug 23 05:50:57 PM UTC 24 Aug 23 05:51:00 PM UTC 24 70324840 ps
T1074 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/23.edn_intr_test.3284943498 Aug 23 05:50:57 PM UTC 24 Aug 23 05:51:00 PM UTC 24 31685903 ps
T1075 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/21.edn_intr_test.1052588667 Aug 23 05:50:57 PM UTC 24 Aug 23 05:51:00 PM UTC 24 20410478 ps
T1076 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/22.edn_intr_test.2503100924 Aug 23 05:50:57 PM UTC 24 Aug 23 05:51:00 PM UTC 24 37667144 ps
T1077 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/17.edn_intr_test.3522339389 Aug 23 05:50:52 PM UTC 24 Aug 23 05:51:01 PM UTC 24 25849569 ps
T1078 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_rw.366333938 Aug 23 05:50:52 PM UTC 24 Aug 23 05:51:01 PM UTC 24 86304345 ps
T1079 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_errors.2504178155 Aug 23 05:50:55 PM UTC 24 Aug 23 05:51:01 PM UTC 24 30869312 ps
T1080 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_rw.2351678277 Aug 23 05:50:56 PM UTC 24 Aug 23 05:51:01 PM UTC 24 22834022 ps
T1081 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/19.edn_intr_test.3166902028 Aug 23 05:50:56 PM UTC 24 Aug 23 05:51:01 PM UTC 24 26778758 ps
T1082 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_intg_err.2130388580 Aug 23 05:50:55 PM UTC 24 Aug 23 05:51:01 PM UTC 24 1525686068 ps
T1083 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.434626219 Aug 23 05:50:56 PM UTC 24 Aug 23 05:51:01 PM UTC 24 62603471 ps
T1084 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.189315115 Aug 23 05:50:46 PM UTC 24 Aug 23 05:51:01 PM UTC 24 35042758 ps
T1085 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/19.edn_same_csr_outstanding.1713641900 Aug 23 05:50:56 PM UTC 24 Aug 23 05:51:02 PM UTC 24 36922057 ps
T1086 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_intg_err.4200368112 Aug 23 05:50:52 PM UTC 24 Aug 23 05:51:02 PM UTC 24 386321973 ps
T1087 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/25.edn_intr_test.1474698975 Aug 23 05:51:01 PM UTC 24 Aug 23 05:51:02 PM UTC 24 14992286 ps
T1088 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/26.edn_intr_test.862785905 Aug 23 05:51:01 PM UTC 24 Aug 23 05:51:02 PM UTC 24 35417446 ps
T1089 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/24.edn_intr_test.2486291185 Aug 23 05:51:00 PM UTC 24 Aug 23 05:51:02 PM UTC 24 16467304 ps
T1090 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/27.edn_intr_test.1572562188 Aug 23 05:51:01 PM UTC 24 Aug 23 05:51:02 PM UTC 24 12450957 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_rw.3775334746 Aug 23 05:50:51 PM UTC 24 Aug 23 05:51:03 PM UTC 24 73479166 ps
T1091 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/16.edn_intr_test.2627500226 Aug 23 05:50:51 PM UTC 24 Aug 23 05:51:03 PM UTC 24 14349799 ps
T1092 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/16.edn_same_csr_outstanding.3942723686 Aug 23 05:50:51 PM UTC 24 Aug 23 05:51:03 PM UTC 24 46394586 ps
T1093 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2046465606 Aug 23 05:50:51 PM UTC 24 Aug 23 05:51:03 PM UTC 24 46880998 ps
T1094 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/28.edn_intr_test.1039843987 Aug 23 05:51:02 PM UTC 24 Aug 23 05:51:03 PM UTC 24 32139569 ps
T1095 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/29.edn_intr_test.1198798546 Aug 23 05:51:02 PM UTC 24 Aug 23 05:51:03 PM UTC 24 46587669 ps
T1096 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/31.edn_intr_test.875248515 Aug 23 05:51:02 PM UTC 24 Aug 23 05:51:04 PM UTC 24 41532823 ps
T1097 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/30.edn_intr_test.1877038297 Aug 23 05:51:02 PM UTC 24 Aug 23 05:51:04 PM UTC 24 15805500 ps
T1098 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/32.edn_intr_test.3356385583 Aug 23 05:51:02 PM UTC 24 Aug 23 05:51:04 PM UTC 24 57815771 ps
T1099 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/33.edn_intr_test.1183014616 Aug 23 05:51:02 PM UTC 24 Aug 23 05:51:04 PM UTC 24 13584919 ps
T1100 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_intg_err.4291793524 Aug 23 05:50:51 PM UTC 24 Aug 23 05:51:04 PM UTC 24 92329613 ps
T1101 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/34.edn_intr_test.1588824896 Aug 23 05:51:03 PM UTC 24 Aug 23 05:51:05 PM UTC 24 21184722 ps
T1102 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/36.edn_intr_test.385523916 Aug 23 05:51:03 PM UTC 24 Aug 23 05:51:05 PM UTC 24 45751611 ps
T1103 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/35.edn_intr_test.351133438 Aug 23 05:51:03 PM UTC 24 Aug 23 05:51:05 PM UTC 24 16931304 ps
T1104 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_errors.3530253976 Aug 23 05:50:51 PM UTC 24 Aug 23 05:51:05 PM UTC 24 87140441 ps
T1105 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/37.edn_intr_test.2194849285 Aug 23 05:51:03 PM UTC 24 Aug 23 05:51:05 PM UTC 24 46173563 ps
T1106 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/38.edn_intr_test.184289614 Aug 23 05:51:03 PM UTC 24 Aug 23 05:51:05 PM UTC 24 19919493 ps
T1107 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/40.edn_intr_test.2123038998 Aug 23 05:51:03 PM UTC 24 Aug 23 05:51:05 PM UTC 24 18905982 ps
T1108 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/39.edn_intr_test.1296692466 Aug 23 05:51:03 PM UTC 24 Aug 23 05:51:05 PM UTC 24 25667698 ps
T1109 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/41.edn_intr_test.2718727473 Aug 23 05:51:03 PM UTC 24 Aug 23 05:51:05 PM UTC 24 69823114 ps
T1110 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/42.edn_intr_test.303751384 Aug 23 05:51:04 PM UTC 24 Aug 23 05:51:06 PM UTC 24 32323091 ps
T1111 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/44.edn_intr_test.3429462071 Aug 23 05:51:04 PM UTC 24 Aug 23 05:51:06 PM UTC 24 20631705 ps
T1112 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/45.edn_intr_test.3304368496 Aug 23 05:51:04 PM UTC 24 Aug 23 05:51:06 PM UTC 24 15701661 ps
T1113 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/43.edn_intr_test.3362924480 Aug 23 05:51:04 PM UTC 24 Aug 23 05:51:06 PM UTC 24 14159765 ps
T1114 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/46.edn_intr_test.1758484992 Aug 23 05:51:04 PM UTC 24 Aug 23 05:51:06 PM UTC 24 24822471 ps
T1115 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/47.edn_intr_test.425001770 Aug 23 05:51:04 PM UTC 24 Aug 23 05:51:06 PM UTC 24 49860669 ps
T1116 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/48.edn_intr_test.625187652 Aug 23 05:51:04 PM UTC 24 Aug 23 05:51:06 PM UTC 24 13962792 ps
T1117 /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/49.edn_intr_test.239291429 Aug 23 05:51:04 PM UTC 24 Aug 23 05:51:06 PM UTC 24 25777601 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/0.edn_disable_auto_req_mode.2612015006
Short name T10
Test name
Test status
Simulation time 43222431 ps
CPU time 0.87 seconds
Started Aug 23 05:45:56 PM UTC 24
Finished Aug 23 05:45:58 PM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612015006 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable_auto_req_mode.2612015006
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/0.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/2.edn_genbits.2525113315
Short name T41
Test name
Test status
Simulation time 80470925 ps
CPU time 1.33 seconds
Started Aug 23 05:46:06 PM UTC 24
Finished Aug 23 05:46:09 PM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525113315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_genbits.2525113315
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/2.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/0.edn_sec_cm.3928281181
Short name T16
Test name
Test status
Simulation time 933807680 ps
CPU time 6.25 seconds
Started Aug 23 05:45:56 PM UTC 24
Finished Aug 23 05:46:04 PM UTC 24
Peak memory 262352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928281181 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.3928281181
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/0.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/0.edn_stress_all.2579653857
Short name T4
Test name
Test status
Simulation time 449551622 ps
CPU time 2.32 seconds
Started Aug 23 05:45:53 PM UTC 24
Finished Aug 23 05:45:57 PM UTC 24
Peak memory 229504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579653857 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2579653857
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/0.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/4.edn_alert.939525397
Short name T47
Test name
Test status
Simulation time 178066962 ps
CPU time 1.05 seconds
Started Aug 23 05:46:10 PM UTC 24
Finished Aug 23 05:46:12 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939525397 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 4.edn_alert.939525397
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/4.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/1.edn_stress_all_with_rand_reset.216233089
Short name T236
Test name
Test status
Simulation time 4781365261 ps
CPU time 68.47 seconds
Started Aug 23 05:46:06 PM UTC 24
Finished Aug 23 05:47:16 PM UTC 24
Peak memory 229728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=216233089 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_w
ith_rand_reset.216233089
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/1.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/1.edn_sec_cm.2572494440
Short name T20
Test name
Test status
Simulation time 1015241883 ps
CPU time 3.76 seconds
Started Aug 23 05:46:06 PM UTC 24
Finished Aug 23 05:46:11 PM UTC 24
Peak memory 260484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572494440 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.2572494440
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/1.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/3.edn_alert.3650486452
Short name T87
Test name
Test status
Simulation time 348510785 ps
CPU time 1.09 seconds
Started Aug 23 05:46:08 PM UTC 24
Finished Aug 23 05:46:10 PM UTC 24
Peak memory 232304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650486452 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 3.edn_alert.3650486452
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/3.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/7.edn_stress_all.3759399208
Short name T64
Test name
Test status
Simulation time 60546244 ps
CPU time 1.45 seconds
Started Aug 23 05:46:15 PM UTC 24
Finished Aug 23 05:46:18 PM UTC 24
Peak memory 226336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759399208 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.3759399208
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/7.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/5.edn_genbits.1143406742
Short name T13
Test name
Test status
Simulation time 51528835 ps
CPU time 1.41 seconds
Started Aug 23 05:46:12 PM UTC 24
Finished Aug 23 05:46:15 PM UTC 24
Peak memory 226296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143406742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1143406742
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/5.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/11.edn_alert.1974746349
Short name T55
Test name
Test status
Simulation time 33219215 ps
CPU time 1.14 seconds
Started Aug 23 05:46:25 PM UTC 24
Finished Aug 23 05:46:27 PM UTC 24
Peak memory 229876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974746349 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 11.edn_alert.1974746349
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/11.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/4.edn_stress_all.765553536
Short name T112
Test name
Test status
Simulation time 231285340 ps
CPU time 4.37 seconds
Started Aug 23 05:46:10 PM UTC 24
Finished Aug 23 05:46:15 PM UTC 24
Peak memory 227304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765553536 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.765553536
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/4.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/5.edn_disable.2262217012
Short name T83
Test name
Test status
Simulation time 15379302 ps
CPU time 0.73 seconds
Started Aug 23 05:46:12 PM UTC 24
Finished Aug 23 05:46:14 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262217012 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.2262217012
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/5.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/2.edn_disable_auto_req_mode.2509676863
Short name T12
Test name
Test status
Simulation time 117756446 ps
CPU time 0.88 seconds
Started Aug 23 05:46:06 PM UTC 24
Finished Aug 23 05:46:08 PM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509676863 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable_auto_req_mode.2509676863
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/2.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_intg_err.112355309
Short name T317
Test name
Test status
Simulation time 76305240 ps
CPU time 1.88 seconds
Started Aug 23 05:50:28 PM UTC 24
Finished Aug 23 05:50:31 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112355309 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.112355309
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/6.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/40.edn_alert.1161279019
Short name T231
Test name
Test status
Simulation time 38947069 ps
CPU time 1.01 seconds
Started Aug 23 05:47:51 PM UTC 24
Finished Aug 23 05:47:53 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161279019 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 40.edn_alert.1161279019
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/40.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_rw.3573885825
Short name T284
Test name
Test status
Simulation time 13033689 ps
CPU time 0.76 seconds
Started Aug 23 05:50:07 PM UTC 24
Finished Aug 23 05:50:26 PM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573885825 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3573885825
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/0.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/10.edn_stress_all.2951436068
Short name T117
Test name
Test status
Simulation time 332427881 ps
CPU time 5.79 seconds
Started Aug 23 05:46:20 PM UTC 24
Finished Aug 23 05:46:27 PM UTC 24
Peak memory 227580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951436068 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.2951436068
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/10.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/1.edn_disable_auto_req_mode.1306264420
Short name T11
Test name
Test status
Simulation time 58908416 ps
CPU time 1.09 seconds
Started Aug 23 05:46:06 PM UTC 24
Finished Aug 23 05:46:08 PM UTC 24
Peak memory 225460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306264420 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable_auto_req_mode.1306264420
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/1.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/11.edn_disable.1123540840
Short name T85
Test name
Test status
Simulation time 18852886 ps
CPU time 0.71 seconds
Started Aug 23 05:46:25 PM UTC 24
Finished Aug 23 05:46:26 PM UTC 24
Peak memory 226284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123540840 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.1123540840
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/11.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/18.edn_alert.1507074942
Short name T213
Test name
Test status
Simulation time 61642460 ps
CPU time 0.96 seconds
Started Aug 23 05:46:42 PM UTC 24
Finished Aug 23 05:46:44 PM UTC 24
Peak memory 230328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507074942 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 18.edn_alert.1507074942
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/18.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/5.edn_intr.527830122
Short name T33
Test name
Test status
Simulation time 21394721 ps
CPU time 0.9 seconds
Started Aug 23 05:46:12 PM UTC 24
Finished Aug 23 05:46:14 PM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527830122 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 5.edn_intr.527830122
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/5.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/40.edn_genbits.1982347052
Short name T517
Test name
Test status
Simulation time 103409433 ps
CPU time 1.25 seconds
Started Aug 23 05:47:50 PM UTC 24
Finished Aug 23 05:47:53 PM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982347052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1982347052
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/40.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/173.edn_alert.4004136887
Short name T842
Test name
Test status
Simulation time 69823335 ps
CPU time 1.1 seconds
Started Aug 23 05:49:38 PM UTC 24
Finished Aug 23 05:49:40 PM UTC 24
Peak memory 228140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004136887 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 173.edn_alert.4004136887
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/173.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/117.edn_alert.3042646354
Short name T275
Test name
Test status
Simulation time 43549393 ps
CPU time 1.03 seconds
Started Aug 23 05:49:17 PM UTC 24
Finished Aug 23 05:49:19 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042646354 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 117.edn_alert.3042646354
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/117.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/46.edn_alert.3239150687
Short name T194
Test name
Test status
Simulation time 66062614 ps
CPU time 0.9 seconds
Started Aug 23 05:48:12 PM UTC 24
Finished Aug 23 05:48:15 PM UTC 24
Peak memory 230164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239150687 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 46.edn_alert.3239150687
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/46.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/1.edn_disable.1759677103
Short name T42
Test name
Test status
Simulation time 13461745 ps
CPU time 0.79 seconds
Started Aug 23 05:46:06 PM UTC 24
Finished Aug 23 05:46:08 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759677103 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1759677103
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/1.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/22.edn_err.608540042
Short name T188
Test name
Test status
Simulation time 88375039 ps
CPU time 0.91 seconds
Started Aug 23 05:46:53 PM UTC 24
Finished Aug 23 05:46:56 PM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608540042 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 22.edn_err.608540042
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/22.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/42.edn_alert.557555106
Short name T536
Test name
Test status
Simulation time 24197433 ps
CPU time 0.98 seconds
Started Aug 23 05:47:58 PM UTC 24
Finished Aug 23 05:48:00 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557555106 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 42.edn_alert.557555106
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/42.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/0.edn_alert_test.3939621665
Short name T26
Test name
Test status
Simulation time 60460747 ps
CPU time 0.76 seconds
Started Aug 23 05:45:56 PM UTC 24
Finished Aug 23 05:45:58 PM UTC 24
Peak memory 216752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939621665 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3939621665
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/0.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/95.edn_genbits.10785542
Short name T336
Test name
Test status
Simulation time 29414824 ps
CPU time 1.14 seconds
Started Aug 23 05:49:06 PM UTC 24
Finished Aug 23 05:49:08 PM UTC 24
Peak memory 226296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10785542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 95.edn_genbits.10785542
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/95.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/115.edn_alert.3763347833
Short name T729
Test name
Test status
Simulation time 96676841 ps
CPU time 1.02 seconds
Started Aug 23 05:49:16 PM UTC 24
Finished Aug 23 05:49:18 PM UTC 24
Peak memory 226356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763347833 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 115.edn_alert.3763347833
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/115.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/199.edn_alert.903916963
Short name T886
Test name
Test status
Simulation time 43272022 ps
CPU time 0.98 seconds
Started Aug 23 05:49:46 PM UTC 24
Finished Aug 23 05:49:48 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903916963 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 199.edn_alert.903916963
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/199.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/13.edn_intr.588091864
Short name T108
Test name
Test status
Simulation time 23366360 ps
CPU time 0.8 seconds
Started Aug 23 05:46:29 PM UTC 24
Finished Aug 23 05:46:32 PM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588091864 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 13.edn_intr.588091864
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/13.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/0.edn_disable.48067034
Short name T25
Test name
Test status
Simulation time 11418033 ps
CPU time 0.77 seconds
Started Aug 23 05:45:56 PM UTC 24
Finished Aug 23 05:45:58 PM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48067034 -assert nopostproc +UVM_TESTNAME=edn_disab
le_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.48067034
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/0.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/10.edn_disable.2240810798
Short name T89
Test name
Test status
Simulation time 12135155 ps
CPU time 0.75 seconds
Started Aug 23 05:46:22 PM UTC 24
Finished Aug 23 05:46:25 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240810798 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2240810798
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/10.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/110.edn_alert.182013678
Short name T724
Test name
Test status
Simulation time 48032460 ps
CPU time 1.06 seconds
Started Aug 23 05:49:15 PM UTC 24
Finished Aug 23 05:49:17 PM UTC 24
Peak memory 230484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182013678 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 110.edn_alert.182013678
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/110.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/113.edn_alert.3974939218
Short name T207
Test name
Test status
Simulation time 25244549 ps
CPU time 1.03 seconds
Started Aug 23 05:49:16 PM UTC 24
Finished Aug 23 05:49:18 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974939218 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 113.edn_alert.3974939218
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/113.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/124.edn_alert.3179536683
Short name T747
Test name
Test status
Simulation time 27755246 ps
CPU time 1.05 seconds
Started Aug 23 05:49:19 PM UTC 24
Finished Aug 23 05:49:22 PM UTC 24
Peak memory 226228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179536683 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 124.edn_alert.3179536683
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/124.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/126.edn_alert.1340401752
Short name T750
Test name
Test status
Simulation time 37765165 ps
CPU time 0.91 seconds
Started Aug 23 05:49:21 PM UTC 24
Finished Aug 23 05:49:23 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340401752 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 126.edn_alert.1340401752
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/126.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/13.edn_disable_auto_req_mode.2420834943
Short name T102
Test name
Test status
Simulation time 50030113 ps
CPU time 0.9 seconds
Started Aug 23 05:46:29 PM UTC 24
Finished Aug 23 05:46:32 PM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420834943 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable_auto_req_mode.2420834943
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/13.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/141.edn_alert.4255512435
Short name T784
Test name
Test status
Simulation time 51469565 ps
CPU time 1.06 seconds
Started Aug 23 05:49:26 PM UTC 24
Finished Aug 23 05:49:29 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255512435 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 141.edn_alert.4255512435
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/141.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/15.edn_disable.3409177335
Short name T92
Test name
Test status
Simulation time 23908915 ps
CPU time 0.76 seconds
Started Aug 23 05:46:34 PM UTC 24
Finished Aug 23 05:46:36 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409177335 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3409177335
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/15.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/15.edn_disable_auto_req_mode.2971120379
Short name T176
Test name
Test status
Simulation time 421924562 ps
CPU time 1.02 seconds
Started Aug 23 05:46:34 PM UTC 24
Finished Aug 23 05:46:36 PM UTC 24
Peak memory 225748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971120379 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable_auto_req_mode.2971120379
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/15.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/16.edn_disable_auto_req_mode.797752948
Short name T148
Test name
Test status
Simulation time 100371454 ps
CPU time 0.95 seconds
Started Aug 23 05:46:38 PM UTC 24
Finished Aug 23 05:46:41 PM UTC 24
Peak memory 225616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797752948 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable_auto_req_mode.797752948
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/16.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/19.edn_disable.2804581547
Short name T208
Test name
Test status
Simulation time 22476135 ps
CPU time 0.72 seconds
Started Aug 23 05:46:45 PM UTC 24
Finished Aug 23 05:46:47 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804581547 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2804581547
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/19.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/2.edn_disable.1914183413
Short name T45
Test name
Test status
Simulation time 39170762 ps
CPU time 0.75 seconds
Started Aug 23 05:46:06 PM UTC 24
Finished Aug 23 05:46:08 PM UTC 24
Peak memory 225396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914183413 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1914183413
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/2.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/25.edn_err.2711696770
Short name T214
Test name
Test status
Simulation time 19872988 ps
CPU time 0.88 seconds
Started Aug 23 05:47:02 PM UTC 24
Finished Aug 23 05:47:04 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711696770 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 25.edn_err.2711696770
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/25.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/65.edn_err.1455762520
Short name T211
Test name
Test status
Simulation time 26439819 ps
CPU time 0.79 seconds
Started Aug 23 05:48:44 PM UTC 24
Finished Aug 23 05:48:46 PM UTC 24
Peak memory 228340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455762520 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 65.edn_err.1455762520
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/65.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/92.edn_err.2220643910
Short name T204
Test name
Test status
Simulation time 32303044 ps
CPU time 0.86 seconds
Started Aug 23 05:49:05 PM UTC 24
Finished Aug 23 05:49:07 PM UTC 24
Peak memory 236816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220643910 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 92.edn_err.2220643910
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/92.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/0.edn_err.4179686406
Short name T6
Test name
Test status
Simulation time 33355373 ps
CPU time 1.04 seconds
Started Aug 23 05:45:56 PM UTC 24
Finished Aug 23 05:45:58 PM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179686406 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 0.edn_err.4179686406
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/0.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/109.edn_genbits.3097915462
Short name T340
Test name
Test status
Simulation time 52744875 ps
CPU time 1.05 seconds
Started Aug 23 05:49:13 PM UTC 24
Finished Aug 23 05:49:16 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097915462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3097915462
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/109.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/113.edn_genbits.27148827
Short name T334
Test name
Test status
Simulation time 122783095 ps
CPU time 1.09 seconds
Started Aug 23 05:49:15 PM UTC 24
Finished Aug 23 05:49:17 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27148827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 113.edn_genbits.27148827
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/113.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/18.edn_stress_all.641159658
Short name T125
Test name
Test status
Simulation time 180273822 ps
CPU time 3.19 seconds
Started Aug 23 05:46:42 PM UTC 24
Finished Aug 23 05:46:46 PM UTC 24
Peak memory 229420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641159658 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.641159658
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/18.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/33.edn_genbits.2383751682
Short name T328
Test name
Test status
Simulation time 345031528 ps
CPU time 2.84 seconds
Started Aug 23 05:47:29 PM UTC 24
Finished Aug 23 05:47:33 PM UTC 24
Peak memory 231568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383751682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2383751682
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/33.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/9.edn_stress_all.277384612
Short name T121
Test name
Test status
Simulation time 453606756 ps
CPU time 3.71 seconds
Started Aug 23 05:46:20 PM UTC 24
Finished Aug 23 05:46:25 PM UTC 24
Peak memory 229580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277384612 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.277384612
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/9.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/15.edn_genbits.296940709
Short name T51
Test name
Test status
Simulation time 59444513 ps
CPU time 1.6 seconds
Started Aug 23 05:46:34 PM UTC 24
Finished Aug 23 05:46:37 PM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296940709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.edn_genbits.296940709
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/15.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/116.edn_genbits.115930524
Short name T345
Test name
Test status
Simulation time 116427714 ps
CPU time 1.25 seconds
Started Aug 23 05:49:17 PM UTC 24
Finished Aug 23 05:49:19 PM UTC 24
Peak memory 230396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115930524 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 116.edn_genbits.115930524
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/116.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/17.edn_intr.2089103959
Short name T109
Test name
Test status
Simulation time 20179374 ps
CPU time 0.96 seconds
Started Aug 23 05:46:40 PM UTC 24
Finished Aug 23 05:46:42 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089103959 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 17.edn_intr.2089103959
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/17.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/1.edn_stress_all.2381346977
Short name T110
Test name
Test status
Simulation time 472066880 ps
CPU time 5.42 seconds
Started Aug 23 05:46:06 PM UTC 24
Finished Aug 23 05:46:12 PM UTC 24
Peak memory 231772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381346977 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2381346977
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/1.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/159.edn_genbits.888601215
Short name T332
Test name
Test status
Simulation time 94242902 ps
CPU time 1.23 seconds
Started Aug 23 05:49:32 PM UTC 24
Finished Aug 23 05:49:34 PM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888601215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 159.edn_genbits.888601215
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/159.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/16.edn_genbits.3402905870
Short name T80
Test name
Test status
Simulation time 89963789 ps
CPU time 1.15 seconds
Started Aug 23 05:46:36 PM UTC 24
Finished Aug 23 05:46:39 PM UTC 24
Peak memory 227964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402905870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_genbits.3402905870
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/16.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/203.edn_genbits.4267934385
Short name T343
Test name
Test status
Simulation time 26479108 ps
CPU time 1.12 seconds
Started Aug 23 05:49:47 PM UTC 24
Finished Aug 23 05:49:50 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267934385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 203.edn_genbits.4267934385
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/203.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/23.edn_genbits.4038924669
Short name T325
Test name
Test status
Simulation time 50832436 ps
CPU time 1.18 seconds
Started Aug 23 05:46:54 PM UTC 24
Finished Aug 23 05:46:57 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038924669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_genbits.4038924669
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/23.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/31.edn_genbits.1470640620
Short name T312
Test name
Test status
Simulation time 34030918 ps
CPU time 1.32 seconds
Started Aug 23 05:47:22 PM UTC 24
Finished Aug 23 05:47:24 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470640620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_genbits.1470640620
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/31.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/21.edn_intr.527157759
Short name T106
Test name
Test status
Simulation time 24993083 ps
CPU time 0.77 seconds
Started Aug 23 05:46:50 PM UTC 24
Finished Aug 23 05:46:52 PM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527157759 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 21.edn_intr.527157759
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/21.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/145.edn_alert.85490527
Short name T137
Test name
Test status
Simulation time 126513762 ps
CPU time 1.12 seconds
Started Aug 23 05:49:28 PM UTC 24
Finished Aug 23 05:49:30 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85490527 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 145.edn_alert.85490527
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/145.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/16.edn_disable.3666353916
Short name T184
Test name
Test status
Simulation time 19084422 ps
CPU time 0.73 seconds
Started Aug 23 05:46:37 PM UTC 24
Finished Aug 23 05:46:39 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666353916 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.3666353916
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/16.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/10.edn_err.448297594
Short name T130
Test name
Test status
Simulation time 31040252 ps
CPU time 0.96 seconds
Started Aug 23 05:46:22 PM UTC 24
Finished Aug 23 05:46:25 PM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448297594 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 10.edn_err.448297594
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/10.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/146.edn_genbits.901647241
Short name T794
Test name
Test status
Simulation time 54226793 ps
CPU time 1.35 seconds
Started Aug 23 05:49:28 PM UTC 24
Finished Aug 23 05:49:30 PM UTC 24
Peak memory 230612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901647241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 146.edn_genbits.901647241
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/146.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_aliasing.915938082
Short name T279
Test name
Test status
Simulation time 298290832 ps
CPU time 1.15 seconds
Started Aug 23 05:50:07 PM UTC 24
Finished Aug 23 05:50:15 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915938082 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.915938082
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/0.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_bit_bash.1225509637
Short name T995
Test name
Test status
Simulation time 200959855 ps
CPU time 2.64 seconds
Started Aug 23 05:50:07 PM UTC 24
Finished Aug 23 05:50:27 PM UTC 24
Peak memory 217428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225509637 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1225509637
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/0.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_hw_reset.3700802854
Short name T983
Test name
Test status
Simulation time 16025504 ps
CPU time 0.73 seconds
Started Aug 23 05:50:06 PM UTC 24
Finished Aug 23 05:50:11 PM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700802854 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.3700802854
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/0.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2863243092
Short name T1043
Test name
Test status
Simulation time 17836400 ps
CPU time 0.93 seconds
Started Aug 23 05:50:07 PM UTC 24
Finished Aug 23 05:50:46 PM UTC 24
Peak memory 225640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2863243092 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2863243092
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/0.edn_intr_test.1637865725
Short name T984
Test name
Test status
Simulation time 23929417 ps
CPU time 0.72 seconds
Started Aug 23 05:50:06 PM UTC 24
Finished Aug 23 05:50:11 PM UTC 24
Peak memory 215448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637865725 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1637865725
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/0.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/0.edn_same_csr_outstanding.3300239526
Short name T292
Test name
Test status
Simulation time 30435178 ps
CPU time 1.15 seconds
Started Aug 23 05:50:07 PM UTC 24
Finished Aug 23 05:50:25 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300239526 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_outstanding.3300239526
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/0.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/0.edn_tl_errors.3799561116
Short name T985
Test name
Test status
Simulation time 48120275 ps
CPU time 1.82 seconds
Started Aug 23 05:50:06 PM UTC 24
Finished Aug 23 05:50:12 PM UTC 24
Peak memory 225688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799561116 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3799561116
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/0.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/0.edn_tl_intg_err.2066561283
Short name T263
Test name
Test status
Simulation time 264877136 ps
CPU time 1.98 seconds
Started Aug 23 05:50:06 PM UTC 24
Finished Aug 23 05:50:12 PM UTC 24
Peak memory 225696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066561283 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.2066561283
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/0.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_aliasing.2620817530
Short name T278
Test name
Test status
Simulation time 79248912 ps
CPU time 0.96 seconds
Started Aug 23 05:50:12 PM UTC 24
Finished Aug 23 05:50:15 PM UTC 24
Peak memory 215348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620817530 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2620817530
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/1.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_bit_bash.2729581043
Short name T988
Test name
Test status
Simulation time 38639722 ps
CPU time 1.67 seconds
Started Aug 23 05:50:12 PM UTC 24
Finished Aug 23 05:50:16 PM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729581043 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2729581043
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/1.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_hw_reset.3334139871
Short name T982
Test name
Test status
Simulation time 45878304 ps
CPU time 0.72 seconds
Started Aug 23 05:50:07 PM UTC 24
Finished Aug 23 05:50:10 PM UTC 24
Peak memory 216972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334139871 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3334139871
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/1.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2200485379
Short name T987
Test name
Test status
Simulation time 28939177 ps
CPU time 1.67 seconds
Started Aug 23 05:50:12 PM UTC 24
Finished Aug 23 05:50:16 PM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2200485379 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2200485379
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_rw.2741555190
Short name T280
Test name
Test status
Simulation time 12887073 ps
CPU time 0.76 seconds
Started Aug 23 05:50:11 PM UTC 24
Finished Aug 23 05:50:20 PM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741555190 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2741555190
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/1.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/1.edn_intr_test.1033924598
Short name T994
Test name
Test status
Simulation time 15130977 ps
CPU time 0.74 seconds
Started Aug 23 05:50:07 PM UTC 24
Finished Aug 23 05:50:26 PM UTC 24
Peak memory 215388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033924598 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.1033924598
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/1.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/1.edn_same_csr_outstanding.321668726
Short name T251
Test name
Test status
Simulation time 151377171 ps
CPU time 1.16 seconds
Started Aug 23 05:50:12 PM UTC 24
Finished Aug 23 05:50:15 PM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321668726 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_outstanding.321668726
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/1.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/1.edn_tl_errors.878739242
Short name T993
Test name
Test status
Simulation time 234664620 ps
CPU time 1.62 seconds
Started Aug 23 05:50:07 PM UTC 24
Finished Aug 23 05:50:26 PM UTC 24
Peak memory 225632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878739242 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.878739242
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/1.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/1.edn_tl_intg_err.2733463411
Short name T315
Test name
Test status
Simulation time 95554605 ps
CPU time 1.85 seconds
Started Aug 23 05:50:07 PM UTC 24
Finished Aug 23 05:50:27 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733463411 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2733463411
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/1.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2573559813
Short name T1035
Test name
Test status
Simulation time 44760954 ps
CPU time 0.99 seconds
Started Aug 23 05:50:36 PM UTC 24
Finished Aug 23 05:50:45 PM UTC 24
Peak memory 225704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2573559813 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2573559813
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_rw.3141294694
Short name T1034
Test name
Test status
Simulation time 20430750 ps
CPU time 0.69 seconds
Started Aug 23 05:50:36 PM UTC 24
Finished Aug 23 05:50:44 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141294694 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3141294694
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/10.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/10.edn_intr_test.1504099794
Short name T1033
Test name
Test status
Simulation time 23970463 ps
CPU time 0.69 seconds
Started Aug 23 05:50:36 PM UTC 24
Finished Aug 23 05:50:44 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504099794 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1504099794
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/10.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/10.edn_same_csr_outstanding.3580221262
Short name T1036
Test name
Test status
Simulation time 144781217 ps
CPU time 0.99 seconds
Started Aug 23 05:50:36 PM UTC 24
Finished Aug 23 05:50:45 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580221262 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_outstanding.3580221262
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/10.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_errors.4093512693
Short name T1027
Test name
Test status
Simulation time 186788185 ps
CPU time 1.57 seconds
Started Aug 23 05:50:35 PM UTC 24
Finished Aug 23 05:50:41 PM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093512693 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.4093512693
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/10.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_intg_err.3887498387
Short name T318
Test name
Test status
Simulation time 586291009 ps
CPU time 2.71 seconds
Started Aug 23 05:50:35 PM UTC 24
Finished Aug 23 05:50:42 PM UTC 24
Peak memory 217432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887498387 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3887498387
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/10.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3583822382
Short name T1040
Test name
Test status
Simulation time 104129672 ps
CPU time 0.88 seconds
Started Aug 23 05:50:41 PM UTC 24
Finished Aug 23 05:50:46 PM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3583822382 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3583822382
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_rw.1344965784
Short name T287
Test name
Test status
Simulation time 22244765 ps
CPU time 0.71 seconds
Started Aug 23 05:50:37 PM UTC 24
Finished Aug 23 05:50:40 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344965784 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1344965784
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/11.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/11.edn_intr_test.818511564
Short name T1038
Test name
Test status
Simulation time 19582116 ps
CPU time 0.77 seconds
Started Aug 23 05:50:36 PM UTC 24
Finished Aug 23 05:50:45 PM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818511564 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.818511564
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/11.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/11.edn_same_csr_outstanding.2598564426
Short name T1024
Test name
Test status
Simulation time 81568952 ps
CPU time 0.93 seconds
Started Aug 23 05:50:38 PM UTC 24
Finished Aug 23 05:50:41 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598564426 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_outstanding.2598564426
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/11.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_errors.618197655
Short name T1039
Test name
Test status
Simulation time 111965435 ps
CPU time 1.89 seconds
Started Aug 23 05:50:36 PM UTC 24
Finished Aug 23 05:50:46 PM UTC 24
Peak memory 225692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618197655 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.618197655
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/11.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_intg_err.2698450355
Short name T1042
Test name
Test status
Simulation time 183960599 ps
CPU time 1.39 seconds
Started Aug 23 05:50:36 PM UTC 24
Finished Aug 23 05:50:46 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698450355 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2698450355
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/11.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.138283889
Short name T1054
Test name
Test status
Simulation time 27586788 ps
CPU time 1.23 seconds
Started Aug 23 05:50:42 PM UTC 24
Finished Aug 23 05:50:50 PM UTC 24
Peak memory 225696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=138283889 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.138283889
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_rw.2089693407
Short name T288
Test name
Test status
Simulation time 40903907 ps
CPU time 0.73 seconds
Started Aug 23 05:50:42 PM UTC 24
Finished Aug 23 05:50:50 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089693407 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2089693407
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/12.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/12.edn_intr_test.2530606525
Short name T1046
Test name
Test status
Simulation time 12091711 ps
CPU time 0.7 seconds
Started Aug 23 05:50:42 PM UTC 24
Finished Aug 23 05:50:50 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530606525 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2530606525
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/12.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/12.edn_same_csr_outstanding.4167720065
Short name T1047
Test name
Test status
Simulation time 15158467 ps
CPU time 0.89 seconds
Started Aug 23 05:50:42 PM UTC 24
Finished Aug 23 05:50:50 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167720065 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_outstanding.4167720065
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/12.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_errors.674567681
Short name T1056
Test name
Test status
Simulation time 40612261 ps
CPU time 1.71 seconds
Started Aug 23 05:50:42 PM UTC 24
Finished Aug 23 05:50:51 PM UTC 24
Peak memory 225632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674567681 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.674567681
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/12.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_intg_err.3927690153
Short name T1052
Test name
Test status
Simulation time 45328858 ps
CPU time 1.32 seconds
Started Aug 23 05:50:42 PM UTC 24
Finished Aug 23 05:50:50 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927690153 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3927690153
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/12.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2463202595
Short name T1053
Test name
Test status
Simulation time 90564073 ps
CPU time 1.01 seconds
Started Aug 23 05:50:45 PM UTC 24
Finished Aug 23 05:50:50 PM UTC 24
Peak memory 229800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2463202595 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2463202595
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_rw.1529738388
Short name T1041
Test name
Test status
Simulation time 34523934 ps
CPU time 0.76 seconds
Started Aug 23 05:50:44 PM UTC 24
Finished Aug 23 05:50:46 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529738388 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1529738388
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/13.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/13.edn_intr_test.1277846142
Short name T1037
Test name
Test status
Simulation time 19731589 ps
CPU time 0.66 seconds
Started Aug 23 05:50:43 PM UTC 24
Finished Aug 23 05:50:45 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277846142 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1277846142
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/13.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/13.edn_same_csr_outstanding.36938486
Short name T1049
Test name
Test status
Simulation time 105247560 ps
CPU time 0.98 seconds
Started Aug 23 05:50:45 PM UTC 24
Finished Aug 23 05:50:50 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36938486 -assert nopostproc +UVM_T
ESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_outstanding.36938486
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/13.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_errors.3888335087
Short name T1002
Test name
Test status
Simulation time 197565108 ps
CPU time 3.04 seconds
Started Aug 23 05:50:43 PM UTC 24
Finished Aug 23 05:50:48 PM UTC 24
Peak memory 227728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888335087 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.3888335087
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/13.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_intg_err.1493605282
Short name T1045
Test name
Test status
Simulation time 146048893 ps
CPU time 1.87 seconds
Started Aug 23 05:50:43 PM UTC 24
Finished Aug 23 05:50:47 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493605282 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1493605282
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/13.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.189315115
Short name T1084
Test name
Test status
Simulation time 35042758 ps
CPU time 1.03 seconds
Started Aug 23 05:50:46 PM UTC 24
Finished Aug 23 05:51:01 PM UTC 24
Peak memory 227744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=189315115 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.189315115
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_rw.147237539
Short name T1057
Test name
Test status
Simulation time 27959887 ps
CPU time 0.66 seconds
Started Aug 23 05:50:46 PM UTC 24
Finished Aug 23 05:50:51 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147237539 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.147237539
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/14.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/14.edn_intr_test.3998744174
Short name T1048
Test name
Test status
Simulation time 25569862 ps
CPU time 0.7 seconds
Started Aug 23 05:50:45 PM UTC 24
Finished Aug 23 05:50:50 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998744174 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.3998744174
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/14.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/14.edn_same_csr_outstanding.3953203809
Short name T1059
Test name
Test status
Simulation time 44384522 ps
CPU time 0.91 seconds
Started Aug 23 05:50:46 PM UTC 24
Finished Aug 23 05:50:51 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953203809 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_outstanding.3953203809
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/14.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_errors.2985005159
Short name T1062
Test name
Test status
Simulation time 129858048 ps
CPU time 3.47 seconds
Started Aug 23 05:50:45 PM UTC 24
Finished Aug 23 05:50:53 PM UTC 24
Peak memory 227792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985005159 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2985005159
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/14.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_intg_err.1467230321
Short name T1061
Test name
Test status
Simulation time 187403284 ps
CPU time 3.18 seconds
Started Aug 23 05:50:45 PM UTC 24
Finished Aug 23 05:50:52 PM UTC 24
Peak memory 217432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467230321 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1467230321
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/14.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.97026966
Short name T1058
Test name
Test status
Simulation time 52971175 ps
CPU time 1.45 seconds
Started Aug 23 05:50:48 PM UTC 24
Finished Aug 23 05:50:51 PM UTC 24
Peak memory 225700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=97026966 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.97026966
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_rw.3774524096
Short name T1050
Test name
Test status
Simulation time 24951105 ps
CPU time 0.68 seconds
Started Aug 23 05:50:47 PM UTC 24
Finished Aug 23 05:50:50 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774524096 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.3774524096
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/15.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/15.edn_intr_test.2507231305
Short name T1051
Test name
Test status
Simulation time 41753548 ps
CPU time 0.67 seconds
Started Aug 23 05:50:47 PM UTC 24
Finished Aug 23 05:50:50 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507231305 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.2507231305
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/15.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/15.edn_same_csr_outstanding.2800101735
Short name T1055
Test name
Test status
Simulation time 19243824 ps
CPU time 0.91 seconds
Started Aug 23 05:50:47 PM UTC 24
Finished Aug 23 05:50:50 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800101735 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_outstanding.2800101735
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/15.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_errors.2290918249
Short name T1071
Test name
Test status
Simulation time 400408423 ps
CPU time 2.94 seconds
Started Aug 23 05:50:46 PM UTC 24
Finished Aug 23 05:50:56 PM UTC 24
Peak memory 227800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290918249 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2290918249
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/15.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_intg_err.1504437935
Short name T1060
Test name
Test status
Simulation time 102478407 ps
CPU time 2.05 seconds
Started Aug 23 05:50:47 PM UTC 24
Finished Aug 23 05:50:52 PM UTC 24
Peak memory 217496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504437935 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1504437935
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/15.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2046465606
Short name T1093
Test name
Test status
Simulation time 46880998 ps
CPU time 1.08 seconds
Started Aug 23 05:50:51 PM UTC 24
Finished Aug 23 05:51:03 PM UTC 24
Peak memory 225704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2046465606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2046465606
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_rw.3775334746
Short name T290
Test name
Test status
Simulation time 73479166 ps
CPU time 0.7 seconds
Started Aug 23 05:50:51 PM UTC 24
Finished Aug 23 05:51:03 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775334746 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.3775334746
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/16.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/16.edn_intr_test.2627500226
Short name T1091
Test name
Test status
Simulation time 14349799 ps
CPU time 0.74 seconds
Started Aug 23 05:50:51 PM UTC 24
Finished Aug 23 05:51:03 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627500226 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.2627500226
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/16.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/16.edn_same_csr_outstanding.3942723686
Short name T1092
Test name
Test status
Simulation time 46394586 ps
CPU time 0.93 seconds
Started Aug 23 05:50:51 PM UTC 24
Finished Aug 23 05:51:03 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942723686 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_outstanding.3942723686
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/16.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_errors.854691315
Short name T1072
Test name
Test status
Simulation time 340951415 ps
CPU time 2.07 seconds
Started Aug 23 05:50:51 PM UTC 24
Finished Aug 23 05:50:57 PM UTC 24
Peak memory 228068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854691315 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.854691315
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/16.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_intg_err.4291793524
Short name T1100
Test name
Test status
Simulation time 92329613 ps
CPU time 2.15 seconds
Started Aug 23 05:50:51 PM UTC 24
Finished Aug 23 05:51:04 PM UTC 24
Peak memory 217560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291793524 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.4291793524
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/16.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3076109784
Short name T1063
Test name
Test status
Simulation time 35515733 ps
CPU time 0.8 seconds
Started Aug 23 05:50:52 PM UTC 24
Finished Aug 23 05:50:55 PM UTC 24
Peak memory 215444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3076109784 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3076109784
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_rw.366333938
Short name T1078
Test name
Test status
Simulation time 86304345 ps
CPU time 0.74 seconds
Started Aug 23 05:50:52 PM UTC 24
Finished Aug 23 05:51:01 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366333938 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.366333938
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/17.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/17.edn_intr_test.3522339389
Short name T1077
Test name
Test status
Simulation time 25849569 ps
CPU time 0.73 seconds
Started Aug 23 05:50:52 PM UTC 24
Finished Aug 23 05:51:01 PM UTC 24
Peak memory 215076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522339389 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.3522339389
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/17.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/17.edn_same_csr_outstanding.668051946
Short name T1065
Test name
Test status
Simulation time 44436406 ps
CPU time 0.83 seconds
Started Aug 23 05:50:52 PM UTC 24
Finished Aug 23 05:50:55 PM UTC 24
Peak memory 214952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668051946 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_outstanding.668051946
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/17.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_errors.3530253976
Short name T1104
Test name
Test status
Simulation time 87140441 ps
CPU time 2.69 seconds
Started Aug 23 05:50:51 PM UTC 24
Finished Aug 23 05:51:05 PM UTC 24
Peak memory 227856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530253976 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3530253976
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/17.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_intg_err.4200368112
Short name T1086
Test name
Test status
Simulation time 386321973 ps
CPU time 2.15 seconds
Started Aug 23 05:50:52 PM UTC 24
Finished Aug 23 05:51:02 PM UTC 24
Peak memory 217248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200368112 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.4200368112
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/17.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.130107014
Short name T1067
Test name
Test status
Simulation time 31950993 ps
CPU time 0.81 seconds
Started Aug 23 05:50:53 PM UTC 24
Finished Aug 23 05:50:55 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=130107014 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.130107014
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_rw.3427763833
Short name T1066
Test name
Test status
Simulation time 15310250 ps
CPU time 0.74 seconds
Started Aug 23 05:50:52 PM UTC 24
Finished Aug 23 05:50:55 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427763833 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.3427763833
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/18.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/18.edn_intr_test.717976004
Short name T1064
Test name
Test status
Simulation time 34792959 ps
CPU time 0.66 seconds
Started Aug 23 05:50:52 PM UTC 24
Finished Aug 23 05:50:55 PM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717976004 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.717976004
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/18.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/18.edn_same_csr_outstanding.1025398492
Short name T1068
Test name
Test status
Simulation time 73899267 ps
CPU time 1.28 seconds
Started Aug 23 05:50:53 PM UTC 24
Finished Aug 23 05:50:56 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025398492 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_outstanding.1025398492
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/18.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_errors.3691613896
Short name T1070
Test name
Test status
Simulation time 42734190 ps
CPU time 2.25 seconds
Started Aug 23 05:50:52 PM UTC 24
Finished Aug 23 05:50:56 PM UTC 24
Peak memory 227796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691613896 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3691613896
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/18.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_intg_err.1247172090
Short name T1069
Test name
Test status
Simulation time 175750829 ps
CPU time 2.05 seconds
Started Aug 23 05:50:52 PM UTC 24
Finished Aug 23 05:50:56 PM UTC 24
Peak memory 217280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247172090 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1247172090
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/18.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.434626219
Short name T1083
Test name
Test status
Simulation time 62603471 ps
CPU time 0.89 seconds
Started Aug 23 05:50:56 PM UTC 24
Finished Aug 23 05:51:01 PM UTC 24
Peak memory 225704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=434626219 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.434626219
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_rw.2351678277
Short name T1080
Test name
Test status
Simulation time 22834022 ps
CPU time 0.77 seconds
Started Aug 23 05:50:56 PM UTC 24
Finished Aug 23 05:51:01 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351678277 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2351678277
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/19.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/19.edn_intr_test.3166902028
Short name T1081
Test name
Test status
Simulation time 26778758 ps
CPU time 0.73 seconds
Started Aug 23 05:50:56 PM UTC 24
Finished Aug 23 05:51:01 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166902028 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.3166902028
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/19.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/19.edn_same_csr_outstanding.1713641900
Short name T1085
Test name
Test status
Simulation time 36922057 ps
CPU time 1.18 seconds
Started Aug 23 05:50:56 PM UTC 24
Finished Aug 23 05:51:02 PM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713641900 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_outstanding.1713641900
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/19.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_errors.2504178155
Short name T1079
Test name
Test status
Simulation time 30869312 ps
CPU time 1.8 seconds
Started Aug 23 05:50:55 PM UTC 24
Finished Aug 23 05:51:01 PM UTC 24
Peak memory 225700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504178155 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2504178155
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/19.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_intg_err.2130388580
Short name T1082
Test name
Test status
Simulation time 1525686068 ps
CPU time 1.97 seconds
Started Aug 23 05:50:55 PM UTC 24
Finished Aug 23 05:51:01 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130388580 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.2130388580
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/19.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_aliasing.3772600870
Short name T992
Test name
Test status
Simulation time 43367749 ps
CPU time 0.83 seconds
Started Aug 23 05:50:13 PM UTC 24
Finished Aug 23 05:50:25 PM UTC 24
Peak memory 215304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772600870 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.3772600870
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/2.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_bit_bash.1738198728
Short name T996
Test name
Test status
Simulation time 60327038 ps
CPU time 2.64 seconds
Started Aug 23 05:50:13 PM UTC 24
Finished Aug 23 05:50:27 PM UTC 24
Peak memory 217556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738198728 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1738198728
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/2.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_hw_reset.3943945739
Short name T277
Test name
Test status
Simulation time 230514677 ps
CPU time 0.75 seconds
Started Aug 23 05:50:12 PM UTC 24
Finished Aug 23 05:50:15 PM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943945739 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3943945739
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/2.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2998396824
Short name T990
Test name
Test status
Simulation time 51729612 ps
CPU time 0.99 seconds
Started Aug 23 05:50:16 PM UTC 24
Finished Aug 23 05:50:25 PM UTC 24
Peak memory 225704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2998396824 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2998396824
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_rw.389374928
Short name T991
Test name
Test status
Simulation time 39044381 ps
CPU time 0.69 seconds
Started Aug 23 05:50:12 PM UTC 24
Finished Aug 23 05:50:25 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389374928 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.389374928
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/2.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/2.edn_intr_test.2645121172
Short name T986
Test name
Test status
Simulation time 175930978 ps
CPU time 0.71 seconds
Started Aug 23 05:50:12 PM UTC 24
Finished Aug 23 05:50:15 PM UTC 24
Peak memory 215448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645121172 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.2645121172
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/2.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/2.edn_same_csr_outstanding.4270884657
Short name T291
Test name
Test status
Simulation time 125274548 ps
CPU time 0.88 seconds
Started Aug 23 05:50:15 PM UTC 24
Finished Aug 23 05:50:21 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270884657 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_outstanding.4270884657
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/2.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/2.edn_tl_errors.1222745331
Short name T252
Test name
Test status
Simulation time 252760175 ps
CPU time 2.09 seconds
Started Aug 23 05:50:12 PM UTC 24
Finished Aug 23 05:50:16 PM UTC 24
Peak memory 228044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222745331 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1222745331
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/2.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/2.edn_tl_intg_err.4232913524
Short name T303
Test name
Test status
Simulation time 196047373 ps
CPU time 2.19 seconds
Started Aug 23 05:50:12 PM UTC 24
Finished Aug 23 05:50:17 PM UTC 24
Peak memory 217492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232913524 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.4232913524
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/2.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/20.edn_intr_test.3676458582
Short name T1073
Test name
Test status
Simulation time 70324840 ps
CPU time 0.73 seconds
Started Aug 23 05:50:57 PM UTC 24
Finished Aug 23 05:51:00 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676458582 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3676458582
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/20.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/21.edn_intr_test.1052588667
Short name T1075
Test name
Test status
Simulation time 20410478 ps
CPU time 0.71 seconds
Started Aug 23 05:50:57 PM UTC 24
Finished Aug 23 05:51:00 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052588667 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.1052588667
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/21.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/22.edn_intr_test.2503100924
Short name T1076
Test name
Test status
Simulation time 37667144 ps
CPU time 0.68 seconds
Started Aug 23 05:50:57 PM UTC 24
Finished Aug 23 05:51:00 PM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503100924 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2503100924
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/22.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/23.edn_intr_test.3284943498
Short name T1074
Test name
Test status
Simulation time 31685903 ps
CPU time 0.64 seconds
Started Aug 23 05:50:57 PM UTC 24
Finished Aug 23 05:51:00 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284943498 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3284943498
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/23.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/24.edn_intr_test.2486291185
Short name T1089
Test name
Test status
Simulation time 16467304 ps
CPU time 0.79 seconds
Started Aug 23 05:51:00 PM UTC 24
Finished Aug 23 05:51:02 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486291185 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.2486291185
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/24.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/25.edn_intr_test.1474698975
Short name T1087
Test name
Test status
Simulation time 14992286 ps
CPU time 0.73 seconds
Started Aug 23 05:51:01 PM UTC 24
Finished Aug 23 05:51:02 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474698975 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1474698975
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/25.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/26.edn_intr_test.862785905
Short name T1088
Test name
Test status
Simulation time 35417446 ps
CPU time 0.71 seconds
Started Aug 23 05:51:01 PM UTC 24
Finished Aug 23 05:51:02 PM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862785905 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.862785905
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/26.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/27.edn_intr_test.1572562188
Short name T1090
Test name
Test status
Simulation time 12450957 ps
CPU time 0.69 seconds
Started Aug 23 05:51:01 PM UTC 24
Finished Aug 23 05:51:02 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572562188 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1572562188
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/27.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/28.edn_intr_test.1039843987
Short name T1094
Test name
Test status
Simulation time 32139569 ps
CPU time 0.64 seconds
Started Aug 23 05:51:02 PM UTC 24
Finished Aug 23 05:51:03 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039843987 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.1039843987
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/28.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/29.edn_intr_test.1198798546
Short name T1095
Test name
Test status
Simulation time 46587669 ps
CPU time 0.72 seconds
Started Aug 23 05:51:02 PM UTC 24
Finished Aug 23 05:51:03 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198798546 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1198798546
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/29.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_aliasing.1584388784
Short name T281
Test name
Test status
Simulation time 77184020 ps
CPU time 0.99 seconds
Started Aug 23 05:50:18 PM UTC 24
Finished Aug 23 05:50:21 PM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584388784 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1584388784
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/3.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_bit_bash.3520116516
Short name T289
Test name
Test status
Simulation time 1001468104 ps
CPU time 5.39 seconds
Started Aug 23 05:50:18 PM UTC 24
Finished Aug 23 05:50:25 PM UTC 24
Peak memory 217616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520116516 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3520116516
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/3.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_hw_reset.3283413572
Short name T283
Test name
Test status
Simulation time 15502146 ps
CPU time 0.78 seconds
Started Aug 23 05:50:17 PM UTC 24
Finished Aug 23 05:50:25 PM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283413572 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.3283413572
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/3.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2801906552
Short name T1003
Test name
Test status
Simulation time 21809144 ps
CPU time 0.8 seconds
Started Aug 23 05:50:22 PM UTC 24
Finished Aug 23 05:50:31 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2801906552 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2801906552
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_rw.3386958098
Short name T282
Test name
Test status
Simulation time 18074617 ps
CPU time 0.72 seconds
Started Aug 23 05:50:17 PM UTC 24
Finished Aug 23 05:50:25 PM UTC 24
Peak memory 215388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386958098 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3386958098
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/3.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/3.edn_intr_test.1431024650
Short name T989
Test name
Test status
Simulation time 42136454 ps
CPU time 0.67 seconds
Started Aug 23 05:50:17 PM UTC 24
Finished Aug 23 05:50:25 PM UTC 24
Peak memory 215448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431024650 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1431024650
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/3.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/3.edn_same_csr_outstanding.1389699818
Short name T293
Test name
Test status
Simulation time 179217818 ps
CPU time 0.82 seconds
Started Aug 23 05:50:21 PM UTC 24
Finished Aug 23 05:50:26 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389699818 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_outstanding.1389699818
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/3.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_errors.3813903266
Short name T997
Test name
Test status
Simulation time 2127937454 ps
CPU time 3.82 seconds
Started Aug 23 05:50:16 PM UTC 24
Finished Aug 23 05:50:28 PM UTC 24
Peak memory 227788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813903266 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3813903266
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/3.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_intg_err.2079952071
Short name T304
Test name
Test status
Simulation time 55712218 ps
CPU time 1.35 seconds
Started Aug 23 05:50:16 PM UTC 24
Finished Aug 23 05:50:25 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079952071 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2079952071
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/3.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/30.edn_intr_test.1877038297
Short name T1097
Test name
Test status
Simulation time 15805500 ps
CPU time 0.77 seconds
Started Aug 23 05:51:02 PM UTC 24
Finished Aug 23 05:51:04 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877038297 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1877038297
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/30.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/31.edn_intr_test.875248515
Short name T1096
Test name
Test status
Simulation time 41532823 ps
CPU time 0.72 seconds
Started Aug 23 05:51:02 PM UTC 24
Finished Aug 23 05:51:04 PM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875248515 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.875248515
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/31.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/32.edn_intr_test.3356385583
Short name T1098
Test name
Test status
Simulation time 57815771 ps
CPU time 0.72 seconds
Started Aug 23 05:51:02 PM UTC 24
Finished Aug 23 05:51:04 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356385583 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3356385583
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/32.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/33.edn_intr_test.1183014616
Short name T1099
Test name
Test status
Simulation time 13584919 ps
CPU time 0.74 seconds
Started Aug 23 05:51:02 PM UTC 24
Finished Aug 23 05:51:04 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183014616 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.1183014616
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/33.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/34.edn_intr_test.1588824896
Short name T1101
Test name
Test status
Simulation time 21184722 ps
CPU time 0.7 seconds
Started Aug 23 05:51:03 PM UTC 24
Finished Aug 23 05:51:05 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588824896 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1588824896
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/34.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/35.edn_intr_test.351133438
Short name T1103
Test name
Test status
Simulation time 16931304 ps
CPU time 0.8 seconds
Started Aug 23 05:51:03 PM UTC 24
Finished Aug 23 05:51:05 PM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351133438 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.351133438
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/35.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/36.edn_intr_test.385523916
Short name T1102
Test name
Test status
Simulation time 45751611 ps
CPU time 0.66 seconds
Started Aug 23 05:51:03 PM UTC 24
Finished Aug 23 05:51:05 PM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385523916 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.385523916
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/36.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/37.edn_intr_test.2194849285
Short name T1105
Test name
Test status
Simulation time 46173563 ps
CPU time 0.72 seconds
Started Aug 23 05:51:03 PM UTC 24
Finished Aug 23 05:51:05 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194849285 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2194849285
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/37.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/38.edn_intr_test.184289614
Short name T1106
Test name
Test status
Simulation time 19919493 ps
CPU time 0.68 seconds
Started Aug 23 05:51:03 PM UTC 24
Finished Aug 23 05:51:05 PM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184289614 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.184289614
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/38.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/39.edn_intr_test.1296692466
Short name T1108
Test name
Test status
Simulation time 25667698 ps
CPU time 0.72 seconds
Started Aug 23 05:51:03 PM UTC 24
Finished Aug 23 05:51:05 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296692466 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.1296692466
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/39.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_aliasing.517707677
Short name T1006
Test name
Test status
Simulation time 49599663 ps
CPU time 0.98 seconds
Started Aug 23 05:50:26 PM UTC 24
Finished Aug 23 05:50:31 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517707677 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.517707677
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/4.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_bit_bash.448797615
Short name T1012
Test name
Test status
Simulation time 93864331 ps
CPU time 2.54 seconds
Started Aug 23 05:50:26 PM UTC 24
Finished Aug 23 05:50:33 PM UTC 24
Peak memory 217508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448797615 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.448797615
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/4.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_hw_reset.592097330
Short name T285
Test name
Test status
Simulation time 124351011 ps
CPU time 0.76 seconds
Started Aug 23 05:50:26 PM UTC 24
Finished Aug 23 05:50:31 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592097330 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.592097330
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/4.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2876526616
Short name T1008
Test name
Test status
Simulation time 33349695 ps
CPU time 1.21 seconds
Started Aug 23 05:50:26 PM UTC 24
Finished Aug 23 05:50:32 PM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2876526616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.2876526616
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_rw.2953307782
Short name T295
Test name
Test status
Simulation time 16295130 ps
CPU time 0.79 seconds
Started Aug 23 05:50:26 PM UTC 24
Finished Aug 23 05:50:31 PM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953307782 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2953307782
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/4.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/4.edn_intr_test.1624593225
Short name T1004
Test name
Test status
Simulation time 28043969 ps
CPU time 0.78 seconds
Started Aug 23 05:50:26 PM UTC 24
Finished Aug 23 05:50:31 PM UTC 24
Peak memory 215448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624593225 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1624593225
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/4.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/4.edn_same_csr_outstanding.2818574837
Short name T296
Test name
Test status
Simulation time 52327536 ps
CPU time 1.07 seconds
Started Aug 23 05:50:26 PM UTC 24
Finished Aug 23 05:50:31 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818574837 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_outstanding.2818574837
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/4.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_errors.2336811051
Short name T1009
Test name
Test status
Simulation time 131994074 ps
CPU time 1.82 seconds
Started Aug 23 05:50:22 PM UTC 24
Finished Aug 23 05:50:32 PM UTC 24
Peak memory 225688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336811051 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2336811051
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/4.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_intg_err.2656713864
Short name T1007
Test name
Test status
Simulation time 51127087 ps
CPU time 1.44 seconds
Started Aug 23 05:50:26 PM UTC 24
Finished Aug 23 05:50:32 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656713864 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2656713864
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/4.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/40.edn_intr_test.2123038998
Short name T1107
Test name
Test status
Simulation time 18905982 ps
CPU time 0.68 seconds
Started Aug 23 05:51:03 PM UTC 24
Finished Aug 23 05:51:05 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123038998 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.2123038998
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/40.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/41.edn_intr_test.2718727473
Short name T1109
Test name
Test status
Simulation time 69823114 ps
CPU time 0.73 seconds
Started Aug 23 05:51:03 PM UTC 24
Finished Aug 23 05:51:05 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718727473 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2718727473
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/41.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/42.edn_intr_test.303751384
Short name T1110
Test name
Test status
Simulation time 32323091 ps
CPU time 0.69 seconds
Started Aug 23 05:51:04 PM UTC 24
Finished Aug 23 05:51:06 PM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303751384 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.303751384
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/42.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/43.edn_intr_test.3362924480
Short name T1113
Test name
Test status
Simulation time 14159765 ps
CPU time 0.75 seconds
Started Aug 23 05:51:04 PM UTC 24
Finished Aug 23 05:51:06 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362924480 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.3362924480
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/43.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/44.edn_intr_test.3429462071
Short name T1111
Test name
Test status
Simulation time 20631705 ps
CPU time 0.72 seconds
Started Aug 23 05:51:04 PM UTC 24
Finished Aug 23 05:51:06 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429462071 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3429462071
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/44.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/45.edn_intr_test.3304368496
Short name T1112
Test name
Test status
Simulation time 15701661 ps
CPU time 0.75 seconds
Started Aug 23 05:51:04 PM UTC 24
Finished Aug 23 05:51:06 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304368496 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.3304368496
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/45.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/46.edn_intr_test.1758484992
Short name T1114
Test name
Test status
Simulation time 24822471 ps
CPU time 0.69 seconds
Started Aug 23 05:51:04 PM UTC 24
Finished Aug 23 05:51:06 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758484992 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1758484992
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/46.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/47.edn_intr_test.425001770
Short name T1115
Test name
Test status
Simulation time 49860669 ps
CPU time 0.73 seconds
Started Aug 23 05:51:04 PM UTC 24
Finished Aug 23 05:51:06 PM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425001770 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.425001770
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/47.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/48.edn_intr_test.625187652
Short name T1116
Test name
Test status
Simulation time 13962792 ps
CPU time 0.75 seconds
Started Aug 23 05:51:04 PM UTC 24
Finished Aug 23 05:51:06 PM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625187652 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.625187652
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/48.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/49.edn_intr_test.239291429
Short name T1117
Test name
Test status
Simulation time 25777601 ps
CPU time 0.73 seconds
Started Aug 23 05:51:04 PM UTC 24
Finished Aug 23 05:51:06 PM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239291429 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.239291429
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/49.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.984043006
Short name T1001
Test name
Test status
Simulation time 61091110 ps
CPU time 1.24 seconds
Started Aug 23 05:50:27 PM UTC 24
Finished Aug 23 05:50:31 PM UTC 24
Peak memory 225704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=984043006 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.984043006
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_rw.2766639588
Short name T999
Test name
Test status
Simulation time 40812965 ps
CPU time 0.7 seconds
Started Aug 23 05:50:27 PM UTC 24
Finished Aug 23 05:50:30 PM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766639588 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2766639588
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/5.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/5.edn_intr_test.516837176
Short name T998
Test name
Test status
Simulation time 24035305 ps
CPU time 0.73 seconds
Started Aug 23 05:50:27 PM UTC 24
Finished Aug 23 05:50:30 PM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516837176 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.516837176
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/5.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/5.edn_same_csr_outstanding.1567240992
Short name T294
Test name
Test status
Simulation time 31288191 ps
CPU time 0.91 seconds
Started Aug 23 05:50:27 PM UTC 24
Finished Aug 23 05:50:30 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567240992 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_outstanding.1567240992
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/5.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_errors.2990281245
Short name T1010
Test name
Test status
Simulation time 36135586 ps
CPU time 1.93 seconds
Started Aug 23 05:50:26 PM UTC 24
Finished Aug 23 05:50:32 PM UTC 24
Peak memory 229784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990281245 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2990281245
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/5.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_intg_err.1232846329
Short name T316
Test name
Test status
Simulation time 904039420 ps
CPU time 2.01 seconds
Started Aug 23 05:50:27 PM UTC 24
Finished Aug 23 05:50:31 PM UTC 24
Peak memory 228008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232846329 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1232846329
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/5.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1662012782
Short name T1015
Test name
Test status
Simulation time 30382534 ps
CPU time 1.21 seconds
Started Aug 23 05:50:32 PM UTC 24
Finished Aug 23 05:50:35 PM UTC 24
Peak memory 227684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1662012782 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1662012782
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_rw.1017692755
Short name T286
Test name
Test status
Simulation time 14302355 ps
CPU time 0.79 seconds
Started Aug 23 05:50:30 PM UTC 24
Finished Aug 23 05:50:32 PM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017692755 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1017692755
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/6.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/6.edn_intr_test.2586632693
Short name T1000
Test name
Test status
Simulation time 43387206 ps
CPU time 0.69 seconds
Started Aug 23 05:50:28 PM UTC 24
Finished Aug 23 05:50:30 PM UTC 24
Peak memory 215448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586632693 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.2586632693
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/6.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/6.edn_same_csr_outstanding.887835860
Short name T1011
Test name
Test status
Simulation time 72743242 ps
CPU time 0.89 seconds
Started Aug 23 05:50:30 PM UTC 24
Finished Aug 23 05:50:32 PM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887835860 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_outstanding.887835860
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/6.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_errors.3025664197
Short name T1005
Test name
Test status
Simulation time 97091710 ps
CPU time 1.64 seconds
Started Aug 23 05:50:27 PM UTC 24
Finished Aug 23 05:50:31 PM UTC 24
Peak memory 225688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025664197 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3025664197
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/6.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3547067991
Short name T1029
Test name
Test status
Simulation time 56955412 ps
CPU time 1.15 seconds
Started Aug 23 05:50:32 PM UTC 24
Finished Aug 23 05:50:41 PM UTC 24
Peak memory 227684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3547067991 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3547067991
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_rw.3650329037
Short name T1025
Test name
Test status
Simulation time 14752687 ps
CPU time 0.81 seconds
Started Aug 23 05:50:32 PM UTC 24
Finished Aug 23 05:50:41 PM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650329037 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.3650329037
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/7.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/7.edn_intr_test.3891339068
Short name T1026
Test name
Test status
Simulation time 14064605 ps
CPU time 0.81 seconds
Started Aug 23 05:50:32 PM UTC 24
Finished Aug 23 05:50:41 PM UTC 24
Peak memory 215448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891339068 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.3891339068
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/7.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/7.edn_same_csr_outstanding.3987961177
Short name T1028
Test name
Test status
Simulation time 52790552 ps
CPU time 1.08 seconds
Started Aug 23 05:50:32 PM UTC 24
Finished Aug 23 05:50:41 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987961177 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_outstanding.3987961177
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/7.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_errors.1298816150
Short name T1023
Test name
Test status
Simulation time 111134785 ps
CPU time 3.21 seconds
Started Aug 23 05:50:32 PM UTC 24
Finished Aug 23 05:50:37 PM UTC 24
Peak memory 227796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298816150 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.1298816150
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/7.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_intg_err.1225601344
Short name T1030
Test name
Test status
Simulation time 95167456 ps
CPU time 2.1 seconds
Started Aug 23 05:50:32 PM UTC 24
Finished Aug 23 05:50:42 PM UTC 24
Peak memory 217488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225601344 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1225601344
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/7.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3419080658
Short name T1017
Test name
Test status
Simulation time 26225366 ps
CPU time 1.37 seconds
Started Aug 23 05:50:33 PM UTC 24
Finished Aug 23 05:50:35 PM UTC 24
Peak memory 227040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3419080658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3419080658
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_rw.3466645508
Short name T1021
Test name
Test status
Simulation time 27331716 ps
CPU time 0.78 seconds
Started Aug 23 05:50:33 PM UTC 24
Finished Aug 23 05:50:36 PM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466645508 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.3466645508
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/8.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/8.edn_intr_test.1668466752
Short name T1018
Test name
Test status
Simulation time 14312116 ps
CPU time 0.75 seconds
Started Aug 23 05:50:33 PM UTC 24
Finished Aug 23 05:50:36 PM UTC 24
Peak memory 215448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668466752 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1668466752
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/8.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/8.edn_same_csr_outstanding.54767613
Short name T1020
Test name
Test status
Simulation time 61478508 ps
CPU time 0.74 seconds
Started Aug 23 05:50:33 PM UTC 24
Finished Aug 23 05:50:36 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54767613 -assert nopostproc +UVM_T
ESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_outstanding.54767613
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/8.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_errors.1708893823
Short name T1032
Test name
Test status
Simulation time 101384944 ps
CPU time 3.12 seconds
Started Aug 23 05:50:32 PM UTC 24
Finished Aug 23 05:50:43 PM UTC 24
Peak memory 227804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708893823 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1708893823
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/8.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_intg_err.2726048378
Short name T1031
Test name
Test status
Simulation time 536867115 ps
CPU time 1.99 seconds
Started Aug 23 05:50:32 PM UTC 24
Finished Aug 23 05:50:42 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726048378 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2726048378
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/8.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.227991961
Short name T1044
Test name
Test status
Simulation time 45766246 ps
CPU time 1.02 seconds
Started Aug 23 05:50:34 PM UTC 24
Finished Aug 23 05:50:46 PM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=227991961 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.227991961
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_rw.3029785438
Short name T1013
Test name
Test status
Simulation time 42873314 ps
CPU time 0.66 seconds
Started Aug 23 05:50:33 PM UTC 24
Finished Aug 23 05:50:35 PM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029785438 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3029785438
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/9.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/9.edn_intr_test.727315958
Short name T1014
Test name
Test status
Simulation time 14634777 ps
CPU time 0.79 seconds
Started Aug 23 05:50:33 PM UTC 24
Finished Aug 23 05:50:35 PM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727315958 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.727315958
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/9.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/9.edn_same_csr_outstanding.3234283284
Short name T1016
Test name
Test status
Simulation time 19327461 ps
CPU time 0.98 seconds
Started Aug 23 05:50:33 PM UTC 24
Finished Aug 23 05:50:35 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234283284 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_outstanding.3234283284
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/9.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_errors.3889159345
Short name T1019
Test name
Test status
Simulation time 46509659 ps
CPU time 1.59 seconds
Started Aug 23 05:50:33 PM UTC 24
Finished Aug 23 05:50:36 PM UTC 24
Peak memory 226524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889159345 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3889159345
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/9.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_intg_err.2446495611
Short name T1022
Test name
Test status
Simulation time 385026196 ps
CPU time 1.97 seconds
Started Aug 23 05:50:33 PM UTC 24
Finished Aug 23 05:50:36 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446495611 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2446495611
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/9.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/0.edn_alert.8604216
Short name T27
Test name
Test status
Simulation time 22699629 ps
CPU time 0.96 seconds
Started Aug 23 05:45:56 PM UTC 24
Finished Aug 23 05:45:58 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8604216 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_al
ert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 0.edn_alert.8604216
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/0.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/0.edn_genbits.1800313622
Short name T3
Test name
Test status
Simulation time 54034396 ps
CPU time 1.16 seconds
Started Aug 23 05:45:53 PM UTC 24
Finished Aug 23 05:45:56 PM UTC 24
Peak memory 228560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800313622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1800313622
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/0.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/0.edn_intr.3748204287
Short name T5
Test name
Test status
Simulation time 28336833 ps
CPU time 0.92 seconds
Started Aug 23 05:45:56 PM UTC 24
Finished Aug 23 05:45:58 PM UTC 24
Peak memory 237820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748204287 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 0.edn_intr.3748204287
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/0.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/0.edn_regwen.4219862749
Short name T2
Test name
Test status
Simulation time 53938841 ps
CPU time 0.81 seconds
Started Aug 23 05:45:53 PM UTC 24
Finished Aug 23 05:45:55 PM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219862749 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 0.edn_regwen.4219862749
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/0.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/0.edn_smoke.883733281
Short name T1
Test name
Test status
Simulation time 35119211 ps
CPU time 0.85 seconds
Started Aug 23 05:45:53 PM UTC 24
Finished Aug 23 05:45:55 PM UTC 24
Peak memory 226816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883733281 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 0.edn_smoke.883733281
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/0.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/1.edn_alert.1032001888
Short name T18
Test name
Test status
Simulation time 24269306 ps
CPU time 1.02 seconds
Started Aug 23 05:46:06 PM UTC 24
Finished Aug 23 05:46:08 PM UTC 24
Peak memory 230316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032001888 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 1.edn_alert.1032001888
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/1.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/1.edn_alert_test.400858045
Short name T66
Test name
Test status
Simulation time 27074205 ps
CPU time 0.78 seconds
Started Aug 23 05:46:06 PM UTC 24
Finished Aug 23 05:46:08 PM UTC 24
Peak memory 216988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400858045 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.400858045
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/1.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/1.edn_err.2806375752
Short name T19
Test name
Test status
Simulation time 52896430 ps
CPU time 0.68 seconds
Started Aug 23 05:46:06 PM UTC 24
Finished Aug 23 05:46:08 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806375752 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 1.edn_err.2806375752
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/1.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/1.edn_genbits.4261329938
Short name T29
Test name
Test status
Simulation time 71956046 ps
CPU time 1.35 seconds
Started Aug 23 05:46:05 PM UTC 24
Finished Aug 23 05:46:07 PM UTC 24
Peak memory 230248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261329938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_genbits.4261329938
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/1.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/1.edn_intr.2313820514
Short name T31
Test name
Test status
Simulation time 22892333 ps
CPU time 0.84 seconds
Started Aug 23 05:46:06 PM UTC 24
Finished Aug 23 05:46:08 PM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313820514 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 1.edn_intr.2313820514
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/1.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/1.edn_regwen.2447682217
Short name T28
Test name
Test status
Simulation time 60651136 ps
CPU time 0.78 seconds
Started Aug 23 05:46:05 PM UTC 24
Finished Aug 23 05:46:06 PM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447682217 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 1.edn_regwen.2447682217
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/1.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/1.edn_smoke.2378047545
Short name T63
Test name
Test status
Simulation time 26891965 ps
CPU time 0.76 seconds
Started Aug 23 05:45:57 PM UTC 24
Finished Aug 23 05:45:59 PM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378047545 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 1.edn_smoke.2378047545
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/1.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/10.edn_alert.1521412101
Short name T100
Test name
Test status
Simulation time 85971109 ps
CPU time 1.04 seconds
Started Aug 23 05:46:22 PM UTC 24
Finished Aug 23 05:46:25 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521412101 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 10.edn_alert.1521412101
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/10.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/10.edn_alert_test.4076974232
Short name T367
Test name
Test status
Simulation time 26646560 ps
CPU time 0.93 seconds
Started Aug 23 05:46:22 PM UTC 24
Finished Aug 23 05:46:25 PM UTC 24
Peak memory 225568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076974232 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.4076974232
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/10.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/10.edn_disable_auto_req_mode.104529940
Short name T94
Test name
Test status
Simulation time 241027745 ps
CPU time 0.98 seconds
Started Aug 23 05:46:22 PM UTC 24
Finished Aug 23 05:46:25 PM UTC 24
Peak memory 230348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104529940 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable_auto_req_mode.104529940
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/10.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/10.edn_genbits.763301001
Short name T305
Test name
Test status
Simulation time 175022548 ps
CPU time 0.82 seconds
Started Aug 23 05:46:20 PM UTC 24
Finished Aug 23 05:46:22 PM UTC 24
Peak memory 228248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763301001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.edn_genbits.763301001
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/10.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/10.edn_intr.3235825206
Short name T50
Test name
Test status
Simulation time 31488753 ps
CPU time 0.79 seconds
Started Aug 23 05:46:22 PM UTC 24
Finished Aug 23 05:46:25 PM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235825206 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 10.edn_intr.3235825206
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/10.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/10.edn_smoke.2718694860
Short name T115
Test name
Test status
Simulation time 48973378 ps
CPU time 0.8 seconds
Started Aug 23 05:46:20 PM UTC 24
Finished Aug 23 05:46:22 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718694860 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 10.edn_smoke.2718694860
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/10.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/100.edn_alert.1362379553
Short name T704
Test name
Test status
Simulation time 75711743 ps
CPU time 1.02 seconds
Started Aug 23 05:49:10 PM UTC 24
Finished Aug 23 05:49:12 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362379553 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 100.edn_alert.1362379553
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/100.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/100.edn_genbits.1212463103
Short name T703
Test name
Test status
Simulation time 39190619 ps
CPU time 1.08 seconds
Started Aug 23 05:49:10 PM UTC 24
Finished Aug 23 05:49:12 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212463103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 100.edn_genbits.1212463103
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/100.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/101.edn_alert.3622432179
Short name T706
Test name
Test status
Simulation time 23463177 ps
CPU time 1.03 seconds
Started Aug 23 05:49:11 PM UTC 24
Finished Aug 23 05:49:13 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622432179 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 101.edn_alert.3622432179
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/101.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/101.edn_genbits.1674348375
Short name T707
Test name
Test status
Simulation time 29745048 ps
CPU time 1.04 seconds
Started Aug 23 05:49:11 PM UTC 24
Finished Aug 23 05:49:13 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674348375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 101.edn_genbits.1674348375
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/101.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/102.edn_alert.1932451066
Short name T710
Test name
Test status
Simulation time 30940656 ps
CPU time 1.12 seconds
Started Aug 23 05:49:11 PM UTC 24
Finished Aug 23 05:49:13 PM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932451066 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 102.edn_alert.1932451066
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/102.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/102.edn_genbits.3558626112
Short name T709
Test name
Test status
Simulation time 40160177 ps
CPU time 1.22 seconds
Started Aug 23 05:49:11 PM UTC 24
Finished Aug 23 05:49:13 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558626112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3558626112
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/102.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/103.edn_alert.2186809034
Short name T708
Test name
Test status
Simulation time 40184533 ps
CPU time 0.92 seconds
Started Aug 23 05:49:11 PM UTC 24
Finished Aug 23 05:49:13 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186809034 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 103.edn_alert.2186809034
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/103.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/103.edn_genbits.2129462216
Short name T705
Test name
Test status
Simulation time 61998693 ps
CPU time 0.82 seconds
Started Aug 23 05:49:11 PM UTC 24
Finished Aug 23 05:49:13 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129462216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2129462216
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/103.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/104.edn_alert.3545264534
Short name T715
Test name
Test status
Simulation time 96259918 ps
CPU time 1.11 seconds
Started Aug 23 05:49:12 PM UTC 24
Finished Aug 23 05:49:14 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545264534 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 104.edn_alert.3545264534
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/104.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/104.edn_genbits.1048604085
Short name T711
Test name
Test status
Simulation time 70572761 ps
CPU time 1.29 seconds
Started Aug 23 05:49:11 PM UTC 24
Finished Aug 23 05:49:13 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048604085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 104.edn_genbits.1048604085
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/104.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/105.edn_alert.2899451487
Short name T714
Test name
Test status
Simulation time 83056109 ps
CPU time 1.08 seconds
Started Aug 23 05:49:12 PM UTC 24
Finished Aug 23 05:49:14 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899451487 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 105.edn_alert.2899451487
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/105.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/105.edn_genbits.756194235
Short name T712
Test name
Test status
Simulation time 36056253 ps
CPU time 1.01 seconds
Started Aug 23 05:49:12 PM UTC 24
Finished Aug 23 05:49:14 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756194235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 105.edn_genbits.756194235
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/105.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/106.edn_alert.1663850573
Short name T713
Test name
Test status
Simulation time 53918949 ps
CPU time 0.91 seconds
Started Aug 23 05:49:12 PM UTC 24
Finished Aug 23 05:49:14 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663850573 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 106.edn_alert.1663850573
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/106.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/106.edn_genbits.4072702808
Short name T719
Test name
Test status
Simulation time 150101594 ps
CPU time 2.31 seconds
Started Aug 23 05:49:12 PM UTC 24
Finished Aug 23 05:49:16 PM UTC 24
Peak memory 229512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072702808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 106.edn_genbits.4072702808
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/106.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/107.edn_alert.3455018123
Short name T717
Test name
Test status
Simulation time 27331241 ps
CPU time 1.06 seconds
Started Aug 23 05:49:12 PM UTC 24
Finished Aug 23 05:49:15 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455018123 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 107.edn_alert.3455018123
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/107.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/107.edn_genbits.3624950543
Short name T716
Test name
Test status
Simulation time 99401215 ps
CPU time 1.1 seconds
Started Aug 23 05:49:12 PM UTC 24
Finished Aug 23 05:49:14 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624950543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3624950543
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/107.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/108.edn_alert.1748059125
Short name T718
Test name
Test status
Simulation time 74181913 ps
CPU time 0.98 seconds
Started Aug 23 05:49:13 PM UTC 24
Finished Aug 23 05:49:15 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748059125 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 108.edn_alert.1748059125
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/108.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/108.edn_genbits.1927333048
Short name T720
Test name
Test status
Simulation time 39439672 ps
CPU time 1.19 seconds
Started Aug 23 05:49:13 PM UTC 24
Finished Aug 23 05:49:16 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927333048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1927333048
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/108.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/109.edn_alert.3561470356
Short name T721
Test name
Test status
Simulation time 212508044 ps
CPU time 1.17 seconds
Started Aug 23 05:49:13 PM UTC 24
Finished Aug 23 05:49:16 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561470356 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 109.edn_alert.3561470356
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/109.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/11.edn_alert_test.165949500
Short name T368
Test name
Test status
Simulation time 38136655 ps
CPU time 0.68 seconds
Started Aug 23 05:46:25 PM UTC 24
Finished Aug 23 05:46:27 PM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165949500 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.165949500
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/11.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/11.edn_disable_auto_req_mode.1794736078
Short name T101
Test name
Test status
Simulation time 43222484 ps
CPU time 0.95 seconds
Started Aug 23 05:46:25 PM UTC 24
Finished Aug 23 05:46:27 PM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794736078 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable_auto_req_mode.1794736078
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/11.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/11.edn_err.3900003033
Short name T61
Test name
Test status
Simulation time 116134553 ps
CPU time 1.03 seconds
Started Aug 23 05:46:25 PM UTC 24
Finished Aug 23 05:46:27 PM UTC 24
Peak memory 242184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900003033 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 11.edn_err.3900003033
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/11.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/11.edn_genbits.3753088855
Short name T14
Test name
Test status
Simulation time 112919619 ps
CPU time 1.09 seconds
Started Aug 23 05:46:22 PM UTC 24
Finished Aug 23 05:46:25 PM UTC 24
Peak memory 230632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753088855 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_genbits.3753088855
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/11.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/11.edn_intr.1268566432
Short name T119
Test name
Test status
Simulation time 102547117 ps
CPU time 0.75 seconds
Started Aug 23 05:46:25 PM UTC 24
Finished Aug 23 05:46:26 PM UTC 24
Peak memory 225840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268566432 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 11.edn_intr.1268566432
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/11.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/11.edn_smoke.1816264624
Short name T366
Test name
Test status
Simulation time 17424993 ps
CPU time 0.84 seconds
Started Aug 23 05:46:22 PM UTC 24
Finished Aug 23 05:46:25 PM UTC 24
Peak memory 226756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816264624 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 11.edn_smoke.1816264624
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/11.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/11.edn_stress_all.2796216674
Short name T114
Test name
Test status
Simulation time 128810626 ps
CPU time 2.53 seconds
Started Aug 23 05:46:22 PM UTC 24
Finished Aug 23 05:46:27 PM UTC 24
Peak memory 229448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796216674 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2796216674
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/11.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/11.edn_stress_all_with_rand_reset.452156468
Short name T495
Test name
Test status
Simulation time 7743258636 ps
CPU time 77.84 seconds
Started Aug 23 05:46:24 PM UTC 24
Finished Aug 23 05:47:44 PM UTC 24
Peak memory 233432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=452156468 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_
with_rand_reset.452156468
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/11.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/110.edn_genbits.3168780269
Short name T722
Test name
Test status
Simulation time 68667263 ps
CPU time 1.54 seconds
Started Aug 23 05:49:13 PM UTC 24
Finished Aug 23 05:49:16 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168780269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 110.edn_genbits.3168780269
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/110.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/111.edn_alert.4070628600
Short name T723
Test name
Test status
Simulation time 149272932 ps
CPU time 0.95 seconds
Started Aug 23 05:49:15 PM UTC 24
Finished Aug 23 05:49:17 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070628600 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 111.edn_alert.4070628600
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/111.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/111.edn_genbits.3717555895
Short name T725
Test name
Test status
Simulation time 70518549 ps
CPU time 1.08 seconds
Started Aug 23 05:49:15 PM UTC 24
Finished Aug 23 05:49:17 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717555895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 111.edn_genbits.3717555895
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/111.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/112.edn_alert.1105480122
Short name T726
Test name
Test status
Simulation time 37007138 ps
CPU time 0.96 seconds
Started Aug 23 05:49:15 PM UTC 24
Finished Aug 23 05:49:17 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105480122 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 112.edn_alert.1105480122
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/112.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/112.edn_genbits.1057437915
Short name T727
Test name
Test status
Simulation time 42368978 ps
CPU time 1.13 seconds
Started Aug 23 05:49:15 PM UTC 24
Finished Aug 23 05:49:17 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057437915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1057437915
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/112.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/114.edn_alert.667623629
Short name T730
Test name
Test status
Simulation time 165123864 ps
CPU time 1.08 seconds
Started Aug 23 05:49:16 PM UTC 24
Finished Aug 23 05:49:18 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667623629 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 114.edn_alert.667623629
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/114.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/114.edn_genbits.3002941335
Short name T728
Test name
Test status
Simulation time 30199483 ps
CPU time 1.03 seconds
Started Aug 23 05:49:16 PM UTC 24
Finished Aug 23 05:49:18 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002941335 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3002941335
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/114.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/115.edn_genbits.1666283821
Short name T731
Test name
Test status
Simulation time 61243745 ps
CPU time 1.41 seconds
Started Aug 23 05:49:16 PM UTC 24
Finished Aug 23 05:49:18 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666283821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1666283821
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/115.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/116.edn_alert.710859577
Short name T733
Test name
Test status
Simulation time 52966651 ps
CPU time 1 seconds
Started Aug 23 05:49:17 PM UTC 24
Finished Aug 23 05:49:19 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710859577 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 116.edn_alert.710859577
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/116.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/117.edn_genbits.412644372
Short name T735
Test name
Test status
Simulation time 250910968 ps
CPU time 1.53 seconds
Started Aug 23 05:49:17 PM UTC 24
Finished Aug 23 05:49:20 PM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412644372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 117.edn_genbits.412644372
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/117.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/118.edn_alert.3849995689
Short name T736
Test name
Test status
Simulation time 49808528 ps
CPU time 1.08 seconds
Started Aug 23 05:49:18 PM UTC 24
Finished Aug 23 05:49:20 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849995689 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 118.edn_alert.3849995689
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/118.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/118.edn_genbits.1259772676
Short name T743
Test name
Test status
Simulation time 236289690 ps
CPU time 2.47 seconds
Started Aug 23 05:49:17 PM UTC 24
Finished Aug 23 05:49:21 PM UTC 24
Peak memory 231548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259772676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1259772676
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/118.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/119.edn_alert.1618519769
Short name T738
Test name
Test status
Simulation time 30079304 ps
CPU time 1.13 seconds
Started Aug 23 05:49:18 PM UTC 24
Finished Aug 23 05:49:20 PM UTC 24
Peak memory 230428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618519769 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 119.edn_alert.1618519769
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/119.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/119.edn_genbits.2064348895
Short name T742
Test name
Test status
Simulation time 35822187 ps
CPU time 1.16 seconds
Started Aug 23 05:49:18 PM UTC 24
Finished Aug 23 05:49:20 PM UTC 24
Peak memory 230604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064348895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 119.edn_genbits.2064348895
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/119.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/12.edn_alert.1445239626
Short name T128
Test name
Test status
Simulation time 82966650 ps
CPU time 0.98 seconds
Started Aug 23 05:46:27 PM UTC 24
Finished Aug 23 05:46:29 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445239626 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 12.edn_alert.1445239626
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/12.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/12.edn_alert_test.518450349
Short name T243
Test name
Test status
Simulation time 43269299 ps
CPU time 0.74 seconds
Started Aug 23 05:46:27 PM UTC 24
Finished Aug 23 05:46:29 PM UTC 24
Peak memory 216912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518450349 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.518450349
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/12.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/12.edn_disable.3511147899
Short name T90
Test name
Test status
Simulation time 72858377 ps
CPU time 0.76 seconds
Started Aug 23 05:46:27 PM UTC 24
Finished Aug 23 05:46:29 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511147899 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.3511147899
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/12.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/12.edn_disable_auto_req_mode.1773590055
Short name T370
Test name
Test status
Simulation time 35966122 ps
CPU time 1.12 seconds
Started Aug 23 05:46:27 PM UTC 24
Finished Aug 23 05:46:30 PM UTC 24
Peak memory 226248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773590055 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable_auto_req_mode.1773590055
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/12.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/12.edn_err.2040912093
Short name T140
Test name
Test status
Simulation time 33021270 ps
CPU time 0.97 seconds
Started Aug 23 05:46:27 PM UTC 24
Finished Aug 23 05:46:30 PM UTC 24
Peak memory 246688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040912093 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 12.edn_err.2040912093
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/12.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/12.edn_genbits.481206901
Short name T77
Test name
Test status
Simulation time 66554493 ps
CPU time 1.15 seconds
Started Aug 23 05:46:27 PM UTC 24
Finished Aug 23 05:46:29 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481206901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.edn_genbits.481206901
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/12.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/12.edn_intr.4117600051
Short name T62
Test name
Test status
Simulation time 32572365 ps
CPU time 0.84 seconds
Started Aug 23 05:46:27 PM UTC 24
Finished Aug 23 05:46:29 PM UTC 24
Peak memory 237644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117600051 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 12.edn_intr.4117600051
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/12.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/12.edn_smoke.3985088158
Short name T369
Test name
Test status
Simulation time 29779073 ps
CPU time 0.76 seconds
Started Aug 23 05:46:25 PM UTC 24
Finished Aug 23 05:46:27 PM UTC 24
Peak memory 216028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985088158 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 12.edn_smoke.3985088158
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/12.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/12.edn_stress_all.1901647646
Short name T242
Test name
Test status
Simulation time 88021554 ps
CPU time 0.94 seconds
Started Aug 23 05:46:27 PM UTC 24
Finished Aug 23 05:46:29 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901647646 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1901647646
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/12.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/12.edn_stress_all_with_rand_reset.4043841293
Short name T483
Test name
Test status
Simulation time 38705061260 ps
CPU time 70.97 seconds
Started Aug 23 05:46:27 PM UTC 24
Finished Aug 23 05:47:40 PM UTC 24
Peak memory 234480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=4043841293 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all
_with_rand_reset.4043841293
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/12.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/120.edn_alert.646834470
Short name T737
Test name
Test status
Simulation time 75907451 ps
CPU time 1 seconds
Started Aug 23 05:49:18 PM UTC 24
Finished Aug 23 05:49:20 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646834470 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 120.edn_alert.646834470
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/120.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/120.edn_genbits.2043899901
Short name T740
Test name
Test status
Simulation time 77935215 ps
CPU time 1.19 seconds
Started Aug 23 05:49:18 PM UTC 24
Finished Aug 23 05:49:20 PM UTC 24
Peak memory 228280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043899901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 120.edn_genbits.2043899901
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/120.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/121.edn_alert.2651871298
Short name T739
Test name
Test status
Simulation time 29703507 ps
CPU time 1.1 seconds
Started Aug 23 05:49:18 PM UTC 24
Finished Aug 23 05:49:20 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651871298 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 121.edn_alert.2651871298
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/121.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/121.edn_genbits.906736811
Short name T741
Test name
Test status
Simulation time 32822041 ps
CPU time 1.08 seconds
Started Aug 23 05:49:18 PM UTC 24
Finished Aug 23 05:49:20 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906736811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 121.edn_genbits.906736811
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/121.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/122.edn_alert.3850915689
Short name T745
Test name
Test status
Simulation time 28381062 ps
CPU time 1.12 seconds
Started Aug 23 05:49:19 PM UTC 24
Finished Aug 23 05:49:21 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850915689 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 122.edn_alert.3850915689
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/122.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/122.edn_genbits.3686100197
Short name T744
Test name
Test status
Simulation time 72199065 ps
CPU time 0.91 seconds
Started Aug 23 05:49:19 PM UTC 24
Finished Aug 23 05:49:21 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686100197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3686100197
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/122.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/123.edn_alert.45905354
Short name T180
Test name
Test status
Simulation time 34305533 ps
CPU time 1.18 seconds
Started Aug 23 05:49:19 PM UTC 24
Finished Aug 23 05:49:22 PM UTC 24
Peak memory 226360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45905354 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 123.edn_alert.45905354
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/123.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/123.edn_genbits.832113663
Short name T746
Test name
Test status
Simulation time 69376047 ps
CPU time 1.1 seconds
Started Aug 23 05:49:19 PM UTC 24
Finished Aug 23 05:49:21 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832113663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 123.edn_genbits.832113663
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/123.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/124.edn_genbits.436069457
Short name T749
Test name
Test status
Simulation time 119335432 ps
CPU time 1.37 seconds
Started Aug 23 05:49:19 PM UTC 24
Finished Aug 23 05:49:22 PM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436069457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 124.edn_genbits.436069457
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/124.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/125.edn_alert.42440422
Short name T751
Test name
Test status
Simulation time 41585512 ps
CPU time 0.99 seconds
Started Aug 23 05:49:20 PM UTC 24
Finished Aug 23 05:49:23 PM UTC 24
Peak memory 230264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42440422 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 125.edn_alert.42440422
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/125.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/125.edn_genbits.1465572564
Short name T748
Test name
Test status
Simulation time 37580851 ps
CPU time 1.18 seconds
Started Aug 23 05:49:19 PM UTC 24
Finished Aug 23 05:49:22 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465572564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 125.edn_genbits.1465572564
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/125.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/126.edn_genbits.3924143559
Short name T329
Test name
Test status
Simulation time 69994739 ps
CPU time 2.4 seconds
Started Aug 23 05:49:20 PM UTC 24
Finished Aug 23 05:49:24 PM UTC 24
Peak memory 229684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924143559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3924143559
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/126.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/127.edn_alert.3313415661
Short name T756
Test name
Test status
Simulation time 85640984 ps
CPU time 1.09 seconds
Started Aug 23 05:49:22 PM UTC 24
Finished Aug 23 05:49:24 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313415661 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 127.edn_alert.3313415661
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/127.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/127.edn_genbits.1536481365
Short name T752
Test name
Test status
Simulation time 49937450 ps
CPU time 1.46 seconds
Started Aug 23 05:49:21 PM UTC 24
Finished Aug 23 05:49:23 PM UTC 24
Peak memory 230604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536481365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 127.edn_genbits.1536481365
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/127.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/128.edn_alert.2933297216
Short name T755
Test name
Test status
Simulation time 78896940 ps
CPU time 1.02 seconds
Started Aug 23 05:49:22 PM UTC 24
Finished Aug 23 05:49:24 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933297216 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 128.edn_alert.2933297216
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/128.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/128.edn_genbits.1881615144
Short name T754
Test name
Test status
Simulation time 111145517 ps
CPU time 0.88 seconds
Started Aug 23 05:49:22 PM UTC 24
Finished Aug 23 05:49:24 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881615144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 128.edn_genbits.1881615144
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/128.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/129.edn_alert.1101807819
Short name T758
Test name
Test status
Simulation time 24646354 ps
CPU time 1.06 seconds
Started Aug 23 05:49:22 PM UTC 24
Finished Aug 23 05:49:24 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101807819 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 129.edn_alert.1101807819
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/129.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/129.edn_genbits.2361591753
Short name T757
Test name
Test status
Simulation time 44717379 ps
CPU time 0.95 seconds
Started Aug 23 05:49:22 PM UTC 24
Finished Aug 23 05:49:24 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361591753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2361591753
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/129.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/13.edn_alert.3681012262
Short name T132
Test name
Test status
Simulation time 48399793 ps
CPU time 0.99 seconds
Started Aug 23 05:46:29 PM UTC 24
Finished Aug 23 05:46:32 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681012262 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 13.edn_alert.3681012262
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/13.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/13.edn_alert_test.1422758015
Short name T371
Test name
Test status
Simulation time 12262436 ps
CPU time 0.73 seconds
Started Aug 23 05:46:29 PM UTC 24
Finished Aug 23 05:46:32 PM UTC 24
Peak memory 216372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422758015 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.1422758015
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/13.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/13.edn_disable.2434543488
Short name T88
Test name
Test status
Simulation time 14686637 ps
CPU time 0.81 seconds
Started Aug 23 05:46:29 PM UTC 24
Finished Aug 23 05:46:32 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434543488 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2434543488
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/13.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/13.edn_err.3809909767
Short name T372
Test name
Test status
Simulation time 22259405 ps
CPU time 0.76 seconds
Started Aug 23 05:46:29 PM UTC 24
Finished Aug 23 05:46:32 PM UTC 24
Peak memory 228252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809909767 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 13.edn_err.3809909767
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/13.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/13.edn_genbits.1460046699
Short name T78
Test name
Test status
Simulation time 215006817 ps
CPU time 2.02 seconds
Started Aug 23 05:46:27 PM UTC 24
Finished Aug 23 05:46:31 PM UTC 24
Peak memory 231644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460046699 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1460046699
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/13.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/13.edn_smoke.873322244
Short name T244
Test name
Test status
Simulation time 40014018 ps
CPU time 0.83 seconds
Started Aug 23 05:46:27 PM UTC 24
Finished Aug 23 05:46:29 PM UTC 24
Peak memory 216016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873322244 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 13.edn_smoke.873322244
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/13.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/13.edn_stress_all.1556123788
Short name T260
Test name
Test status
Simulation time 521424516 ps
CPU time 3.02 seconds
Started Aug 23 05:46:27 PM UTC 24
Finished Aug 23 05:46:32 PM UTC 24
Peak memory 229776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556123788 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1556123788
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/13.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/13.edn_stress_all_with_rand_reset.3043086810
Short name T472
Test name
Test status
Simulation time 3298931637 ps
CPU time 65.82 seconds
Started Aug 23 05:46:27 PM UTC 24
Finished Aug 23 05:47:35 PM UTC 24
Peak memory 234212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3043086810 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all
_with_rand_reset.3043086810
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/13.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/130.edn_alert.3207074664
Short name T760
Test name
Test status
Simulation time 30213950 ps
CPU time 1.12 seconds
Started Aug 23 05:49:22 PM UTC 24
Finished Aug 23 05:49:24 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207074664 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 130.edn_alert.3207074664
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/130.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/130.edn_genbits.154129093
Short name T759
Test name
Test status
Simulation time 37406047 ps
CPU time 1.18 seconds
Started Aug 23 05:49:22 PM UTC 24
Finished Aug 23 05:49:24 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154129093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 130.edn_genbits.154129093
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/130.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/131.edn_alert.3732462023
Short name T763
Test name
Test status
Simulation time 29489739 ps
CPU time 1.07 seconds
Started Aug 23 05:49:23 PM UTC 24
Finished Aug 23 05:49:25 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732462023 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 131.edn_alert.3732462023
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/131.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/131.edn_genbits.2443247127
Short name T761
Test name
Test status
Simulation time 42693023 ps
CPU time 1.27 seconds
Started Aug 23 05:49:22 PM UTC 24
Finished Aug 23 05:49:24 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443247127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2443247127
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/131.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/132.edn_alert.2321875177
Short name T765
Test name
Test status
Simulation time 96631600 ps
CPU time 1.08 seconds
Started Aug 23 05:49:23 PM UTC 24
Finished Aug 23 05:49:25 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321875177 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 132.edn_alert.2321875177
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/132.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/132.edn_genbits.2342485248
Short name T781
Test name
Test status
Simulation time 718598647 ps
CPU time 3.78 seconds
Started Aug 23 05:49:23 PM UTC 24
Finished Aug 23 05:49:28 PM UTC 24
Peak memory 231508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342485248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2342485248
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/132.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/133.edn_alert.2674394128
Short name T762
Test name
Test status
Simulation time 35337204 ps
CPU time 0.96 seconds
Started Aug 23 05:49:23 PM UTC 24
Finished Aug 23 05:49:25 PM UTC 24
Peak memory 228500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674394128 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 133.edn_alert.2674394128
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/133.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/133.edn_genbits.1937087298
Short name T768
Test name
Test status
Simulation time 53196090 ps
CPU time 1.46 seconds
Started Aug 23 05:49:23 PM UTC 24
Finished Aug 23 05:49:26 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937087298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1937087298
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/133.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/134.edn_alert.4191313741
Short name T764
Test name
Test status
Simulation time 28414030 ps
CPU time 1.03 seconds
Started Aug 23 05:49:23 PM UTC 24
Finished Aug 23 05:49:25 PM UTC 24
Peak memory 228608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191313741 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 134.edn_alert.4191313741
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/134.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/134.edn_genbits.1666235589
Short name T766
Test name
Test status
Simulation time 65253758 ps
CPU time 0.98 seconds
Started Aug 23 05:49:23 PM UTC 24
Finished Aug 23 05:49:25 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666235589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 134.edn_genbits.1666235589
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/134.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/135.edn_alert.3656084600
Short name T769
Test name
Test status
Simulation time 82689136 ps
CPU time 1 seconds
Started Aug 23 05:49:24 PM UTC 24
Finished Aug 23 05:49:26 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656084600 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 135.edn_alert.3656084600
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/135.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/135.edn_genbits.1107904697
Short name T767
Test name
Test status
Simulation time 113528275 ps
CPU time 1.23 seconds
Started Aug 23 05:49:23 PM UTC 24
Finished Aug 23 05:49:26 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107904697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 135.edn_genbits.1107904697
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/135.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/136.edn_alert.2314759484
Short name T771
Test name
Test status
Simulation time 47430517 ps
CPU time 0.97 seconds
Started Aug 23 05:49:24 PM UTC 24
Finished Aug 23 05:49:26 PM UTC 24
Peak memory 230320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314759484 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 136.edn_alert.2314759484
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/136.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/136.edn_genbits.3034585202
Short name T774
Test name
Test status
Simulation time 101706785 ps
CPU time 1.26 seconds
Started Aug 23 05:49:24 PM UTC 24
Finished Aug 23 05:49:27 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034585202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3034585202
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/136.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/137.edn_alert.1452657204
Short name T773
Test name
Test status
Simulation time 275714340 ps
CPU time 1.18 seconds
Started Aug 23 05:49:24 PM UTC 24
Finished Aug 23 05:49:27 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452657204 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 137.edn_alert.1452657204
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/137.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/137.edn_genbits.1641293134
Short name T770
Test name
Test status
Simulation time 61072561 ps
CPU time 1.06 seconds
Started Aug 23 05:49:24 PM UTC 24
Finished Aug 23 05:49:26 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641293134 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1641293134
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/137.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/138.edn_alert.2132542955
Short name T776
Test name
Test status
Simulation time 48796274 ps
CPU time 1.03 seconds
Started Aug 23 05:49:25 PM UTC 24
Finished Aug 23 05:49:27 PM UTC 24
Peak memory 229888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132542955 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 138.edn_alert.2132542955
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/138.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/138.edn_genbits.1836986345
Short name T772
Test name
Test status
Simulation time 117682635 ps
CPU time 1.04 seconds
Started Aug 23 05:49:24 PM UTC 24
Finished Aug 23 05:49:26 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836986345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1836986345
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/138.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/139.edn_alert.4094941443
Short name T780
Test name
Test status
Simulation time 311193862 ps
CPU time 1.21 seconds
Started Aug 23 05:49:25 PM UTC 24
Finished Aug 23 05:49:28 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094941443 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 139.edn_alert.4094941443
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/139.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/139.edn_genbits.3687809109
Short name T775
Test name
Test status
Simulation time 80941699 ps
CPU time 1.02 seconds
Started Aug 23 05:49:25 PM UTC 24
Finished Aug 23 05:49:27 PM UTC 24
Peak memory 227864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687809109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3687809109
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/139.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/14.edn_alert.1344564014
Short name T79
Test name
Test status
Simulation time 60139726 ps
CPU time 0.99 seconds
Started Aug 23 05:46:32 PM UTC 24
Finished Aug 23 05:46:34 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344564014 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 14.edn_alert.1344564014
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/14.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/14.edn_alert_test.3967705431
Short name T376
Test name
Test status
Simulation time 16243021 ps
CPU time 0.84 seconds
Started Aug 23 05:46:32 PM UTC 24
Finished Aug 23 05:46:34 PM UTC 24
Peak memory 226904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967705431 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3967705431
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/14.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/14.edn_disable.1305093806
Short name T375
Test name
Test status
Simulation time 22193080 ps
CPU time 0.76 seconds
Started Aug 23 05:46:32 PM UTC 24
Finished Aug 23 05:46:34 PM UTC 24
Peak memory 226288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305093806 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1305093806
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/14.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/14.edn_disable_auto_req_mode.2285317781
Short name T378
Test name
Test status
Simulation time 29125069 ps
CPU time 0.97 seconds
Started Aug 23 05:46:32 PM UTC 24
Finished Aug 23 05:46:34 PM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285317781 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable_auto_req_mode.2285317781
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/14.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/14.edn_err.922416807
Short name T197
Test name
Test status
Simulation time 66295991 ps
CPU time 0.78 seconds
Started Aug 23 05:46:32 PM UTC 24
Finished Aug 23 05:46:34 PM UTC 24
Peak memory 237144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922416807 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 14.edn_err.922416807
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/14.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/14.edn_genbits.3724391221
Short name T310
Test name
Test status
Simulation time 98764874 ps
CPU time 0.94 seconds
Started Aug 23 05:46:31 PM UTC 24
Finished Aug 23 05:46:34 PM UTC 24
Peak memory 228004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724391221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3724391221
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/14.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/14.edn_intr.122828285
Short name T374
Test name
Test status
Simulation time 46662717 ps
CPU time 0.72 seconds
Started Aug 23 05:46:32 PM UTC 24
Finished Aug 23 05:46:34 PM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122828285 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 14.edn_intr.122828285
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/14.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/14.edn_smoke.2336994589
Short name T373
Test name
Test status
Simulation time 99616397 ps
CPU time 0.79 seconds
Started Aug 23 05:46:29 PM UTC 24
Finished Aug 23 05:46:32 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336994589 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 14.edn_smoke.2336994589
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/14.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/14.edn_stress_all.4157143296
Short name T380
Test name
Test status
Simulation time 227714755 ps
CPU time 4 seconds
Started Aug 23 05:46:31 PM UTC 24
Finished Aug 23 05:46:37 PM UTC 24
Peak memory 229292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157143296 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.4157143296
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/14.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/14.edn_stress_all_with_rand_reset.3971274611
Short name T604
Test name
Test status
Simulation time 5985404723 ps
CPU time 120.86 seconds
Started Aug 23 05:46:32 PM UTC 24
Finished Aug 23 05:48:35 PM UTC 24
Peak memory 229844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3971274611 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all
_with_rand_reset.3971274611
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/14.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/140.edn_alert.2241612999
Short name T778
Test name
Test status
Simulation time 40800481 ps
CPU time 0.99 seconds
Started Aug 23 05:49:25 PM UTC 24
Finished Aug 23 05:49:28 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241612999 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 140.edn_alert.2241612999
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/140.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/140.edn_genbits.2355917445
Short name T777
Test name
Test status
Simulation time 42913198 ps
CPU time 0.99 seconds
Started Aug 23 05:49:25 PM UTC 24
Finished Aug 23 05:49:28 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355917445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2355917445
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/140.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/141.edn_genbits.1660652297
Short name T779
Test name
Test status
Simulation time 63767495 ps
CPU time 1.12 seconds
Started Aug 23 05:49:25 PM UTC 24
Finished Aug 23 05:49:28 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660652297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1660652297
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/141.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/142.edn_alert.2742044547
Short name T783
Test name
Test status
Simulation time 22486032 ps
CPU time 0.97 seconds
Started Aug 23 05:49:27 PM UTC 24
Finished Aug 23 05:49:29 PM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742044547 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 142.edn_alert.2742044547
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/142.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/142.edn_genbits.1022538479
Short name T782
Test name
Test status
Simulation time 88195239 ps
CPU time 0.99 seconds
Started Aug 23 05:49:26 PM UTC 24
Finished Aug 23 05:49:29 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022538479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1022538479
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/142.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/143.edn_alert.3557902140
Short name T785
Test name
Test status
Simulation time 58483969 ps
CPU time 0.94 seconds
Started Aug 23 05:49:27 PM UTC 24
Finished Aug 23 05:49:29 PM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557902140 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 143.edn_alert.3557902140
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/143.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/143.edn_genbits.2326938634
Short name T786
Test name
Test status
Simulation time 50573365 ps
CPU time 1.16 seconds
Started Aug 23 05:49:27 PM UTC 24
Finished Aug 23 05:49:29 PM UTC 24
Peak memory 228280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326938634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2326938634
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/143.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/144.edn_alert.1870157104
Short name T790
Test name
Test status
Simulation time 26751567 ps
CPU time 1.06 seconds
Started Aug 23 05:49:28 PM UTC 24
Finished Aug 23 05:49:30 PM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870157104 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 144.edn_alert.1870157104
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/144.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/144.edn_genbits.4017384206
Short name T787
Test name
Test status
Simulation time 143043754 ps
CPU time 1.41 seconds
Started Aug 23 05:49:27 PM UTC 24
Finished Aug 23 05:49:29 PM UTC 24
Peak memory 230664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017384206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 144.edn_genbits.4017384206
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/144.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/145.edn_genbits.1027464739
Short name T788
Test name
Test status
Simulation time 71026007 ps
CPU time 0.91 seconds
Started Aug 23 05:49:28 PM UTC 24
Finished Aug 23 05:49:30 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027464739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1027464739
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/145.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/146.edn_alert.418431372
Short name T789
Test name
Test status
Simulation time 41140703 ps
CPU time 0.95 seconds
Started Aug 23 05:49:28 PM UTC 24
Finished Aug 23 05:49:30 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418431372 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 146.edn_alert.418431372
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/146.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/147.edn_alert.1691694651
Short name T791
Test name
Test status
Simulation time 26315639 ps
CPU time 1.01 seconds
Started Aug 23 05:49:28 PM UTC 24
Finished Aug 23 05:49:30 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691694651 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 147.edn_alert.1691694651
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/147.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/147.edn_genbits.2879558741
Short name T792
Test name
Test status
Simulation time 69920786 ps
CPU time 1.03 seconds
Started Aug 23 05:49:28 PM UTC 24
Finished Aug 23 05:49:30 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879558741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 147.edn_genbits.2879558741
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/147.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/148.edn_alert.685252301
Short name T796
Test name
Test status
Simulation time 50203722 ps
CPU time 1.08 seconds
Started Aug 23 05:49:29 PM UTC 24
Finished Aug 23 05:49:31 PM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685252301 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 148.edn_alert.685252301
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/148.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/148.edn_genbits.1394099534
Short name T793
Test name
Test status
Simulation time 126442620 ps
CPU time 1.18 seconds
Started Aug 23 05:49:28 PM UTC 24
Finished Aug 23 05:49:30 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394099534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 148.edn_genbits.1394099534
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/148.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/149.edn_alert.1778445480
Short name T795
Test name
Test status
Simulation time 36031016 ps
CPU time 1.03 seconds
Started Aug 23 05:49:29 PM UTC 24
Finished Aug 23 05:49:31 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778445480 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 149.edn_alert.1778445480
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/149.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/149.edn_genbits.1997151263
Short name T805
Test name
Test status
Simulation time 69642308 ps
CPU time 2.41 seconds
Started Aug 23 05:49:29 PM UTC 24
Finished Aug 23 05:49:32 PM UTC 24
Peak memory 231568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997151263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1997151263
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/149.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/15.edn_alert.741136514
Short name T129
Test name
Test status
Simulation time 43347313 ps
CPU time 1.02 seconds
Started Aug 23 05:46:34 PM UTC 24
Finished Aug 23 05:46:36 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741136514 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 15.edn_alert.741136514
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/15.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/15.edn_alert_test.106390674
Short name T382
Test name
Test status
Simulation time 15913168 ps
CPU time 0.82 seconds
Started Aug 23 05:46:36 PM UTC 24
Finished Aug 23 05:46:38 PM UTC 24
Peak memory 215968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106390674 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.106390674
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/15.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/15.edn_err.2289792805
Short name T165
Test name
Test status
Simulation time 73379186 ps
CPU time 0.75 seconds
Started Aug 23 05:46:34 PM UTC 24
Finished Aug 23 05:46:36 PM UTC 24
Peak memory 227944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289792805 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 15.edn_err.2289792805
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/15.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/15.edn_intr.420375039
Short name T379
Test name
Test status
Simulation time 24706200 ps
CPU time 0.83 seconds
Started Aug 23 05:46:34 PM UTC 24
Finished Aug 23 05:46:36 PM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420375039 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 15.edn_intr.420375039
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/15.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/15.edn_smoke.4242605515
Short name T377
Test name
Test status
Simulation time 30892651 ps
CPU time 0.84 seconds
Started Aug 23 05:46:32 PM UTC 24
Finished Aug 23 05:46:34 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242605515 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 15.edn_smoke.4242605515
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/15.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/15.edn_stress_all.3201420910
Short name T261
Test name
Test status
Simulation time 2703807446 ps
CPU time 3.61 seconds
Started Aug 23 05:46:34 PM UTC 24
Finished Aug 23 05:46:39 PM UTC 24
Peak memory 229860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201420910 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.3201420910
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/15.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/15.edn_stress_all_with_rand_reset.4012975661
Short name T238
Test name
Test status
Simulation time 4224918528 ps
CPU time 41.52 seconds
Started Aug 23 05:46:34 PM UTC 24
Finished Aug 23 05:47:17 PM UTC 24
Peak memory 229720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=4012975661 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all
_with_rand_reset.4012975661
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/15.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/150.edn_alert.3179426049
Short name T797
Test name
Test status
Simulation time 25370978 ps
CPU time 1.02 seconds
Started Aug 23 05:49:29 PM UTC 24
Finished Aug 23 05:49:31 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179426049 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 150.edn_alert.3179426049
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/150.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/150.edn_genbits.1171510716
Short name T798
Test name
Test status
Simulation time 33974269 ps
CPU time 1.18 seconds
Started Aug 23 05:49:29 PM UTC 24
Finished Aug 23 05:49:31 PM UTC 24
Peak memory 228352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171510716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 150.edn_genbits.1171510716
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/150.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/151.edn_alert.4262131836
Short name T800
Test name
Test status
Simulation time 28652963 ps
CPU time 1.09 seconds
Started Aug 23 05:49:29 PM UTC 24
Finished Aug 23 05:49:31 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262131836 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 151.edn_alert.4262131836
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/151.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/151.edn_genbits.4111932438
Short name T806
Test name
Test status
Simulation time 74181361 ps
CPU time 2.31 seconds
Started Aug 23 05:49:29 PM UTC 24
Finished Aug 23 05:49:33 PM UTC 24
Peak memory 229508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111932438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 151.edn_genbits.4111932438
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/151.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/152.edn_alert.1538306645
Short name T801
Test name
Test status
Simulation time 168188902 ps
CPU time 1.12 seconds
Started Aug 23 05:49:29 PM UTC 24
Finished Aug 23 05:49:31 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538306645 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 152.edn_alert.1538306645
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/152.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/152.edn_genbits.408445340
Short name T799
Test name
Test status
Simulation time 166652813 ps
CPU time 1.09 seconds
Started Aug 23 05:49:29 PM UTC 24
Finished Aug 23 05:49:31 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408445340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 152.edn_genbits.408445340
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/152.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/153.edn_alert.3948023873
Short name T276
Test name
Test status
Simulation time 46675274 ps
CPU time 1 seconds
Started Aug 23 05:49:30 PM UTC 24
Finished Aug 23 05:49:32 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948023873 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 153.edn_alert.3948023873
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/153.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/153.edn_genbits.892690304
Short name T802
Test name
Test status
Simulation time 71432417 ps
CPU time 0.95 seconds
Started Aug 23 05:49:30 PM UTC 24
Finished Aug 23 05:49:32 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892690304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 153.edn_genbits.892690304
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/153.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/154.edn_alert.973805093
Short name T804
Test name
Test status
Simulation time 42560443 ps
CPU time 0.95 seconds
Started Aug 23 05:49:30 PM UTC 24
Finished Aug 23 05:49:32 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973805093 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 154.edn_alert.973805093
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/154.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/154.edn_genbits.2183353974
Short name T807
Test name
Test status
Simulation time 57269969 ps
CPU time 1.15 seconds
Started Aug 23 05:49:30 PM UTC 24
Finished Aug 23 05:49:33 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183353974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2183353974
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/154.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/155.edn_alert.861736790
Short name T803
Test name
Test status
Simulation time 41452106 ps
CPU time 1 seconds
Started Aug 23 05:49:30 PM UTC 24
Finished Aug 23 05:49:32 PM UTC 24
Peak memory 228436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861736790 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 155.edn_alert.861736790
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/155.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/155.edn_genbits.2735957926
Short name T808
Test name
Test status
Simulation time 56783594 ps
CPU time 1.13 seconds
Started Aug 23 05:49:30 PM UTC 24
Finished Aug 23 05:49:33 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735957926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2735957926
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/155.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/156.edn_alert.3646372052
Short name T809
Test name
Test status
Simulation time 27252443 ps
CPU time 1.02 seconds
Started Aug 23 05:49:31 PM UTC 24
Finished Aug 23 05:49:34 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646372052 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 156.edn_alert.3646372052
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/156.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/156.edn_genbits.3912263845
Short name T814
Test name
Test status
Simulation time 96317009 ps
CPU time 2.55 seconds
Started Aug 23 05:49:31 PM UTC 24
Finished Aug 23 05:49:35 PM UTC 24
Peak memory 231572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912263845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3912263845
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/156.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/157.edn_alert.1513441350
Short name T810
Test name
Test status
Simulation time 36315776 ps
CPU time 0.94 seconds
Started Aug 23 05:49:31 PM UTC 24
Finished Aug 23 05:49:34 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513441350 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 157.edn_alert.1513441350
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/157.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/157.edn_genbits.4024361197
Short name T812
Test name
Test status
Simulation time 36341025 ps
CPU time 1.27 seconds
Started Aug 23 05:49:31 PM UTC 24
Finished Aug 23 05:49:34 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024361197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 157.edn_genbits.4024361197
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/157.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/158.edn_alert.2712701864
Short name T811
Test name
Test status
Simulation time 22011474 ps
CPU time 0.95 seconds
Started Aug 23 05:49:31 PM UTC 24
Finished Aug 23 05:49:34 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712701864 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 158.edn_alert.2712701864
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/158.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/158.edn_genbits.3582199516
Short name T813
Test name
Test status
Simulation time 40547170 ps
CPU time 1.35 seconds
Started Aug 23 05:49:31 PM UTC 24
Finished Aug 23 05:49:34 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582199516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 158.edn_genbits.3582199516
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/158.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/159.edn_alert.3723022470
Short name T817
Test name
Test status
Simulation time 34728475 ps
CPU time 1.01 seconds
Started Aug 23 05:49:33 PM UTC 24
Finished Aug 23 05:49:35 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723022470 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 159.edn_alert.3723022470
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/159.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/16.edn_alert.621536575
Short name T133
Test name
Test status
Simulation time 157684908 ps
CPU time 0.99 seconds
Started Aug 23 05:46:36 PM UTC 24
Finished Aug 23 05:46:39 PM UTC 24
Peak memory 226356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621536575 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 16.edn_alert.621536575
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/16.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/16.edn_alert_test.1615031192
Short name T384
Test name
Test status
Simulation time 25913297 ps
CPU time 0.77 seconds
Started Aug 23 05:46:38 PM UTC 24
Finished Aug 23 05:46:41 PM UTC 24
Peak memory 215980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615031192 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1615031192
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/16.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/16.edn_err.3140217383
Short name T198
Test name
Test status
Simulation time 29666758 ps
CPU time 0.73 seconds
Started Aug 23 05:46:36 PM UTC 24
Finished Aug 23 05:46:39 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140217383 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 16.edn_err.3140217383
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/16.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/16.edn_intr.3620154906
Short name T34
Test name
Test status
Simulation time 22672429 ps
CPU time 0.82 seconds
Started Aug 23 05:46:36 PM UTC 24
Finished Aug 23 05:46:39 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620154906 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 16.edn_intr.3620154906
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/16.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/16.edn_smoke.1770224067
Short name T381
Test name
Test status
Simulation time 26115731 ps
CPU time 0.81 seconds
Started Aug 23 05:46:36 PM UTC 24
Finished Aug 23 05:46:38 PM UTC 24
Peak memory 226144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770224067 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 16.edn_smoke.1770224067
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/16.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/16.edn_stress_all.3723889264
Short name T383
Test name
Test status
Simulation time 36685044 ps
CPU time 1.16 seconds
Started Aug 23 05:46:36 PM UTC 24
Finished Aug 23 05:46:39 PM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723889264 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3723889264
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/16.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/160.edn_alert.2306035533
Short name T816
Test name
Test status
Simulation time 40821197 ps
CPU time 0.93 seconds
Started Aug 23 05:49:33 PM UTC 24
Finished Aug 23 05:49:35 PM UTC 24
Peak memory 230364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306035533 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 160.edn_alert.2306035533
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/160.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/160.edn_genbits.1475705934
Short name T815
Test name
Test status
Simulation time 224873746 ps
CPU time 0.85 seconds
Started Aug 23 05:49:33 PM UTC 24
Finished Aug 23 05:49:35 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475705934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1475705934
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/160.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/161.edn_alert.2656180362
Short name T734
Test name
Test status
Simulation time 85957765 ps
CPU time 1 seconds
Started Aug 23 05:49:33 PM UTC 24
Finished Aug 23 05:49:35 PM UTC 24
Peak memory 226356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656180362 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 161.edn_alert.2656180362
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/161.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/161.edn_genbits.3241469921
Short name T818
Test name
Test status
Simulation time 61904370 ps
CPU time 0.91 seconds
Started Aug 23 05:49:33 PM UTC 24
Finished Aug 23 05:49:35 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241469921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 161.edn_genbits.3241469921
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/161.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/162.edn_alert.3196686249
Short name T822
Test name
Test status
Simulation time 24219561 ps
CPU time 1 seconds
Started Aug 23 05:49:34 PM UTC 24
Finished Aug 23 05:49:36 PM UTC 24
Peak memory 230288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196686249 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 162.edn_alert.3196686249
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/162.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/162.edn_genbits.2562704299
Short name T821
Test name
Test status
Simulation time 161989471 ps
CPU time 1.79 seconds
Started Aug 23 05:49:33 PM UTC 24
Finished Aug 23 05:49:36 PM UTC 24
Peak memory 230384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562704299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 162.edn_genbits.2562704299
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/162.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/163.edn_alert.56760042
Short name T824
Test name
Test status
Simulation time 28687010 ps
CPU time 1.03 seconds
Started Aug 23 05:49:34 PM UTC 24
Finished Aug 23 05:49:36 PM UTC 24
Peak memory 227860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56760042 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 163.edn_alert.56760042
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/163.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/163.edn_genbits.2829086146
Short name T819
Test name
Test status
Simulation time 20004184 ps
CPU time 0.92 seconds
Started Aug 23 05:49:34 PM UTC 24
Finished Aug 23 05:49:36 PM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829086146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2829086146
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/163.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/164.edn_alert.2153671114
Short name T825
Test name
Test status
Simulation time 27270009 ps
CPU time 1.07 seconds
Started Aug 23 05:49:34 PM UTC 24
Finished Aug 23 05:49:36 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153671114 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 164.edn_alert.2153671114
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/164.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/164.edn_genbits.1518844487
Short name T820
Test name
Test status
Simulation time 37153730 ps
CPU time 0.9 seconds
Started Aug 23 05:49:34 PM UTC 24
Finished Aug 23 05:49:36 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518844487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 164.edn_genbits.1518844487
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/164.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/165.edn_alert.3199039148
Short name T309
Test name
Test status
Simulation time 25345722 ps
CPU time 1 seconds
Started Aug 23 05:49:34 PM UTC 24
Finished Aug 23 05:49:36 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199039148 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 165.edn_alert.3199039148
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/165.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/165.edn_genbits.1506949505
Short name T823
Test name
Test status
Simulation time 44475758 ps
CPU time 0.88 seconds
Started Aug 23 05:49:34 PM UTC 24
Finished Aug 23 05:49:36 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506949505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1506949505
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/165.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/166.edn_alert.678231365
Short name T829
Test name
Test status
Simulation time 29075583 ps
CPU time 1.04 seconds
Started Aug 23 05:49:35 PM UTC 24
Finished Aug 23 05:49:37 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678231365 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 166.edn_alert.678231365
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/166.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/166.edn_genbits.373675489
Short name T826
Test name
Test status
Simulation time 89197658 ps
CPU time 0.95 seconds
Started Aug 23 05:49:35 PM UTC 24
Finished Aug 23 05:49:37 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373675489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 166.edn_genbits.373675489
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/166.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/167.edn_alert.3185878300
Short name T827
Test name
Test status
Simulation time 70449344 ps
CPU time 0.93 seconds
Started Aug 23 05:49:35 PM UTC 24
Finished Aug 23 05:49:37 PM UTC 24
Peak memory 228292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185878300 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 167.edn_alert.3185878300
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/167.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/167.edn_genbits.287616060
Short name T828
Test name
Test status
Simulation time 87904408 ps
CPU time 0.95 seconds
Started Aug 23 05:49:35 PM UTC 24
Finished Aug 23 05:49:37 PM UTC 24
Peak memory 226188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287616060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 167.edn_genbits.287616060
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/167.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/168.edn_alert.2202821989
Short name T830
Test name
Test status
Simulation time 55759090 ps
CPU time 1.11 seconds
Started Aug 23 05:49:35 PM UTC 24
Finished Aug 23 05:49:37 PM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202821989 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 168.edn_alert.2202821989
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/168.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/168.edn_genbits.4287448056
Short name T839
Test name
Test status
Simulation time 230863853 ps
CPU time 2.62 seconds
Started Aug 23 05:49:35 PM UTC 24
Finished Aug 23 05:49:39 PM UTC 24
Peak memory 231568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287448056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 168.edn_genbits.4287448056
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/168.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/169.edn_alert.3270387116
Short name T831
Test name
Test status
Simulation time 44213167 ps
CPU time 1.02 seconds
Started Aug 23 05:49:36 PM UTC 24
Finished Aug 23 05:49:39 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270387116 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 169.edn_alert.3270387116
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/169.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/169.edn_genbits.3119193549
Short name T832
Test name
Test status
Simulation time 53783721 ps
CPU time 1.04 seconds
Started Aug 23 05:49:36 PM UTC 24
Finished Aug 23 05:49:39 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119193549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 169.edn_genbits.3119193549
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/169.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/17.edn_alert.3091994021
Short name T189
Test name
Test status
Simulation time 115063345 ps
CPU time 0.96 seconds
Started Aug 23 05:46:40 PM UTC 24
Finished Aug 23 05:46:42 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091994021 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 17.edn_alert.3091994021
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/17.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/17.edn_alert_test.1087212305
Short name T387
Test name
Test status
Simulation time 40460134 ps
CPU time 0.73 seconds
Started Aug 23 05:46:40 PM UTC 24
Finished Aug 23 05:46:42 PM UTC 24
Peak memory 217044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087212305 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.1087212305
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/17.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/17.edn_disable.2069070806
Short name T388
Test name
Test status
Simulation time 12096819 ps
CPU time 0.82 seconds
Started Aug 23 05:46:40 PM UTC 24
Finished Aug 23 05:46:42 PM UTC 24
Peak memory 226344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069070806 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2069070806
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/17.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/17.edn_disable_auto_req_mode.3121083282
Short name T391
Test name
Test status
Simulation time 59414120 ps
CPU time 1.01 seconds
Started Aug 23 05:46:40 PM UTC 24
Finished Aug 23 05:46:42 PM UTC 24
Peak memory 228112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121083282 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable_auto_req_mode.3121083282
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/17.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/17.edn_err.2407259561
Short name T390
Test name
Test status
Simulation time 19582066 ps
CPU time 0.98 seconds
Started Aug 23 05:46:40 PM UTC 24
Finished Aug 23 05:46:42 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407259561 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 17.edn_err.2407259561
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/17.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/17.edn_genbits.710529242
Short name T386
Test name
Test status
Simulation time 58253233 ps
CPU time 1.12 seconds
Started Aug 23 05:46:38 PM UTC 24
Finished Aug 23 05:46:41 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710529242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.edn_genbits.710529242
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/17.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/17.edn_smoke.2065976543
Short name T385
Test name
Test status
Simulation time 43029861 ps
CPU time 0.77 seconds
Started Aug 23 05:46:38 PM UTC 24
Finished Aug 23 05:46:41 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065976543 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 17.edn_smoke.2065976543
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/17.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/17.edn_stress_all.1949442937
Short name T322
Test name
Test status
Simulation time 1610193718 ps
CPU time 2.67 seconds
Started Aug 23 05:46:39 PM UTC 24
Finished Aug 23 05:46:43 PM UTC 24
Peak memory 229648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949442937 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1949442937
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/17.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/17.edn_stress_all_with_rand_reset.1155261545
Short name T348
Test name
Test status
Simulation time 3327244203 ps
CPU time 77.76 seconds
Started Aug 23 05:46:40 PM UTC 24
Finished Aug 23 05:47:59 PM UTC 24
Peak memory 230136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1155261545 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all
_with_rand_reset.1155261545
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/17.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/170.edn_alert.4028151975
Short name T834
Test name
Test status
Simulation time 42610050 ps
CPU time 0.99 seconds
Started Aug 23 05:49:36 PM UTC 24
Finished Aug 23 05:49:39 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028151975 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 170.edn_alert.4028151975
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/170.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/170.edn_genbits.3865495290
Short name T836
Test name
Test status
Simulation time 42992492 ps
CPU time 1.3 seconds
Started Aug 23 05:49:36 PM UTC 24
Finished Aug 23 05:49:39 PM UTC 24
Peak memory 230604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865495290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 170.edn_genbits.3865495290
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/170.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/171.edn_alert.3959186071
Short name T835
Test name
Test status
Simulation time 28427387 ps
CPU time 1.07 seconds
Started Aug 23 05:49:36 PM UTC 24
Finished Aug 23 05:49:39 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959186071 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 171.edn_alert.3959186071
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/171.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/171.edn_genbits.170619853
Short name T837
Test name
Test status
Simulation time 92277792 ps
CPU time 1.25 seconds
Started Aug 23 05:49:36 PM UTC 24
Finished Aug 23 05:49:39 PM UTC 24
Peak memory 228180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170619853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 171.edn_genbits.170619853
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/171.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/172.edn_alert.2377570470
Short name T833
Test name
Test status
Simulation time 66850116 ps
CPU time 0.87 seconds
Started Aug 23 05:49:36 PM UTC 24
Finished Aug 23 05:49:39 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377570470 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 172.edn_alert.2377570470
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/172.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/172.edn_genbits.1826538348
Short name T838
Test name
Test status
Simulation time 118277499 ps
CPU time 1.33 seconds
Started Aug 23 05:49:36 PM UTC 24
Finished Aug 23 05:49:39 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826538348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 172.edn_genbits.1826538348
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/172.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/173.edn_genbits.3788445461
Short name T346
Test name
Test status
Simulation time 98258667 ps
CPU time 1.62 seconds
Started Aug 23 05:49:36 PM UTC 24
Finished Aug 23 05:49:39 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788445461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 173.edn_genbits.3788445461
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/173.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/174.edn_alert.4097800323
Short name T841
Test name
Test status
Simulation time 22378479 ps
CPU time 1.02 seconds
Started Aug 23 05:49:38 PM UTC 24
Finished Aug 23 05:49:40 PM UTC 24
Peak memory 228072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097800323 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 174.edn_alert.4097800323
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/174.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/174.edn_genbits.1946660558
Short name T840
Test name
Test status
Simulation time 105964582 ps
CPU time 0.92 seconds
Started Aug 23 05:49:38 PM UTC 24
Finished Aug 23 05:49:40 PM UTC 24
Peak memory 228200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946660558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 174.edn_genbits.1946660558
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/174.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/175.edn_alert.1238596780
Short name T846
Test name
Test status
Simulation time 28690701 ps
CPU time 1.01 seconds
Started Aug 23 05:49:38 PM UTC 24
Finished Aug 23 05:49:40 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238596780 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 175.edn_alert.1238596780
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/175.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/175.edn_genbits.4265937834
Short name T845
Test name
Test status
Simulation time 121151174 ps
CPU time 1.01 seconds
Started Aug 23 05:49:38 PM UTC 24
Finished Aug 23 05:49:40 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265937834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 175.edn_genbits.4265937834
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/175.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/176.edn_alert.3512253261
Short name T844
Test name
Test status
Simulation time 24404652 ps
CPU time 0.96 seconds
Started Aug 23 05:49:38 PM UTC 24
Finished Aug 23 05:49:40 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512253261 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 176.edn_alert.3512253261
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/176.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/176.edn_genbits.3024746205
Short name T843
Test name
Test status
Simulation time 27812462 ps
CPU time 0.99 seconds
Started Aug 23 05:49:38 PM UTC 24
Finished Aug 23 05:49:40 PM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024746205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 176.edn_genbits.3024746205
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/176.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/177.edn_alert.3898244525
Short name T848
Test name
Test status
Simulation time 43014563 ps
CPU time 0.96 seconds
Started Aug 23 05:49:39 PM UTC 24
Finished Aug 23 05:49:41 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898244525 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 177.edn_alert.3898244525
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/177.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/177.edn_genbits.673718714
Short name T847
Test name
Test status
Simulation time 81945358 ps
CPU time 1.12 seconds
Started Aug 23 05:49:38 PM UTC 24
Finished Aug 23 05:49:40 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673718714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 177.edn_genbits.673718714
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/177.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/178.edn_alert.1258074209
Short name T851
Test name
Test status
Simulation time 78264719 ps
CPU time 1 seconds
Started Aug 23 05:49:40 PM UTC 24
Finished Aug 23 05:49:42 PM UTC 24
Peak memory 230352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258074209 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 178.edn_alert.1258074209
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/178.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/178.edn_genbits.952904860
Short name T849
Test name
Test status
Simulation time 37981505 ps
CPU time 1.18 seconds
Started Aug 23 05:49:39 PM UTC 24
Finished Aug 23 05:49:41 PM UTC 24
Peak memory 226516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952904860 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 178.edn_genbits.952904860
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/178.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/179.edn_alert.3987205192
Short name T850
Test name
Test status
Simulation time 24898598 ps
CPU time 0.98 seconds
Started Aug 23 05:49:40 PM UTC 24
Finished Aug 23 05:49:42 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987205192 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 179.edn_alert.3987205192
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/179.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/179.edn_genbits.4186989435
Short name T852
Test name
Test status
Simulation time 71482548 ps
CPU time 1.04 seconds
Started Aug 23 05:49:40 PM UTC 24
Finished Aug 23 05:49:42 PM UTC 24
Peak memory 228148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186989435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 179.edn_genbits.4186989435
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/179.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/18.edn_alert_test.1488922647
Short name T393
Test name
Test status
Simulation time 79369210 ps
CPU time 0.67 seconds
Started Aug 23 05:46:44 PM UTC 24
Finished Aug 23 05:46:46 PM UTC 24
Peak memory 216264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488922647 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.1488922647
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/18.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/18.edn_disable.1378399576
Short name T394
Test name
Test status
Simulation time 28494724 ps
CPU time 0.78 seconds
Started Aug 23 05:46:44 PM UTC 24
Finished Aug 23 05:46:46 PM UTC 24
Peak memory 226024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378399576 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1378399576
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/18.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/18.edn_disable_auto_req_mode.3624998759
Short name T396
Test name
Test status
Simulation time 25650361 ps
CPU time 1.06 seconds
Started Aug 23 05:46:44 PM UTC 24
Finished Aug 23 05:46:46 PM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624998759 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable_auto_req_mode.3624998759
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/18.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/18.edn_err.2064915831
Short name T217
Test name
Test status
Simulation time 24354275 ps
CPU time 0.83 seconds
Started Aug 23 05:46:42 PM UTC 24
Finished Aug 23 05:46:44 PM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064915831 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 18.edn_err.2064915831
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/18.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/18.edn_genbits.1540922391
Short name T313
Test name
Test status
Simulation time 58821043 ps
CPU time 1.24 seconds
Started Aug 23 05:46:40 PM UTC 24
Finished Aug 23 05:46:42 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540922391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1540922391
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/18.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/18.edn_intr.3577247877
Short name T392
Test name
Test status
Simulation time 21090703 ps
CPU time 0.84 seconds
Started Aug 23 05:46:42 PM UTC 24
Finished Aug 23 05:46:44 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577247877 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 18.edn_intr.3577247877
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/18.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/18.edn_smoke.4052443498
Short name T389
Test name
Test status
Simulation time 16376862 ps
CPU time 0.82 seconds
Started Aug 23 05:46:40 PM UTC 24
Finished Aug 23 05:46:42 PM UTC 24
Peak memory 226040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052443498 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 18.edn_smoke.4052443498
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/18.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/18.edn_stress_all_with_rand_reset.3539381473
Short name T540
Test name
Test status
Simulation time 12552947622 ps
CPU time 78.53 seconds
Started Aug 23 05:46:42 PM UTC 24
Finished Aug 23 05:48:02 PM UTC 24
Peak memory 230008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3539381473 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all
_with_rand_reset.3539381473
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/18.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/180.edn_alert.2303906958
Short name T853
Test name
Test status
Simulation time 89855736 ps
CPU time 1.02 seconds
Started Aug 23 05:49:40 PM UTC 24
Finished Aug 23 05:49:42 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303906958 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 180.edn_alert.2303906958
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/180.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/180.edn_genbits.3828567488
Short name T857
Test name
Test status
Simulation time 56029286 ps
CPU time 1.16 seconds
Started Aug 23 05:49:40 PM UTC 24
Finished Aug 23 05:49:42 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828567488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3828567488
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/180.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/181.edn_alert.1520803814
Short name T855
Test name
Test status
Simulation time 49843477 ps
CPU time 0.98 seconds
Started Aug 23 05:49:40 PM UTC 24
Finished Aug 23 05:49:42 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520803814 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 181.edn_alert.1520803814
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/181.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/181.edn_genbits.3474998254
Short name T854
Test name
Test status
Simulation time 51874287 ps
CPU time 1.04 seconds
Started Aug 23 05:49:40 PM UTC 24
Finished Aug 23 05:49:42 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474998254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3474998254
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/181.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/182.edn_alert.2227211954
Short name T858
Test name
Test status
Simulation time 39175014 ps
CPU time 0.94 seconds
Started Aug 23 05:49:40 PM UTC 24
Finished Aug 23 05:49:42 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227211954 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 182.edn_alert.2227211954
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/182.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/182.edn_genbits.3440570905
Short name T859
Test name
Test status
Simulation time 99090450 ps
CPU time 1.82 seconds
Started Aug 23 05:49:40 PM UTC 24
Finished Aug 23 05:49:43 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440570905 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 182.edn_genbits.3440570905
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/182.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/183.edn_alert.1032426769
Short name T860
Test name
Test status
Simulation time 81946437 ps
CPU time 0.95 seconds
Started Aug 23 05:49:41 PM UTC 24
Finished Aug 23 05:49:43 PM UTC 24
Peak memory 232520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032426769 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 183.edn_alert.1032426769
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/183.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/183.edn_genbits.690899671
Short name T856
Test name
Test status
Simulation time 36083857 ps
CPU time 0.94 seconds
Started Aug 23 05:49:40 PM UTC 24
Finished Aug 23 05:49:42 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690899671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 183.edn_genbits.690899671
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/183.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/184.edn_alert.737325758
Short name T861
Test name
Test status
Simulation time 27505295 ps
CPU time 1.06 seconds
Started Aug 23 05:49:41 PM UTC 24
Finished Aug 23 05:49:43 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737325758 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 184.edn_alert.737325758
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/184.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/184.edn_genbits.1384567083
Short name T862
Test name
Test status
Simulation time 201705239 ps
CPU time 1.15 seconds
Started Aug 23 05:49:41 PM UTC 24
Finished Aug 23 05:49:44 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384567083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1384567083
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/184.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/185.edn_alert.3495693222
Short name T863
Test name
Test status
Simulation time 27030981 ps
CPU time 0.99 seconds
Started Aug 23 05:49:41 PM UTC 24
Finished Aug 23 05:49:44 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495693222 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 185.edn_alert.3495693222
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/185.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/185.edn_genbits.1290860648
Short name T347
Test name
Test status
Simulation time 81624483 ps
CPU time 2.41 seconds
Started Aug 23 05:49:41 PM UTC 24
Finished Aug 23 05:49:45 PM UTC 24
Peak memory 229496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290860648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 185.edn_genbits.1290860648
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/185.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/186.edn_alert.1185711076
Short name T865
Test name
Test status
Simulation time 80472950 ps
CPU time 0.99 seconds
Started Aug 23 05:49:41 PM UTC 24
Finished Aug 23 05:49:44 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185711076 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 186.edn_alert.1185711076
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/186.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/186.edn_genbits.3333837923
Short name T864
Test name
Test status
Simulation time 33257416 ps
CPU time 1.07 seconds
Started Aug 23 05:49:41 PM UTC 24
Finished Aug 23 05:49:44 PM UTC 24
Peak memory 230604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333837923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3333837923
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/186.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/187.edn_alert.3764772986
Short name T868
Test name
Test status
Simulation time 29582944 ps
CPU time 1.08 seconds
Started Aug 23 05:49:42 PM UTC 24
Finished Aug 23 05:49:45 PM UTC 24
Peak memory 226356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764772986 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 187.edn_alert.3764772986
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/187.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/187.edn_genbits.3088350683
Short name T330
Test name
Test status
Simulation time 179943535 ps
CPU time 0.97 seconds
Started Aug 23 05:49:41 PM UTC 24
Finished Aug 23 05:49:43 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088350683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3088350683
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/187.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/188.edn_alert.1717978133
Short name T869
Test name
Test status
Simulation time 86440408 ps
CPU time 1.07 seconds
Started Aug 23 05:49:43 PM UTC 24
Finished Aug 23 05:49:45 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717978133 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 188.edn_alert.1717978133
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/188.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/188.edn_genbits.2616760316
Short name T866
Test name
Test status
Simulation time 102309409 ps
CPU time 0.97 seconds
Started Aug 23 05:49:42 PM UTC 24
Finished Aug 23 05:49:45 PM UTC 24
Peak memory 228356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616760316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 188.edn_genbits.2616760316
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/188.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/189.edn_alert.2462349504
Short name T867
Test name
Test status
Simulation time 69194630 ps
CPU time 0.91 seconds
Started Aug 23 05:49:43 PM UTC 24
Finished Aug 23 05:49:45 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462349504 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 189.edn_alert.2462349504
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/189.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/189.edn_genbits.3419044895
Short name T870
Test name
Test status
Simulation time 115055208 ps
CPU time 1.29 seconds
Started Aug 23 05:49:43 PM UTC 24
Finished Aug 23 05:49:45 PM UTC 24
Peak memory 228356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419044895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 189.edn_genbits.3419044895
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/189.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/19.edn_alert.3826316855
Short name T201
Test name
Test status
Simulation time 71233333 ps
CPU time 0.89 seconds
Started Aug 23 05:46:44 PM UTC 24
Finished Aug 23 05:46:46 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826316855 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 19.edn_alert.3826316855
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/19.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/19.edn_alert_test.3512122834
Short name T397
Test name
Test status
Simulation time 28218893 ps
CPU time 0.75 seconds
Started Aug 23 05:46:45 PM UTC 24
Finished Aug 23 05:46:47 PM UTC 24
Peak memory 216988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512122834 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3512122834
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/19.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/19.edn_disable_auto_req_mode.2117649772
Short name T259
Test name
Test status
Simulation time 136606872 ps
CPU time 1.01 seconds
Started Aug 23 05:46:45 PM UTC 24
Finished Aug 23 05:46:47 PM UTC 24
Peak memory 226448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117649772 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable_auto_req_mode.2117649772
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/19.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/19.edn_err.1166419887
Short name T153
Test name
Test status
Simulation time 22391222 ps
CPU time 0.95 seconds
Started Aug 23 05:46:45 PM UTC 24
Finished Aug 23 05:46:47 PM UTC 24
Peak memory 243864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166419887 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 19.edn_err.1166419887
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/19.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/19.edn_genbits.3279489262
Short name T311
Test name
Test status
Simulation time 86459327 ps
CPU time 1.22 seconds
Started Aug 23 05:46:44 PM UTC 24
Finished Aug 23 05:46:47 PM UTC 24
Peak memory 229448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279489262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3279489262
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/19.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/19.edn_intr.2822025851
Short name T135
Test name
Test status
Simulation time 19968549 ps
CPU time 0.9 seconds
Started Aug 23 05:46:44 PM UTC 24
Finished Aug 23 05:46:46 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822025851 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 19.edn_intr.2822025851
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/19.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/19.edn_smoke.279289801
Short name T395
Test name
Test status
Simulation time 29423793 ps
CPU time 0.79 seconds
Started Aug 23 05:46:44 PM UTC 24
Finished Aug 23 05:46:46 PM UTC 24
Peak memory 225360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279289801 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 19.edn_smoke.279289801
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/19.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/19.edn_stress_all.4250824798
Short name T306
Test name
Test status
Simulation time 716243729 ps
CPU time 3.61 seconds
Started Aug 23 05:46:44 PM UTC 24
Finished Aug 23 05:46:49 PM UTC 24
Peak memory 229644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250824798 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.4250824798
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/19.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/19.edn_stress_all_with_rand_reset.43748205
Short name T247
Test name
Test status
Simulation time 12246991705 ps
CPU time 61.25 seconds
Started Aug 23 05:46:44 PM UTC 24
Finished Aug 23 05:47:47 PM UTC 24
Peak memory 230120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=43748205 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_w
ith_rand_reset.43748205
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/19.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/190.edn_alert.2366967576
Short name T871
Test name
Test status
Simulation time 23840772 ps
CPU time 0.97 seconds
Started Aug 23 05:49:44 PM UTC 24
Finished Aug 23 05:49:46 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366967576 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 190.edn_alert.2366967576
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/190.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/190.edn_genbits.97898130
Short name T338
Test name
Test status
Simulation time 78671454 ps
CPU time 0.77 seconds
Started Aug 23 05:49:44 PM UTC 24
Finished Aug 23 05:49:46 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97898130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 190.edn_genbits.97898130
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/190.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/191.edn_alert.3409974297
Short name T873
Test name
Test status
Simulation time 89906889 ps
CPU time 1.06 seconds
Started Aug 23 05:49:44 PM UTC 24
Finished Aug 23 05:49:46 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409974297 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 191.edn_alert.3409974297
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/191.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/191.edn_genbits.3168000153
Short name T874
Test name
Test status
Simulation time 74787269 ps
CPU time 1.2 seconds
Started Aug 23 05:49:44 PM UTC 24
Finished Aug 23 05:49:46 PM UTC 24
Peak memory 228620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168000153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 191.edn_genbits.3168000153
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/191.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/192.edn_alert.3999882372
Short name T872
Test name
Test status
Simulation time 38080973 ps
CPU time 0.94 seconds
Started Aug 23 05:49:44 PM UTC 24
Finished Aug 23 05:49:46 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999882372 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 192.edn_alert.3999882372
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/192.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/192.edn_genbits.1325881350
Short name T875
Test name
Test status
Simulation time 25727928 ps
CPU time 1.08 seconds
Started Aug 23 05:49:44 PM UTC 24
Finished Aug 23 05:49:46 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325881350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1325881350
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/192.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/193.edn_alert.3369435822
Short name T876
Test name
Test status
Simulation time 100648848 ps
CPU time 0.96 seconds
Started Aug 23 05:49:44 PM UTC 24
Finished Aug 23 05:49:46 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369435822 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 193.edn_alert.3369435822
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/193.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/193.edn_genbits.1187629236
Short name T877
Test name
Test status
Simulation time 103602257 ps
CPU time 1.08 seconds
Started Aug 23 05:49:44 PM UTC 24
Finished Aug 23 05:49:46 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187629236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 193.edn_genbits.1187629236
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/193.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/194.edn_alert.1211070021
Short name T879
Test name
Test status
Simulation time 32075077 ps
CPU time 1.16 seconds
Started Aug 23 05:49:45 PM UTC 24
Finished Aug 23 05:49:47 PM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211070021 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 194.edn_alert.1211070021
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/194.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/194.edn_genbits.876376941
Short name T882
Test name
Test status
Simulation time 86357805 ps
CPU time 1.24 seconds
Started Aug 23 05:49:45 PM UTC 24
Finished Aug 23 05:49:47 PM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876376941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 194.edn_genbits.876376941
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/194.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/195.edn_alert.3634472921
Short name T881
Test name
Test status
Simulation time 28776172 ps
CPU time 1.1 seconds
Started Aug 23 05:49:45 PM UTC 24
Finished Aug 23 05:49:47 PM UTC 24
Peak memory 226356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634472921 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 195.edn_alert.3634472921
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/195.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/195.edn_genbits.3474988709
Short name T878
Test name
Test status
Simulation time 72274313 ps
CPU time 0.96 seconds
Started Aug 23 05:49:45 PM UTC 24
Finished Aug 23 05:49:47 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474988709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3474988709
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/195.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/196.edn_alert.3602129636
Short name T880
Test name
Test status
Simulation time 74635365 ps
CPU time 0.94 seconds
Started Aug 23 05:49:45 PM UTC 24
Finished Aug 23 05:49:47 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602129636 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 196.edn_alert.3602129636
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/196.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/196.edn_genbits.1185237241
Short name T889
Test name
Test status
Simulation time 278544703 ps
CPU time 2.72 seconds
Started Aug 23 05:49:45 PM UTC 24
Finished Aug 23 05:49:49 PM UTC 24
Peak memory 231496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185237241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 196.edn_genbits.1185237241
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/196.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/197.edn_alert.2884638138
Short name T884
Test name
Test status
Simulation time 80216619 ps
CPU time 1.01 seconds
Started Aug 23 05:49:46 PM UTC 24
Finished Aug 23 05:49:48 PM UTC 24
Peak memory 230180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884638138 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 197.edn_alert.2884638138
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/197.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/197.edn_genbits.1407715399
Short name T333
Test name
Test status
Simulation time 48026926 ps
CPU time 1.34 seconds
Started Aug 23 05:49:45 PM UTC 24
Finished Aug 23 05:49:47 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407715399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1407715399
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/197.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/198.edn_alert.3028433771
Short name T887
Test name
Test status
Simulation time 28857016 ps
CPU time 1.02 seconds
Started Aug 23 05:49:46 PM UTC 24
Finished Aug 23 05:49:48 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028433771 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 198.edn_alert.3028433771
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/198.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/198.edn_genbits.180388929
Short name T891
Test name
Test status
Simulation time 156193496 ps
CPU time 1.94 seconds
Started Aug 23 05:49:46 PM UTC 24
Finished Aug 23 05:49:49 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180388929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 198.edn_genbits.180388929
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/198.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/199.edn_genbits.2817441891
Short name T883
Test name
Test status
Simulation time 361359235 ps
CPU time 0.94 seconds
Started Aug 23 05:49:46 PM UTC 24
Finished Aug 23 05:49:48 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817441891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2817441891
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/199.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/2.edn_alert.4184432601
Short name T30
Test name
Test status
Simulation time 26368100 ps
CPU time 1.08 seconds
Started Aug 23 05:46:06 PM UTC 24
Finished Aug 23 05:46:09 PM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184432601 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 2.edn_alert.4184432601
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/2.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/2.edn_alert_test.1152352779
Short name T67
Test name
Test status
Simulation time 14848119 ps
CPU time 0.79 seconds
Started Aug 23 05:46:06 PM UTC 24
Finished Aug 23 05:46:08 PM UTC 24
Peak memory 217052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152352779 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.1152352779
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/2.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/2.edn_err.1684597569
Short name T40
Test name
Test status
Simulation time 30005989 ps
CPU time 1.03 seconds
Started Aug 23 05:46:06 PM UTC 24
Finished Aug 23 05:46:08 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684597569 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 2.edn_err.1684597569
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/2.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/2.edn_intr.1238244149
Short name T32
Test name
Test status
Simulation time 24665816 ps
CPU time 0.77 seconds
Started Aug 23 05:46:06 PM UTC 24
Finished Aug 23 05:46:08 PM UTC 24
Peak memory 228916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238244149 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 2.edn_intr.1238244149
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/2.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/2.edn_regwen.1902556510
Short name T103
Test name
Test status
Simulation time 17469890 ps
CPU time 0.88 seconds
Started Aug 23 05:46:06 PM UTC 24
Finished Aug 23 05:46:08 PM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902556510 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 2.edn_regwen.1902556510
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/2.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/2.edn_sec_cm.2857259644
Short name T21
Test name
Test status
Simulation time 500108322 ps
CPU time 6.9 seconds
Started Aug 23 05:46:06 PM UTC 24
Finished Aug 23 05:46:15 PM UTC 24
Peak memory 262496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857259644 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2857259644
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/2.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/2.edn_smoke.3693465301
Short name T69
Test name
Test status
Simulation time 20964845 ps
CPU time 0.87 seconds
Started Aug 23 05:46:06 PM UTC 24
Finished Aug 23 05:46:08 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693465301 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 2.edn_smoke.3693465301
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/2.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/2.edn_stress_all.1675550813
Short name T56
Test name
Test status
Simulation time 188571074 ps
CPU time 2.13 seconds
Started Aug 23 05:46:06 PM UTC 24
Finished Aug 23 05:46:10 PM UTC 24
Peak memory 229660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675550813 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1675550813
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/2.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/2.edn_stress_all_with_rand_reset.139230392
Short name T37
Test name
Test status
Simulation time 923192949 ps
CPU time 19.35 seconds
Started Aug 23 05:46:06 PM UTC 24
Finished Aug 23 05:46:27 PM UTC 24
Peak memory 229660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=139230392 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_w
ith_rand_reset.139230392
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/2.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/20.edn_alert.894619671
Short name T209
Test name
Test status
Simulation time 60826566 ps
CPU time 0.99 seconds
Started Aug 23 05:46:48 PM UTC 24
Finished Aug 23 05:46:50 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894619671 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 20.edn_alert.894619671
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/20.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/20.edn_alert_test.4147568113
Short name T401
Test name
Test status
Simulation time 21588773 ps
CPU time 0.72 seconds
Started Aug 23 05:46:48 PM UTC 24
Finished Aug 23 05:46:50 PM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147568113 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.4147568113
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/20.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/20.edn_disable.3626631243
Short name T234
Test name
Test status
Simulation time 13554858 ps
CPU time 0.71 seconds
Started Aug 23 05:46:48 PM UTC 24
Finished Aug 23 05:46:49 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626631243 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3626631243
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/20.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/20.edn_disable_auto_req_mode.3044541245
Short name T173
Test name
Test status
Simulation time 38257136 ps
CPU time 1.13 seconds
Started Aug 23 05:46:48 PM UTC 24
Finished Aug 23 05:46:50 PM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044541245 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable_auto_req_mode.3044541245
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/20.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/20.edn_err.3183653142
Short name T219
Test name
Test status
Simulation time 72272086 ps
CPU time 0.87 seconds
Started Aug 23 05:46:48 PM UTC 24
Finished Aug 23 05:46:50 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183653142 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 20.edn_err.3183653142
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/20.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/20.edn_genbits.1899389718
Short name T399
Test name
Test status
Simulation time 194158752 ps
CPU time 0.82 seconds
Started Aug 23 05:46:46 PM UTC 24
Finished Aug 23 05:46:49 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899389718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1899389718
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/20.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/20.edn_intr.372544066
Short name T105
Test name
Test status
Simulation time 31584967 ps
CPU time 0.75 seconds
Started Aug 23 05:46:48 PM UTC 24
Finished Aug 23 05:46:50 PM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372544066 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 20.edn_intr.372544066
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/20.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/20.edn_smoke.268516999
Short name T398
Test name
Test status
Simulation time 85354928 ps
CPU time 0.8 seconds
Started Aug 23 05:46:46 PM UTC 24
Finished Aug 23 05:46:49 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268516999 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 20.edn_smoke.268516999
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/20.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/20.edn_stress_all.3572788
Short name T400
Test name
Test status
Simulation time 162386751 ps
CPU time 1.88 seconds
Started Aug 23 05:46:46 PM UTC 24
Finished Aug 23 05:46:50 PM UTC 24
Peak memory 226512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572788 -assert nopostproc +UVM_TESTNAME=edn_st
ress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3572788
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/20.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/20.edn_stress_all_with_rand_reset.101713600
Short name T555
Test name
Test status
Simulation time 3492894350 ps
CPU time 80.82 seconds
Started Aug 23 05:46:47 PM UTC 24
Finished Aug 23 05:48:09 PM UTC 24
Peak memory 229872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=101713600 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_
with_rand_reset.101713600
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/20.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/200.edn_genbits.3944802955
Short name T890
Test name
Test status
Simulation time 226500300 ps
CPU time 1.61 seconds
Started Aug 23 05:49:46 PM UTC 24
Finished Aug 23 05:49:49 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944802955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3944802955
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/200.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/201.edn_genbits.813226762
Short name T885
Test name
Test status
Simulation time 66282024 ps
CPU time 0.9 seconds
Started Aug 23 05:49:46 PM UTC 24
Finished Aug 23 05:49:48 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813226762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 201.edn_genbits.813226762
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/201.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/202.edn_genbits.3654422201
Short name T888
Test name
Test status
Simulation time 54188468 ps
CPU time 0.98 seconds
Started Aug 23 05:49:46 PM UTC 24
Finished Aug 23 05:49:49 PM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654422201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3654422201
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/202.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/204.edn_genbits.663232682
Short name T896
Test name
Test status
Simulation time 37686086 ps
CPU time 1.37 seconds
Started Aug 23 05:49:47 PM UTC 24
Finished Aug 23 05:49:50 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663232682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 204.edn_genbits.663232682
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/204.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/205.edn_genbits.1520141250
Short name T895
Test name
Test status
Simulation time 51098263 ps
CPU time 1.2 seconds
Started Aug 23 05:49:47 PM UTC 24
Finished Aug 23 05:49:50 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520141250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1520141250
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/205.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/206.edn_genbits.277958458
Short name T892
Test name
Test status
Simulation time 54612672 ps
CPU time 1.09 seconds
Started Aug 23 05:49:47 PM UTC 24
Finished Aug 23 05:49:50 PM UTC 24
Peak memory 227904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277958458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 206.edn_genbits.277958458
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/206.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/207.edn_genbits.3366354717
Short name T894
Test name
Test status
Simulation time 29380137 ps
CPU time 1.07 seconds
Started Aug 23 05:49:47 PM UTC 24
Finished Aug 23 05:49:50 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366354717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3366354717
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/207.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/208.edn_genbits.698529980
Short name T893
Test name
Test status
Simulation time 29589856 ps
CPU time 1.06 seconds
Started Aug 23 05:49:47 PM UTC 24
Finished Aug 23 05:49:50 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698529980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 208.edn_genbits.698529980
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/208.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/209.edn_genbits.3390465230
Short name T897
Test name
Test status
Simulation time 49322712 ps
CPU time 1.33 seconds
Started Aug 23 05:49:48 PM UTC 24
Finished Aug 23 05:49:50 PM UTC 24
Peak memory 228692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390465230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 209.edn_genbits.3390465230
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/209.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/21.edn_alert.3070251472
Short name T185
Test name
Test status
Simulation time 79069552 ps
CPU time 0.95 seconds
Started Aug 23 05:46:50 PM UTC 24
Finished Aug 23 05:46:52 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070251472 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 21.edn_alert.3070251472
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/21.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/21.edn_alert_test.4285683390
Short name T403
Test name
Test status
Simulation time 24661225 ps
CPU time 0.74 seconds
Started Aug 23 05:46:51 PM UTC 24
Finished Aug 23 05:46:53 PM UTC 24
Peak memory 216320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285683390 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.4285683390
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/21.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/21.edn_disable.1350106617
Short name T404
Test name
Test status
Simulation time 36363664 ps
CPU time 0.73 seconds
Started Aug 23 05:46:51 PM UTC 24
Finished Aug 23 05:46:53 PM UTC 24
Peak memory 225972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350106617 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1350106617
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/21.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/21.edn_disable_auto_req_mode.1954881581
Short name T160
Test name
Test status
Simulation time 73755653 ps
CPU time 1.02 seconds
Started Aug 23 05:46:51 PM UTC 24
Finished Aug 23 05:46:53 PM UTC 24
Peak memory 230348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954881581 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable_auto_req_mode.1954881581
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/21.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/21.edn_err.4186281738
Short name T190
Test name
Test status
Simulation time 26937066 ps
CPU time 0.73 seconds
Started Aug 23 05:46:50 PM UTC 24
Finished Aug 23 05:46:52 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186281738 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 21.edn_err.4186281738
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/21.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/21.edn_genbits.708321952
Short name T350
Test name
Test status
Simulation time 92627624 ps
CPU time 0.96 seconds
Started Aug 23 05:46:49 PM UTC 24
Finished Aug 23 05:46:51 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708321952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_genbits.708321952
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/21.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/21.edn_smoke.3256413739
Short name T402
Test name
Test status
Simulation time 40310683 ps
CPU time 0.78 seconds
Started Aug 23 05:46:48 PM UTC 24
Finished Aug 23 05:46:50 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256413739 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 21.edn_smoke.3256413739
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/21.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/21.edn_stress_all.1164242469
Short name T406
Test name
Test status
Simulation time 156742264 ps
CPU time 2.88 seconds
Started Aug 23 05:46:50 PM UTC 24
Finished Aug 23 05:46:54 PM UTC 24
Peak memory 229456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164242469 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.1164242469
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/21.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/21.edn_stress_all_with_rand_reset.2104855909
Short name T38
Test name
Test status
Simulation time 358181520 ps
CPU time 8.86 seconds
Started Aug 23 05:46:50 PM UTC 24
Finished Aug 23 05:47:00 PM UTC 24
Peak memory 231356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2104855909 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all
_with_rand_reset.2104855909
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/21.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/210.edn_genbits.1221843607
Short name T902
Test name
Test status
Simulation time 34837939 ps
CPU time 1.26 seconds
Started Aug 23 05:49:49 PM UTC 24
Finished Aug 23 05:49:51 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221843607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 210.edn_genbits.1221843607
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/210.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/211.edn_genbits.3934999749
Short name T901
Test name
Test status
Simulation time 58128322 ps
CPU time 1.12 seconds
Started Aug 23 05:49:49 PM UTC 24
Finished Aug 23 05:49:51 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934999749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 211.edn_genbits.3934999749
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/211.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/212.edn_genbits.2685173545
Short name T898
Test name
Test status
Simulation time 97907870 ps
CPU time 1.11 seconds
Started Aug 23 05:49:49 PM UTC 24
Finished Aug 23 05:49:51 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685173545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2685173545
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/212.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/213.edn_genbits.2085576526
Short name T903
Test name
Test status
Simulation time 163422451 ps
CPU time 1.38 seconds
Started Aug 23 05:49:49 PM UTC 24
Finished Aug 23 05:49:52 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085576526 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 213.edn_genbits.2085576526
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/213.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/214.edn_genbits.456184512
Short name T900
Test name
Test status
Simulation time 90935045 ps
CPU time 1.01 seconds
Started Aug 23 05:49:49 PM UTC 24
Finished Aug 23 05:49:51 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456184512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 214.edn_genbits.456184512
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/214.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/215.edn_genbits.2640632687
Short name T899
Test name
Test status
Simulation time 24892202 ps
CPU time 0.99 seconds
Started Aug 23 05:49:49 PM UTC 24
Finished Aug 23 05:49:51 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640632687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 215.edn_genbits.2640632687
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/215.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/216.edn_genbits.4090954866
Short name T904
Test name
Test status
Simulation time 26852697 ps
CPU time 0.99 seconds
Started Aug 23 05:49:50 PM UTC 24
Finished Aug 23 05:49:52 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090954866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 216.edn_genbits.4090954866
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/216.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/217.edn_genbits.4050407397
Short name T905
Test name
Test status
Simulation time 96903957 ps
CPU time 0.96 seconds
Started Aug 23 05:49:50 PM UTC 24
Finished Aug 23 05:49:52 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050407397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 217.edn_genbits.4050407397
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/217.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/218.edn_genbits.222323984
Short name T908
Test name
Test status
Simulation time 53387001 ps
CPU time 1.44 seconds
Started Aug 23 05:49:50 PM UTC 24
Finished Aug 23 05:49:52 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222323984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 218.edn_genbits.222323984
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/218.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/219.edn_genbits.3788856538
Short name T906
Test name
Test status
Simulation time 163302538 ps
CPU time 0.93 seconds
Started Aug 23 05:49:50 PM UTC 24
Finished Aug 23 05:49:52 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788856538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 219.edn_genbits.3788856538
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/219.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/22.edn_alert.1785639404
Short name T104
Test name
Test status
Simulation time 44934087 ps
CPU time 1 seconds
Started Aug 23 05:46:52 PM UTC 24
Finished Aug 23 05:46:55 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785639404 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 22.edn_alert.1785639404
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/22.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/22.edn_alert_test.41252234
Short name T409
Test name
Test status
Simulation time 23323277 ps
CPU time 0.88 seconds
Started Aug 23 05:46:54 PM UTC 24
Finished Aug 23 05:46:57 PM UTC 24
Peak memory 217048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41252234 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.41252234
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/22.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/22.edn_disable.2251989801
Short name T95
Test name
Test status
Simulation time 25646537 ps
CPU time 0.68 seconds
Started Aug 23 05:46:53 PM UTC 24
Finished Aug 23 05:46:55 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251989801 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2251989801
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/22.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/22.edn_disable_auto_req_mode.1592632150
Short name T226
Test name
Test status
Simulation time 105688642 ps
CPU time 0.94 seconds
Started Aug 23 05:46:53 PM UTC 24
Finished Aug 23 05:46:56 PM UTC 24
Peak memory 230348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592632150 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable_auto_req_mode.1592632150
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/22.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/22.edn_genbits.767940118
Short name T351
Test name
Test status
Simulation time 56135873 ps
CPU time 1.09 seconds
Started Aug 23 05:46:51 PM UTC 24
Finished Aug 23 05:46:54 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767940118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.edn_genbits.767940118
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/22.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/22.edn_intr.4256659985
Short name T407
Test name
Test status
Simulation time 27581178 ps
CPU time 0.8 seconds
Started Aug 23 05:46:52 PM UTC 24
Finished Aug 23 05:46:54 PM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256659985 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 22.edn_intr.4256659985
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/22.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/22.edn_smoke.2601858234
Short name T405
Test name
Test status
Simulation time 29008453 ps
CPU time 0.8 seconds
Started Aug 23 05:46:51 PM UTC 24
Finished Aug 23 05:46:53 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601858234 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 22.edn_smoke.2601858234
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/22.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/22.edn_stress_all.4203277825
Short name T307
Test name
Test status
Simulation time 237154536 ps
CPU time 4.04 seconds
Started Aug 23 05:46:51 PM UTC 24
Finished Aug 23 05:46:56 PM UTC 24
Peak memory 227688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203277825 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.4203277825
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/22.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/22.edn_stress_all_with_rand_reset.829073847
Short name T599
Test name
Test status
Simulation time 6417201412 ps
CPU time 99.06 seconds
Started Aug 23 05:46:52 PM UTC 24
Finished Aug 23 05:48:34 PM UTC 24
Peak memory 229920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=829073847 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_
with_rand_reset.829073847
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/22.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/220.edn_genbits.2345523673
Short name T337
Test name
Test status
Simulation time 146242928 ps
CPU time 2.44 seconds
Started Aug 23 05:49:50 PM UTC 24
Finished Aug 23 05:49:53 PM UTC 24
Peak memory 231512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345523673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 220.edn_genbits.2345523673
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/220.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/221.edn_genbits.711829309
Short name T907
Test name
Test status
Simulation time 121949866 ps
CPU time 1.14 seconds
Started Aug 23 05:49:50 PM UTC 24
Finished Aug 23 05:49:52 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711829309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 221.edn_genbits.711829309
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/221.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/222.edn_genbits.2768534499
Short name T910
Test name
Test status
Simulation time 40434121 ps
CPU time 1.16 seconds
Started Aug 23 05:49:51 PM UTC 24
Finished Aug 23 05:49:53 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768534499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 222.edn_genbits.2768534499
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/222.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/223.edn_genbits.1335877893
Short name T911
Test name
Test status
Simulation time 44057617 ps
CPU time 1.23 seconds
Started Aug 23 05:49:51 PM UTC 24
Finished Aug 23 05:49:53 PM UTC 24
Peak memory 228556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335877893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 223.edn_genbits.1335877893
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/223.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/224.edn_genbits.2655210534
Short name T914
Test name
Test status
Simulation time 47598256 ps
CPU time 1.31 seconds
Started Aug 23 05:49:51 PM UTC 24
Finished Aug 23 05:49:54 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655210534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2655210534
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/224.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/225.edn_genbits.804241391
Short name T923
Test name
Test status
Simulation time 278326860 ps
CPU time 3.24 seconds
Started Aug 23 05:49:51 PM UTC 24
Finished Aug 23 05:49:55 PM UTC 24
Peak memory 231444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804241391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 225.edn_genbits.804241391
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/225.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/226.edn_genbits.252595572
Short name T909
Test name
Test status
Simulation time 78626925 ps
CPU time 1.02 seconds
Started Aug 23 05:49:51 PM UTC 24
Finished Aug 23 05:49:53 PM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252595572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 226.edn_genbits.252595572
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/226.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/227.edn_genbits.1306686230
Short name T912
Test name
Test status
Simulation time 34083974 ps
CPU time 1.13 seconds
Started Aug 23 05:49:51 PM UTC 24
Finished Aug 23 05:49:53 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306686230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1306686230
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/227.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/228.edn_genbits.302165783
Short name T915
Test name
Test status
Simulation time 155223659 ps
CPU time 1.41 seconds
Started Aug 23 05:49:51 PM UTC 24
Finished Aug 23 05:49:54 PM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302165783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 228.edn_genbits.302165783
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/228.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/229.edn_genbits.1747223049
Short name T913
Test name
Test status
Simulation time 41025553 ps
CPU time 1.23 seconds
Started Aug 23 05:49:51 PM UTC 24
Finished Aug 23 05:49:54 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747223049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1747223049
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/229.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/23.edn_alert.950546848
Short name T319
Test name
Test status
Simulation time 48642356 ps
CPU time 1.02 seconds
Started Aug 23 05:46:57 PM UTC 24
Finished Aug 23 05:46:59 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950546848 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 23.edn_alert.950546848
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/23.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/23.edn_alert_test.70444651
Short name T415
Test name
Test status
Simulation time 66560417 ps
CPU time 0.85 seconds
Started Aug 23 05:46:58 PM UTC 24
Finished Aug 23 05:47:00 PM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70444651 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.70444651
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/23.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/23.edn_disable.2533477096
Short name T412
Test name
Test status
Simulation time 26997114 ps
CPU time 0.71 seconds
Started Aug 23 05:46:57 PM UTC 24
Finished Aug 23 05:46:58 PM UTC 24
Peak memory 216132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533477096 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2533477096
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/23.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/23.edn_disable_auto_req_mode.2496230124
Short name T149
Test name
Test status
Simulation time 39628867 ps
CPU time 0.9 seconds
Started Aug 23 05:46:58 PM UTC 24
Finished Aug 23 05:47:00 PM UTC 24
Peak memory 226028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496230124 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable_auto_req_mode.2496230124
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/23.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/23.edn_err.1555040173
Short name T413
Test name
Test status
Simulation time 24679002 ps
CPU time 0.8 seconds
Started Aug 23 05:46:57 PM UTC 24
Finished Aug 23 05:46:59 PM UTC 24
Peak memory 228308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555040173 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 23.edn_err.1555040173
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/23.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/23.edn_intr.2008774444
Short name T411
Test name
Test status
Simulation time 77867674 ps
CPU time 0.71 seconds
Started Aug 23 05:46:56 PM UTC 24
Finished Aug 23 05:46:58 PM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008774444 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 23.edn_intr.2008774444
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/23.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/23.edn_smoke.2855068271
Short name T408
Test name
Test status
Simulation time 29549293 ps
CPU time 0.79 seconds
Started Aug 23 05:46:54 PM UTC 24
Finished Aug 23 05:46:56 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855068271 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 23.edn_smoke.2855068271
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/23.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/23.edn_stress_all.457158011
Short name T410
Test name
Test status
Simulation time 751608767 ps
CPU time 1.51 seconds
Started Aug 23 05:46:55 PM UTC 24
Finished Aug 23 05:46:57 PM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457158011 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.457158011
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/23.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/23.edn_stress_all_with_rand_reset.1657359760
Short name T245
Test name
Test status
Simulation time 3907874583 ps
CPU time 37.66 seconds
Started Aug 23 05:46:56 PM UTC 24
Finished Aug 23 05:47:35 PM UTC 24
Peak memory 229984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1657359760 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all
_with_rand_reset.1657359760
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/23.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/230.edn_genbits.3222565327
Short name T924
Test name
Test status
Simulation time 77468234 ps
CPU time 2.44 seconds
Started Aug 23 05:49:52 PM UTC 24
Finished Aug 23 05:49:56 PM UTC 24
Peak memory 229032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222565327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 230.edn_genbits.3222565327
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/230.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/231.edn_genbits.1262841868
Short name T922
Test name
Test status
Simulation time 50891655 ps
CPU time 1.71 seconds
Started Aug 23 05:49:52 PM UTC 24
Finished Aug 23 05:49:55 PM UTC 24
Peak memory 229760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262841868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1262841868
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/231.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/232.edn_genbits.3366995497
Short name T917
Test name
Test status
Simulation time 40951097 ps
CPU time 1.2 seconds
Started Aug 23 05:49:52 PM UTC 24
Finished Aug 23 05:49:55 PM UTC 24
Peak memory 228556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366995497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 232.edn_genbits.3366995497
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/232.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/233.edn_genbits.2374230117
Short name T918
Test name
Test status
Simulation time 42378176 ps
CPU time 1.26 seconds
Started Aug 23 05:49:52 PM UTC 24
Finished Aug 23 05:49:55 PM UTC 24
Peak memory 228528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374230117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 233.edn_genbits.2374230117
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/233.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/234.edn_genbits.1287407797
Short name T916
Test name
Test status
Simulation time 38098960 ps
CPU time 1.19 seconds
Started Aug 23 05:49:52 PM UTC 24
Finished Aug 23 05:49:55 PM UTC 24
Peak memory 228332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287407797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 234.edn_genbits.1287407797
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/234.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/235.edn_genbits.2163611084
Short name T920
Test name
Test status
Simulation time 34288671 ps
CPU time 1.25 seconds
Started Aug 23 05:49:52 PM UTC 24
Finished Aug 23 05:49:55 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163611084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2163611084
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/235.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/236.edn_genbits.1130259262
Short name T327
Test name
Test status
Simulation time 63576295 ps
CPU time 1.42 seconds
Started Aug 23 05:49:52 PM UTC 24
Finished Aug 23 05:49:55 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130259262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 236.edn_genbits.1130259262
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/236.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/237.edn_genbits.1704334283
Short name T919
Test name
Test status
Simulation time 64425624 ps
CPU time 1.14 seconds
Started Aug 23 05:49:52 PM UTC 24
Finished Aug 23 05:49:55 PM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704334283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1704334283
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/237.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/238.edn_genbits.270073766
Short name T921
Test name
Test status
Simulation time 71930246 ps
CPU time 1.45 seconds
Started Aug 23 05:49:52 PM UTC 24
Finished Aug 23 05:49:55 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270073766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 238.edn_genbits.270073766
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/238.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/239.edn_genbits.1406271235
Short name T926
Test name
Test status
Simulation time 99568904 ps
CPU time 1.17 seconds
Started Aug 23 05:49:54 PM UTC 24
Finished Aug 23 05:49:56 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406271235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 239.edn_genbits.1406271235
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/239.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/24.edn_alert.4136068111
Short name T210
Test name
Test status
Simulation time 98051349 ps
CPU time 0.95 seconds
Started Aug 23 05:46:59 PM UTC 24
Finished Aug 23 05:47:01 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136068111 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 24.edn_alert.4136068111
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/24.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/24.edn_alert_test.91569144
Short name T419
Test name
Test status
Simulation time 23435228 ps
CPU time 0.87 seconds
Started Aug 23 05:47:00 PM UTC 24
Finished Aug 23 05:47:02 PM UTC 24
Peak memory 217168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91569144 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.91569144
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/24.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/24.edn_disable.76095681
Short name T228
Test name
Test status
Simulation time 16480263 ps
CPU time 0.75 seconds
Started Aug 23 05:47:00 PM UTC 24
Finished Aug 23 05:47:02 PM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76095681 -assert nopostproc +UVM_TESTNAME=edn_disab
le_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.76095681
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/24.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/24.edn_disable_auto_req_mode.3215242400
Short name T418
Test name
Test status
Simulation time 39237113 ps
CPU time 0.9 seconds
Started Aug 23 05:47:00 PM UTC 24
Finished Aug 23 05:47:02 PM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215242400 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable_auto_req_mode.3215242400
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/24.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/24.edn_err.746086538
Short name T227
Test name
Test status
Simulation time 78877800 ps
CPU time 1.03 seconds
Started Aug 23 05:47:00 PM UTC 24
Finished Aug 23 05:47:02 PM UTC 24
Peak memory 242072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746086538 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 24.edn_err.746086538
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/24.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/24.edn_genbits.3704101570
Short name T323
Test name
Test status
Simulation time 66726899 ps
CPU time 0.87 seconds
Started Aug 23 05:46:58 PM UTC 24
Finished Aug 23 05:47:00 PM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704101570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_genbits.3704101570
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/24.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/24.edn_intr.3929691570
Short name T417
Test name
Test status
Simulation time 74970397 ps
CPU time 0.72 seconds
Started Aug 23 05:46:59 PM UTC 24
Finished Aug 23 05:47:01 PM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929691570 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 24.edn_intr.3929691570
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/24.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/24.edn_smoke.814797041
Short name T414
Test name
Test status
Simulation time 50276703 ps
CPU time 0.78 seconds
Started Aug 23 05:46:58 PM UTC 24
Finished Aug 23 05:47:00 PM UTC 24
Peak memory 216012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814797041 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 24.edn_smoke.814797041
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/24.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/24.edn_stress_all.872843230
Short name T416
Test name
Test status
Simulation time 71012260 ps
CPU time 1.36 seconds
Started Aug 23 05:46:58 PM UTC 24
Finished Aug 23 05:47:00 PM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872843230 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.872843230
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/24.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/24.edn_stress_all_with_rand_reset.2350874806
Short name T240
Test name
Test status
Simulation time 1009713983 ps
CPU time 21.85 seconds
Started Aug 23 05:46:59 PM UTC 24
Finished Aug 23 05:47:22 PM UTC 24
Peak memory 229660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2350874806 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all
_with_rand_reset.2350874806
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/24.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/240.edn_genbits.917553694
Short name T925
Test name
Test status
Simulation time 50212520 ps
CPU time 1.08 seconds
Started Aug 23 05:49:54 PM UTC 24
Finished Aug 23 05:49:56 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917553694 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 240.edn_genbits.917553694
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/240.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/241.edn_genbits.608714750
Short name T341
Test name
Test status
Simulation time 47265543 ps
CPU time 0.97 seconds
Started Aug 23 05:49:54 PM UTC 24
Finished Aug 23 05:49:56 PM UTC 24
Peak memory 228200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608714750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 241.edn_genbits.608714750
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/241.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/242.edn_genbits.1336524996
Short name T927
Test name
Test status
Simulation time 41148223 ps
CPU time 1.3 seconds
Started Aug 23 05:49:54 PM UTC 24
Finished Aug 23 05:49:56 PM UTC 24
Peak memory 228548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336524996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1336524996
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/242.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/243.edn_genbits.358272358
Short name T929
Test name
Test status
Simulation time 77460092 ps
CPU time 1.04 seconds
Started Aug 23 05:49:55 PM UTC 24
Finished Aug 23 05:49:57 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358272358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 243.edn_genbits.358272358
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/243.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/244.edn_genbits.480288993
Short name T928
Test name
Test status
Simulation time 68413099 ps
CPU time 1.01 seconds
Started Aug 23 05:49:55 PM UTC 24
Finished Aug 23 05:49:57 PM UTC 24
Peak memory 228092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480288993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 244.edn_genbits.480288993
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/244.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/245.edn_genbits.1251565523
Short name T931
Test name
Test status
Simulation time 80678150 ps
CPU time 1.01 seconds
Started Aug 23 05:49:55 PM UTC 24
Finished Aug 23 05:49:57 PM UTC 24
Peak memory 230140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251565523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 245.edn_genbits.1251565523
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/245.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/246.edn_genbits.1798339178
Short name T933
Test name
Test status
Simulation time 53369301 ps
CPU time 1.35 seconds
Started Aug 23 05:49:55 PM UTC 24
Finished Aug 23 05:49:58 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798339178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1798339178
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/246.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/247.edn_genbits.132530859
Short name T932
Test name
Test status
Simulation time 39589929 ps
CPU time 1.31 seconds
Started Aug 23 05:49:55 PM UTC 24
Finished Aug 23 05:49:58 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132530859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 247.edn_genbits.132530859
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/247.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/248.edn_genbits.2144782289
Short name T930
Test name
Test status
Simulation time 69410062 ps
CPU time 0.9 seconds
Started Aug 23 05:49:55 PM UTC 24
Finished Aug 23 05:49:57 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144782289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 248.edn_genbits.2144782289
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/248.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/249.edn_genbits.995482847
Short name T935
Test name
Test status
Simulation time 113478680 ps
CPU time 1.11 seconds
Started Aug 23 05:49:56 PM UTC 24
Finished Aug 23 05:49:58 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995482847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 249.edn_genbits.995482847
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/249.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/25.edn_alert.3934769329
Short name T320
Test name
Test status
Simulation time 28074452 ps
CPU time 1.03 seconds
Started Aug 23 05:47:02 PM UTC 24
Finished Aug 23 05:47:04 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934769329 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 25.edn_alert.3934769329
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/25.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/25.edn_alert_test.1907405427
Short name T423
Test name
Test status
Simulation time 26239551 ps
CPU time 0.72 seconds
Started Aug 23 05:47:03 PM UTC 24
Finished Aug 23 05:47:05 PM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907405427 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1907405427
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/25.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/25.edn_disable.1337609624
Short name T229
Test name
Test status
Simulation time 50507541 ps
CPU time 0.75 seconds
Started Aug 23 05:47:02 PM UTC 24
Finished Aug 23 05:47:04 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337609624 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.1337609624
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/25.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/25.edn_disable_auto_req_mode.968910356
Short name T126
Test name
Test status
Simulation time 97650005 ps
CPU time 0.89 seconds
Started Aug 23 05:47:03 PM UTC 24
Finished Aug 23 05:47:05 PM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968910356 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable_auto_req_mode.968910356
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/25.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/25.edn_genbits.3069738856
Short name T421
Test name
Test status
Simulation time 36498367 ps
CPU time 1.19 seconds
Started Aug 23 05:47:01 PM UTC 24
Finished Aug 23 05:47:03 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069738856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3069738856
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/25.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/25.edn_intr.640376782
Short name T422
Test name
Test status
Simulation time 24804798 ps
CPU time 0.81 seconds
Started Aug 23 05:47:02 PM UTC 24
Finished Aug 23 05:47:04 PM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640376782 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 25.edn_intr.640376782
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/25.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/25.edn_smoke.2899552140
Short name T420
Test name
Test status
Simulation time 17591896 ps
CPU time 0.85 seconds
Started Aug 23 05:47:01 PM UTC 24
Finished Aug 23 05:47:03 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899552140 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 25.edn_smoke.2899552140
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/25.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/25.edn_stress_all.1559314723
Short name T262
Test name
Test status
Simulation time 4723463776 ps
CPU time 6.01 seconds
Started Aug 23 05:47:01 PM UTC 24
Finished Aug 23 05:47:08 PM UTC 24
Peak memory 229796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559314723 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1559314723
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/25.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/25.edn_stress_all_with_rand_reset.2028618364
Short name T241
Test name
Test status
Simulation time 3001841433 ps
CPU time 31.94 seconds
Started Aug 23 05:47:01 PM UTC 24
Finished Aug 23 05:47:34 PM UTC 24
Peak memory 229796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2028618364 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all
_with_rand_reset.2028618364
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/25.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/250.edn_genbits.2866308717
Short name T936
Test name
Test status
Simulation time 70394107 ps
CPU time 1.21 seconds
Started Aug 23 05:49:56 PM UTC 24
Finished Aug 23 05:49:58 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866308717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 250.edn_genbits.2866308717
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/250.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/251.edn_genbits.4116340437
Short name T937
Test name
Test status
Simulation time 150056534 ps
CPU time 1.39 seconds
Started Aug 23 05:49:56 PM UTC 24
Finished Aug 23 05:49:59 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116340437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 251.edn_genbits.4116340437
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/251.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/252.edn_genbits.1036079398
Short name T934
Test name
Test status
Simulation time 74358103 ps
CPU time 0.93 seconds
Started Aug 23 05:49:56 PM UTC 24
Finished Aug 23 05:49:58 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036079398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1036079398
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/252.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/253.edn_genbits.3201120738
Short name T949
Test name
Test status
Simulation time 30450581 ps
CPU time 1.08 seconds
Started Aug 23 05:49:56 PM UTC 24
Finished Aug 23 05:50:02 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201120738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3201120738
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/253.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/254.edn_genbits.1994695533
Short name T948
Test name
Test status
Simulation time 34773513 ps
CPU time 1.08 seconds
Started Aug 23 05:49:56 PM UTC 24
Finished Aug 23 05:50:02 PM UTC 24
Peak memory 227756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994695533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 254.edn_genbits.1994695533
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/254.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/255.edn_genbits.2831883977
Short name T342
Test name
Test status
Simulation time 140959265 ps
CPU time 2.44 seconds
Started Aug 23 05:49:56 PM UTC 24
Finished Aug 23 05:50:03 PM UTC 24
Peak memory 231508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831883977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2831883977
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/255.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/256.edn_genbits.3300307992
Short name T950
Test name
Test status
Simulation time 204380368 ps
CPU time 1.04 seconds
Started Aug 23 05:49:56 PM UTC 24
Finished Aug 23 05:50:02 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300307992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 256.edn_genbits.3300307992
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/256.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/257.edn_genbits.3799415754
Short name T947
Test name
Test status
Simulation time 95643536 ps
CPU time 1 seconds
Started Aug 23 05:49:56 PM UTC 24
Finished Aug 23 05:50:02 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799415754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 257.edn_genbits.3799415754
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/257.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/258.edn_genbits.2040424907
Short name T944
Test name
Test status
Simulation time 67673069 ps
CPU time 1.4 seconds
Started Aug 23 05:49:57 PM UTC 24
Finished Aug 23 05:50:01 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040424907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 258.edn_genbits.2040424907
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/258.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/259.edn_genbits.3222149351
Short name T939
Test name
Test status
Simulation time 46935621 ps
CPU time 0.99 seconds
Started Aug 23 05:49:57 PM UTC 24
Finished Aug 23 05:50:01 PM UTC 24
Peak memory 226112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222149351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 259.edn_genbits.3222149351
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/259.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/26.edn_alert.1445859234
Short name T168
Test name
Test status
Simulation time 40964405 ps
CPU time 0.97 seconds
Started Aug 23 05:47:06 PM UTC 24
Finished Aug 23 05:47:07 PM UTC 24
Peak memory 228436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445859234 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 26.edn_alert.1445859234
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/26.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/26.edn_alert_test.1933722953
Short name T430
Test name
Test status
Simulation time 18467709 ps
CPU time 0.87 seconds
Started Aug 23 05:47:09 PM UTC 24
Finished Aug 23 05:47:11 PM UTC 24
Peak memory 226460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933722953 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.1933722953
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/26.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/26.edn_disable.48887738
Short name T233
Test name
Test status
Simulation time 28002692 ps
CPU time 0.73 seconds
Started Aug 23 05:47:07 PM UTC 24
Finished Aug 23 05:47:08 PM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48887738 -assert nopostproc +UVM_TESTNAME=edn_disab
le_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.48887738
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/26.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/26.edn_disable_auto_req_mode.3669059494
Short name T174
Test name
Test status
Simulation time 72410308 ps
CPU time 0.97 seconds
Started Aug 23 05:47:08 PM UTC 24
Finished Aug 23 05:47:10 PM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669059494 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable_auto_req_mode.3669059494
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/26.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/26.edn_err.2225772483
Short name T426
Test name
Test status
Simulation time 20413331 ps
CPU time 0.99 seconds
Started Aug 23 05:47:06 PM UTC 24
Finished Aug 23 05:47:08 PM UTC 24
Peak memory 237344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225772483 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 26.edn_err.2225772483
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/26.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/26.edn_genbits.2562085750
Short name T96
Test name
Test status
Simulation time 67512170 ps
CPU time 1.38 seconds
Started Aug 23 05:47:04 PM UTC 24
Finished Aug 23 05:47:07 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562085750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_genbits.2562085750
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/26.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/26.edn_intr.2460881137
Short name T425
Test name
Test status
Simulation time 33543511 ps
CPU time 0.85 seconds
Started Aug 23 05:47:06 PM UTC 24
Finished Aug 23 05:47:07 PM UTC 24
Peak memory 237164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460881137 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 26.edn_intr.2460881137
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/26.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/26.edn_smoke.4096026672
Short name T424
Test name
Test status
Simulation time 54300319 ps
CPU time 0.78 seconds
Started Aug 23 05:47:04 PM UTC 24
Finished Aug 23 05:47:06 PM UTC 24
Peak memory 226120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096026672 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 26.edn_smoke.4096026672
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/26.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/26.edn_stress_all.544162158
Short name T427
Test name
Test status
Simulation time 1401580791 ps
CPU time 2.76 seconds
Started Aug 23 05:47:04 PM UTC 24
Finished Aug 23 05:47:08 PM UTC 24
Peak memory 229528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544162158 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.544162158
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/26.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/260.edn_genbits.3980819138
Short name T938
Test name
Test status
Simulation time 60295843 ps
CPU time 0.86 seconds
Started Aug 23 05:49:57 PM UTC 24
Finished Aug 23 05:50:00 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980819138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 260.edn_genbits.3980819138
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/260.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/261.edn_genbits.615197719
Short name T943
Test name
Test status
Simulation time 72156817 ps
CPU time 1.15 seconds
Started Aug 23 05:49:57 PM UTC 24
Finished Aug 23 05:50:01 PM UTC 24
Peak memory 226064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615197719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 261.edn_genbits.615197719
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/261.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/262.edn_genbits.2250092207
Short name T942
Test name
Test status
Simulation time 97024639 ps
CPU time 0.99 seconds
Started Aug 23 05:49:57 PM UTC 24
Finished Aug 23 05:50:01 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250092207 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 262.edn_genbits.2250092207
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/262.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/263.edn_genbits.3884911003
Short name T955
Test name
Test status
Simulation time 276140282 ps
CPU time 3.28 seconds
Started Aug 23 05:49:58 PM UTC 24
Finished Aug 23 05:50:03 PM UTC 24
Peak memory 229440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884911003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3884911003
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/263.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/264.edn_genbits.2036992732
Short name T941
Test name
Test status
Simulation time 47709409 ps
CPU time 0.95 seconds
Started Aug 23 05:49:58 PM UTC 24
Finished Aug 23 05:50:01 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036992732 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 264.edn_genbits.2036992732
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/264.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/265.edn_genbits.47596750
Short name T945
Test name
Test status
Simulation time 49790807 ps
CPU time 1.46 seconds
Started Aug 23 05:49:58 PM UTC 24
Finished Aug 23 05:50:01 PM UTC 24
Peak memory 230604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47596750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 265.edn_genbits.47596750
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/265.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/266.edn_genbits.1358836192
Short name T940
Test name
Test status
Simulation time 42839357 ps
CPU time 0.95 seconds
Started Aug 23 05:49:58 PM UTC 24
Finished Aug 23 05:50:01 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358836192 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1358836192
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/266.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/267.edn_genbits.840924659
Short name T335
Test name
Test status
Simulation time 126621432 ps
CPU time 1.46 seconds
Started Aug 23 05:49:58 PM UTC 24
Finished Aug 23 05:50:01 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840924659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 267.edn_genbits.840924659
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/267.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/268.edn_genbits.2312193821
Short name T946
Test name
Test status
Simulation time 43681401 ps
CPU time 1.58 seconds
Started Aug 23 05:49:58 PM UTC 24
Finished Aug 23 05:50:01 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312193821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 268.edn_genbits.2312193821
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/268.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/269.edn_genbits.1936643042
Short name T952
Test name
Test status
Simulation time 85057944 ps
CPU time 0.93 seconds
Started Aug 23 05:49:59 PM UTC 24
Finished Aug 23 05:50:02 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936643042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 269.edn_genbits.1936643042
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/269.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/27.edn_alert.2636175545
Short name T202
Test name
Test status
Simulation time 72570719 ps
CPU time 1.03 seconds
Started Aug 23 05:47:09 PM UTC 24
Finished Aug 23 05:47:11 PM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636175545 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 27.edn_alert.2636175545
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/27.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/27.edn_alert_test.65186390
Short name T432
Test name
Test status
Simulation time 24931213 ps
CPU time 0.73 seconds
Started Aug 23 05:47:12 PM UTC 24
Finished Aug 23 05:47:14 PM UTC 24
Peak memory 217004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65186390 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.65186390
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/27.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/27.edn_disable.2750967057
Short name T431
Test name
Test status
Simulation time 31413521 ps
CPU time 0.73 seconds
Started Aug 23 05:47:12 PM UTC 24
Finished Aug 23 05:47:14 PM UTC 24
Peak memory 216132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750967057 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.2750967057
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/27.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/27.edn_disable_auto_req_mode.1220234061
Short name T434
Test name
Test status
Simulation time 103382537 ps
CPU time 0.98 seconds
Started Aug 23 05:47:12 PM UTC 24
Finished Aug 23 05:47:14 PM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220234061 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable_auto_req_mode.1220234061
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/27.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/27.edn_err.4082425876
Short name T139
Test name
Test status
Simulation time 24366553 ps
CPU time 1.02 seconds
Started Aug 23 05:47:11 PM UTC 24
Finished Aug 23 05:47:13 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082425876 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 27.edn_err.4082425876
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/27.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/27.edn_genbits.540935302
Short name T97
Test name
Test status
Simulation time 63141931 ps
CPU time 1.81 seconds
Started Aug 23 05:47:09 PM UTC 24
Finished Aug 23 05:47:12 PM UTC 24
Peak memory 230580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540935302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.edn_genbits.540935302
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/27.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/27.edn_intr.1481111253
Short name T429
Test name
Test status
Simulation time 28785416 ps
CPU time 0.79 seconds
Started Aug 23 05:47:09 PM UTC 24
Finished Aug 23 05:47:11 PM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481111253 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 27.edn_intr.1481111253
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/27.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/27.edn_smoke.3962253487
Short name T428
Test name
Test status
Simulation time 20076922 ps
CPU time 0.83 seconds
Started Aug 23 05:47:09 PM UTC 24
Finished Aug 23 05:47:11 PM UTC 24
Peak memory 226100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962253487 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 27.edn_smoke.3962253487
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/27.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/27.edn_stress_all.1132885188
Short name T308
Test name
Test status
Simulation time 263848616 ps
CPU time 3.7 seconds
Started Aug 23 05:47:09 PM UTC 24
Finished Aug 23 05:47:14 PM UTC 24
Peak memory 229648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132885188 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1132885188
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/27.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/27.edn_stress_all_with_rand_reset.830704576
Short name T527
Test name
Test status
Simulation time 2041751799 ps
CPU time 47.1 seconds
Started Aug 23 05:47:09 PM UTC 24
Finished Aug 23 05:47:58 PM UTC 24
Peak memory 231864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=830704576 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_
with_rand_reset.830704576
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/27.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/270.edn_genbits.1661126666
Short name T951
Test name
Test status
Simulation time 77281949 ps
CPU time 0.89 seconds
Started Aug 23 05:50:00 PM UTC 24
Finished Aug 23 05:50:02 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661126666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 270.edn_genbits.1661126666
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/270.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/271.edn_genbits.3057176921
Short name T953
Test name
Test status
Simulation time 42200323 ps
CPU time 0.99 seconds
Started Aug 23 05:50:00 PM UTC 24
Finished Aug 23 05:50:02 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057176921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 271.edn_genbits.3057176921
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/271.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/272.edn_genbits.1616845807
Short name T954
Test name
Test status
Simulation time 52131390 ps
CPU time 1.39 seconds
Started Aug 23 05:50:00 PM UTC 24
Finished Aug 23 05:50:02 PM UTC 24
Peak memory 230604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616845807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1616845807
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/272.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/273.edn_genbits.3372674187
Short name T956
Test name
Test status
Simulation time 63788172 ps
CPU time 1.07 seconds
Started Aug 23 05:50:02 PM UTC 24
Finished Aug 23 05:50:04 PM UTC 24
Peak memory 228204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372674187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3372674187
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/273.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/274.edn_genbits.2025722055
Short name T957
Test name
Test status
Simulation time 78411647 ps
CPU time 1.1 seconds
Started Aug 23 05:50:02 PM UTC 24
Finished Aug 23 05:50:04 PM UTC 24
Peak memory 228180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025722055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 274.edn_genbits.2025722055
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/274.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/275.edn_genbits.3602519886
Short name T961
Test name
Test status
Simulation time 76736619 ps
CPU time 1.19 seconds
Started Aug 23 05:50:02 PM UTC 24
Finished Aug 23 05:50:04 PM UTC 24
Peak memory 228556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602519886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3602519886
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/275.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/276.edn_genbits.3357795163
Short name T962
Test name
Test status
Simulation time 61548918 ps
CPU time 1.22 seconds
Started Aug 23 05:50:02 PM UTC 24
Finished Aug 23 05:50:04 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357795163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3357795163
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/276.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/277.edn_genbits.4092929838
Short name T958
Test name
Test status
Simulation time 85171530 ps
CPU time 0.97 seconds
Started Aug 23 05:50:02 PM UTC 24
Finished Aug 23 05:50:04 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092929838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 277.edn_genbits.4092929838
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/277.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/278.edn_genbits.2074368048
Short name T344
Test name
Test status
Simulation time 59214375 ps
CPU time 0.99 seconds
Started Aug 23 05:50:02 PM UTC 24
Finished Aug 23 05:50:04 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074368048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 278.edn_genbits.2074368048
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/278.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/279.edn_genbits.3015904893
Short name T964
Test name
Test status
Simulation time 117590128 ps
CPU time 1.24 seconds
Started Aug 23 05:50:02 PM UTC 24
Finished Aug 23 05:50:04 PM UTC 24
Peak memory 230376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015904893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 279.edn_genbits.3015904893
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/279.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/28.edn_alert.852280565
Short name T156
Test name
Test status
Simulation time 29488846 ps
CPU time 1.07 seconds
Started Aug 23 05:47:14 PM UTC 24
Finished Aug 23 05:47:16 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852280565 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 28.edn_alert.852280565
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/28.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/28.edn_alert_test.2525791873
Short name T253
Test name
Test status
Simulation time 34699362 ps
CPU time 0.81 seconds
Started Aug 23 05:47:16 PM UTC 24
Finished Aug 23 05:47:18 PM UTC 24
Peak memory 216748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525791873 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2525791873
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/28.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/28.edn_disable.2341865910
Short name T436
Test name
Test status
Simulation time 10863150 ps
CPU time 0.72 seconds
Started Aug 23 05:47:14 PM UTC 24
Finished Aug 23 05:47:16 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341865910 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2341865910
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/28.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/28.edn_disable_auto_req_mode.2360231126
Short name T161
Test name
Test status
Simulation time 85368083 ps
CPU time 0.89 seconds
Started Aug 23 05:47:15 PM UTC 24
Finished Aug 23 05:47:17 PM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360231126 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable_auto_req_mode.2360231126
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/28.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/28.edn_err.195889242
Short name T437
Test name
Test status
Simulation time 33779257 ps
CPU time 0.77 seconds
Started Aug 23 05:47:14 PM UTC 24
Finished Aug 23 05:47:16 PM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195889242 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 28.edn_err.195889242
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/28.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/28.edn_genbits.583197976
Short name T98
Test name
Test status
Simulation time 66750965 ps
CPU time 1.28 seconds
Started Aug 23 05:47:13 PM UTC 24
Finished Aug 23 05:47:15 PM UTC 24
Peak memory 230612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583197976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_genbits.583197976
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/28.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/28.edn_intr.3915979267
Short name T435
Test name
Test status
Simulation time 28038557 ps
CPU time 0.81 seconds
Started Aug 23 05:47:14 PM UTC 24
Finished Aug 23 05:47:16 PM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915979267 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 28.edn_intr.3915979267
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/28.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/28.edn_smoke.2701309150
Short name T433
Test name
Test status
Simulation time 15231214 ps
CPU time 0.78 seconds
Started Aug 23 05:47:12 PM UTC 24
Finished Aug 23 05:47:14 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701309150 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 28.edn_smoke.2701309150
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/28.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/28.edn_stress_all.2093065300
Short name T256
Test name
Test status
Simulation time 441641636 ps
CPU time 5.03 seconds
Started Aug 23 05:47:13 PM UTC 24
Finished Aug 23 05:47:19 PM UTC 24
Peak memory 229444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093065300 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2093065300
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/28.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/28.edn_stress_all_with_rand_reset.2158924005
Short name T497
Test name
Test status
Simulation time 1239746610 ps
CPU time 30.38 seconds
Started Aug 23 05:47:14 PM UTC 24
Finished Aug 23 05:47:46 PM UTC 24
Peak memory 231712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2158924005 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all
_with_rand_reset.2158924005
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/28.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/280.edn_genbits.226849541
Short name T959
Test name
Test status
Simulation time 61825315 ps
CPU time 1.11 seconds
Started Aug 23 05:50:02 PM UTC 24
Finished Aug 23 05:50:04 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226849541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 280.edn_genbits.226849541
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/280.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/281.edn_genbits.1596772015
Short name T963
Test name
Test status
Simulation time 91147338 ps
CPU time 1.14 seconds
Started Aug 23 05:50:02 PM UTC 24
Finished Aug 23 05:50:04 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596772015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1596772015
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/281.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/282.edn_genbits.857282345
Short name T960
Test name
Test status
Simulation time 106528060 ps
CPU time 1.09 seconds
Started Aug 23 05:50:02 PM UTC 24
Finished Aug 23 05:50:04 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857282345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 282.edn_genbits.857282345
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/282.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/283.edn_genbits.512813077
Short name T969
Test name
Test status
Simulation time 94554712 ps
CPU time 1.26 seconds
Started Aug 23 05:50:03 PM UTC 24
Finished Aug 23 05:50:05 PM UTC 24
Peak memory 227744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512813077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 283.edn_genbits.512813077
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/283.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/284.edn_genbits.943099510
Short name T967
Test name
Test status
Simulation time 51152368 ps
CPU time 1.05 seconds
Started Aug 23 05:50:03 PM UTC 24
Finished Aug 23 05:50:05 PM UTC 24
Peak memory 227300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943099510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 284.edn_genbits.943099510
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/284.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/285.edn_genbits.62183925
Short name T971
Test name
Test status
Simulation time 46518835 ps
CPU time 1.48 seconds
Started Aug 23 05:50:03 PM UTC 24
Finished Aug 23 05:50:06 PM UTC 24
Peak memory 227516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62183925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 285.edn_genbits.62183925
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/285.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/286.edn_genbits.582075657
Short name T965
Test name
Test status
Simulation time 75361694 ps
CPU time 0.93 seconds
Started Aug 23 05:50:03 PM UTC 24
Finished Aug 23 05:50:05 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582075657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 286.edn_genbits.582075657
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/286.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/287.edn_genbits.1142832639
Short name T966
Test name
Test status
Simulation time 59010652 ps
CPU time 0.92 seconds
Started Aug 23 05:50:03 PM UTC 24
Finished Aug 23 05:50:05 PM UTC 24
Peak memory 227664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142832639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1142832639
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/287.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/288.edn_genbits.287726337
Short name T968
Test name
Test status
Simulation time 72991304 ps
CPU time 1.07 seconds
Started Aug 23 05:50:03 PM UTC 24
Finished Aug 23 05:50:05 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287726337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 288.edn_genbits.287726337
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/288.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/289.edn_genbits.2712944394
Short name T972
Test name
Test status
Simulation time 78837547 ps
CPU time 1.59 seconds
Started Aug 23 05:50:03 PM UTC 24
Finished Aug 23 05:50:06 PM UTC 24
Peak memory 226508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712944394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2712944394
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/289.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/29.edn_alert.3036438964
Short name T205
Test name
Test status
Simulation time 73839836 ps
CPU time 0.92 seconds
Started Aug 23 05:47:18 PM UTC 24
Finished Aug 23 05:47:20 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036438964 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 29.edn_alert.3036438964
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/29.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/29.edn_alert_test.1518435779
Short name T440
Test name
Test status
Simulation time 25588382 ps
CPU time 0.76 seconds
Started Aug 23 05:47:19 PM UTC 24
Finished Aug 23 05:47:20 PM UTC 24
Peak memory 216868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518435779 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1518435779
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/29.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/29.edn_disable.2913507321
Short name T438
Test name
Test status
Simulation time 32342373 ps
CPU time 0.73 seconds
Started Aug 23 05:47:18 PM UTC 24
Finished Aug 23 05:47:19 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913507321 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2913507321
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/29.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/29.edn_disable_auto_req_mode.1963626944
Short name T441
Test name
Test status
Simulation time 57927456 ps
CPU time 1 seconds
Started Aug 23 05:47:19 PM UTC 24
Finished Aug 23 05:47:21 PM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963626944 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable_auto_req_mode.1963626944
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/29.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/29.edn_err.1222491509
Short name T158
Test name
Test status
Simulation time 30954316 ps
CPU time 0.86 seconds
Started Aug 23 05:47:18 PM UTC 24
Finished Aug 23 05:47:20 PM UTC 24
Peak memory 246680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222491509 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 29.edn_err.1222491509
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/29.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/29.edn_genbits.2069393804
Short name T255
Test name
Test status
Simulation time 40176855 ps
CPU time 0.99 seconds
Started Aug 23 05:47:16 PM UTC 24
Finished Aug 23 05:47:18 PM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069393804 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2069393804
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/29.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/29.edn_intr.2839919386
Short name T439
Test name
Test status
Simulation time 19842992 ps
CPU time 0.9 seconds
Started Aug 23 05:47:18 PM UTC 24
Finished Aug 23 05:47:19 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839919386 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 29.edn_intr.2839919386
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/29.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/29.edn_smoke.339592082
Short name T254
Test name
Test status
Simulation time 127401715 ps
CPU time 0.77 seconds
Started Aug 23 05:47:16 PM UTC 24
Finished Aug 23 05:47:18 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339592082 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 29.edn_smoke.339592082
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/29.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/29.edn_stress_all.3040797766
Short name T442
Test name
Test status
Simulation time 872754189 ps
CPU time 4.03 seconds
Started Aug 23 05:47:16 PM UTC 24
Finished Aug 23 05:47:22 PM UTC 24
Peak memory 231580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040797766 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3040797766
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/29.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/290.edn_genbits.1973485888
Short name T970
Test name
Test status
Simulation time 91469599 ps
CPU time 1.05 seconds
Started Aug 23 05:50:03 PM UTC 24
Finished Aug 23 05:50:05 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973485888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1973485888
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/290.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/291.edn_genbits.2315746612
Short name T973
Test name
Test status
Simulation time 31209900 ps
CPU time 0.88 seconds
Started Aug 23 05:50:04 PM UTC 24
Finished Aug 23 05:50:06 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315746612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2315746612
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/291.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/292.edn_genbits.619465459
Short name T974
Test name
Test status
Simulation time 31828116 ps
CPU time 1.05 seconds
Started Aug 23 05:50:04 PM UTC 24
Finished Aug 23 05:50:06 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619465459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 292.edn_genbits.619465459
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/292.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/293.edn_genbits.3668419478
Short name T976
Test name
Test status
Simulation time 34927823 ps
CPU time 1.02 seconds
Started Aug 23 05:50:05 PM UTC 24
Finished Aug 23 05:50:11 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668419478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 293.edn_genbits.3668419478
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/293.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/294.edn_genbits.1362132638
Short name T975
Test name
Test status
Simulation time 77876195 ps
CPU time 0.91 seconds
Started Aug 23 05:50:05 PM UTC 24
Finished Aug 23 05:50:11 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362132638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1362132638
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/294.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/295.edn_genbits.4192571818
Short name T979
Test name
Test status
Simulation time 41139224 ps
CPU time 1.3 seconds
Started Aug 23 05:50:05 PM UTC 24
Finished Aug 23 05:50:11 PM UTC 24
Peak memory 228556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192571818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 295.edn_genbits.4192571818
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/295.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/296.edn_genbits.4112996113
Short name T977
Test name
Test status
Simulation time 47196225 ps
CPU time 0.95 seconds
Started Aug 23 05:50:05 PM UTC 24
Finished Aug 23 05:50:11 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112996113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 296.edn_genbits.4112996113
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/296.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/297.edn_genbits.1007221202
Short name T978
Test name
Test status
Simulation time 52553736 ps
CPU time 1.15 seconds
Started Aug 23 05:50:05 PM UTC 24
Finished Aug 23 05:50:11 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007221202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1007221202
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/297.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/298.edn_genbits.2966092016
Short name T981
Test name
Test status
Simulation time 38512064 ps
CPU time 1.36 seconds
Started Aug 23 05:50:05 PM UTC 24
Finished Aug 23 05:50:12 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966092016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 298.edn_genbits.2966092016
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/298.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/299.edn_genbits.2873999856
Short name T980
Test name
Test status
Simulation time 40775319 ps
CPU time 1.1 seconds
Started Aug 23 05:50:06 PM UTC 24
Finished Aug 23 05:50:11 PM UTC 24
Peak memory 228556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873999856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 299.edn_genbits.2873999856
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/299.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/3.edn_alert_test.2283287842
Short name T68
Test name
Test status
Simulation time 176873088 ps
CPU time 0.77 seconds
Started Aug 23 05:46:10 PM UTC 24
Finished Aug 23 05:46:12 PM UTC 24
Peak memory 226556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283287842 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2283287842
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/3.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/3.edn_disable.1182377065
Short name T86
Test name
Test status
Simulation time 13407378 ps
CPU time 0.77 seconds
Started Aug 23 05:46:08 PM UTC 24
Finished Aug 23 05:46:10 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182377065 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1182377065
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/3.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/3.edn_disable_auto_req_mode.3801829923
Short name T22
Test name
Test status
Simulation time 87916145 ps
CPU time 0.91 seconds
Started Aug 23 05:46:10 PM UTC 24
Finished Aug 23 05:46:12 PM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801829923 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable_auto_req_mode.3801829923
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/3.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/3.edn_err.3836798962
Short name T70
Test name
Test status
Simulation time 22337821 ps
CPU time 0.78 seconds
Started Aug 23 05:46:08 PM UTC 24
Finished Aug 23 05:46:10 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836798962 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 3.edn_err.3836798962
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/3.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/3.edn_genbits.3434836055
Short name T91
Test name
Test status
Simulation time 54265365 ps
CPU time 1.16 seconds
Started Aug 23 05:46:07 PM UTC 24
Finished Aug 23 05:46:10 PM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434836055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3434836055
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/3.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/3.edn_intr.406413792
Short name T17
Test name
Test status
Simulation time 35569179 ps
CPU time 0.83 seconds
Started Aug 23 05:46:08 PM UTC 24
Finished Aug 23 05:46:10 PM UTC 24
Peak memory 236700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406413792 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 3.edn_intr.406413792
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/3.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/3.edn_regwen.178339958
Short name T76
Test name
Test status
Simulation time 28523972 ps
CPU time 0.84 seconds
Started Aug 23 05:46:07 PM UTC 24
Finished Aug 23 05:46:09 PM UTC 24
Peak memory 216016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178339958 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 3.edn_regwen.178339958
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/3.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/3.edn_sec_cm.3529883673
Short name T60
Test name
Test status
Simulation time 455749974 ps
CPU time 6.46 seconds
Started Aug 23 05:46:10 PM UTC 24
Finished Aug 23 05:46:17 PM UTC 24
Peak memory 262512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529883673 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3529883673
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/3.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/3.edn_smoke.1225041803
Short name T75
Test name
Test status
Simulation time 16815686 ps
CPU time 0.84 seconds
Started Aug 23 05:46:07 PM UTC 24
Finished Aug 23 05:46:09 PM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225041803 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 3.edn_smoke.1225041803
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/3.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/3.edn_stress_all.3587667148
Short name T57
Test name
Test status
Simulation time 132487607 ps
CPU time 1.11 seconds
Started Aug 23 05:46:07 PM UTC 24
Finished Aug 23 05:46:10 PM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587667148 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3587667148
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/3.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/3.edn_stress_all_with_rand_reset.2839842282
Short name T239
Test name
Test status
Simulation time 3009342518 ps
CPU time 69.51 seconds
Started Aug 23 05:46:07 PM UTC 24
Finished Aug 23 05:47:19 PM UTC 24
Peak memory 229800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2839842282 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_
with_rand_reset.2839842282
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/3.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/30.edn_alert.721232675
Short name T230
Test name
Test status
Simulation time 83865920 ps
CPU time 0.97 seconds
Started Aug 23 05:47:21 PM UTC 24
Finished Aug 23 05:47:23 PM UTC 24
Peak memory 228256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721232675 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 30.edn_alert.721232675
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/30.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/30.edn_alert_test.2189694732
Short name T449
Test name
Test status
Simulation time 24775189 ps
CPU time 0.74 seconds
Started Aug 23 05:47:22 PM UTC 24
Finished Aug 23 05:47:24 PM UTC 24
Peak memory 216868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189694732 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.2189694732
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/30.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/30.edn_disable.36997478
Short name T447
Test name
Test status
Simulation time 33804141 ps
CPU time 0.72 seconds
Started Aug 23 05:47:21 PM UTC 24
Finished Aug 23 05:47:23 PM UTC 24
Peak memory 216136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36997478 -assert nopostproc +UVM_TESTNAME=edn_disab
le_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.36997478
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/30.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/30.edn_disable_auto_req_mode.1199338757
Short name T298
Test name
Test status
Simulation time 90747186 ps
CPU time 0.83 seconds
Started Aug 23 05:47:22 PM UTC 24
Finished Aug 23 05:47:24 PM UTC 24
Peak memory 228216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199338757 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable_auto_req_mode.1199338757
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/30.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/30.edn_err.1294853993
Short name T448
Test name
Test status
Simulation time 34714035 ps
CPU time 0.77 seconds
Started Aug 23 05:47:21 PM UTC 24
Finished Aug 23 05:47:23 PM UTC 24
Peak memory 228220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294853993 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 30.edn_err.1294853993
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/30.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/30.edn_genbits.3179587341
Short name T445
Test name
Test status
Simulation time 42496850 ps
CPU time 1.21 seconds
Started Aug 23 05:47:20 PM UTC 24
Finished Aug 23 05:47:22 PM UTC 24
Peak memory 230180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179587341 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3179587341
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/30.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/30.edn_intr.1586676654
Short name T444
Test name
Test status
Simulation time 41528988 ps
CPU time 0.75 seconds
Started Aug 23 05:47:20 PM UTC 24
Finished Aug 23 05:47:22 PM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586676654 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 30.edn_intr.1586676654
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/30.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/30.edn_smoke.3173173106
Short name T443
Test name
Test status
Simulation time 52012733 ps
CPU time 0.79 seconds
Started Aug 23 05:47:20 PM UTC 24
Finished Aug 23 05:47:22 PM UTC 24
Peak memory 226124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173173106 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 30.edn_smoke.3173173106
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/30.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/30.edn_stress_all.1999562677
Short name T446
Test name
Test status
Simulation time 180377922 ps
CPU time 1.75 seconds
Started Aug 23 05:47:20 PM UTC 24
Finished Aug 23 05:47:23 PM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999562677 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1999562677
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/30.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/31.edn_alert.898693987
Short name T169
Test name
Test status
Simulation time 58705794 ps
CPU time 1.05 seconds
Started Aug 23 05:47:23 PM UTC 24
Finished Aug 23 05:47:25 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898693987 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 31.edn_alert.898693987
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/31.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/31.edn_alert_test.179031126
Short name T453
Test name
Test status
Simulation time 35430123 ps
CPU time 0.7 seconds
Started Aug 23 05:47:24 PM UTC 24
Finished Aug 23 05:47:26 PM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179031126 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.179031126
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/31.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/31.edn_disable.856061201
Short name T454
Test name
Test status
Simulation time 12013243 ps
CPU time 0.75 seconds
Started Aug 23 05:47:24 PM UTC 24
Finished Aug 23 05:47:26 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856061201 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.856061201
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/31.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/31.edn_disable_auto_req_mode.1746038544
Short name T456
Test name
Test status
Simulation time 45826093 ps
CPU time 1.23 seconds
Started Aug 23 05:47:24 PM UTC 24
Finished Aug 23 05:47:27 PM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746038544 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable_auto_req_mode.1746038544
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/31.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/31.edn_err.591497590
Short name T452
Test name
Test status
Simulation time 24666170 ps
CPU time 0.89 seconds
Started Aug 23 05:47:23 PM UTC 24
Finished Aug 23 05:47:25 PM UTC 24
Peak memory 237416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591497590 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 31.edn_err.591497590
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/31.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/31.edn_intr.217784383
Short name T451
Test name
Test status
Simulation time 23548336 ps
CPU time 0.92 seconds
Started Aug 23 05:47:23 PM UTC 24
Finished Aug 23 05:47:25 PM UTC 24
Peak memory 237520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217784383 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 31.edn_intr.217784383
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/31.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/31.edn_smoke.2158978970
Short name T450
Test name
Test status
Simulation time 31608303 ps
CPU time 0.82 seconds
Started Aug 23 05:47:22 PM UTC 24
Finished Aug 23 05:47:24 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158978970 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 31.edn_smoke.2158978970
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/31.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/31.edn_stress_all.254042679
Short name T457
Test name
Test status
Simulation time 177209192 ps
CPU time 2.77 seconds
Started Aug 23 05:47:23 PM UTC 24
Finished Aug 23 05:47:27 PM UTC 24
Peak memory 229656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254042679 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.254042679
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/31.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/32.edn_alert.3640765000
Short name T461
Test name
Test status
Simulation time 141978280 ps
CPU time 1.1 seconds
Started Aug 23 05:47:27 PM UTC 24
Finished Aug 23 05:47:29 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640765000 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 32.edn_alert.3640765000
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/32.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/32.edn_alert_test.1832841411
Short name T462
Test name
Test status
Simulation time 67237370 ps
CPU time 0.83 seconds
Started Aug 23 05:47:28 PM UTC 24
Finished Aug 23 05:47:30 PM UTC 24
Peak memory 226964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832841411 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.1832841411
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/32.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/32.edn_disable.2892144185
Short name T460
Test name
Test status
Simulation time 14533754 ps
CPU time 0.79 seconds
Started Aug 23 05:47:27 PM UTC 24
Finished Aug 23 05:47:29 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892144185 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2892144185
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/32.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/32.edn_disable_auto_req_mode.4194116500
Short name T463
Test name
Test status
Simulation time 72178130 ps
CPU time 1.04 seconds
Started Aug 23 05:47:28 PM UTC 24
Finished Aug 23 05:47:30 PM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194116500 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable_auto_req_mode.4194116500
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/32.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/32.edn_err.486865354
Short name T181
Test name
Test status
Simulation time 43243122 ps
CPU time 0.8 seconds
Started Aug 23 05:47:27 PM UTC 24
Finished Aug 23 05:47:29 PM UTC 24
Peak memory 236964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486865354 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 32.edn_err.486865354
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/32.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/32.edn_genbits.1246571496
Short name T458
Test name
Test status
Simulation time 41566377 ps
CPU time 1.26 seconds
Started Aug 23 05:47:25 PM UTC 24
Finished Aug 23 05:47:28 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246571496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_genbits.1246571496
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/32.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/32.edn_intr.3259994080
Short name T459
Test name
Test status
Simulation time 24565172 ps
CPU time 0.77 seconds
Started Aug 23 05:47:27 PM UTC 24
Finished Aug 23 05:47:28 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259994080 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 32.edn_intr.3259994080
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/32.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/32.edn_smoke.3666543473
Short name T455
Test name
Test status
Simulation time 25052749 ps
CPU time 0.77 seconds
Started Aug 23 05:47:24 PM UTC 24
Finished Aug 23 05:47:26 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666543473 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 32.edn_smoke.3666543473
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/32.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/32.edn_stress_all.2209527188
Short name T464
Test name
Test status
Simulation time 773305390 ps
CPU time 3.32 seconds
Started Aug 23 05:47:26 PM UTC 24
Finished Aug 23 05:47:30 PM UTC 24
Peak memory 229608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209527188 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.2209527188
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/32.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/32.edn_stress_all_with_rand_reset.3457990792
Short name T248
Test name
Test status
Simulation time 23240406117 ps
CPU time 98.49 seconds
Started Aug 23 05:47:27 PM UTC 24
Finished Aug 23 05:49:07 PM UTC 24
Peak memory 231768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3457990792 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all
_with_rand_reset.3457990792
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/32.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/33.edn_alert.2503319865
Short name T157
Test name
Test status
Simulation time 23124706 ps
CPU time 0.97 seconds
Started Aug 23 05:47:31 PM UTC 24
Finished Aug 23 05:47:33 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503319865 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 33.edn_alert.2503319865
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/33.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/33.edn_alert_test.2309350597
Short name T469
Test name
Test status
Simulation time 56140169 ps
CPU time 0.79 seconds
Started Aug 23 05:47:32 PM UTC 24
Finished Aug 23 05:47:34 PM UTC 24
Peak memory 216688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309350597 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2309350597
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/33.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/33.edn_disable.99817585
Short name T467
Test name
Test status
Simulation time 23828619 ps
CPU time 0.78 seconds
Started Aug 23 05:47:31 PM UTC 24
Finished Aug 23 05:47:33 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99817585 -assert nopostproc +UVM_TESTNAME=edn_disab
le_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.99817585
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/33.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/33.edn_disable_auto_req_mode.3581832698
Short name T468
Test name
Test status
Simulation time 87630439 ps
CPU time 1.19 seconds
Started Aug 23 05:47:31 PM UTC 24
Finished Aug 23 05:47:33 PM UTC 24
Peak memory 230348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581832698 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable_auto_req_mode.3581832698
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/33.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/33.edn_err.958054138
Short name T218
Test name
Test status
Simulation time 36086015 ps
CPU time 1.15 seconds
Started Aug 23 05:47:31 PM UTC 24
Finished Aug 23 05:47:33 PM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958054138 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 33.edn_err.958054138
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/33.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/33.edn_intr.2725621006
Short name T466
Test name
Test status
Simulation time 25696409 ps
CPU time 0.78 seconds
Started Aug 23 05:47:30 PM UTC 24
Finished Aug 23 05:47:32 PM UTC 24
Peak memory 226056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725621006 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 33.edn_intr.2725621006
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/33.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/33.edn_smoke.2346763043
Short name T465
Test name
Test status
Simulation time 22802261 ps
CPU time 0.76 seconds
Started Aug 23 05:47:29 PM UTC 24
Finished Aug 23 05:47:31 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346763043 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 33.edn_smoke.2346763043
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/33.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/33.edn_stress_all.221062935
Short name T470
Test name
Test status
Simulation time 232607565 ps
CPU time 4.12 seconds
Started Aug 23 05:47:29 PM UTC 24
Finished Aug 23 05:47:34 PM UTC 24
Peak memory 229512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221062935 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.221062935
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/33.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/34.edn_alert.2007522323
Short name T143
Test name
Test status
Simulation time 26381484 ps
CPU time 1.05 seconds
Started Aug 23 05:47:34 PM UTC 24
Finished Aug 23 05:47:36 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007522323 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 34.edn_alert.2007522323
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/34.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/34.edn_alert_test.4193919063
Short name T477
Test name
Test status
Simulation time 69576386 ps
CPU time 0.75 seconds
Started Aug 23 05:47:35 PM UTC 24
Finished Aug 23 05:47:37 PM UTC 24
Peak memory 217108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193919063 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.4193919063
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/34.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/34.edn_disable.777978043
Short name T476
Test name
Test status
Simulation time 111048959 ps
CPU time 0.71 seconds
Started Aug 23 05:47:35 PM UTC 24
Finished Aug 23 05:47:37 PM UTC 24
Peak memory 226336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777978043 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.777978043
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/34.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/34.edn_disable_auto_req_mode.3733405492
Short name T478
Test name
Test status
Simulation time 39457825 ps
CPU time 1.12 seconds
Started Aug 23 05:47:35 PM UTC 24
Finished Aug 23 05:47:38 PM UTC 24
Peak memory 226448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733405492 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable_auto_req_mode.3733405492
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/34.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/34.edn_err.1846943322
Short name T221
Test name
Test status
Simulation time 80901620 ps
CPU time 0.9 seconds
Started Aug 23 05:47:35 PM UTC 24
Finished Aug 23 05:47:37 PM UTC 24
Peak memory 226276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846943322 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 34.edn_err.1846943322
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/34.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/34.edn_genbits.3120961127
Short name T473
Test name
Test status
Simulation time 121732887 ps
CPU time 1.14 seconds
Started Aug 23 05:47:33 PM UTC 24
Finished Aug 23 05:47:35 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120961127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3120961127
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/34.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/34.edn_intr.590880486
Short name T474
Test name
Test status
Simulation time 39712202 ps
CPU time 0.76 seconds
Started Aug 23 05:47:34 PM UTC 24
Finished Aug 23 05:47:36 PM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590880486 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 34.edn_intr.590880486
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/34.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/34.edn_smoke.3022427528
Short name T471
Test name
Test status
Simulation time 42665893 ps
CPU time 0.76 seconds
Started Aug 23 05:47:33 PM UTC 24
Finished Aug 23 05:47:35 PM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022427528 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 34.edn_smoke.3022427528
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/34.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/34.edn_stress_all.2369689687
Short name T475
Test name
Test status
Simulation time 126446560 ps
CPU time 2.51 seconds
Started Aug 23 05:47:33 PM UTC 24
Finished Aug 23 05:47:37 PM UTC 24
Peak memory 227744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369689687 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.2369689687
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/34.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/34.edn_stress_all_with_rand_reset.3919498296
Short name T571
Test name
Test status
Simulation time 1925784622 ps
CPU time 42.76 seconds
Started Aug 23 05:47:34 PM UTC 24
Finished Aug 23 05:48:18 PM UTC 24
Peak memory 231776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3919498296 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all
_with_rand_reset.3919498296
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/34.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/35.edn_alert.206150681
Short name T482
Test name
Test status
Simulation time 33252294 ps
CPU time 1.16 seconds
Started Aug 23 05:47:38 PM UTC 24
Finished Aug 23 05:47:40 PM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206150681 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 35.edn_alert.206150681
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/35.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/35.edn_alert_test.3118811200
Short name T484
Test name
Test status
Simulation time 15935957 ps
CPU time 0.81 seconds
Started Aug 23 05:47:39 PM UTC 24
Finished Aug 23 05:47:41 PM UTC 24
Peak memory 216688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118811200 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.3118811200
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/35.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/35.edn_disable.2502873199
Short name T223
Test name
Test status
Simulation time 55689950 ps
CPU time 0.76 seconds
Started Aug 23 05:47:38 PM UTC 24
Finished Aug 23 05:47:40 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502873199 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2502873199
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/35.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/35.edn_disable_auto_req_mode.3344513920
Short name T485
Test name
Test status
Simulation time 32567021 ps
CPU time 1.03 seconds
Started Aug 23 05:47:39 PM UTC 24
Finished Aug 23 05:47:41 PM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344513920 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable_auto_req_mode.3344513920
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/35.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/35.edn_err.2778615775
Short name T481
Test name
Test status
Simulation time 25416254 ps
CPU time 1.04 seconds
Started Aug 23 05:47:38 PM UTC 24
Finished Aug 23 05:47:40 PM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778615775 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 35.edn_err.2778615775
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/35.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/35.edn_genbits.1508581001
Short name T314
Test name
Test status
Simulation time 159282656 ps
CPU time 0.98 seconds
Started Aug 23 05:47:37 PM UTC 24
Finished Aug 23 05:47:39 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508581001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1508581001
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/35.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/35.edn_intr.1789698124
Short name T480
Test name
Test status
Simulation time 28922452 ps
CPU time 0.82 seconds
Started Aug 23 05:47:38 PM UTC 24
Finished Aug 23 05:47:39 PM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789698124 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 35.edn_intr.1789698124
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/35.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/35.edn_smoke.3686644589
Short name T479
Test name
Test status
Simulation time 18059297 ps
CPU time 0.85 seconds
Started Aug 23 05:47:36 PM UTC 24
Finished Aug 23 05:47:38 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686644589 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 35.edn_smoke.3686644589
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/35.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/35.edn_stress_all.2296025639
Short name T486
Test name
Test status
Simulation time 343485499 ps
CPU time 3.22 seconds
Started Aug 23 05:47:37 PM UTC 24
Finished Aug 23 05:47:41 PM UTC 24
Peak memory 227676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296025639 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2296025639
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/35.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/35.edn_stress_all_with_rand_reset.1560614908
Short name T575
Test name
Test status
Simulation time 7644540222 ps
CPU time 41.44 seconds
Started Aug 23 05:47:38 PM UTC 24
Finished Aug 23 05:48:21 PM UTC 24
Peak memory 233956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1560614908 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all
_with_rand_reset.1560614908
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/35.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/36.edn_alert.2289642218
Short name T191
Test name
Test status
Simulation time 49564288 ps
CPU time 0.94 seconds
Started Aug 23 05:47:41 PM UTC 24
Finished Aug 23 05:47:43 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289642218 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 36.edn_alert.2289642218
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/36.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/36.edn_alert_test.1249962997
Short name T493
Test name
Test status
Simulation time 39680508 ps
CPU time 0.85 seconds
Started Aug 23 05:47:42 PM UTC 24
Finished Aug 23 05:47:44 PM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249962997 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.1249962997
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/36.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/36.edn_disable.949176555
Short name T490
Test name
Test status
Simulation time 130241948 ps
CPU time 0.74 seconds
Started Aug 23 05:47:41 PM UTC 24
Finished Aug 23 05:47:43 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949176555 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.949176555
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/36.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/36.edn_disable_auto_req_mode.686120310
Short name T492
Test name
Test status
Simulation time 126955551 ps
CPU time 0.91 seconds
Started Aug 23 05:47:42 PM UTC 24
Finished Aug 23 05:47:44 PM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686120310 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable_auto_req_mode.686120310
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/36.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/36.edn_err.3790942080
Short name T199
Test name
Test status
Simulation time 18634727 ps
CPU time 0.98 seconds
Started Aug 23 05:47:41 PM UTC 24
Finished Aug 23 05:47:43 PM UTC 24
Peak memory 237336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790942080 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 36.edn_err.3790942080
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/36.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/36.edn_genbits.3809873780
Short name T352
Test name
Test status
Simulation time 47941561 ps
CPU time 1.02 seconds
Started Aug 23 05:47:40 PM UTC 24
Finished Aug 23 05:47:42 PM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809873780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3809873780
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/36.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/36.edn_intr.2958057841
Short name T489
Test name
Test status
Simulation time 60894441 ps
CPU time 0.77 seconds
Started Aug 23 05:47:41 PM UTC 24
Finished Aug 23 05:47:43 PM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958057841 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 36.edn_intr.2958057841
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/36.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/36.edn_smoke.710033673
Short name T487
Test name
Test status
Simulation time 27505198 ps
CPU time 0.82 seconds
Started Aug 23 05:47:40 PM UTC 24
Finished Aug 23 05:47:42 PM UTC 24
Peak memory 226096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710033673 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 36.edn_smoke.710033673
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/36.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/36.edn_stress_all.675593503
Short name T491
Test name
Test status
Simulation time 105169716 ps
CPU time 2.21 seconds
Started Aug 23 05:47:40 PM UTC 24
Finished Aug 23 05:47:43 PM UTC 24
Peak memory 229528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675593503 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.675593503
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/36.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/36.edn_stress_all_with_rand_reset.1636894791
Short name T620
Test name
Test status
Simulation time 10830422320 ps
CPU time 63.05 seconds
Started Aug 23 05:47:41 PM UTC 24
Finished Aug 23 05:48:46 PM UTC 24
Peak memory 233768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1636894791 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all
_with_rand_reset.1636894791
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/36.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/37.edn_alert.848295797
Short name T500
Test name
Test status
Simulation time 26004290 ps
CPU time 1.02 seconds
Started Aug 23 05:47:44 PM UTC 24
Finished Aug 23 05:47:46 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848295797 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 37.edn_alert.848295797
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/37.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/37.edn_alert_test.3519365270
Short name T499
Test name
Test status
Simulation time 13265309 ps
CPU time 0.73 seconds
Started Aug 23 05:47:45 PM UTC 24
Finished Aug 23 05:47:46 PM UTC 24
Peak memory 216972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519365270 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.3519365270
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/37.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/37.edn_disable.1983218231
Short name T498
Test name
Test status
Simulation time 20302960 ps
CPU time 0.77 seconds
Started Aug 23 05:47:44 PM UTC 24
Finished Aug 23 05:47:46 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983218231 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1983218231
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/37.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/37.edn_disable_auto_req_mode.568787902
Short name T299
Test name
Test status
Simulation time 61843671 ps
CPU time 0.84 seconds
Started Aug 23 05:47:44 PM UTC 24
Finished Aug 23 05:47:46 PM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568787902 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable_auto_req_mode.568787902
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/37.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/37.edn_err.10190765
Short name T193
Test name
Test status
Simulation time 72427152 ps
CPU time 0.83 seconds
Started Aug 23 05:47:44 PM UTC 24
Finished Aug 23 05:47:46 PM UTC 24
Peak memory 236964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10190765 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 37.edn_err.10190765
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/37.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/37.edn_genbits.3371486588
Short name T15
Test name
Test status
Simulation time 68006693 ps
CPU time 0.89 seconds
Started Aug 23 05:47:43 PM UTC 24
Finished Aug 23 05:47:45 PM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371486588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3371486588
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/37.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/37.edn_intr.515195558
Short name T496
Test name
Test status
Simulation time 21484391 ps
CPU time 0.89 seconds
Started Aug 23 05:47:43 PM UTC 24
Finished Aug 23 05:47:45 PM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515195558 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 37.edn_intr.515195558
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/37.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/37.edn_smoke.3805776202
Short name T494
Test name
Test status
Simulation time 122881340 ps
CPU time 0.8 seconds
Started Aug 23 05:47:42 PM UTC 24
Finished Aug 23 05:47:44 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805776202 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 37.edn_smoke.3805776202
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/37.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/37.edn_stress_all.2544034118
Short name T502
Test name
Test status
Simulation time 454396270 ps
CPU time 2.62 seconds
Started Aug 23 05:47:43 PM UTC 24
Finished Aug 23 05:47:47 PM UTC 24
Peak memory 229536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544034118 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2544034118
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/37.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/37.edn_stress_all_with_rand_reset.22944326
Short name T658
Test name
Test status
Simulation time 11619107118 ps
CPU time 74.19 seconds
Started Aug 23 05:47:43 PM UTC 24
Finished Aug 23 05:48:59 PM UTC 24
Peak memory 230140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=22944326 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_w
ith_rand_reset.22944326
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/37.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/38.edn_alert.3239584271
Short name T186
Test name
Test status
Simulation time 101065007 ps
CPU time 1.03 seconds
Started Aug 23 05:47:47 PM UTC 24
Finished Aug 23 05:47:49 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239584271 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 38.edn_alert.3239584271
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/38.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/38.edn_alert_test.53936886
Short name T509
Test name
Test status
Simulation time 74338631 ps
CPU time 0.75 seconds
Started Aug 23 05:47:48 PM UTC 24
Finished Aug 23 05:47:50 PM UTC 24
Peak memory 226072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53936886 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.53936886
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/38.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/38.edn_disable.4251391493
Short name T200
Test name
Test status
Simulation time 13584966 ps
CPU time 0.79 seconds
Started Aug 23 05:47:47 PM UTC 24
Finished Aug 23 05:47:49 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251391493 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.4251391493
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/38.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/38.edn_disable_auto_req_mode.1783421372
Short name T506
Test name
Test status
Simulation time 48781617 ps
CPU time 0.92 seconds
Started Aug 23 05:47:47 PM UTC 24
Finished Aug 23 05:47:49 PM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783421372 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable_auto_req_mode.1783421372
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/38.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/38.edn_err.85414528
Short name T154
Test name
Test status
Simulation time 50937244 ps
CPU time 0.85 seconds
Started Aug 23 05:47:47 PM UTC 24
Finished Aug 23 05:47:49 PM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85414528 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 38.edn_err.85414528
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/38.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/38.edn_genbits.748482783
Short name T503
Test name
Test status
Simulation time 76346550 ps
CPU time 0.98 seconds
Started Aug 23 05:47:46 PM UTC 24
Finished Aug 23 05:47:48 PM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748482783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_genbits.748482783
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/38.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/38.edn_intr.2358863720
Short name T505
Test name
Test status
Simulation time 33279881 ps
CPU time 0.77 seconds
Started Aug 23 05:47:47 PM UTC 24
Finished Aug 23 05:47:49 PM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358863720 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 38.edn_intr.2358863720
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/38.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/38.edn_smoke.2001589268
Short name T501
Test name
Test status
Simulation time 27262134 ps
CPU time 0.81 seconds
Started Aug 23 05:47:45 PM UTC 24
Finished Aug 23 05:47:46 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001589268 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 38.edn_smoke.2001589268
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/38.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/38.edn_stress_all.3129474000
Short name T504
Test name
Test status
Simulation time 69435420 ps
CPU time 1.63 seconds
Started Aug 23 05:47:46 PM UTC 24
Finished Aug 23 05:47:48 PM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129474000 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3129474000
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/38.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/38.edn_stress_all_with_rand_reset.933126801
Short name T645
Test name
Test status
Simulation time 7103931135 ps
CPU time 67.93 seconds
Started Aug 23 05:47:46 PM UTC 24
Finished Aug 23 05:48:55 PM UTC 24
Peak memory 229780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=933126801 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_
with_rand_reset.933126801
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/38.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/39.edn_alert.1047192020
Short name T513
Test name
Test status
Simulation time 72413313 ps
CPU time 0.94 seconds
Started Aug 23 05:47:49 PM UTC 24
Finished Aug 23 05:47:51 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047192020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 39.edn_alert.1047192020
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/39.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/39.edn_alert_test.577604426
Short name T515
Test name
Test status
Simulation time 26005103 ps
CPU time 0.77 seconds
Started Aug 23 05:47:50 PM UTC 24
Finished Aug 23 05:47:52 PM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577604426 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.577604426
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/39.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/39.edn_disable.2567624753
Short name T510
Test name
Test status
Simulation time 15559446 ps
CPU time 0.69 seconds
Started Aug 23 05:47:49 PM UTC 24
Finished Aug 23 05:47:51 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567624753 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2567624753
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/39.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/39.edn_disable_auto_req_mode.2143299972
Short name T150
Test name
Test status
Simulation time 57508603 ps
CPU time 0.89 seconds
Started Aug 23 05:47:50 PM UTC 24
Finished Aug 23 05:47:52 PM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143299972 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable_auto_req_mode.2143299972
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/39.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/39.edn_err.2738527513
Short name T514
Test name
Test status
Simulation time 30189187 ps
CPU time 1.14 seconds
Started Aug 23 05:47:49 PM UTC 24
Finished Aug 23 05:47:51 PM UTC 24
Peak memory 242240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738527513 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 39.edn_err.2738527513
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/39.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/39.edn_genbits.3297065091
Short name T339
Test name
Test status
Simulation time 410142897 ps
CPU time 1.79 seconds
Started Aug 23 05:47:48 PM UTC 24
Finished Aug 23 05:47:51 PM UTC 24
Peak memory 230420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297065091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3297065091
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/39.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/39.edn_intr.1773301817
Short name T511
Test name
Test status
Simulation time 22085812 ps
CPU time 0.91 seconds
Started Aug 23 05:47:49 PM UTC 24
Finished Aug 23 05:47:51 PM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773301817 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 39.edn_intr.1773301817
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/39.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/39.edn_smoke.3082180106
Short name T508
Test name
Test status
Simulation time 33664414 ps
CPU time 0.77 seconds
Started Aug 23 05:47:48 PM UTC 24
Finished Aug 23 05:47:50 PM UTC 24
Peak memory 225568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082180106 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 39.edn_smoke.3082180106
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/39.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/39.edn_stress_all.2273936977
Short name T512
Test name
Test status
Simulation time 211702312 ps
CPU time 1.96 seconds
Started Aug 23 05:47:48 PM UTC 24
Finished Aug 23 05:47:51 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273936977 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2273936977
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/39.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/4.edn_alert_test.4153900685
Short name T356
Test name
Test status
Simulation time 21863742 ps
CPU time 0.75 seconds
Started Aug 23 05:46:10 PM UTC 24
Finished Aug 23 05:46:12 PM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153900685 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.4153900685
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/4.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/4.edn_disable.780967025
Short name T257
Test name
Test status
Simulation time 19101387 ps
CPU time 0.73 seconds
Started Aug 23 05:46:10 PM UTC 24
Finished Aug 23 05:46:12 PM UTC 24
Peak memory 216132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780967025 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.780967025
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/4.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/4.edn_disable_auto_req_mode.2271658672
Short name T43
Test name
Test status
Simulation time 50692689 ps
CPU time 0.9 seconds
Started Aug 23 05:46:10 PM UTC 24
Finished Aug 23 05:46:12 PM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271658672 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable_auto_req_mode.2271658672
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/4.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/4.edn_err.981440976
Short name T7
Test name
Test status
Simulation time 20153518 ps
CPU time 0.95 seconds
Started Aug 23 05:46:10 PM UTC 24
Finished Aug 23 05:46:12 PM UTC 24
Peak memory 230400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981440976 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 4.edn_err.981440976
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/4.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/4.edn_genbits.1425715461
Short name T46
Test name
Test status
Simulation time 54262998 ps
CPU time 1.39 seconds
Started Aug 23 05:46:10 PM UTC 24
Finished Aug 23 05:46:12 PM UTC 24
Peak memory 228560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425715461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1425715461
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/4.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/4.edn_intr.3604001303
Short name T35
Test name
Test status
Simulation time 20877350 ps
CPU time 0.94 seconds
Started Aug 23 05:46:10 PM UTC 24
Finished Aug 23 05:46:12 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604001303 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 4.edn_intr.3604001303
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/4.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/4.edn_regwen.1409978352
Short name T349
Test name
Test status
Simulation time 20946409 ps
CPU time 0.78 seconds
Started Aug 23 05:46:10 PM UTC 24
Finished Aug 23 05:46:12 PM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409978352 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 4.edn_regwen.1409978352
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/4.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/4.edn_sec_cm.1779530179
Short name T58
Test name
Test status
Simulation time 644953251 ps
CPU time 4.03 seconds
Started Aug 23 05:46:10 PM UTC 24
Finished Aug 23 05:46:15 PM UTC 24
Peak memory 260512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779530179 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.1779530179
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/4.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/4.edn_smoke.196478620
Short name T118
Test name
Test status
Simulation time 15505847 ps
CPU time 0.85 seconds
Started Aug 23 05:46:10 PM UTC 24
Finished Aug 23 05:46:12 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196478620 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 4.edn_smoke.196478620
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/4.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/4.edn_stress_all_with_rand_reset.1633400725
Short name T235
Test name
Test status
Simulation time 12366542935 ps
CPU time 60.06 seconds
Started Aug 23 05:46:10 PM UTC 24
Finished Aug 23 05:47:12 PM UTC 24
Peak memory 229780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1633400725 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_
with_rand_reset.1633400725
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/4.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/40.edn_alert_test.3189143922
Short name T523
Test name
Test status
Simulation time 104697727 ps
CPU time 1.22 seconds
Started Aug 23 05:47:53 PM UTC 24
Finished Aug 23 05:47:55 PM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189143922 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3189143922
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/40.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/40.edn_disable.3488955065
Short name T520
Test name
Test status
Simulation time 13205466 ps
CPU time 0.77 seconds
Started Aug 23 05:47:52 PM UTC 24
Finished Aug 23 05:47:54 PM UTC 24
Peak memory 226004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488955065 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.3488955065
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/40.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/40.edn_disable_auto_req_mode.1869018013
Short name T141
Test name
Test status
Simulation time 56031580 ps
CPU time 1.03 seconds
Started Aug 23 05:47:52 PM UTC 24
Finished Aug 23 05:47:55 PM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869018013 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable_auto_req_mode.1869018013
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/40.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/40.edn_err.2842836353
Short name T522
Test name
Test status
Simulation time 44525949 ps
CPU time 0.93 seconds
Started Aug 23 05:47:52 PM UTC 24
Finished Aug 23 05:47:54 PM UTC 24
Peak memory 230004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842836353 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 40.edn_err.2842836353
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/40.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/40.edn_intr.3025339048
Short name T518
Test name
Test status
Simulation time 27897215 ps
CPU time 0.82 seconds
Started Aug 23 05:47:51 PM UTC 24
Finished Aug 23 05:47:53 PM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025339048 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 40.edn_intr.3025339048
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/40.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/40.edn_smoke.74498390
Short name T516
Test name
Test status
Simulation time 18495190 ps
CPU time 0.88 seconds
Started Aug 23 05:47:50 PM UTC 24
Finished Aug 23 05:47:52 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74498390 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 40.edn_smoke.74498390
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/40.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/40.edn_stress_all.34897510
Short name T519
Test name
Test status
Simulation time 496303950 ps
CPU time 1.83 seconds
Started Aug 23 05:47:51 PM UTC 24
Finished Aug 23 05:47:54 PM UTC 24
Peak memory 228184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34897510 -assert nopostproc +UVM_TESTNAME=edn_s
tress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.34897510
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/40.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/40.edn_stress_all_with_rand_reset.3829940691
Short name T249
Test name
Test status
Simulation time 13890011073 ps
CPU time 84.41 seconds
Started Aug 23 05:47:51 PM UTC 24
Finished Aug 23 05:49:18 PM UTC 24
Peak memory 229636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3829940691 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all
_with_rand_reset.3829940691
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/40.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/41.edn_alert.1399307629
Short name T170
Test name
Test status
Simulation time 66587820 ps
CPU time 0.9 seconds
Started Aug 23 05:47:55 PM UTC 24
Finished Aug 23 05:47:57 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399307629 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 41.edn_alert.1399307629
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/41.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/41.edn_alert_test.2743096710
Short name T528
Test name
Test status
Simulation time 57050213 ps
CPU time 0.75 seconds
Started Aug 23 05:47:56 PM UTC 24
Finished Aug 23 05:47:58 PM UTC 24
Peak memory 216868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743096710 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2743096710
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/41.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/41.edn_disable.1504565049
Short name T525
Test name
Test status
Simulation time 59330468 ps
CPU time 0.72 seconds
Started Aug 23 05:47:55 PM UTC 24
Finished Aug 23 05:47:57 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504565049 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.1504565049
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/41.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/41.edn_disable_auto_req_mode.1820003747
Short name T529
Test name
Test status
Simulation time 21515215 ps
CPU time 0.83 seconds
Started Aug 23 05:47:56 PM UTC 24
Finished Aug 23 05:47:58 PM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820003747 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable_auto_req_mode.1820003747
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/41.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/41.edn_err.3968359538
Short name T171
Test name
Test status
Simulation time 28699827 ps
CPU time 0.97 seconds
Started Aug 23 05:47:55 PM UTC 24
Finished Aug 23 05:47:57 PM UTC 24
Peak memory 243636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968359538 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 41.edn_err.3968359538
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/41.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/41.edn_genbits.1477169886
Short name T524
Test name
Test status
Simulation time 38192792 ps
CPU time 1.29 seconds
Started Aug 23 05:47:54 PM UTC 24
Finished Aug 23 05:47:56 PM UTC 24
Peak memory 228176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477169886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1477169886
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/41.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/41.edn_intr.1655029864
Short name T526
Test name
Test status
Simulation time 31810261 ps
CPU time 0.95 seconds
Started Aug 23 05:47:55 PM UTC 24
Finished Aug 23 05:47:57 PM UTC 24
Peak memory 237464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655029864 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 41.edn_intr.1655029864
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/41.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/41.edn_smoke.2895401106
Short name T521
Test name
Test status
Simulation time 27970700 ps
CPU time 0.8 seconds
Started Aug 23 05:47:53 PM UTC 24
Finished Aug 23 05:47:54 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895401106 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 41.edn_smoke.2895401106
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/41.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/41.edn_stress_all.533803813
Short name T530
Test name
Test status
Simulation time 189649321 ps
CPU time 3.35 seconds
Started Aug 23 05:47:54 PM UTC 24
Finished Aug 23 05:47:58 PM UTC 24
Peak memory 231600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533803813 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.533803813
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/41.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/41.edn_stress_all_with_rand_reset.4037984025
Short name T753
Test name
Test status
Simulation time 4325914773 ps
CPU time 86.69 seconds
Started Aug 23 05:47:55 PM UTC 24
Finished Aug 23 05:49:23 PM UTC 24
Peak memory 229988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=4037984025 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all
_with_rand_reset.4037984025
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/41.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/42.edn_alert_test.3217105221
Short name T537
Test name
Test status
Simulation time 38639576 ps
CPU time 0.68 seconds
Started Aug 23 05:47:59 PM UTC 24
Finished Aug 23 05:48:01 PM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217105221 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.3217105221
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/42.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/42.edn_disable.2619990031
Short name T535
Test name
Test status
Simulation time 13569569 ps
CPU time 0.8 seconds
Started Aug 23 05:47:58 PM UTC 24
Finished Aug 23 05:48:00 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619990031 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.2619990031
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/42.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/42.edn_disable_auto_req_mode.2868993997
Short name T177
Test name
Test status
Simulation time 106136080 ps
CPU time 0.95 seconds
Started Aug 23 05:47:59 PM UTC 24
Finished Aug 23 05:48:01 PM UTC 24
Peak memory 230348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868993997 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable_auto_req_mode.2868993997
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/42.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/42.edn_err.3815998510
Short name T533
Test name
Test status
Simulation time 29344418 ps
CPU time 0.71 seconds
Started Aug 23 05:47:58 PM UTC 24
Finished Aug 23 05:48:00 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815998510 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 42.edn_err.3815998510
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/42.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/42.edn_genbits.1505073592
Short name T532
Test name
Test status
Simulation time 66346617 ps
CPU time 0.98 seconds
Started Aug 23 05:47:57 PM UTC 24
Finished Aug 23 05:47:59 PM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505073592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_genbits.1505073592
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/42.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/42.edn_intr.4103595647
Short name T534
Test name
Test status
Simulation time 44729255 ps
CPU time 0.72 seconds
Started Aug 23 05:47:58 PM UTC 24
Finished Aug 23 05:48:00 PM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103595647 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 42.edn_intr.4103595647
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/42.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/42.edn_smoke.3677779477
Short name T531
Test name
Test status
Simulation time 25962939 ps
CPU time 0.75 seconds
Started Aug 23 05:47:57 PM UTC 24
Finished Aug 23 05:47:59 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677779477 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 42.edn_smoke.3677779477
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/42.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/42.edn_stress_all.3716737437
Short name T539
Test name
Test status
Simulation time 275879831 ps
CPU time 3.03 seconds
Started Aug 23 05:47:57 PM UTC 24
Finished Aug 23 05:48:01 PM UTC 24
Peak memory 227664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716737437 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.3716737437
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/42.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/43.edn_alert.240193779
Short name T151
Test name
Test status
Simulation time 47574061 ps
CPU time 0.97 seconds
Started Aug 23 05:48:01 PM UTC 24
Finished Aug 23 05:48:04 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240193779 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 43.edn_alert.240193779
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/43.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/43.edn_alert_test.1515896455
Short name T544
Test name
Test status
Simulation time 20962121 ps
CPU time 0.72 seconds
Started Aug 23 05:48:03 PM UTC 24
Finished Aug 23 05:48:04 PM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515896455 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1515896455
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/43.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/43.edn_disable.1126201716
Short name T543
Test name
Test status
Simulation time 30223120 ps
CPU time 0.69 seconds
Started Aug 23 05:48:01 PM UTC 24
Finished Aug 23 05:48:03 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126201716 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.1126201716
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/43.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/43.edn_disable_auto_req_mode.2243583758
Short name T220
Test name
Test status
Simulation time 76449758 ps
CPU time 0.85 seconds
Started Aug 23 05:48:02 PM UTC 24
Finished Aug 23 05:48:03 PM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243583758 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable_auto_req_mode.2243583758
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/43.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/43.edn_err.2875697879
Short name T155
Test name
Test status
Simulation time 30777353 ps
CPU time 0.94 seconds
Started Aug 23 05:48:01 PM UTC 24
Finished Aug 23 05:48:03 PM UTC 24
Peak memory 244276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875697879 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 43.edn_err.2875697879
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/43.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/43.edn_genbits.3197917983
Short name T542
Test name
Test status
Simulation time 43753209 ps
CPU time 1.43 seconds
Started Aug 23 05:48:00 PM UTC 24
Finished Aug 23 05:48:03 PM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197917983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_genbits.3197917983
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/43.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/43.edn_intr.3235903387
Short name T541
Test name
Test status
Simulation time 30513307 ps
CPU time 0.86 seconds
Started Aug 23 05:48:00 PM UTC 24
Finished Aug 23 05:48:02 PM UTC 24
Peak memory 237404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235903387 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 43.edn_intr.3235903387
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/43.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/43.edn_smoke.1445168485
Short name T538
Test name
Test status
Simulation time 42846611 ps
CPU time 0.72 seconds
Started Aug 23 05:47:59 PM UTC 24
Finished Aug 23 05:48:01 PM UTC 24
Peak memory 216016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445168485 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 43.edn_smoke.1445168485
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/43.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/43.edn_stress_all.1865633102
Short name T547
Test name
Test status
Simulation time 844959290 ps
CPU time 3.91 seconds
Started Aug 23 05:48:00 PM UTC 24
Finished Aug 23 05:48:05 PM UTC 24
Peak memory 231516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865633102 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1865633102
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/43.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/44.edn_alert.685416874
Short name T551
Test name
Test status
Simulation time 73988138 ps
CPU time 0.9 seconds
Started Aug 23 05:48:05 PM UTC 24
Finished Aug 23 05:48:07 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685416874 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 44.edn_alert.685416874
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/44.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/44.edn_alert_test.3823208385
Short name T554
Test name
Test status
Simulation time 37273094 ps
CPU time 0.7 seconds
Started Aug 23 05:48:06 PM UTC 24
Finished Aug 23 05:48:08 PM UTC 24
Peak memory 216240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823208385 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3823208385
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/44.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/44.edn_disable.2096283448
Short name T550
Test name
Test status
Simulation time 26670824 ps
CPU time 0.69 seconds
Started Aug 23 05:48:05 PM UTC 24
Finished Aug 23 05:48:07 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096283448 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2096283448
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/44.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/44.edn_disable_auto_req_mode.1966599643
Short name T552
Test name
Test status
Simulation time 27591940 ps
CPU time 0.97 seconds
Started Aug 23 05:48:05 PM UTC 24
Finished Aug 23 05:48:07 PM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966599643 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable_auto_req_mode.1966599643
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/44.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/44.edn_err.2445681906
Short name T166
Test name
Test status
Simulation time 29095849 ps
CPU time 1.02 seconds
Started Aug 23 05:48:05 PM UTC 24
Finished Aug 23 05:48:07 PM UTC 24
Peak memory 236608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445681906 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 44.edn_err.2445681906
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/44.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/44.edn_genbits.1824815897
Short name T546
Test name
Test status
Simulation time 69202451 ps
CPU time 1.16 seconds
Started Aug 23 05:48:03 PM UTC 24
Finished Aug 23 05:48:05 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824815897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1824815897
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/44.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/44.edn_intr.2465633170
Short name T548
Test name
Test status
Simulation time 33108923 ps
CPU time 0.73 seconds
Started Aug 23 05:48:04 PM UTC 24
Finished Aug 23 05:48:05 PM UTC 24
Peak memory 226500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465633170 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 44.edn_intr.2465633170
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/44.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/44.edn_smoke.802771584
Short name T545
Test name
Test status
Simulation time 45037655 ps
CPU time 0.77 seconds
Started Aug 23 05:48:03 PM UTC 24
Finished Aug 23 05:48:04 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802771584 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 44.edn_smoke.802771584
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/44.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/44.edn_stress_all.3272905335
Short name T549
Test name
Test status
Simulation time 846868579 ps
CPU time 1.2 seconds
Started Aug 23 05:48:04 PM UTC 24
Finished Aug 23 05:48:06 PM UTC 24
Peak memory 226808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272905335 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3272905335
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/44.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/44.edn_stress_all_with_rand_reset.1930680589
Short name T586
Test name
Test status
Simulation time 6039177518 ps
CPU time 21.68 seconds
Started Aug 23 05:48:04 PM UTC 24
Finished Aug 23 05:48:27 PM UTC 24
Peak memory 229720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1930680589 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all
_with_rand_reset.1930680589
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/44.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/45.edn_alert.1886962059
Short name T144
Test name
Test status
Simulation time 39064223 ps
CPU time 0.94 seconds
Started Aug 23 05:48:08 PM UTC 24
Finished Aug 23 05:48:10 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886962059 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 45.edn_alert.1886962059
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/45.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/45.edn_alert_test.2133524239
Short name T558
Test name
Test status
Simulation time 23157557 ps
CPU time 0.71 seconds
Started Aug 23 05:48:09 PM UTC 24
Finished Aug 23 05:48:11 PM UTC 24
Peak memory 217272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133524239 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2133524239
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/45.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/45.edn_disable.2750760119
Short name T559
Test name
Test status
Simulation time 37647943 ps
CPU time 0.72 seconds
Started Aug 23 05:48:09 PM UTC 24
Finished Aug 23 05:48:11 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750760119 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2750760119
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/45.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/45.edn_disable_auto_req_mode.3580544165
Short name T560
Test name
Test status
Simulation time 22121397 ps
CPU time 0.87 seconds
Started Aug 23 05:48:09 PM UTC 24
Finished Aug 23 05:48:11 PM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580544165 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable_auto_req_mode.3580544165
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/45.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/45.edn_err.3833455586
Short name T182
Test name
Test status
Simulation time 25760489 ps
CPU time 0.8 seconds
Started Aug 23 05:48:08 PM UTC 24
Finished Aug 23 05:48:10 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833455586 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 45.edn_err.3833455586
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/45.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/45.edn_genbits.2348958491
Short name T354
Test name
Test status
Simulation time 24733539 ps
CPU time 1.11 seconds
Started Aug 23 05:48:06 PM UTC 24
Finished Aug 23 05:48:08 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348958491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_genbits.2348958491
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/45.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/45.edn_intr.2965252165
Short name T556
Test name
Test status
Simulation time 28625353 ps
CPU time 0.76 seconds
Started Aug 23 05:48:08 PM UTC 24
Finished Aug 23 05:48:10 PM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965252165 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 45.edn_intr.2965252165
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/45.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/45.edn_smoke.3346147721
Short name T553
Test name
Test status
Simulation time 77410562 ps
CPU time 0.76 seconds
Started Aug 23 05:48:06 PM UTC 24
Finished Aug 23 05:48:08 PM UTC 24
Peak memory 226208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346147721 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 45.edn_smoke.3346147721
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/45.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/45.edn_stress_all.140446998
Short name T557
Test name
Test status
Simulation time 519294069 ps
CPU time 2.13 seconds
Started Aug 23 05:48:07 PM UTC 24
Finished Aug 23 05:48:11 PM UTC 24
Peak memory 229852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140446998 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.140446998
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/45.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/45.edn_stress_all_with_rand_reset.334344481
Short name T732
Test name
Test status
Simulation time 8199660937 ps
CPU time 69.2 seconds
Started Aug 23 05:48:07 PM UTC 24
Finished Aug 23 05:49:18 PM UTC 24
Peak memory 234232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=334344481 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_
with_rand_reset.334344481
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/45.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/46.edn_alert_test.827313522
Short name T566
Test name
Test status
Simulation time 30827335 ps
CPU time 0.77 seconds
Started Aug 23 05:48:14 PM UTC 24
Finished Aug 23 05:48:16 PM UTC 24
Peak memory 216688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827313522 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.827313522
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/46.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/46.edn_disable.2103609256
Short name T564
Test name
Test status
Simulation time 13931544 ps
CPU time 0.77 seconds
Started Aug 23 05:48:12 PM UTC 24
Finished Aug 23 05:48:15 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103609256 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.2103609256
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/46.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/46.edn_disable_auto_req_mode.3201958962
Short name T565
Test name
Test status
Simulation time 50945660 ps
CPU time 1 seconds
Started Aug 23 05:48:12 PM UTC 24
Finished Aug 23 05:48:15 PM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201958962 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable_auto_req_mode.3201958962
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/46.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/46.edn_err.428416780
Short name T507
Test name
Test status
Simulation time 36433881 ps
CPU time 0.88 seconds
Started Aug 23 05:48:12 PM UTC 24
Finished Aug 23 05:48:15 PM UTC 24
Peak memory 229968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428416780 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 46.edn_err.428416780
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/46.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/46.edn_genbits.355376104
Short name T562
Test name
Test status
Simulation time 32089026 ps
CPU time 0.87 seconds
Started Aug 23 05:48:10 PM UTC 24
Finished Aug 23 05:48:12 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355376104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.edn_genbits.355376104
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/46.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/46.edn_intr.1262113868
Short name T563
Test name
Test status
Simulation time 36733426 ps
CPU time 0.74 seconds
Started Aug 23 05:48:11 PM UTC 24
Finished Aug 23 05:48:14 PM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262113868 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 46.edn_intr.1262113868
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/46.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/46.edn_smoke.3230386215
Short name T561
Test name
Test status
Simulation time 16672638 ps
CPU time 0.85 seconds
Started Aug 23 05:48:10 PM UTC 24
Finished Aug 23 05:48:12 PM UTC 24
Peak memory 226108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230386215 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 46.edn_smoke.3230386215
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/46.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/46.edn_stress_all.3782453626
Short name T568
Test name
Test status
Simulation time 1343055378 ps
CPU time 4.1 seconds
Started Aug 23 05:48:11 PM UTC 24
Finished Aug 23 05:48:17 PM UTC 24
Peak memory 227448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782453626 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.3782453626
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/46.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/46.edn_stress_all_with_rand_reset.2988893833
Short name T659
Test name
Test status
Simulation time 6614972783 ps
CPU time 46.2 seconds
Started Aug 23 05:48:11 PM UTC 24
Finished Aug 23 05:48:59 PM UTC 24
Peak memory 234000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2988893833 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all
_with_rand_reset.2988893833
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/46.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/47.edn_alert.1916171039
Short name T572
Test name
Test status
Simulation time 23738257 ps
CPU time 0.98 seconds
Started Aug 23 05:48:17 PM UTC 24
Finished Aug 23 05:48:19 PM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916171039 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 47.edn_alert.1916171039
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/47.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/47.edn_alert_test.4226443329
Short name T577
Test name
Test status
Simulation time 25963868 ps
CPU time 0.76 seconds
Started Aug 23 05:48:19 PM UTC 24
Finished Aug 23 05:48:21 PM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226443329 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.4226443329
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/47.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/47.edn_disable.1758964016
Short name T573
Test name
Test status
Simulation time 12403746 ps
CPU time 0.86 seconds
Started Aug 23 05:48:18 PM UTC 24
Finished Aug 23 05:48:20 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758964016 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1758964016
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/47.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/47.edn_disable_auto_req_mode.1766452623
Short name T142
Test name
Test status
Simulation time 69603595 ps
CPU time 1.07 seconds
Started Aug 23 05:48:19 PM UTC 24
Finished Aug 23 05:48:21 PM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766452623 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable_auto_req_mode.1766452623
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/47.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/47.edn_err.2781439507
Short name T183
Test name
Test status
Simulation time 19689627 ps
CPU time 1.01 seconds
Started Aug 23 05:48:18 PM UTC 24
Finished Aug 23 05:48:20 PM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781439507 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 47.edn_err.2781439507
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/47.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/47.edn_genbits.1467240584
Short name T570
Test name
Test status
Simulation time 29058287 ps
CPU time 1.08 seconds
Started Aug 23 05:48:16 PM UTC 24
Finished Aug 23 05:48:18 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467240584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1467240584
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/47.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/47.edn_intr.1727049448
Short name T569
Test name
Test status
Simulation time 28216556 ps
CPU time 0.9 seconds
Started Aug 23 05:48:16 PM UTC 24
Finished Aug 23 05:48:18 PM UTC 24
Peak memory 237824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727049448 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 47.edn_intr.1727049448
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/47.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/47.edn_smoke.3704264963
Short name T567
Test name
Test status
Simulation time 19115249 ps
CPU time 0.85 seconds
Started Aug 23 05:48:15 PM UTC 24
Finished Aug 23 05:48:17 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704264963 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 47.edn_smoke.3704264963
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/47.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/47.edn_stress_all.3675067679
Short name T574
Test name
Test status
Simulation time 151078244 ps
CPU time 2.79 seconds
Started Aug 23 05:48:16 PM UTC 24
Finished Aug 23 05:48:20 PM UTC 24
Peak memory 231628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675067679 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3675067679
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/47.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/47.edn_stress_all_with_rand_reset.1200320063
Short name T250
Test name
Test status
Simulation time 3680967141 ps
CPU time 71.77 seconds
Started Aug 23 05:48:16 PM UTC 24
Finished Aug 23 05:49:29 PM UTC 24
Peak memory 229720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1200320063 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all
_with_rand_reset.1200320063
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/47.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/48.edn_alert.3922451538
Short name T195
Test name
Test status
Simulation time 46624823 ps
CPU time 0.96 seconds
Started Aug 23 05:48:21 PM UTC 24
Finished Aug 23 05:48:23 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922451538 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 48.edn_alert.3922451538
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/48.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/48.edn_alert_test.2350899773
Short name T583
Test name
Test status
Simulation time 25229663 ps
CPU time 0.73 seconds
Started Aug 23 05:48:23 PM UTC 24
Finished Aug 23 05:48:25 PM UTC 24
Peak memory 216688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350899773 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.2350899773
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/48.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/48.edn_disable.852571264
Short name T579
Test name
Test status
Simulation time 19409207 ps
CPU time 0.79 seconds
Started Aug 23 05:48:22 PM UTC 24
Finished Aug 23 05:48:24 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852571264 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.852571264
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/48.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/48.edn_disable_auto_req_mode.2736529659
Short name T582
Test name
Test status
Simulation time 65230485 ps
CPU time 0.99 seconds
Started Aug 23 05:48:22 PM UTC 24
Finished Aug 23 05:48:24 PM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736529659 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable_auto_req_mode.2736529659
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/48.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/48.edn_err.2459073607
Short name T581
Test name
Test status
Simulation time 29538984 ps
CPU time 0.85 seconds
Started Aug 23 05:48:22 PM UTC 24
Finished Aug 23 05:48:24 PM UTC 24
Peak memory 237140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459073607 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 48.edn_err.2459073607
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/48.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/48.edn_genbits.4096945559
Short name T355
Test name
Test status
Simulation time 120127562 ps
CPU time 1.16 seconds
Started Aug 23 05:48:20 PM UTC 24
Finished Aug 23 05:48:22 PM UTC 24
Peak memory 230608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096945559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_genbits.4096945559
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/48.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/48.edn_intr.292240041
Short name T107
Test name
Test status
Simulation time 27707085 ps
CPU time 0.73 seconds
Started Aug 23 05:48:21 PM UTC 24
Finished Aug 23 05:48:23 PM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292240041 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 48.edn_intr.292240041
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/48.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/48.edn_smoke.2355429688
Short name T576
Test name
Test status
Simulation time 54318961 ps
CPU time 0.78 seconds
Started Aug 23 05:48:19 PM UTC 24
Finished Aug 23 05:48:21 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355429688 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 48.edn_smoke.2355429688
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/48.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/48.edn_stress_all.2725623305
Short name T578
Test name
Test status
Simulation time 2744705979 ps
CPU time 2.97 seconds
Started Aug 23 05:48:20 PM UTC 24
Finished Aug 23 05:48:24 PM UTC 24
Peak memory 231636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725623305 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.2725623305
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/48.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/48.edn_stress_all_with_rand_reset.461832658
Short name T690
Test name
Test status
Simulation time 6077502305 ps
CPU time 46.13 seconds
Started Aug 23 05:48:21 PM UTC 24
Finished Aug 23 05:49:09 PM UTC 24
Peak memory 234368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=461832658 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_
with_rand_reset.461832658
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/48.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/49.edn_alert.4292836937
Short name T178
Test name
Test status
Simulation time 111444357 ps
CPU time 1.02 seconds
Started Aug 23 05:48:25 PM UTC 24
Finished Aug 23 05:48:28 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292836937 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 49.edn_alert.4292836937
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/49.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/49.edn_alert_test.2481820380
Short name T591
Test name
Test status
Simulation time 42223035 ps
CPU time 0.74 seconds
Started Aug 23 05:48:28 PM UTC 24
Finished Aug 23 05:48:30 PM UTC 24
Peak memory 216988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481820380 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.2481820380
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/49.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/49.edn_disable.1131218900
Short name T590
Test name
Test status
Simulation time 13247884 ps
CPU time 0.74 seconds
Started Aug 23 05:48:27 PM UTC 24
Finished Aug 23 05:48:28 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131218900 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.1131218900
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/49.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/49.edn_disable_auto_req_mode.1925039264
Short name T592
Test name
Test status
Simulation time 38556860 ps
CPU time 1.03 seconds
Started Aug 23 05:48:28 PM UTC 24
Finished Aug 23 05:48:30 PM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925039264 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable_auto_req_mode.1925039264
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/49.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/49.edn_err.3628733698
Short name T589
Test name
Test status
Simulation time 25370304 ps
CPU time 0.98 seconds
Started Aug 23 05:48:26 PM UTC 24
Finished Aug 23 05:48:28 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628733698 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 49.edn_err.3628733698
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/49.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/49.edn_genbits.2855907007
Short name T585
Test name
Test status
Simulation time 39787710 ps
CPU time 1.16 seconds
Started Aug 23 05:48:24 PM UTC 24
Finished Aug 23 05:48:27 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855907007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2855907007
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/49.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/49.edn_intr.75391230
Short name T580
Test name
Test status
Simulation time 27380267 ps
CPU time 0.78 seconds
Started Aug 23 05:48:25 PM UTC 24
Finished Aug 23 05:48:28 PM UTC 24
Peak memory 228480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75391230 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_in
tr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 49.edn_intr.75391230
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/49.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/49.edn_smoke.2291531777
Short name T584
Test name
Test status
Simulation time 16263209 ps
CPU time 0.81 seconds
Started Aug 23 05:48:23 PM UTC 24
Finished Aug 23 05:48:25 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291531777 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 49.edn_smoke.2291531777
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/49.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/49.edn_stress_all.1358686743
Short name T588
Test name
Test status
Simulation time 554924023 ps
CPU time 2.15 seconds
Started Aug 23 05:48:24 PM UTC 24
Finished Aug 23 05:48:28 PM UTC 24
Peak memory 229452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358686743 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1358686743
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/49.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/5.edn_alert.3118560825
Short name T84
Test name
Test status
Simulation time 79193224 ps
CPU time 1.02 seconds
Started Aug 23 05:46:12 PM UTC 24
Finished Aug 23 05:46:15 PM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118560825 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 5.edn_alert.3118560825
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/5.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/5.edn_alert_test.665439212
Short name T357
Test name
Test status
Simulation time 93813841 ps
CPU time 0.79 seconds
Started Aug 23 05:46:12 PM UTC 24
Finished Aug 23 05:46:15 PM UTC 24
Peak memory 227044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665439212 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.665439212
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/5.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/5.edn_disable_auto_req_mode.1329978665
Short name T24
Test name
Test status
Simulation time 80338758 ps
CPU time 0.85 seconds
Started Aug 23 05:46:12 PM UTC 24
Finished Aug 23 05:46:15 PM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329978665 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable_auto_req_mode.1329978665
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/5.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/5.edn_err.3213224745
Short name T111
Test name
Test status
Simulation time 22184324 ps
CPU time 0.93 seconds
Started Aug 23 05:46:12 PM UTC 24
Finished Aug 23 05:46:14 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213224745 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 5.edn_err.3213224745
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/5.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/5.edn_regwen.3023140019
Short name T124
Test name
Test status
Simulation time 29318466 ps
CPU time 0.86 seconds
Started Aug 23 05:46:10 PM UTC 24
Finished Aug 23 05:46:12 PM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023140019 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 5.edn_regwen.3023140019
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/5.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/5.edn_smoke.2285043724
Short name T297
Test name
Test status
Simulation time 53873748 ps
CPU time 0.78 seconds
Started Aug 23 05:46:10 PM UTC 24
Finished Aug 23 05:46:12 PM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285043724 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 5.edn_smoke.2285043724
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/5.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/5.edn_stress_all.3827547665
Short name T122
Test name
Test status
Simulation time 245866945 ps
CPU time 2.56 seconds
Started Aug 23 05:46:12 PM UTC 24
Finished Aug 23 05:46:16 PM UTC 24
Peak memory 229792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827547665 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.3827547665
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/5.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/5.edn_stress_all_with_rand_reset.2858773066
Short name T488
Test name
Test status
Simulation time 3676218225 ps
CPU time 87.86 seconds
Started Aug 23 05:46:12 PM UTC 24
Finished Aug 23 05:47:42 PM UTC 24
Peak memory 229724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2858773066 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_
with_rand_reset.2858773066
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/5.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/50.edn_alert.774095139
Short name T593
Test name
Test status
Simulation time 25951831 ps
CPU time 1.02 seconds
Started Aug 23 05:48:29 PM UTC 24
Finished Aug 23 05:48:31 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774095139 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 50.edn_alert.774095139
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/50.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/50.edn_err.1977655155
Short name T215
Test name
Test status
Simulation time 60843322 ps
CPU time 0.77 seconds
Started Aug 23 05:48:29 PM UTC 24
Finished Aug 23 05:48:31 PM UTC 24
Peak memory 246084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977655155 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 50.edn_err.1977655155
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/50.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/50.edn_genbits.1500010488
Short name T595
Test name
Test status
Simulation time 42439725 ps
CPU time 1.18 seconds
Started Aug 23 05:48:29 PM UTC 24
Finished Aug 23 05:48:31 PM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500010488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1500010488
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/50.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/51.edn_alert.307598781
Short name T594
Test name
Test status
Simulation time 60498959 ps
CPU time 0.84 seconds
Started Aug 23 05:48:29 PM UTC 24
Finished Aug 23 05:48:31 PM UTC 24
Peak memory 227944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307598781 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 51.edn_alert.307598781
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/51.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/51.edn_err.565335071
Short name T596
Test name
Test status
Simulation time 25621615 ps
CPU time 0.99 seconds
Started Aug 23 05:48:29 PM UTC 24
Finished Aug 23 05:48:31 PM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565335071 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 51.edn_err.565335071
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/51.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/51.edn_genbits.2456377828
Short name T597
Test name
Test status
Simulation time 40107172 ps
CPU time 1.29 seconds
Started Aug 23 05:48:29 PM UTC 24
Finished Aug 23 05:48:31 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456377828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2456377828
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/51.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/52.edn_alert.124292902
Short name T131
Test name
Test status
Simulation time 156421659 ps
CPU time 1.08 seconds
Started Aug 23 05:48:31 PM UTC 24
Finished Aug 23 05:48:33 PM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124292902 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 52.edn_alert.124292902
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/52.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/52.edn_err.2531243700
Short name T600
Test name
Test status
Simulation time 43256122 ps
CPU time 0.87 seconds
Started Aug 23 05:48:32 PM UTC 24
Finished Aug 23 05:48:34 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531243700 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 52.edn_err.2531243700
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/52.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/52.edn_genbits.466356657
Short name T598
Test name
Test status
Simulation time 64096629 ps
CPU time 0.94 seconds
Started Aug 23 05:48:30 PM UTC 24
Finished Aug 23 05:48:32 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466356657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 52.edn_genbits.466356657
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/52.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/53.edn_alert.3568280251
Short name T162
Test name
Test status
Simulation time 28369213 ps
CPU time 1.06 seconds
Started Aug 23 05:48:32 PM UTC 24
Finished Aug 23 05:48:35 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568280251 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 53.edn_alert.3568280251
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/53.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/53.edn_err.3762176454
Short name T167
Test name
Test status
Simulation time 29847134 ps
CPU time 0.94 seconds
Started Aug 23 05:48:32 PM UTC 24
Finished Aug 23 05:48:34 PM UTC 24
Peak memory 237156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762176454 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 53.edn_err.3762176454
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/53.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/53.edn_genbits.1458058851
Short name T601
Test name
Test status
Simulation time 54609347 ps
CPU time 1.06 seconds
Started Aug 23 05:48:32 PM UTC 24
Finished Aug 23 05:48:35 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458058851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1458058851
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/53.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/54.edn_alert.3454991588
Short name T602
Test name
Test status
Simulation time 34310752 ps
CPU time 1.15 seconds
Started Aug 23 05:48:32 PM UTC 24
Finished Aug 23 05:48:35 PM UTC 24
Peak memory 226356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454991588 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 54.edn_alert.3454991588
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/54.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/54.edn_err.4254989797
Short name T605
Test name
Test status
Simulation time 69466025 ps
CPU time 1.01 seconds
Started Aug 23 05:48:33 PM UTC 24
Finished Aug 23 05:48:35 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254989797 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 54.edn_err.4254989797
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/54.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/54.edn_genbits.2484928899
Short name T603
Test name
Test status
Simulation time 47114304 ps
CPU time 1.32 seconds
Started Aug 23 05:48:32 PM UTC 24
Finished Aug 23 05:48:35 PM UTC 24
Peak memory 230612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484928899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2484928899
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/54.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/55.edn_alert.3685728957
Short name T264
Test name
Test status
Simulation time 68548090 ps
CPU time 1.05 seconds
Started Aug 23 05:48:34 PM UTC 24
Finished Aug 23 05:48:37 PM UTC 24
Peak memory 230484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685728957 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 55.edn_alert.3685728957
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/55.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/55.edn_err.557265186
Short name T145
Test name
Test status
Simulation time 26624079 ps
CPU time 1.03 seconds
Started Aug 23 05:48:35 PM UTC 24
Finished Aug 23 05:48:38 PM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557265186 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 55.edn_err.557265186
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/55.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/55.edn_genbits.1074155663
Short name T331
Test name
Test status
Simulation time 75365904 ps
CPU time 1.07 seconds
Started Aug 23 05:48:34 PM UTC 24
Finished Aug 23 05:48:37 PM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074155663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 55.edn_genbits.1074155663
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/55.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/56.edn_alert.278460957
Short name T266
Test name
Test status
Simulation time 26254257 ps
CPU time 1.01 seconds
Started Aug 23 05:48:35 PM UTC 24
Finished Aug 23 05:48:38 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278460957 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 56.edn_alert.278460957
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/56.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/56.edn_err.905051614
Short name T265
Test name
Test status
Simulation time 134333171 ps
CPU time 0.99 seconds
Started Aug 23 05:48:35 PM UTC 24
Finished Aug 23 05:48:38 PM UTC 24
Peak memory 242184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905051614 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 56.edn_err.905051614
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/56.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/56.edn_genbits.2579932346
Short name T267
Test name
Test status
Simulation time 45998816 ps
CPU time 1.22 seconds
Started Aug 23 05:48:35 PM UTC 24
Finished Aug 23 05:48:38 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579932346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2579932346
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/56.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/57.edn_alert.1830310936
Short name T269
Test name
Test status
Simulation time 76645603 ps
CPU time 0.9 seconds
Started Aug 23 05:48:36 PM UTC 24
Finished Aug 23 05:48:39 PM UTC 24
Peak memory 230484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830310936 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 57.edn_alert.1830310936
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/57.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/57.edn_err.2593547662
Short name T270
Test name
Test status
Simulation time 29861803 ps
CPU time 1.04 seconds
Started Aug 23 05:48:37 PM UTC 24
Finished Aug 23 05:48:39 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593547662 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 57.edn_err.2593547662
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/57.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/57.edn_genbits.3678204559
Short name T268
Test name
Test status
Simulation time 56440860 ps
CPU time 1.15 seconds
Started Aug 23 05:48:35 PM UTC 24
Finished Aug 23 05:48:38 PM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678204559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3678204559
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/57.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/58.edn_alert.1644364461
Short name T232
Test name
Test status
Simulation time 178014657 ps
CPU time 1.11 seconds
Started Aug 23 05:48:38 PM UTC 24
Finished Aug 23 05:48:40 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644364461 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 58.edn_alert.1644364461
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/58.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/58.edn_err.3279624342
Short name T272
Test name
Test status
Simulation time 89264753 ps
CPU time 0.7 seconds
Started Aug 23 05:48:38 PM UTC 24
Finished Aug 23 05:48:40 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279624342 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 58.edn_err.3279624342
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/58.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/58.edn_genbits.554314052
Short name T271
Test name
Test status
Simulation time 33056240 ps
CPU time 1.5 seconds
Started Aug 23 05:48:37 PM UTC 24
Finished Aug 23 05:48:40 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554314052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 58.edn_genbits.554314052
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/58.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/59.edn_alert.296024836
Short name T163
Test name
Test status
Simulation time 40909751 ps
CPU time 0.99 seconds
Started Aug 23 05:48:39 PM UTC 24
Finished Aug 23 05:48:41 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296024836 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 59.edn_alert.296024836
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/59.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/59.edn_err.1705454276
Short name T606
Test name
Test status
Simulation time 19585544 ps
CPU time 0.91 seconds
Started Aug 23 05:48:39 PM UTC 24
Finished Aug 23 05:48:41 PM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705454276 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 59.edn_err.1705454276
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/59.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/59.edn_genbits.578967451
Short name T607
Test name
Test status
Simulation time 106257134 ps
CPU time 1.04 seconds
Started Aug 23 05:48:39 PM UTC 24
Finished Aug 23 05:48:41 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578967451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 59.edn_genbits.578967451
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/59.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/6.edn_alert.3518991615
Short name T53
Test name
Test status
Simulation time 48275287 ps
CPU time 0.94 seconds
Started Aug 23 05:46:15 PM UTC 24
Finished Aug 23 05:46:17 PM UTC 24
Peak memory 230436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518991615 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 6.edn_alert.3518991615
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/6.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/6.edn_alert_test.1077056647
Short name T359
Test name
Test status
Simulation time 107180589 ps
CPU time 0.69 seconds
Started Aug 23 05:46:15 PM UTC 24
Finished Aug 23 05:46:17 PM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077056647 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.1077056647
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/6.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/6.edn_disable.1359937252
Short name T99
Test name
Test status
Simulation time 10316861 ps
CPU time 0.78 seconds
Started Aug 23 05:46:15 PM UTC 24
Finished Aug 23 05:46:17 PM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359937252 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.1359937252
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/6.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/6.edn_disable_auto_req_mode.2677322004
Short name T48
Test name
Test status
Simulation time 46371292 ps
CPU time 1.45 seconds
Started Aug 23 05:46:15 PM UTC 24
Finished Aug 23 05:46:18 PM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677322004 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable_auto_req_mode.2677322004
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/6.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/6.edn_err.4028457945
Short name T192
Test name
Test status
Simulation time 21635713 ps
CPU time 0.78 seconds
Started Aug 23 05:46:15 PM UTC 24
Finished Aug 23 05:46:17 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028457945 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 6.edn_err.4028457945
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/6.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/6.edn_genbits.2727865878
Short name T71
Test name
Test status
Simulation time 53957671 ps
CPU time 1.03 seconds
Started Aug 23 05:46:13 PM UTC 24
Finished Aug 23 05:46:15 PM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727865878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_genbits.2727865878
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/6.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/6.edn_intr.3795000849
Short name T44
Test name
Test status
Simulation time 31612975 ps
CPU time 0.76 seconds
Started Aug 23 05:46:15 PM UTC 24
Finished Aug 23 05:46:17 PM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795000849 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 6.edn_intr.3795000849
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/6.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/6.edn_regwen.1392669925
Short name T258
Test name
Test status
Simulation time 23152433 ps
CPU time 0.77 seconds
Started Aug 23 05:46:13 PM UTC 24
Finished Aug 23 05:46:15 PM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392669925 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 6.edn_regwen.1392669925
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/6.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/6.edn_smoke.3956784980
Short name T358
Test name
Test status
Simulation time 18733961 ps
CPU time 0.89 seconds
Started Aug 23 05:46:13 PM UTC 24
Finished Aug 23 05:46:15 PM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956784980 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 6.edn_smoke.3956784980
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/6.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/6.edn_stress_all.1986682971
Short name T123
Test name
Test status
Simulation time 126016507 ps
CPU time 2.39 seconds
Started Aug 23 05:46:13 PM UTC 24
Finished Aug 23 05:46:16 PM UTC 24
Peak memory 229456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986682971 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.1986682971
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/6.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/60.edn_alert.1371446331
Short name T203
Test name
Test status
Simulation time 30257254 ps
CPU time 0.96 seconds
Started Aug 23 05:48:39 PM UTC 24
Finished Aug 23 05:48:41 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371446331 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 60.edn_alert.1371446331
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/60.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/60.edn_err.1862506599
Short name T610
Test name
Test status
Simulation time 48556643 ps
CPU time 0.85 seconds
Started Aug 23 05:48:40 PM UTC 24
Finished Aug 23 05:48:42 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862506599 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 60.edn_err.1862506599
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/60.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/60.edn_genbits.585591486
Short name T608
Test name
Test status
Simulation time 84779035 ps
CPU time 1.05 seconds
Started Aug 23 05:48:39 PM UTC 24
Finished Aug 23 05:48:41 PM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585591486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 60.edn_genbits.585591486
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/60.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/61.edn_alert.3103491414
Short name T612
Test name
Test status
Simulation time 24603390 ps
CPU time 1.02 seconds
Started Aug 23 05:48:41 PM UTC 24
Finished Aug 23 05:48:43 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103491414 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 61.edn_alert.3103491414
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/61.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/61.edn_err.4085565722
Short name T611
Test name
Test status
Simulation time 79153612 ps
CPU time 0.74 seconds
Started Aug 23 05:48:41 PM UTC 24
Finished Aug 23 05:48:43 PM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085565722 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 61.edn_err.4085565722
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/61.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/61.edn_genbits.3456061578
Short name T609
Test name
Test status
Simulation time 41008043 ps
CPU time 0.98 seconds
Started Aug 23 05:48:40 PM UTC 24
Finished Aug 23 05:48:42 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456061578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 61.edn_genbits.3456061578
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/61.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/62.edn_alert.1089446108
Short name T616
Test name
Test status
Simulation time 46694812 ps
CPU time 1.03 seconds
Started Aug 23 05:48:42 PM UTC 24
Finished Aug 23 05:48:44 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089446108 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 62.edn_alert.1089446108
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/62.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/62.edn_err.1145367444
Short name T614
Test name
Test status
Simulation time 82257346 ps
CPU time 0.88 seconds
Started Aug 23 05:48:42 PM UTC 24
Finished Aug 23 05:48:44 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145367444 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 62.edn_err.1145367444
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/62.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/62.edn_genbits.2007613256
Short name T613
Test name
Test status
Simulation time 37801441 ps
CPU time 1.09 seconds
Started Aug 23 05:48:41 PM UTC 24
Finished Aug 23 05:48:43 PM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007613256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2007613256
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/62.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/63.edn_alert.2891728559
Short name T152
Test name
Test status
Simulation time 47165061 ps
CPU time 1.05 seconds
Started Aug 23 05:48:42 PM UTC 24
Finished Aug 23 05:48:44 PM UTC 24
Peak memory 228436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891728559 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 63.edn_alert.2891728559
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/63.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/63.edn_err.802616794
Short name T615
Test name
Test status
Simulation time 33056692 ps
CPU time 0.75 seconds
Started Aug 23 05:48:42 PM UTC 24
Finished Aug 23 05:48:44 PM UTC 24
Peak memory 230400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802616794 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 63.edn_err.802616794
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/63.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/63.edn_genbits.2098385805
Short name T353
Test name
Test status
Simulation time 31575451 ps
CPU time 1.08 seconds
Started Aug 23 05:48:42 PM UTC 24
Finished Aug 23 05:48:44 PM UTC 24
Peak memory 230612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098385805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2098385805
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/63.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/64.edn_alert.1895565306
Short name T617
Test name
Test status
Simulation time 102398675 ps
CPU time 0.94 seconds
Started Aug 23 05:48:43 PM UTC 24
Finished Aug 23 05:48:45 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895565306 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 64.edn_alert.1895565306
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/64.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/64.edn_err.119078803
Short name T618
Test name
Test status
Simulation time 189987259 ps
CPU time 0.95 seconds
Started Aug 23 05:48:43 PM UTC 24
Finished Aug 23 05:48:45 PM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119078803 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 64.edn_err.119078803
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/64.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/64.edn_genbits.844023672
Short name T619
Test name
Test status
Simulation time 32656722 ps
CPU time 1.27 seconds
Started Aug 23 05:48:43 PM UTC 24
Finished Aug 23 05:48:46 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844023672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 64.edn_genbits.844023672
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/64.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/65.edn_alert.2211906871
Short name T622
Test name
Test status
Simulation time 41288353 ps
CPU time 0.97 seconds
Started Aug 23 05:48:44 PM UTC 24
Finished Aug 23 05:48:46 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211906871 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 65.edn_alert.2211906871
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/65.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/65.edn_genbits.1445846705
Short name T621
Test name
Test status
Simulation time 106931229 ps
CPU time 0.95 seconds
Started Aug 23 05:48:44 PM UTC 24
Finished Aug 23 05:48:46 PM UTC 24
Peak memory 228356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445846705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1445846705
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/65.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/66.edn_alert.3345062445
Short name T625
Test name
Test status
Simulation time 178278913 ps
CPU time 1.04 seconds
Started Aug 23 05:48:45 PM UTC 24
Finished Aug 23 05:48:48 PM UTC 24
Peak memory 230484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345062445 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 66.edn_alert.3345062445
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/66.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/66.edn_err.219557431
Short name T624
Test name
Test status
Simulation time 26058283 ps
CPU time 0.98 seconds
Started Aug 23 05:48:45 PM UTC 24
Finished Aug 23 05:48:47 PM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219557431 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 66.edn_err.219557431
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/66.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/66.edn_genbits.2395869877
Short name T623
Test name
Test status
Simulation time 51822181 ps
CPU time 0.97 seconds
Started Aug 23 05:48:44 PM UTC 24
Finished Aug 23 05:48:46 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395869877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 66.edn_genbits.2395869877
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/66.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/67.edn_alert.1974047843
Short name T628
Test name
Test status
Simulation time 64782202 ps
CPU time 1.09 seconds
Started Aug 23 05:48:47 PM UTC 24
Finished Aug 23 05:48:49 PM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974047843 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 67.edn_alert.1974047843
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/67.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/67.edn_err.2803704510
Short name T222
Test name
Test status
Simulation time 37115432 ps
CPU time 0.82 seconds
Started Aug 23 05:48:47 PM UTC 24
Finished Aug 23 05:48:48 PM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803704510 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 67.edn_err.2803704510
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/67.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/67.edn_genbits.671362669
Short name T631
Test name
Test status
Simulation time 124159737 ps
CPU time 2.25 seconds
Started Aug 23 05:48:45 PM UTC 24
Finished Aug 23 05:48:49 PM UTC 24
Peak memory 231584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671362669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 67.edn_genbits.671362669
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/67.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/68.edn_alert.1828499541
Short name T629
Test name
Test status
Simulation time 26264936 ps
CPU time 0.99 seconds
Started Aug 23 05:48:47 PM UTC 24
Finished Aug 23 05:48:49 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828499541 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 68.edn_alert.1828499541
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/68.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/68.edn_err.2471653912
Short name T627
Test name
Test status
Simulation time 18598031 ps
CPU time 0.88 seconds
Started Aug 23 05:48:47 PM UTC 24
Finished Aug 23 05:48:49 PM UTC 24
Peak memory 228540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471653912 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 68.edn_err.2471653912
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/68.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/68.edn_genbits.1442864088
Short name T626
Test name
Test status
Simulation time 203491038 ps
CPU time 0.87 seconds
Started Aug 23 05:48:47 PM UTC 24
Finished Aug 23 05:48:48 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442864088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1442864088
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/68.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/69.edn_alert.825863090
Short name T300
Test name
Test status
Simulation time 149859666 ps
CPU time 1.09 seconds
Started Aug 23 05:48:48 PM UTC 24
Finished Aug 23 05:48:50 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825863090 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 69.edn_alert.825863090
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/69.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/69.edn_err.1353976293
Short name T632
Test name
Test status
Simulation time 93059328 ps
CPU time 0.9 seconds
Started Aug 23 05:48:48 PM UTC 24
Finished Aug 23 05:48:50 PM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353976293 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 69.edn_err.1353976293
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/69.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/69.edn_genbits.1388070302
Short name T630
Test name
Test status
Simulation time 35989560 ps
CPU time 1.04 seconds
Started Aug 23 05:48:47 PM UTC 24
Finished Aug 23 05:48:49 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388070302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1388070302
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/69.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/7.edn_alert.3860802849
Short name T54
Test name
Test status
Simulation time 47899419 ps
CPU time 1.09 seconds
Started Aug 23 05:46:17 PM UTC 24
Finished Aug 23 05:46:19 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860802849 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 7.edn_alert.3860802849
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/7.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/7.edn_alert_test.4133663981
Short name T361
Test name
Test status
Simulation time 27378778 ps
CPU time 0.95 seconds
Started Aug 23 05:46:17 PM UTC 24
Finished Aug 23 05:46:19 PM UTC 24
Peak memory 226912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133663981 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.4133663981
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/7.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/7.edn_disable.2609173106
Short name T72
Test name
Test status
Simulation time 31517446 ps
CPU time 0.72 seconds
Started Aug 23 05:46:17 PM UTC 24
Finished Aug 23 05:46:19 PM UTC 24
Peak memory 216132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609173106 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.2609173106
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/7.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/7.edn_disable_auto_req_mode.450507881
Short name T23
Test name
Test status
Simulation time 156776021 ps
CPU time 0.99 seconds
Started Aug 23 05:46:17 PM UTC 24
Finished Aug 23 05:46:19 PM UTC 24
Peak memory 230340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450507881 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable_auto_req_mode.450507881
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/7.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/7.edn_err.477235084
Short name T59
Test name
Test status
Simulation time 41234316 ps
CPU time 0.78 seconds
Started Aug 23 05:46:17 PM UTC 24
Finished Aug 23 05:46:19 PM UTC 24
Peak memory 236968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477235084 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 7.edn_err.477235084
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/7.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/7.edn_genbits.1144924562
Short name T360
Test name
Test status
Simulation time 93516196 ps
CPU time 1.2 seconds
Started Aug 23 05:46:15 PM UTC 24
Finished Aug 23 05:46:18 PM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144924562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1144924562
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/7.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/7.edn_intr.3707023037
Short name T36
Test name
Test status
Simulation time 20198650 ps
CPU time 0.91 seconds
Started Aug 23 05:46:17 PM UTC 24
Finished Aug 23 05:46:19 PM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707023037 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 7.edn_intr.3707023037
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/7.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/7.edn_regwen.1675265528
Short name T120
Test name
Test status
Simulation time 16841787 ps
CPU time 0.85 seconds
Started Aug 23 05:46:15 PM UTC 24
Finished Aug 23 05:46:17 PM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675265528 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 7.edn_regwen.1675265528
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/7.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/7.edn_smoke.176735446
Short name T113
Test name
Test status
Simulation time 49494582 ps
CPU time 0.79 seconds
Started Aug 23 05:46:15 PM UTC 24
Finished Aug 23 05:46:17 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176735446 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 7.edn_smoke.176735446
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/7.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/7.edn_stress_all_with_rand_reset.2618988017
Short name T246
Test name
Test status
Simulation time 17104011971 ps
CPU time 82.71 seconds
Started Aug 23 05:46:15 PM UTC 24
Finished Aug 23 05:47:40 PM UTC 24
Peak memory 229856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2618988017 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_
with_rand_reset.2618988017
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/7.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/70.edn_alert.3039719129
Short name T175
Test name
Test status
Simulation time 304185769 ps
CPU time 1.13 seconds
Started Aug 23 05:48:49 PM UTC 24
Finished Aug 23 05:48:51 PM UTC 24
Peak memory 226356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039719129 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 70.edn_alert.3039719129
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/70.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/70.edn_err.2430698095
Short name T634
Test name
Test status
Simulation time 63981929 ps
CPU time 0.8 seconds
Started Aug 23 05:48:49 PM UTC 24
Finished Aug 23 05:48:51 PM UTC 24
Peak memory 237140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430698095 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 70.edn_err.2430698095
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/70.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/70.edn_genbits.626102637
Short name T633
Test name
Test status
Simulation time 107482734 ps
CPU time 1.03 seconds
Started Aug 23 05:48:48 PM UTC 24
Finished Aug 23 05:48:50 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626102637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 70.edn_genbits.626102637
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/70.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/71.edn_alert.3222423459
Short name T301
Test name
Test status
Simulation time 25325662 ps
CPU time 1.04 seconds
Started Aug 23 05:48:50 PM UTC 24
Finished Aug 23 05:48:52 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222423459 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 71.edn_alert.3222423459
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/71.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/71.edn_err.4207402564
Short name T212
Test name
Test status
Simulation time 20841484 ps
CPU time 0.88 seconds
Started Aug 23 05:48:50 PM UTC 24
Finished Aug 23 05:48:52 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207402564 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 71.edn_err.4207402564
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/71.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/71.edn_genbits.774053623
Short name T635
Test name
Test status
Simulation time 144314460 ps
CPU time 1.11 seconds
Started Aug 23 05:48:49 PM UTC 24
Finished Aug 23 05:48:51 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774053623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 71.edn_genbits.774053623
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/71.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/72.edn_alert.1769259582
Short name T637
Test name
Test status
Simulation time 44817425 ps
CPU time 1 seconds
Started Aug 23 05:48:50 PM UTC 24
Finished Aug 23 05:48:52 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769259582 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 72.edn_alert.1769259582
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/72.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/72.edn_err.2425949082
Short name T172
Test name
Test status
Simulation time 40744521 ps
CPU time 0.99 seconds
Started Aug 23 05:48:50 PM UTC 24
Finished Aug 23 05:48:52 PM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425949082 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 72.edn_err.2425949082
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/72.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/72.edn_genbits.593718912
Short name T636
Test name
Test status
Simulation time 60599286 ps
CPU time 1.02 seconds
Started Aug 23 05:48:50 PM UTC 24
Finished Aug 23 05:48:52 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593718912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 72.edn_genbits.593718912
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/72.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/73.edn_alert.4233204188
Short name T638
Test name
Test status
Simulation time 24969383 ps
CPU time 1 seconds
Started Aug 23 05:48:51 PM UTC 24
Finished Aug 23 05:48:53 PM UTC 24
Peak memory 230432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233204188 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 73.edn_alert.4233204188
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/73.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/73.edn_err.2552004028
Short name T159
Test name
Test status
Simulation time 20253897 ps
CPU time 0.94 seconds
Started Aug 23 05:48:51 PM UTC 24
Finished Aug 23 05:48:53 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552004028 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 73.edn_err.2552004028
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/73.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/73.edn_genbits.2124388502
Short name T639
Test name
Test status
Simulation time 67255462 ps
CPU time 0.92 seconds
Started Aug 23 05:48:51 PM UTC 24
Finished Aug 23 05:48:53 PM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124388502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 73.edn_genbits.2124388502
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/73.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/74.edn_alert.2673012329
Short name T641
Test name
Test status
Simulation time 90471951 ps
CPU time 1 seconds
Started Aug 23 05:48:52 PM UTC 24
Finished Aug 23 05:48:54 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673012329 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 74.edn_alert.2673012329
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/74.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/74.edn_err.801526464
Short name T642
Test name
Test status
Simulation time 44957153 ps
CPU time 1.06 seconds
Started Aug 23 05:48:52 PM UTC 24
Finished Aug 23 05:48:54 PM UTC 24
Peak memory 242132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801526464 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 74.edn_err.801526464
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/74.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/74.edn_genbits.2542050580
Short name T640
Test name
Test status
Simulation time 316455330 ps
CPU time 1 seconds
Started Aug 23 05:48:51 PM UTC 24
Finished Aug 23 05:48:53 PM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542050580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2542050580
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/74.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/75.edn_alert.2016500699
Short name T206
Test name
Test status
Simulation time 24811867 ps
CPU time 1.08 seconds
Started Aug 23 05:48:53 PM UTC 24
Finished Aug 23 05:48:55 PM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016500699 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 75.edn_alert.2016500699
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/75.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/75.edn_err.3750286001
Short name T644
Test name
Test status
Simulation time 36190548 ps
CPU time 0.8 seconds
Started Aug 23 05:48:53 PM UTC 24
Finished Aug 23 05:48:55 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750286001 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 75.edn_err.3750286001
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/75.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/75.edn_genbits.2221418018
Short name T643
Test name
Test status
Simulation time 96862335 ps
CPU time 1.26 seconds
Started Aug 23 05:48:52 PM UTC 24
Finished Aug 23 05:48:55 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221418018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 75.edn_genbits.2221418018
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/75.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/76.edn_alert.838504906
Short name T302
Test name
Test status
Simulation time 53451902 ps
CPU time 1.11 seconds
Started Aug 23 05:48:53 PM UTC 24
Finished Aug 23 05:48:56 PM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838504906 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 76.edn_alert.838504906
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/76.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/76.edn_err.1877433646
Short name T647
Test name
Test status
Simulation time 69212875 ps
CPU time 0.95 seconds
Started Aug 23 05:48:54 PM UTC 24
Finished Aug 23 05:48:57 PM UTC 24
Peak memory 244112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877433646 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 76.edn_err.1877433646
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/76.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/76.edn_genbits.3547298535
Short name T646
Test name
Test status
Simulation time 43529606 ps
CPU time 1.38 seconds
Started Aug 23 05:48:53 PM UTC 24
Finished Aug 23 05:48:56 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547298535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3547298535
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/76.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/77.edn_alert.2933691271
Short name T587
Test name
Test status
Simulation time 24167726 ps
CPU time 1.01 seconds
Started Aug 23 05:48:55 PM UTC 24
Finished Aug 23 05:48:57 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933691271 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 77.edn_alert.2933691271
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/77.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/77.edn_err.2365102927
Short name T224
Test name
Test status
Simulation time 93942721 ps
CPU time 0.98 seconds
Started Aug 23 05:48:55 PM UTC 24
Finished Aug 23 05:48:57 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365102927 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 77.edn_err.2365102927
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/77.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/77.edn_genbits.620294429
Short name T648
Test name
Test status
Simulation time 131683023 ps
CPU time 1.19 seconds
Started Aug 23 05:48:54 PM UTC 24
Finished Aug 23 05:48:57 PM UTC 24
Peak memory 227868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620294429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 77.edn_genbits.620294429
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/77.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/78.edn_alert.240601521
Short name T650
Test name
Test status
Simulation time 53201757 ps
CPU time 1 seconds
Started Aug 23 05:48:56 PM UTC 24
Finished Aug 23 05:48:58 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240601521 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 78.edn_alert.240601521
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/78.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/78.edn_err.1480877692
Short name T651
Test name
Test status
Simulation time 19295225 ps
CPU time 0.91 seconds
Started Aug 23 05:48:56 PM UTC 24
Finished Aug 23 05:48:58 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480877692 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 78.edn_err.1480877692
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/78.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/78.edn_genbits.3162147942
Short name T652
Test name
Test status
Simulation time 44831744 ps
CPU time 1.1 seconds
Started Aug 23 05:48:56 PM UTC 24
Finished Aug 23 05:48:58 PM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162147942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 78.edn_genbits.3162147942
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/78.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/79.edn_alert.4012855468
Short name T653
Test name
Test status
Simulation time 25192479 ps
CPU time 1 seconds
Started Aug 23 05:48:56 PM UTC 24
Finished Aug 23 05:48:58 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012855468 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 79.edn_alert.4012855468
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/79.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/79.edn_err.2542539097
Short name T657
Test name
Test status
Simulation time 166245391 ps
CPU time 1.12 seconds
Started Aug 23 05:48:57 PM UTC 24
Finished Aug 23 05:48:59 PM UTC 24
Peak memory 242084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542539097 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 79.edn_err.2542539097
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/79.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/79.edn_genbits.2517195604
Short name T649
Test name
Test status
Simulation time 37614611 ps
CPU time 0.85 seconds
Started Aug 23 05:48:56 PM UTC 24
Finished Aug 23 05:48:58 PM UTC 24
Peak memory 228188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517195604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 79.edn_genbits.2517195604
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/79.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/8.edn_alert.1562794172
Short name T127
Test name
Test status
Simulation time 42836740 ps
CPU time 1 seconds
Started Aug 23 05:46:18 PM UTC 24
Finished Aug 23 05:46:20 PM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562794172 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 8.edn_alert.1562794172
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/8.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/8.edn_alert_test.2340480168
Short name T363
Test name
Test status
Simulation time 182799362 ps
CPU time 0.84 seconds
Started Aug 23 05:46:18 PM UTC 24
Finished Aug 23 05:46:20 PM UTC 24
Peak memory 226912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340480168 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2340480168
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/8.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/8.edn_disable.1463063564
Short name T93
Test name
Test status
Simulation time 128710892 ps
CPU time 0.8 seconds
Started Aug 23 05:46:18 PM UTC 24
Finished Aug 23 05:46:20 PM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463063564 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.1463063564
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/8.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/8.edn_disable_auto_req_mode.547466685
Short name T74
Test name
Test status
Simulation time 80789084 ps
CPU time 0.87 seconds
Started Aug 23 05:46:18 PM UTC 24
Finished Aug 23 05:46:20 PM UTC 24
Peak memory 228036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547466685 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable_auto_req_mode.547466685
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/8.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/8.edn_err.219745152
Short name T9
Test name
Test status
Simulation time 67699748 ps
CPU time 0.76 seconds
Started Aug 23 05:46:18 PM UTC 24
Finished Aug 23 05:46:20 PM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219745152 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 8.edn_err.219745152
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/8.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/8.edn_genbits.2351446409
Short name T49
Test name
Test status
Simulation time 79965572 ps
CPU time 1.24 seconds
Started Aug 23 05:46:17 PM UTC 24
Finished Aug 23 05:46:20 PM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351446409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_genbits.2351446409
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/8.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/8.edn_intr.855083284
Short name T73
Test name
Test status
Simulation time 21976549 ps
CPU time 0.97 seconds
Started Aug 23 05:46:18 PM UTC 24
Finished Aug 23 05:46:20 PM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855083284 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 8.edn_intr.855083284
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/8.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/8.edn_regwen.3512745966
Short name T321
Test name
Test status
Simulation time 22546435 ps
CPU time 0.89 seconds
Started Aug 23 05:46:17 PM UTC 24
Finished Aug 23 05:46:19 PM UTC 24
Peak memory 216012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512745966 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 8.edn_regwen.3512745966
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/8.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/8.edn_smoke.2163985926
Short name T362
Test name
Test status
Simulation time 125878091 ps
CPU time 0.99 seconds
Started Aug 23 05:46:17 PM UTC 24
Finished Aug 23 05:46:20 PM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163985926 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 8.edn_smoke.2163985926
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/8.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/8.edn_stress_all.1515772288
Short name T116
Test name
Test status
Simulation time 361429801 ps
CPU time 5.72 seconds
Started Aug 23 05:46:17 PM UTC 24
Finished Aug 23 05:46:24 PM UTC 24
Peak memory 227744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515772288 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.1515772288
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/8.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/8.edn_stress_all_with_rand_reset.1411599487
Short name T39
Test name
Test status
Simulation time 7455795722 ps
CPU time 48.68 seconds
Started Aug 23 05:46:17 PM UTC 24
Finished Aug 23 05:47:08 PM UTC 24
Peak memory 229880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1411599487 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_
with_rand_reset.1411599487
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/8.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/80.edn_alert.2228613084
Short name T655
Test name
Test status
Simulation time 26478340 ps
CPU time 1.07 seconds
Started Aug 23 05:48:57 PM UTC 24
Finished Aug 23 05:48:59 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228613084 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 80.edn_alert.2228613084
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/80.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/80.edn_err.2876698896
Short name T654
Test name
Test status
Simulation time 28354617 ps
CPU time 0.81 seconds
Started Aug 23 05:48:57 PM UTC 24
Finished Aug 23 05:48:59 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876698896 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 80.edn_err.2876698896
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/80.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/80.edn_genbits.2736503098
Short name T324
Test name
Test status
Simulation time 106196110 ps
CPU time 2.41 seconds
Started Aug 23 05:48:57 PM UTC 24
Finished Aug 23 05:49:00 PM UTC 24
Peak memory 231520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736503098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2736503098
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/80.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/81.edn_alert.1338172000
Short name T273
Test name
Test status
Simulation time 105951804 ps
CPU time 1.29 seconds
Started Aug 23 05:48:57 PM UTC 24
Finished Aug 23 05:48:59 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338172000 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 81.edn_alert.1338172000
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/81.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/81.edn_err.3078421537
Short name T661
Test name
Test status
Simulation time 38056752 ps
CPU time 0.92 seconds
Started Aug 23 05:48:58 PM UTC 24
Finished Aug 23 05:49:00 PM UTC 24
Peak memory 236552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078421537 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 81.edn_err.3078421537
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/81.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/81.edn_genbits.935686419
Short name T656
Test name
Test status
Simulation time 66776798 ps
CPU time 0.93 seconds
Started Aug 23 05:48:57 PM UTC 24
Finished Aug 23 05:48:59 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935686419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 81.edn_genbits.935686419
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/81.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/82.edn_alert.450177286
Short name T660
Test name
Test status
Simulation time 37908394 ps
CPU time 0.93 seconds
Started Aug 23 05:48:58 PM UTC 24
Finished Aug 23 05:49:00 PM UTC 24
Peak memory 229628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450177286 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 82.edn_alert.450177286
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/82.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/82.edn_err.4158630489
Short name T225
Test name
Test status
Simulation time 73147062 ps
CPU time 1 seconds
Started Aug 23 05:48:58 PM UTC 24
Finished Aug 23 05:49:00 PM UTC 24
Peak memory 242180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158630489 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 82.edn_err.4158630489
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/82.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/82.edn_genbits.3720927625
Short name T662
Test name
Test status
Simulation time 33430338 ps
CPU time 1.2 seconds
Started Aug 23 05:48:58 PM UTC 24
Finished Aug 23 05:49:00 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720927625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3720927625
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/82.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/83.edn_alert.3577078969
Short name T164
Test name
Test status
Simulation time 105425014 ps
CPU time 1.01 seconds
Started Aug 23 05:48:59 PM UTC 24
Finished Aug 23 05:49:01 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577078969 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 83.edn_alert.3577078969
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/83.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/83.edn_err.219789552
Short name T663
Test name
Test status
Simulation time 22290014 ps
CPU time 0.95 seconds
Started Aug 23 05:48:59 PM UTC 24
Finished Aug 23 05:49:01 PM UTC 24
Peak memory 237160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219789552 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 83.edn_err.219789552
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/83.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/83.edn_genbits.1351033683
Short name T664
Test name
Test status
Simulation time 81093217 ps
CPU time 1.67 seconds
Started Aug 23 05:48:59 PM UTC 24
Finished Aug 23 05:49:02 PM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351033683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 83.edn_genbits.1351033683
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/83.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/84.edn_alert.3431359362
Short name T665
Test name
Test status
Simulation time 46872837 ps
CPU time 1.01 seconds
Started Aug 23 05:49:00 PM UTC 24
Finished Aug 23 05:49:02 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431359362 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 84.edn_alert.3431359362
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/84.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/84.edn_err.440027089
Short name T668
Test name
Test status
Simulation time 184177108 ps
CPU time 1.04 seconds
Started Aug 23 05:49:00 PM UTC 24
Finished Aug 23 05:49:02 PM UTC 24
Peak memory 242184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440027089 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 84.edn_err.440027089
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/84.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/84.edn_genbits.1753548060
Short name T671
Test name
Test status
Simulation time 49669482 ps
CPU time 1.6 seconds
Started Aug 23 05:49:00 PM UTC 24
Finished Aug 23 05:49:03 PM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753548060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 84.edn_genbits.1753548060
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/84.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/85.edn_alert.2667350228
Short name T670
Test name
Test status
Simulation time 29631122 ps
CPU time 1.14 seconds
Started Aug 23 05:49:00 PM UTC 24
Finished Aug 23 05:49:03 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667350228 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 85.edn_alert.2667350228
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/85.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/85.edn_err.3204746734
Short name T666
Test name
Test status
Simulation time 19318471 ps
CPU time 0.88 seconds
Started Aug 23 05:49:00 PM UTC 24
Finished Aug 23 05:49:02 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204746734 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 85.edn_err.3204746734
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/85.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/85.edn_genbits.3684274521
Short name T672
Test name
Test status
Simulation time 53354545 ps
CPU time 1.45 seconds
Started Aug 23 05:49:00 PM UTC 24
Finished Aug 23 05:49:03 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684274521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3684274521
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/85.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/86.edn_alert.1327563325
Short name T669
Test name
Test status
Simulation time 46941354 ps
CPU time 1 seconds
Started Aug 23 05:49:00 PM UTC 24
Finished Aug 23 05:49:03 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327563325 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 86.edn_alert.1327563325
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/86.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/86.edn_err.725341671
Short name T216
Test name
Test status
Simulation time 23095786 ps
CPU time 0.8 seconds
Started Aug 23 05:49:02 PM UTC 24
Finished Aug 23 05:49:03 PM UTC 24
Peak memory 230308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725341671 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 86.edn_err.725341671
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/86.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/86.edn_genbits.1196625366
Short name T667
Test name
Test status
Simulation time 38283129 ps
CPU time 0.93 seconds
Started Aug 23 05:49:00 PM UTC 24
Finished Aug 23 05:49:02 PM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196625366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 86.edn_genbits.1196625366
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/86.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/87.edn_alert.896184973
Short name T675
Test name
Test status
Simulation time 339114586 ps
CPU time 1.21 seconds
Started Aug 23 05:49:02 PM UTC 24
Finished Aug 23 05:49:04 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896184973 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 87.edn_alert.896184973
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/87.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/87.edn_err.943922771
Short name T673
Test name
Test status
Simulation time 25385162 ps
CPU time 0.82 seconds
Started Aug 23 05:49:02 PM UTC 24
Finished Aug 23 05:49:04 PM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943922771 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 87.edn_err.943922771
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/87.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/87.edn_genbits.1953056890
Short name T674
Test name
Test status
Simulation time 107762157 ps
CPU time 1.1 seconds
Started Aug 23 05:49:02 PM UTC 24
Finished Aug 23 05:49:04 PM UTC 24
Peak memory 228264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953056890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 87.edn_genbits.1953056890
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/87.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/88.edn_alert.3465311837
Short name T196
Test name
Test status
Simulation time 26507970 ps
CPU time 1.06 seconds
Started Aug 23 05:49:03 PM UTC 24
Finished Aug 23 05:49:05 PM UTC 24
Peak memory 231748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465311837 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 88.edn_alert.3465311837
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/88.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/88.edn_err.1184519873
Short name T677
Test name
Test status
Simulation time 18823476 ps
CPU time 0.91 seconds
Started Aug 23 05:49:03 PM UTC 24
Finished Aug 23 05:49:05 PM UTC 24
Peak memory 227892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184519873 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 88.edn_err.1184519873
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/88.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/88.edn_genbits.23294356
Short name T676
Test name
Test status
Simulation time 38465612 ps
CPU time 1.16 seconds
Started Aug 23 05:49:02 PM UTC 24
Finished Aug 23 05:49:04 PM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23294356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 88.edn_genbits.23294356
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/88.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/89.edn_alert.978991134
Short name T682
Test name
Test status
Simulation time 29089538 ps
CPU time 1.12 seconds
Started Aug 23 05:49:04 PM UTC 24
Finished Aug 23 05:49:06 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978991134 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 89.edn_alert.978991134
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/89.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/89.edn_err.636712165
Short name T679
Test name
Test status
Simulation time 52978180 ps
CPU time 0.73 seconds
Started Aug 23 05:49:04 PM UTC 24
Finished Aug 23 05:49:06 PM UTC 24
Peak memory 230400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636712165 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 89.edn_err.636712165
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/89.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/89.edn_genbits.1932295413
Short name T678
Test name
Test status
Simulation time 151976925 ps
CPU time 0.95 seconds
Started Aug 23 05:49:03 PM UTC 24
Finished Aug 23 05:49:05 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932295413 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1932295413
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/89.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/9.edn_alert.922457701
Short name T138
Test name
Test status
Simulation time 23767348 ps
CPU time 1.04 seconds
Started Aug 23 05:46:20 PM UTC 24
Finished Aug 23 05:46:22 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922457701 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 9.edn_alert.922457701
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/9.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/9.edn_alert_test.3332112461
Short name T365
Test name
Test status
Simulation time 58558815 ps
CPU time 1.33 seconds
Started Aug 23 05:46:20 PM UTC 24
Finished Aug 23 05:46:23 PM UTC 24
Peak memory 226852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332112461 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.3332112461
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/9.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/9.edn_disable.2825317426
Short name T81
Test name
Test status
Simulation time 27818954 ps
CPU time 0.69 seconds
Started Aug 23 05:46:20 PM UTC 24
Finished Aug 23 05:46:22 PM UTC 24
Peak memory 225768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825317426 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2825317426
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/9.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/9.edn_disable_auto_req_mode.1352929666
Short name T52
Test name
Test status
Simulation time 55261705 ps
CPU time 0.82 seconds
Started Aug 23 05:46:20 PM UTC 24
Finished Aug 23 05:46:22 PM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352929666 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable_auto_req_mode.1352929666
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/9.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/9.edn_err.891385452
Short name T8
Test name
Test status
Simulation time 34103434 ps
CPU time 0.77 seconds
Started Aug 23 05:46:20 PM UTC 24
Finished Aug 23 05:46:22 PM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891385452 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 9.edn_err.891385452
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/9.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/9.edn_genbits.1311517925
Short name T82
Test name
Test status
Simulation time 29179284 ps
CPU time 1.24 seconds
Started Aug 23 05:46:20 PM UTC 24
Finished Aug 23 05:46:22 PM UTC 24
Peak memory 229676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311517925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1311517925
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/9.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/9.edn_intr.3516071701
Short name T134
Test name
Test status
Simulation time 24031202 ps
CPU time 0.77 seconds
Started Aug 23 05:46:20 PM UTC 24
Finished Aug 23 05:46:22 PM UTC 24
Peak memory 229540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516071701 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 9.edn_intr.3516071701
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/9.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/9.edn_regwen.2818086253
Short name T364
Test name
Test status
Simulation time 24519515 ps
CPU time 0.81 seconds
Started Aug 23 05:46:20 PM UTC 24
Finished Aug 23 05:46:22 PM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818086253 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 9.edn_regwen.2818086253
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/9.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/9.edn_smoke.3710319982
Short name T65
Test name
Test status
Simulation time 46145422 ps
CPU time 0.78 seconds
Started Aug 23 05:46:20 PM UTC 24
Finished Aug 23 05:46:22 PM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710319982 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 9.edn_smoke.3710319982
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/9.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/9.edn_stress_all_with_rand_reset.2252744712
Short name T237
Test name
Test status
Simulation time 5572160915 ps
CPU time 54.98 seconds
Started Aug 23 05:46:20 PM UTC 24
Finished Aug 23 05:47:17 PM UTC 24
Peak memory 233308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2252744712 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_
with_rand_reset.2252744712
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/9.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/90.edn_alert.1013976293
Short name T136
Test name
Test status
Simulation time 23220174 ps
CPU time 1.05 seconds
Started Aug 23 05:49:04 PM UTC 24
Finished Aug 23 05:49:06 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013976293 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 90.edn_alert.1013976293
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/90.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/90.edn_err.2123957904
Short name T683
Test name
Test status
Simulation time 43979382 ps
CPU time 0.98 seconds
Started Aug 23 05:49:04 PM UTC 24
Finished Aug 23 05:49:06 PM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123957904 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 90.edn_err.2123957904
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/90.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/90.edn_genbits.3666084998
Short name T681
Test name
Test status
Simulation time 158569236 ps
CPU time 1.01 seconds
Started Aug 23 05:49:04 PM UTC 24
Finished Aug 23 05:49:06 PM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666084998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3666084998
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/90.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/91.edn_alert.2351222526
Short name T274
Test name
Test status
Simulation time 48725166 ps
CPU time 1.04 seconds
Started Aug 23 05:49:04 PM UTC 24
Finished Aug 23 05:49:06 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351222526 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 91.edn_alert.2351222526
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/91.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/91.edn_err.2944421129
Short name T680
Test name
Test status
Simulation time 30940712 ps
CPU time 0.72 seconds
Started Aug 23 05:49:04 PM UTC 24
Finished Aug 23 05:49:06 PM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944421129 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 91.edn_err.2944421129
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/91.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/91.edn_genbits.208312133
Short name T684
Test name
Test status
Simulation time 99371423 ps
CPU time 1.1 seconds
Started Aug 23 05:49:04 PM UTC 24
Finished Aug 23 05:49:06 PM UTC 24
Peak memory 230632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208312133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 91.edn_genbits.208312133
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/91.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/92.edn_alert.2746291017
Short name T685
Test name
Test status
Simulation time 89958338 ps
CPU time 0.93 seconds
Started Aug 23 05:49:05 PM UTC 24
Finished Aug 23 05:49:07 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746291017 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 92.edn_alert.2746291017
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/92.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/92.edn_genbits.1453329475
Short name T326
Test name
Test status
Simulation time 71869003 ps
CPU time 1.09 seconds
Started Aug 23 05:49:05 PM UTC 24
Finished Aug 23 05:49:07 PM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453329475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1453329475
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/92.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/93.edn_alert.3901085012
Short name T687
Test name
Test status
Simulation time 29924099 ps
CPU time 1.09 seconds
Started Aug 23 05:49:05 PM UTC 24
Finished Aug 23 05:49:07 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901085012 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 93.edn_alert.3901085012
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/93.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/93.edn_err.3314653273
Short name T146
Test name
Test status
Simulation time 30240541 ps
CPU time 1.1 seconds
Started Aug 23 05:49:06 PM UTC 24
Finished Aug 23 05:49:08 PM UTC 24
Peak memory 226292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314653273 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 93.edn_err.3314653273
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/93.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/93.edn_genbits.3051859401
Short name T686
Test name
Test status
Simulation time 49099743 ps
CPU time 1.22 seconds
Started Aug 23 05:49:05 PM UTC 24
Finished Aug 23 05:49:07 PM UTC 24
Peak memory 228220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051859401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 93.edn_genbits.3051859401
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/93.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/94.edn_alert.1068424815
Short name T689
Test name
Test status
Simulation time 61463583 ps
CPU time 0.94 seconds
Started Aug 23 05:49:06 PM UTC 24
Finished Aug 23 05:49:08 PM UTC 24
Peak memory 230256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068424815 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 94.edn_alert.1068424815
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/94.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/94.edn_err.192437540
Short name T688
Test name
Test status
Simulation time 72884772 ps
CPU time 0.72 seconds
Started Aug 23 05:49:06 PM UTC 24
Finished Aug 23 05:49:08 PM UTC 24
Peak memory 228484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192437540 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 94.edn_err.192437540
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/94.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/94.edn_genbits.2833674267
Short name T691
Test name
Test status
Simulation time 57009376 ps
CPU time 1.54 seconds
Started Aug 23 05:49:06 PM UTC 24
Finished Aug 23 05:49:09 PM UTC 24
Peak memory 228160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833674267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2833674267
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/94.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/95.edn_alert.1991589958
Short name T693
Test name
Test status
Simulation time 28726188 ps
CPU time 1.11 seconds
Started Aug 23 05:49:07 PM UTC 24
Finished Aug 23 05:49:10 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991589958 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 95.edn_alert.1991589958
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/95.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/95.edn_err.3961392315
Short name T147
Test name
Test status
Simulation time 24955074 ps
CPU time 1.05 seconds
Started Aug 23 05:49:07 PM UTC 24
Finished Aug 23 05:49:10 PM UTC 24
Peak memory 244036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961392315 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 95.edn_err.3961392315
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/95.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/96.edn_alert.2973913777
Short name T695
Test name
Test status
Simulation time 27722307 ps
CPU time 1.08 seconds
Started Aug 23 05:49:07 PM UTC 24
Finished Aug 23 05:49:10 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973913777 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 96.edn_alert.2973913777
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/96.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/96.edn_err.2276844607
Short name T692
Test name
Test status
Simulation time 52039342 ps
CPU time 0.82 seconds
Started Aug 23 05:49:07 PM UTC 24
Finished Aug 23 05:49:09 PM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276844607 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 96.edn_err.2276844607
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/96.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/96.edn_genbits.2161964804
Short name T697
Test name
Test status
Simulation time 114655114 ps
CPU time 1.45 seconds
Started Aug 23 05:49:07 PM UTC 24
Finished Aug 23 05:49:10 PM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161964804 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2161964804
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/96.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/97.edn_alert.2498104261
Short name T696
Test name
Test status
Simulation time 25471632 ps
CPU time 1.01 seconds
Started Aug 23 05:49:08 PM UTC 24
Finished Aug 23 05:49:10 PM UTC 24
Peak memory 228436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498104261 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 97.edn_alert.2498104261
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/97.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/97.edn_err.3074404153
Short name T187
Test name
Test status
Simulation time 22582925 ps
CPU time 0.91 seconds
Started Aug 23 05:49:09 PM UTC 24
Finished Aug 23 05:49:11 PM UTC 24
Peak memory 236520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074404153 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 97.edn_err.3074404153
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/97.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/97.edn_genbits.2193792539
Short name T694
Test name
Test status
Simulation time 62531017 ps
CPU time 0.93 seconds
Started Aug 23 05:49:08 PM UTC 24
Finished Aug 23 05:49:10 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193792539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2193792539
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/97.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/98.edn_alert.4205773905
Short name T698
Test name
Test status
Simulation time 23937652 ps
CPU time 0.95 seconds
Started Aug 23 05:49:09 PM UTC 24
Finished Aug 23 05:49:11 PM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205773905 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 98.edn_alert.4205773905
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/98.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/98.edn_err.1734731020
Short name T700
Test name
Test status
Simulation time 21230090 ps
CPU time 1.07 seconds
Started Aug 23 05:49:09 PM UTC 24
Finished Aug 23 05:49:11 PM UTC 24
Peak memory 245132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734731020 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 98.edn_err.1734731020
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/98.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/98.edn_genbits.2919214218
Short name T699
Test name
Test status
Simulation time 45421379 ps
CPU time 0.99 seconds
Started Aug 23 05:49:09 PM UTC 24
Finished Aug 23 05:49:11 PM UTC 24
Peak memory 227576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919214218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2919214218
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/98.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/99.edn_alert.168959723
Short name T179
Test name
Test status
Simulation time 36057642 ps
CPU time 1.02 seconds
Started Aug 23 05:49:10 PM UTC 24
Finished Aug 23 05:49:12 PM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168959723 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 99.edn_alert.168959723
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/99.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/99.edn_err.516626840
Short name T702
Test name
Test status
Simulation time 27531602 ps
CPU time 0.77 seconds
Started Aug 23 05:49:10 PM UTC 24
Finished Aug 23 05:49:12 PM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516626840 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 99.edn_err.516626840
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/99.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/default/99.edn_genbits.1433107881
Short name T701
Test name
Test status
Simulation time 59187263 ps
CPU time 1.35 seconds
Started Aug 23 05:49:09 PM UTC 24
Finished Aug 23 05:49:11 PM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433107881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 99.edn_genbits.1433107881
Directory /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/99.edn_genbits/latest
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