Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=1}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=1}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=1}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	2	0	2	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=1}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	8	0	8	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_intr

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

73538

1

T1

1

T2

12

T3

14

all_values[1]

73538

1

T1

1

T2

12

T3

14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

115838

1

T1

2

T2

24

T3

28

auto[1]

31238

1

T6

46

T61

53

T62

57

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

129702

1

T1

2

T2

20

T3

22

auto[1]

17374

1

T2

4

T3

6

T7

10

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	46559	1			T1	1		T2	8		T3	8
all_values[0]	auto[0]	auto[1]	11521	1			T2	4		T3	6		T7	10
all_values[0]	auto[1]	auto[0]	11592	1			T6	26		T61	26		T62	11
all_values[0]	auto[1]	auto[1]	3866	1			T6	11		T61	15		T62	16
all_values[1]	auto[0]	auto[0]	56791	1			T1	1		T2	12		T3	14
all_values[1]	auto[0]	auto[1]	967	1			T6	9		T61	22		T62	7
all_values[1]	auto[1]	auto[0]	14760	1			T6	3		T61	6		T62	15
all_values[1]	auto[1]	auto[1]	1020	1			T6	6		T61	6		T62	15