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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.90 98.25 93.91 97.02 93.02 96.37 99.77 92.99


Total test records in report: 1102
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T1009 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_rw.318226757 Aug 25 06:54:06 AM UTC 24 Aug 25 06:54:09 AM UTC 24 41988936 ps
T1010 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2740400630 Aug 25 06:54:06 AM UTC 24 Aug 25 06:54:09 AM UTC 24 49611606 ps
T1011 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/9.edn_same_csr_outstanding.4257664246 Aug 25 06:54:06 AM UTC 24 Aug 25 06:54:09 AM UTC 24 26133755 ps
T1012 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/9.edn_intr_test.4094924440 Aug 25 06:54:06 AM UTC 24 Aug 25 06:54:09 AM UTC 24 44156841 ps
T1013 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/8.edn_same_csr_outstanding.3838888027 Aug 25 06:54:06 AM UTC 24 Aug 25 06:54:09 AM UTC 24 26661192 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_intg_err.3310637974 Aug 25 06:54:06 AM UTC 24 Aug 25 06:54:09 AM UTC 24 57218453 ps
T1014 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_intg_err.4018918720 Aug 25 06:54:06 AM UTC 24 Aug 25 06:54:09 AM UTC 24 82837605 ps
T1015 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_errors.1749934909 Aug 25 06:54:06 AM UTC 24 Aug 25 06:54:09 AM UTC 24 230461581 ps
T1016 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_errors.825028062 Aug 25 06:54:06 AM UTC 24 Aug 25 06:54:09 AM UTC 24 58495902 ps
T1017 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_errors.1242459624 Aug 25 06:54:06 AM UTC 24 Aug 25 06:54:09 AM UTC 24 105342397 ps
T1018 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_errors.3202264469 Aug 25 06:54:05 AM UTC 24 Aug 25 06:54:09 AM UTC 24 134086982 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_intg_err.4232886990 Aug 25 06:54:05 AM UTC 24 Aug 25 06:54:09 AM UTC 24 113960081 ps
T1019 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3684239107 Aug 25 06:54:06 AM UTC 24 Aug 25 06:54:10 AM UTC 24 36085155 ps
T1020 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/10.edn_same_csr_outstanding.284151160 Aug 25 06:54:06 AM UTC 24 Aug 25 06:54:10 AM UTC 24 53119217 ps
T1021 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_rw.22242483 Aug 25 06:54:07 AM UTC 24 Aug 25 06:54:10 AM UTC 24 71499205 ps
T1022 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1731001962 Aug 25 06:54:06 AM UTC 24 Aug 25 06:54:10 AM UTC 24 15620465 ps
T1023 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/11.edn_same_csr_outstanding.3521093879 Aug 25 06:54:07 AM UTC 24 Aug 25 06:54:10 AM UTC 24 37968640 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_rw.983940189 Aug 25 06:54:07 AM UTC 24 Aug 25 06:54:10 AM UTC 24 34760180 ps
T1024 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/12.edn_intr_test.2514516798 Aug 25 06:54:07 AM UTC 24 Aug 25 06:54:10 AM UTC 24 12073957 ps
T1025 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_rw.1110465137 Aug 25 06:54:08 AM UTC 24 Aug 25 06:54:10 AM UTC 24 41547794 ps
T1026 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1945453958 Aug 25 06:54:07 AM UTC 24 Aug 25 06:54:10 AM UTC 24 25506456 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_intg_err.510145034 Aug 25 06:54:06 AM UTC 24 Aug 25 06:54:11 AM UTC 24 837474035 ps
T1027 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/15.edn_intr_test.2228545799 Aug 25 06:54:08 AM UTC 24 Aug 25 06:54:11 AM UTC 24 25843945 ps
T1028 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/14.edn_same_csr_outstanding.2499506760 Aug 25 06:54:08 AM UTC 24 Aug 25 06:54:11 AM UTC 24 53564829 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_rw.589891107 Aug 25 06:54:08 AM UTC 24 Aug 25 06:54:11 AM UTC 24 16633119 ps
T1029 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.891423039 Aug 25 06:54:08 AM UTC 24 Aug 25 06:54:11 AM UTC 24 41295467 ps
T1030 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_intg_err.729209637 Aug 25 06:54:07 AM UTC 24 Aug 25 06:54:11 AM UTC 24 269334597 ps
T1031 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_bit_bash.3519666426 Aug 25 06:54:04 AM UTC 24 Aug 25 06:54:11 AM UTC 24 426902321 ps
T1032 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/12.edn_same_csr_outstanding.41520420 Aug 25 06:54:08 AM UTC 24 Aug 25 06:54:12 AM UTC 24 28891009 ps
T1033 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/13.edn_intr_test.1127308645 Aug 25 06:54:08 AM UTC 24 Aug 25 06:54:12 AM UTC 24 45524112 ps
T1034 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/14.edn_intr_test.2018127454 Aug 25 06:54:08 AM UTC 24 Aug 25 06:54:12 AM UTC 24 14449744 ps
T1035 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_intg_err.2487224202 Aug 25 06:54:08 AM UTC 24 Aug 25 06:54:12 AM UTC 24 50637665 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_rw.3356179196 Aug 25 06:54:08 AM UTC 24 Aug 25 06:54:12 AM UTC 24 12264114 ps
T1036 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/10.edn_intr_test.4148790048 Aug 25 06:54:06 AM UTC 24 Aug 25 06:54:12 AM UTC 24 16154908 ps
T1037 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_intg_err.3570151814 Aug 25 06:54:08 AM UTC 24 Aug 25 06:54:12 AM UTC 24 79787004 ps
T1038 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_intg_err.1088900719 Aug 25 06:54:06 AM UTC 24 Aug 25 06:54:12 AM UTC 24 447050467 ps
T1039 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1646085113 Aug 25 06:54:08 AM UTC 24 Aug 25 06:54:12 AM UTC 24 53349771 ps
T1040 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/13.edn_same_csr_outstanding.2779000697 Aug 25 06:54:08 AM UTC 24 Aug 25 06:54:12 AM UTC 24 42607049 ps
T1041 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_errors.3339513293 Aug 25 06:54:06 AM UTC 24 Aug 25 06:54:12 AM UTC 24 103943199 ps
T1042 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_errors.3182150895 Aug 25 06:54:08 AM UTC 24 Aug 25 06:54:12 AM UTC 24 89009815 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_rw.2276543290 Aug 25 06:54:10 AM UTC 24 Aug 25 06:54:12 AM UTC 24 24801116 ps
T1043 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_errors.893570371 Aug 25 06:54:07 AM UTC 24 Aug 25 06:54:12 AM UTC 24 804012453 ps
T1044 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_errors.1116832355 Aug 25 06:54:08 AM UTC 24 Aug 25 06:54:12 AM UTC 24 73941196 ps
T1045 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.977853556 Aug 25 06:54:09 AM UTC 24 Aug 25 06:54:12 AM UTC 24 44550857 ps
T1046 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.882814257 Aug 25 06:54:08 AM UTC 24 Aug 25 06:54:12 AM UTC 24 142041558 ps
T1047 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_intg_err.1410948306 Aug 25 06:54:08 AM UTC 24 Aug 25 06:54:13 AM UTC 24 293001203 ps
T1048 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_errors.2473838438 Aug 25 06:54:08 AM UTC 24 Aug 25 06:54:13 AM UTC 24 29916844 ps
T1049 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_intg_err.1040257202 Aug 25 06:54:10 AM UTC 24 Aug 25 06:54:13 AM UTC 24 73388626 ps
T1050 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/22.edn_intr_test.1356762225 Aug 25 06:54:12 AM UTC 24 Aug 25 06:54:15 AM UTC 24 20877575 ps
T1051 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/15.edn_same_csr_outstanding.3033887686 Aug 25 06:54:09 AM UTC 24 Aug 25 06:54:15 AM UTC 24 21414333 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_rw.1033431495 Aug 25 06:54:10 AM UTC 24 Aug 25 06:54:15 AM UTC 24 14683944 ps
T1052 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/16.edn_intr_test.4170639795 Aug 25 06:54:10 AM UTC 24 Aug 25 06:54:15 AM UTC 24 57803986 ps
T1053 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/18.edn_intr_test.4076533916 Aug 25 06:54:10 AM UTC 24 Aug 25 06:54:15 AM UTC 24 31851231 ps
T1054 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/17.edn_same_csr_outstanding.2340580072 Aug 25 06:54:10 AM UTC 24 Aug 25 06:54:15 AM UTC 24 29247782 ps
T1055 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_rw.1142935687 Aug 25 06:54:10 AM UTC 24 Aug 25 06:54:15 AM UTC 24 12570273 ps
T1056 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/39.edn_intr_test.1208238445 Aug 25 06:54:13 AM UTC 24 Aug 25 06:54:15 AM UTC 24 18861464 ps
T1057 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2182148632 Aug 25 06:54:10 AM UTC 24 Aug 25 06:54:15 AM UTC 24 30437369 ps
T1058 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/17.edn_intr_test.3825665685 Aug 25 06:54:10 AM UTC 24 Aug 25 06:54:15 AM UTC 24 16783761 ps
T1059 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/18.edn_same_csr_outstanding.781797476 Aug 25 06:54:10 AM UTC 24 Aug 25 06:54:15 AM UTC 24 20835146 ps
T1060 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/16.edn_same_csr_outstanding.4115663070 Aug 25 06:54:10 AM UTC 24 Aug 25 06:54:15 AM UTC 24 19775983 ps
T1061 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/40.edn_intr_test.2881577954 Aug 25 06:54:13 AM UTC 24 Aug 25 06:54:16 AM UTC 24 13461576 ps
T1062 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/38.edn_intr_test.3966041567 Aug 25 06:54:13 AM UTC 24 Aug 25 06:54:16 AM UTC 24 24791127 ps
T1063 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/41.edn_intr_test.3524005195 Aug 25 06:54:13 AM UTC 24 Aug 25 06:54:16 AM UTC 24 25988174 ps
T1064 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/43.edn_intr_test.2446244407 Aug 25 06:54:13 AM UTC 24 Aug 25 06:54:16 AM UTC 24 14587203 ps
T1065 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/47.edn_intr_test.2369755831 Aug 25 06:54:13 AM UTC 24 Aug 25 06:54:16 AM UTC 24 11814231 ps
T1066 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/42.edn_intr_test.4034639934 Aug 25 06:54:13 AM UTC 24 Aug 25 06:54:16 AM UTC 24 25018286 ps
T1067 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.457827185 Aug 25 06:54:10 AM UTC 24 Aug 25 06:54:16 AM UTC 24 97165607 ps
T1068 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/48.edn_intr_test.375546042 Aug 25 06:54:14 AM UTC 24 Aug 25 06:54:16 AM UTC 24 27965072 ps
T1069 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_intg_err.4148774938 Aug 25 06:54:10 AM UTC 24 Aug 25 06:54:16 AM UTC 24 66004647 ps
T1070 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/44.edn_intr_test.2682174080 Aug 25 06:54:13 AM UTC 24 Aug 25 06:54:16 AM UTC 24 54016168 ps
T1071 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/46.edn_intr_test.737329886 Aug 25 06:54:13 AM UTC 24 Aug 25 06:54:16 AM UTC 24 12244427 ps
T1072 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/45.edn_intr_test.2077251059 Aug 25 06:54:13 AM UTC 24 Aug 25 06:54:16 AM UTC 24 13417290 ps
T1073 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/49.edn_intr_test.1730099818 Aug 25 06:54:14 AM UTC 24 Aug 25 06:54:16 AM UTC 24 45424560 ps
T1074 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.541946602 Aug 25 06:54:10 AM UTC 24 Aug 25 06:54:16 AM UTC 24 28164783 ps
T1075 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_intg_err.308412068 Aug 25 06:54:10 AM UTC 24 Aug 25 06:54:16 AM UTC 24 645983689 ps
T1076 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_errors.2582842073 Aug 25 06:54:10 AM UTC 24 Aug 25 06:54:16 AM UTC 24 86343840 ps
T1077 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_errors.3587083804 Aug 25 06:54:10 AM UTC 24 Aug 25 06:54:17 AM UTC 24 71692954 ps
T1078 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_errors.1053810429 Aug 25 06:54:10 AM UTC 24 Aug 25 06:54:17 AM UTC 24 393522575 ps
T1079 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_errors.2328640960 Aug 25 06:54:10 AM UTC 24 Aug 25 06:54:17 AM UTC 24 506874205 ps
T1080 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_rw.2352565164 Aug 25 06:54:06 AM UTC 24 Aug 25 06:54:26 AM UTC 24 20342898 ps
T1081 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/35.edn_intr_test.4174937838 Aug 25 06:54:13 AM UTC 24 Aug 25 06:54:26 AM UTC 24 30782961 ps
T1082 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/34.edn_intr_test.171628873 Aug 25 06:54:13 AM UTC 24 Aug 25 06:54:26 AM UTC 24 53491943 ps
T1083 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/36.edn_intr_test.3193342883 Aug 25 06:54:13 AM UTC 24 Aug 25 06:54:27 AM UTC 24 18828113 ps
T1084 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/37.edn_intr_test.928294364 Aug 25 06:54:13 AM UTC 24 Aug 25 06:54:27 AM UTC 24 15311322 ps
T1085 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_rw.883876072 Aug 25 06:54:11 AM UTC 24 Aug 25 06:54:27 AM UTC 24 17603564 ps
T1086 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/19.edn_same_csr_outstanding.3854046797 Aug 25 06:54:11 AM UTC 24 Aug 25 06:54:27 AM UTC 24 50818619 ps
T1087 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/19.edn_intr_test.914867773 Aug 25 06:54:11 AM UTC 24 Aug 25 06:54:27 AM UTC 24 14681840 ps
T1088 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/21.edn_intr_test.2426594484 Aug 25 06:54:12 AM UTC 24 Aug 25 06:54:27 AM UTC 24 12880611 ps
T1089 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/25.edn_intr_test.1141423986 Aug 25 06:54:12 AM UTC 24 Aug 25 06:54:27 AM UTC 24 26172061 ps
T1090 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/20.edn_intr_test.3206973764 Aug 25 06:54:11 AM UTC 24 Aug 25 06:54:27 AM UTC 24 26857726 ps
T1091 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.4124771052 Aug 25 06:54:11 AM UTC 24 Aug 25 06:54:27 AM UTC 24 184007613 ps
T1092 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/23.edn_intr_test.3649770831 Aug 25 06:54:12 AM UTC 24 Aug 25 06:54:30 AM UTC 24 14207564 ps
T1093 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/26.edn_intr_test.3656944296 Aug 25 06:54:12 AM UTC 24 Aug 25 06:54:30 AM UTC 24 31107230 ps
T1094 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/31.edn_intr_test.3058866914 Aug 25 06:54:12 AM UTC 24 Aug 25 06:54:30 AM UTC 24 26460685 ps
T1095 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/24.edn_intr_test.1646378934 Aug 25 06:54:12 AM UTC 24 Aug 25 06:54:30 AM UTC 24 47315698 ps
T1096 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/32.edn_intr_test.4063715748 Aug 25 06:54:12 AM UTC 24 Aug 25 06:54:30 AM UTC 24 21669285 ps
T1097 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/28.edn_intr_test.1578989199 Aug 25 06:54:12 AM UTC 24 Aug 25 06:54:30 AM UTC 24 14316858 ps
T1098 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/30.edn_intr_test.3888080240 Aug 25 06:54:12 AM UTC 24 Aug 25 06:54:31 AM UTC 24 19770031 ps
T1099 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/27.edn_intr_test.1321461863 Aug 25 06:54:12 AM UTC 24 Aug 25 06:54:31 AM UTC 24 15326445 ps
T1100 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/33.edn_intr_test.1493072979 Aug 25 06:54:12 AM UTC 24 Aug 25 06:54:31 AM UTC 24 36350847 ps
T1101 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/29.edn_intr_test.1081147674 Aug 25 06:54:12 AM UTC 24 Aug 25 06:54:31 AM UTC 24 32830864 ps
T1102 /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_intg_err.2289050544 Aug 25 06:54:11 AM UTC 24 Aug 25 06:54:34 AM UTC 24 111587868 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/0.edn_disable_auto_req_mode.388769267
Short name T2
Test name
Test status
Simulation time 52977697 ps
CPU time 1.55 seconds
Started Aug 25 06:49:45 AM UTC 24
Finished Aug 25 06:49:52 AM UTC 24
Peak memory 225960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388769267 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable_auto_req_mode.388769267
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/0.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/0.edn_sec_cm.2530993205
Short name T16
Test name
Test status
Simulation time 1519087695 ps
CPU time 4.91 seconds
Started Aug 25 06:49:45 AM UTC 24
Finished Aug 25 06:49:55 AM UTC 24
Peak memory 260232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530993205 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.2530993205
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/0.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/3.edn_genbits.4054345297
Short name T30
Test name
Test status
Simulation time 39614480 ps
CPU time 1.2 seconds
Started Aug 25 06:49:53 AM UTC 24
Finished Aug 25 06:49:56 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054345297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_genbits.4054345297
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/3.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/0.edn_alert.4247758344
Short name T24
Test name
Test status
Simulation time 24816437 ps
CPU time 1.2 seconds
Started Aug 25 06:49:42 AM UTC 24
Finished Aug 25 06:49:52 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247758344 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 0.edn_alert.4247758344
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/0.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/0.edn_stress_all.2181856473
Short name T6
Test name
Test status
Simulation time 192004739 ps
CPU time 3.63 seconds
Started Aug 25 06:49:42 AM UTC 24
Finished Aug 25 06:49:54 AM UTC 24
Peak memory 229600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181856473 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2181856473
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/0.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/9.edn_stress_all_with_rand_reset.4206489888
Short name T39
Test name
Test status
Simulation time 4860988204 ps
CPU time 16.77 seconds
Started Aug 25 06:50:02 AM UTC 24
Finished Aug 25 06:50:20 AM UTC 24
Peak memory 231904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=4206489888 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_
with_rand_reset.4206489888
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/9.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/10.edn_genbits.132821191
Short name T23
Test name
Test status
Simulation time 660457938 ps
CPU time 4.02 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:50:10 AM UTC 24
Peak memory 231516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132821191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.edn_genbits.132821191
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/10.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/4.edn_alert.268717508
Short name T100
Test name
Test status
Simulation time 26913478 ps
CPU time 1.2 seconds
Started Aug 25 06:50:00 AM UTC 24
Finished Aug 25 06:50:03 AM UTC 24
Peak memory 230084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268717508 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 4.edn_alert.268717508
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/4.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/3.edn_alert.3788518709
Short name T28
Test name
Test status
Simulation time 27172944 ps
CPU time 1.48 seconds
Started Aug 25 06:49:54 AM UTC 24
Finished Aug 25 06:49:56 AM UTC 24
Peak memory 226760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788518709 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 3.edn_alert.3788518709
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/3.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/2.edn_disable.1357978530
Short name T26
Test name
Test status
Simulation time 12513815 ps
CPU time 0.84 seconds
Started Aug 25 06:49:53 AM UTC 24
Finished Aug 25 06:49:55 AM UTC 24
Peak memory 216132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357978530 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1357978530
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/2.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/9.edn_alert.3530275444
Short name T126
Test name
Test status
Simulation time 103864086 ps
CPU time 1.39 seconds
Started Aug 25 06:50:02 AM UTC 24
Finished Aug 25 06:50:05 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530275444 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 9.edn_alert.3530275444
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/9.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/2.edn_stress_all_with_rand_reset.1724506716
Short name T228
Test name
Test status
Simulation time 63104606621 ps
CPU time 89.74 seconds
Started Aug 25 06:49:53 AM UTC 24
Finished Aug 25 06:51:27 AM UTC 24
Peak memory 231976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1724506716 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_
with_rand_reset.1724506716
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/2.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/11.edn_err.2409113248
Short name T232
Test name
Test status
Simulation time 38265811 ps
CPU time 1.16 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:50:18 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409113248 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 11.edn_err.2409113248
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/11.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/7.edn_genbits.4100804546
Short name T21
Test name
Test status
Simulation time 82734991 ps
CPU time 1.27 seconds
Started Aug 25 06:50:01 AM UTC 24
Finished Aug 25 06:50:04 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100804546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_genbits.4100804546
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/7.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/19.edn_alert.1661834546
Short name T137
Test name
Test status
Simulation time 84088303 ps
CPU time 1.47 seconds
Started Aug 25 06:50:19 AM UTC 24
Finished Aug 25 06:50:22 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661834546 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 19.edn_alert.1661834546
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/19.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_intg_err.1138414971
Short name T315
Test name
Test status
Simulation time 174135215 ps
CPU time 1.72 seconds
Started Aug 25 06:54:04 AM UTC 24
Finished Aug 25 06:54:07 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138414971 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1138414971
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/5.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/27.edn_disable.373738493
Short name T208
Test name
Test status
Simulation time 55040135 ps
CPU time 1.24 seconds
Started Aug 25 06:50:57 AM UTC 24
Finished Aug 25 06:51:01 AM UTC 24
Peak memory 226332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373738493 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.373738493
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/27.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/1.edn_genbits.91880043
Short name T45
Test name
Test status
Simulation time 118426207 ps
CPU time 1.61 seconds
Started Aug 25 06:49:51 AM UTC 24
Finished Aug 25 06:49:57 AM UTC 24
Peak memory 230384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91880043 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 1.edn_genbits.91880043
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/1.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/12.edn_disable.764676491
Short name T48
Test name
Test status
Simulation time 52184962 ps
CPU time 0.72 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:50:15 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764676491 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.764676491
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/12.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/33.edn_disable.787167891
Short name T457
Test name
Test status
Simulation time 80475830 ps
CPU time 0.86 seconds
Started Aug 25 06:51:08 AM UTC 24
Finished Aug 25 06:51:28 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787167891 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.787167891
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/33.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/36.edn_disable_auto_req_mode.1518173124
Short name T143
Test name
Test status
Simulation time 68700571 ps
CPU time 1.98 seconds
Started Aug 25 06:51:29 AM UTC 24
Finished Aug 25 06:51:32 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518173124 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable_auto_req_mode.1518173124
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/36.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/9.edn_err.3006952150
Short name T110
Test name
Test status
Simulation time 62868058 ps
CPU time 1.08 seconds
Started Aug 25 06:50:02 AM UTC 24
Finished Aug 25 06:50:04 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006952150 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 9.edn_err.3006952150
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/9.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_hw_reset.2762723198
Short name T279
Test name
Test status
Simulation time 14023919 ps
CPU time 1.18 seconds
Started Aug 25 06:54:02 AM UTC 24
Finished Aug 25 06:54:05 AM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762723198 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2762723198
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/3.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/13.edn_genbits.1646665081
Short name T14
Test name
Test status
Simulation time 138082477 ps
CPU time 1.48 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:50:18 AM UTC 24
Peak memory 230608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646665081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1646665081
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/13.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/15.edn_alert.2905302487
Short name T215
Test name
Test status
Simulation time 56101845 ps
CPU time 1.82 seconds
Started Aug 25 06:50:09 AM UTC 24
Finished Aug 25 06:50:22 AM UTC 24
Peak memory 226356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905302487 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 15.edn_alert.2905302487
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/15.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/12.edn_intr.1796867687
Short name T36
Test name
Test status
Simulation time 19444334 ps
CPU time 1.01 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:50:15 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796867687 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 12.edn_intr.1796867687
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/12.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/70.edn_alert.3054146377
Short name T171
Test name
Test status
Simulation time 53410219 ps
CPU time 1.54 seconds
Started Aug 25 06:52:08 AM UTC 24
Finished Aug 25 06:52:11 AM UTC 24
Peak memory 230360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054146377 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 70.edn_alert.3054146377
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/70.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/16.edn_alert.3262726847
Short name T96
Test name
Test status
Simulation time 23917520 ps
CPU time 1.16 seconds
Started Aug 25 06:50:12 AM UTC 24
Finished Aug 25 06:50:18 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262726847 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 16.edn_alert.3262726847
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/16.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/13.edn_disable_auto_req_mode.2191192988
Short name T123
Test name
Test status
Simulation time 236041153 ps
CPU time 1.28 seconds
Started Aug 25 06:50:06 AM UTC 24
Finished Aug 25 06:50:18 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191192988 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable_auto_req_mode.2191192988
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/13.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/47.edn_alert.793370402
Short name T157
Test name
Test status
Simulation time 28219723 ps
CPU time 1.77 seconds
Started Aug 25 06:51:58 AM UTC 24
Finished Aug 25 06:52:01 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793370402 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 47.edn_alert.793370402
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/47.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/2.edn_alert.4136394209
Short name T76
Test name
Test status
Simulation time 33071571 ps
CPU time 1.18 seconds
Started Aug 25 06:49:53 AM UTC 24
Finished Aug 25 06:49:57 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136394209 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 2.edn_alert.4136394209
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/2.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/43.edn_intr.883263593
Short name T99
Test name
Test status
Simulation time 60518142 ps
CPU time 1.2 seconds
Started Aug 25 06:51:35 AM UTC 24
Finished Aug 25 06:51:58 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883263593 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 43.edn_intr.883263593
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/43.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/0.edn_alert_test.2078687293
Short name T25
Test name
Test status
Simulation time 23605758 ps
CPU time 0.79 seconds
Started Aug 25 06:49:46 AM UTC 24
Finished Aug 25 06:49:55 AM UTC 24
Peak memory 217292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078687293 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2078687293
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/0.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/3.edn_stress_all.1695747417
Short name T43
Test name
Test status
Simulation time 88953909 ps
CPU time 2.21 seconds
Started Aug 25 06:49:53 AM UTC 24
Finished Aug 25 06:49:57 AM UTC 24
Peak memory 229664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695747417 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1695747417
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/3.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/30.edn_disable.4219093254
Short name T236
Test name
Test status
Simulation time 23625912 ps
CPU time 1.11 seconds
Started Aug 25 06:51:03 AM UTC 24
Finished Aug 25 06:51:26 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219093254 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.4219093254
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/30.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/1.edn_disable.1788342628
Short name T42
Test name
Test status
Simulation time 35337430 ps
CPU time 1.04 seconds
Started Aug 25 06:49:53 AM UTC 24
Finished Aug 25 06:49:57 AM UTC 24
Peak memory 226352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788342628 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1788342628
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/1.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/10.edn_alert.3592275733
Short name T128
Test name
Test status
Simulation time 28701817 ps
CPU time 1.19 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:50:17 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592275733 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 10.edn_alert.3592275733
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/10.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/10.edn_disable_auto_req_mode.1492110218
Short name T149
Test name
Test status
Simulation time 193321802 ps
CPU time 1.26 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:50:18 AM UTC 24
Peak memory 226240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492110218 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable_auto_req_mode.1492110218
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/10.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/101.edn_alert.1344336630
Short name T153
Test name
Test status
Simulation time 76186999 ps
CPU time 1.3 seconds
Started Aug 25 06:52:23 AM UTC 24
Finished Aug 25 06:52:26 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344336630 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 101.edn_alert.1344336630
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/101.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/103.edn_alert.2461451201
Short name T680
Test name
Test status
Simulation time 83659336 ps
CPU time 1.27 seconds
Started Aug 25 06:52:23 AM UTC 24
Finished Aug 25 06:52:26 AM UTC 24
Peak memory 228408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461451201 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 103.edn_alert.2461451201
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/103.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/11.edn_disable_auto_req_mode.3968037186
Short name T92
Test name
Test status
Simulation time 86499578 ps
CPU time 1.07 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:50:15 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968037186 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable_auto_req_mode.3968037186
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/11.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/130.edn_alert.3041969600
Short name T741
Test name
Test status
Simulation time 200159191 ps
CPU time 1.15 seconds
Started Aug 25 06:52:29 AM UTC 24
Finished Aug 25 06:52:45 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041969600 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 130.edn_alert.3041969600
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/130.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/144.edn_alert.3943466900
Short name T772
Test name
Test status
Simulation time 53334916 ps
CPU time 1.15 seconds
Started Aug 25 06:52:32 AM UTC 24
Finished Aug 25 06:53:00 AM UTC 24
Peak memory 230456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943466900 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 144.edn_alert.3943466900
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/144.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/148.edn_alert.2780279320
Short name T864
Test name
Test status
Simulation time 43954507 ps
CPU time 1.15 seconds
Started Aug 25 06:52:32 AM UTC 24
Finished Aug 25 06:53:32 AM UTC 24
Peak memory 230456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780279320 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 148.edn_alert.2780279320
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/148.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/17.edn_err.1528591502
Short name T217
Test name
Test status
Simulation time 31735765 ps
CPU time 0.83 seconds
Started Aug 25 06:50:16 AM UTC 24
Finished Aug 25 06:50:25 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528591502 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 17.edn_err.1528591502
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/17.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/20.edn_disable.4108752366
Short name T225
Test name
Test status
Simulation time 29391809 ps
CPU time 0.9 seconds
Started Aug 25 06:50:22 AM UTC 24
Finished Aug 25 06:50:57 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108752366 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.4108752366
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/20.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/36.edn_disable.2660204639
Short name T209
Test name
Test status
Simulation time 37758464 ps
CPU time 1.22 seconds
Started Aug 25 06:51:29 AM UTC 24
Finished Aug 25 06:51:32 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660204639 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2660204639
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/36.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/42.edn_err.3902853437
Short name T212
Test name
Test status
Simulation time 21264714 ps
CPU time 1.18 seconds
Started Aug 25 06:51:34 AM UTC 24
Finished Aug 25 06:51:40 AM UTC 24
Peak memory 237212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902853437 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 42.edn_err.3902853437
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/42.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/43.edn_disable.2269924029
Short name T227
Test name
Test status
Simulation time 11022021 ps
CPU time 1.32 seconds
Started Aug 25 06:51:35 AM UTC 24
Finished Aug 25 06:51:58 AM UTC 24
Peak memory 226368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269924029 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2269924029
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/43.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/46.edn_disable.3454385696
Short name T230
Test name
Test status
Simulation time 12007994 ps
CPU time 1.27 seconds
Started Aug 25 06:51:47 AM UTC 24
Finished Aug 25 06:51:57 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454385696 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3454385696
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/46.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/114.edn_genbits.2470252806
Short name T707
Test name
Test status
Simulation time 83085247 ps
CPU time 1.65 seconds
Started Aug 25 06:52:25 AM UTC 24
Finished Aug 25 06:52:28 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470252806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 114.edn_genbits.2470252806
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/114.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/144.edn_genbits.1837317135
Short name T347
Test name
Test status
Simulation time 49727435 ps
CPU time 1.18 seconds
Started Aug 25 06:52:32 AM UTC 24
Finished Aug 25 06:53:00 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837317135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1837317135
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/144.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/55.edn_genbits.1121912353
Short name T336
Test name
Test status
Simulation time 53314505 ps
CPU time 1.7 seconds
Started Aug 25 06:52:02 AM UTC 24
Finished Aug 25 06:52:05 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121912353 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 55.edn_genbits.1121912353
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/55.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/15.edn_intr.1891051856
Short name T34
Test name
Test status
Simulation time 28534763 ps
CPU time 1.15 seconds
Started Aug 25 06:50:09 AM UTC 24
Finished Aug 25 06:50:22 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891051856 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 15.edn_intr.1891051856
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/15.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_rw.41159266
Short name T277
Test name
Test status
Simulation time 23140664 ps
CPU time 1.01 seconds
Started Aug 25 06:53:40 AM UTC 24
Finished Aug 25 06:54:03 AM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41159266 -assert nopostproc +UVM_TESTNAME=edn_base_t
est +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.41159266
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/0.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/0.edn_tl_intg_err.2125775657
Short name T307
Test name
Test status
Simulation time 164642366 ps
CPU time 2.09 seconds
Started Aug 25 06:53:38 AM UTC 24
Finished Aug 25 06:53:42 AM UTC 24
Peak memory 217556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125775657 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.2125775657
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/0.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/0.edn_smoke.1598420879
Short name T44
Test name
Test status
Simulation time 72681180 ps
CPU time 0.78 seconds
Started Aug 25 06:49:41 AM UTC 24
Finished Aug 25 06:49:56 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598420879 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 0.edn_smoke.1598420879
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/0.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/1.edn_alert.4152374230
Short name T29
Test name
Test status
Simulation time 26164711 ps
CPU time 1.16 seconds
Started Aug 25 06:49:53 AM UTC 24
Finished Aug 25 06:49:57 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152374230 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 1.edn_alert.4152374230
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/1.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/11.edn_genbits.1990192729
Short name T53
Test name
Test status
Simulation time 27685850 ps
CPU time 1.75 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:50:18 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990192729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1990192729
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/11.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/149.edn_genbits.2270637654
Short name T346
Test name
Test status
Simulation time 113194115 ps
CPU time 2.14 seconds
Started Aug 25 06:52:32 AM UTC 24
Finished Aug 25 06:53:29 AM UTC 24
Peak memory 229520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270637654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2270637654
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/149.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/150.edn_genbits.2042706560
Short name T341
Test name
Test status
Simulation time 437563072 ps
CPU time 3.99 seconds
Started Aug 25 06:52:32 AM UTC 24
Finished Aug 25 06:52:58 AM UTC 24
Peak memory 229532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042706560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 150.edn_genbits.2042706560
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/150.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/160.edn_genbits.2435027250
Short name T334
Test name
Test status
Simulation time 71400690 ps
CPU time 1.06 seconds
Started Aug 25 06:52:56 AM UTC 24
Finished Aug 25 06:53:05 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435027250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 160.edn_genbits.2435027250
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/160.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/164.edn_genbits.2049918436
Short name T351
Test name
Test status
Simulation time 48949257 ps
CPU time 1.98 seconds
Started Aug 25 06:52:57 AM UTC 24
Finished Aug 25 06:53:02 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049918436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2049918436
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/164.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/194.edn_genbits.1851481392
Short name T350
Test name
Test status
Simulation time 57271654 ps
CPU time 1.74 seconds
Started Aug 25 06:53:27 AM UTC 24
Finished Aug 25 06:53:32 AM UTC 24
Peak memory 228556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851481392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 194.edn_genbits.1851481392
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/194.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/202.edn_genbits.248136730
Short name T882
Test name
Test status
Simulation time 151085734 ps
CPU time 1.79 seconds
Started Aug 25 06:53:28 AM UTC 24
Finished Aug 25 06:53:32 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248136730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 202.edn_genbits.248136730
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/202.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/65.edn_genbits.2333378858
Short name T343
Test name
Test status
Simulation time 55087679 ps
CPU time 1.99 seconds
Started Aug 25 06:52:06 AM UTC 24
Finished Aug 25 06:52:09 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333378858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 65.edn_genbits.2333378858
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/65.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/75.edn_genbits.3198427893
Short name T338
Test name
Test status
Simulation time 94550032 ps
CPU time 2.08 seconds
Started Aug 25 06:52:09 AM UTC 24
Finished Aug 25 06:52:12 AM UTC 24
Peak memory 229592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198427893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 75.edn_genbits.3198427893
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/75.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/11.edn_intr.3121644773
Short name T37
Test name
Test status
Simulation time 35196998 ps
CPU time 0.91 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:50:18 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121644773 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 11.edn_intr.3121644773
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/11.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/105.edn_alert.1566794982
Short name T687
Test name
Test status
Simulation time 132809612 ps
CPU time 1.65 seconds
Started Aug 25 06:52:23 AM UTC 24
Finished Aug 25 06:52:27 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566794982 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 105.edn_alert.1566794982
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/105.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/181.edn_alert.511137031
Short name T135
Test name
Test status
Simulation time 25850737 ps
CPU time 1.1 seconds
Started Aug 25 06:53:02 AM UTC 24
Finished Aug 25 06:53:26 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511137031 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 181.edn_alert.511137031
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/181.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/25.edn_disable.2626065996
Short name T238
Test name
Test status
Simulation time 28344769 ps
CPU time 0.9 seconds
Started Aug 25 06:50:28 AM UTC 24
Finished Aug 25 06:51:01 AM UTC 24
Peak memory 226368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626065996 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2626065996
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/25.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/103.edn_genbits.4040255664
Short name T681
Test name
Test status
Simulation time 73211055 ps
CPU time 1.29 seconds
Started Aug 25 06:52:23 AM UTC 24
Finished Aug 25 06:52:26 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040255664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 103.edn_genbits.4040255664
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/103.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_aliasing.366070943
Short name T273
Test name
Test status
Simulation time 123285769 ps
CPU time 1.32 seconds
Started Aug 25 06:53:42 AM UTC 24
Finished Aug 25 06:54:01 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366070943 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.366070943
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/0.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_bit_bash.2557599972
Short name T283
Test name
Test status
Simulation time 219790986 ps
CPU time 2.93 seconds
Started Aug 25 06:53:41 AM UTC 24
Finished Aug 25 06:54:03 AM UTC 24
Peak memory 217612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557599972 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2557599972
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/0.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_hw_reset.3177750472
Short name T278
Test name
Test status
Simulation time 15010275 ps
CPU time 1.22 seconds
Started Aug 25 06:53:40 AM UTC 24
Finished Aug 25 06:54:03 AM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177750472 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.3177750472
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/0.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3479547988
Short name T976
Test name
Test status
Simulation time 22327343 ps
CPU time 1.11 seconds
Started Aug 25 06:53:42 AM UTC 24
Finished Aug 25 06:54:01 AM UTC 24
Peak memory 225700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3479547988 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3479547988
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/0.edn_intr_test.2222458177
Short name T982
Test name
Test status
Simulation time 21917377 ps
CPU time 0.96 seconds
Started Aug 25 06:53:40 AM UTC 24
Finished Aug 25 06:54:03 AM UTC 24
Peak memory 215448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222458177 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.2222458177
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/0.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/0.edn_same_csr_outstanding.728234950
Short name T290
Test name
Test status
Simulation time 15344430 ps
CPU time 0.89 seconds
Started Aug 25 06:53:42 AM UTC 24
Finished Aug 25 06:54:01 AM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728234950 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_outstanding.728234950
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/0.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/0.edn_tl_errors.4278679894
Short name T973
Test name
Test status
Simulation time 423374283 ps
CPU time 3 seconds
Started Aug 25 06:53:38 AM UTC 24
Finished Aug 25 06:53:42 AM UTC 24
Peak memory 227788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278679894 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.4278679894
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/0.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_aliasing.417880541
Short name T980
Test name
Test status
Simulation time 74783562 ps
CPU time 1.41 seconds
Started Aug 25 06:53:43 AM UTC 24
Finished Aug 25 06:54:02 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417880541 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.417880541
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/1.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_bit_bash.574737228
Short name T1001
Test name
Test status
Simulation time 169093502 ps
CPU time 5.87 seconds
Started Aug 25 06:53:43 AM UTC 24
Finished Aug 25 06:54:08 AM UTC 24
Peak memory 217624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574737228 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.574737228
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/1.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_hw_reset.1272700323
Short name T984
Test name
Test status
Simulation time 53508123 ps
CPU time 0.99 seconds
Started Aug 25 06:53:43 AM UTC 24
Finished Aug 25 06:54:03 AM UTC 24
Peak memory 215016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272700323 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1272700323
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/1.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3470441444
Short name T974
Test name
Test status
Simulation time 47445862 ps
CPU time 1.06 seconds
Started Aug 25 06:53:43 AM UTC 24
Finished Aug 25 06:53:45 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3470441444 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3470441444
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_rw.1838099232
Short name T276
Test name
Test status
Simulation time 15178094 ps
CPU time 0.71 seconds
Started Aug 25 06:53:43 AM UTC 24
Finished Aug 25 06:54:02 AM UTC 24
Peak memory 215096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838099232 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.1838099232
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/1.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/1.edn_intr_test.1960372887
Short name T978
Test name
Test status
Simulation time 36939140 ps
CPU time 0.75 seconds
Started Aug 25 06:53:43 AM UTC 24
Finished Aug 25 06:54:02 AM UTC 24
Peak memory 215388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960372887 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.1960372887
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/1.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/1.edn_same_csr_outstanding.2915680244
Short name T291
Test name
Test status
Simulation time 26161240 ps
CPU time 1.12 seconds
Started Aug 25 06:53:43 AM UTC 24
Finished Aug 25 06:54:02 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915680244 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_outstanding.2915680244
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/1.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/1.edn_tl_errors.3785702740
Short name T983
Test name
Test status
Simulation time 407768764 ps
CPU time 3.04 seconds
Started Aug 25 06:53:42 AM UTC 24
Finished Aug 25 06:54:03 AM UTC 24
Peak memory 227788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785702740 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3785702740
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/1.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/1.edn_tl_intg_err.3885136986
Short name T308
Test name
Test status
Simulation time 49923327 ps
CPU time 1.49 seconds
Started Aug 25 06:53:42 AM UTC 24
Finished Aug 25 06:54:01 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885136986 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3885136986
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/1.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1731001962
Short name T1022
Test name
Test status
Simulation time 15620465 ps
CPU time 1.05 seconds
Started Aug 25 06:54:06 AM UTC 24
Finished Aug 25 06:54:10 AM UTC 24
Peak memory 225704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1731001962 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1731001962
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_rw.2352565164
Short name T1080
Test name
Test status
Simulation time 20342898 ps
CPU time 0.9 seconds
Started Aug 25 06:54:06 AM UTC 24
Finished Aug 25 06:54:26 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352565164 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2352565164
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/10.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/10.edn_intr_test.4148790048
Short name T1036
Test name
Test status
Simulation time 16154908 ps
CPU time 1.11 seconds
Started Aug 25 06:54:06 AM UTC 24
Finished Aug 25 06:54:12 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148790048 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.4148790048
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/10.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/10.edn_same_csr_outstanding.284151160
Short name T1020
Test name
Test status
Simulation time 53119217 ps
CPU time 1.17 seconds
Started Aug 25 06:54:06 AM UTC 24
Finished Aug 25 06:54:10 AM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284151160 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_outstanding.284151160
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/10.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_errors.2987572791
Short name T1004
Test name
Test status
Simulation time 84024717 ps
CPU time 3.37 seconds
Started Aug 25 06:54:06 AM UTC 24
Finished Aug 25 06:54:11 AM UTC 24
Peak memory 227612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987572791 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2987572791
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/10.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_intg_err.1088900719
Short name T1038
Test name
Test status
Simulation time 447050467 ps
CPU time 1.42 seconds
Started Aug 25 06:54:06 AM UTC 24
Finished Aug 25 06:54:12 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088900719 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1088900719
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/10.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1945453958
Short name T1026
Test name
Test status
Simulation time 25506456 ps
CPU time 1.5 seconds
Started Aug 25 06:54:07 AM UTC 24
Finished Aug 25 06:54:10 AM UTC 24
Peak memory 225704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1945453958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.1945453958
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_rw.22242483
Short name T1021
Test name
Test status
Simulation time 71499205 ps
CPU time 0.86 seconds
Started Aug 25 06:54:07 AM UTC 24
Finished Aug 25 06:54:10 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22242483 -assert nopostproc +UVM_TESTNAME=edn_base_t
est +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.22242483
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/11.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/11.edn_intr_test.1769062602
Short name T981
Test name
Test status
Simulation time 33341297 ps
CPU time 0.73 seconds
Started Aug 25 06:54:06 AM UTC 24
Finished Aug 25 06:54:10 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769062602 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1769062602
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/11.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/11.edn_same_csr_outstanding.3521093879
Short name T1023
Test name
Test status
Simulation time 37968640 ps
CPU time 0.96 seconds
Started Aug 25 06:54:07 AM UTC 24
Finished Aug 25 06:54:10 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521093879 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_outstanding.3521093879
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/11.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_errors.3339513293
Short name T1041
Test name
Test status
Simulation time 103943199 ps
CPU time 3.58 seconds
Started Aug 25 06:54:06 AM UTC 24
Finished Aug 25 06:54:12 AM UTC 24
Peak memory 227852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339513293 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3339513293
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/11.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_intg_err.510145034
Short name T317
Test name
Test status
Simulation time 837474035 ps
CPU time 1.85 seconds
Started Aug 25 06:54:06 AM UTC 24
Finished Aug 25 06:54:11 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510145034 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.510145034
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/11.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1646085113
Short name T1039
Test name
Test status
Simulation time 53349771 ps
CPU time 1.8 seconds
Started Aug 25 06:54:08 AM UTC 24
Finished Aug 25 06:54:12 AM UTC 24
Peak memory 225512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1646085113 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1646085113
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_rw.983940189
Short name T282
Test name
Test status
Simulation time 34760180 ps
CPU time 0.89 seconds
Started Aug 25 06:54:07 AM UTC 24
Finished Aug 25 06:54:10 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983940189 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.983940189
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/12.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/12.edn_intr_test.2514516798
Short name T1024
Test name
Test status
Simulation time 12073957 ps
CPU time 1.1 seconds
Started Aug 25 06:54:07 AM UTC 24
Finished Aug 25 06:54:10 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514516798 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2514516798
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/12.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/12.edn_same_csr_outstanding.41520420
Short name T1032
Test name
Test status
Simulation time 28891009 ps
CPU time 1.12 seconds
Started Aug 25 06:54:08 AM UTC 24
Finished Aug 25 06:54:12 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41520420 -assert nopostproc +UVM_T
ESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_outstanding.41520420
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/12.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_errors.893570371
Short name T1043
Test name
Test status
Simulation time 804012453 ps
CPU time 3.38 seconds
Started Aug 25 06:54:07 AM UTC 24
Finished Aug 25 06:54:12 AM UTC 24
Peak memory 227856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893570371 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.893570371
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/12.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_intg_err.729209637
Short name T1030
Test name
Test status
Simulation time 269334597 ps
CPU time 2.31 seconds
Started Aug 25 06:54:07 AM UTC 24
Finished Aug 25 06:54:11 AM UTC 24
Peak memory 228008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729209637 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.729209637
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/12.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.882814257
Short name T1046
Test name
Test status
Simulation time 142041558 ps
CPU time 1.86 seconds
Started Aug 25 06:54:08 AM UTC 24
Finished Aug 25 06:54:12 AM UTC 24
Peak memory 229792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=882814257 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.882814257
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_rw.3356179196
Short name T289
Test name
Test status
Simulation time 12264114 ps
CPU time 1.2 seconds
Started Aug 25 06:54:08 AM UTC 24
Finished Aug 25 06:54:12 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356179196 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3356179196
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/13.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/13.edn_intr_test.1127308645
Short name T1033
Test name
Test status
Simulation time 45524112 ps
CPU time 0.92 seconds
Started Aug 25 06:54:08 AM UTC 24
Finished Aug 25 06:54:12 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127308645 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1127308645
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/13.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/13.edn_same_csr_outstanding.2779000697
Short name T1040
Test name
Test status
Simulation time 42607049 ps
CPU time 1.73 seconds
Started Aug 25 06:54:08 AM UTC 24
Finished Aug 25 06:54:12 AM UTC 24
Peak memory 215096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779000697 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_outstanding.2779000697
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/13.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_errors.1116832355
Short name T1044
Test name
Test status
Simulation time 73941196 ps
CPU time 1.85 seconds
Started Aug 25 06:54:08 AM UTC 24
Finished Aug 25 06:54:12 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116832355 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1116832355
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/13.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_intg_err.3570151814
Short name T1037
Test name
Test status
Simulation time 79787004 ps
CPU time 1.56 seconds
Started Aug 25 06:54:08 AM UTC 24
Finished Aug 25 06:54:12 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570151814 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3570151814
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/13.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.891423039
Short name T1029
Test name
Test status
Simulation time 41295467 ps
CPU time 1.31 seconds
Started Aug 25 06:54:08 AM UTC 24
Finished Aug 25 06:54:11 AM UTC 24
Peak memory 225696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=891423039 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.891423039
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_rw.1110465137
Short name T1025
Test name
Test status
Simulation time 41547794 ps
CPU time 0.88 seconds
Started Aug 25 06:54:08 AM UTC 24
Finished Aug 25 06:54:10 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110465137 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1110465137
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/14.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/14.edn_intr_test.2018127454
Short name T1034
Test name
Test status
Simulation time 14449744 ps
CPU time 0.91 seconds
Started Aug 25 06:54:08 AM UTC 24
Finished Aug 25 06:54:12 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018127454 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.2018127454
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/14.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/14.edn_same_csr_outstanding.2499506760
Short name T1028
Test name
Test status
Simulation time 53564829 ps
CPU time 1.27 seconds
Started Aug 25 06:54:08 AM UTC 24
Finished Aug 25 06:54:11 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499506760 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_outstanding.2499506760
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/14.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_errors.2473838438
Short name T1048
Test name
Test status
Simulation time 29916844 ps
CPU time 2.08 seconds
Started Aug 25 06:54:08 AM UTC 24
Finished Aug 25 06:54:13 AM UTC 24
Peak memory 227796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473838438 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2473838438
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/14.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_intg_err.1410948306
Short name T1047
Test name
Test status
Simulation time 293001203 ps
CPU time 1.96 seconds
Started Aug 25 06:54:08 AM UTC 24
Finished Aug 25 06:54:13 AM UTC 24
Peak memory 215348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410948306 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1410948306
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/14.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.977853556
Short name T1045
Test name
Test status
Simulation time 44550857 ps
CPU time 1.58 seconds
Started Aug 25 06:54:09 AM UTC 24
Finished Aug 25 06:54:12 AM UTC 24
Peak memory 225696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=977853556 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.977853556
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_rw.589891107
Short name T285
Test name
Test status
Simulation time 16633119 ps
CPU time 0.86 seconds
Started Aug 25 06:54:08 AM UTC 24
Finished Aug 25 06:54:11 AM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589891107 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.589891107
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/15.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/15.edn_intr_test.2228545799
Short name T1027
Test name
Test status
Simulation time 25843945 ps
CPU time 0.89 seconds
Started Aug 25 06:54:08 AM UTC 24
Finished Aug 25 06:54:11 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228545799 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.2228545799
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/15.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/15.edn_same_csr_outstanding.3033887686
Short name T1051
Test name
Test status
Simulation time 21414333 ps
CPU time 1.02 seconds
Started Aug 25 06:54:09 AM UTC 24
Finished Aug 25 06:54:15 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033887686 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_outstanding.3033887686
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/15.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_errors.3182150895
Short name T1042
Test name
Test status
Simulation time 89009815 ps
CPU time 2.63 seconds
Started Aug 25 06:54:08 AM UTC 24
Finished Aug 25 06:54:12 AM UTC 24
Peak memory 227884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182150895 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.3182150895
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/15.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_intg_err.2487224202
Short name T1035
Test name
Test status
Simulation time 50637665 ps
CPU time 1.8 seconds
Started Aug 25 06:54:08 AM UTC 24
Finished Aug 25 06:54:12 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487224202 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2487224202
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/15.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2182148632
Short name T1057
Test name
Test status
Simulation time 30437369 ps
CPU time 1.3 seconds
Started Aug 25 06:54:10 AM UTC 24
Finished Aug 25 06:54:15 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2182148632 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2182148632
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_rw.1033431495
Short name T287
Test name
Test status
Simulation time 14683944 ps
CPU time 0.89 seconds
Started Aug 25 06:54:10 AM UTC 24
Finished Aug 25 06:54:15 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033431495 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1033431495
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/16.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/16.edn_intr_test.4170639795
Short name T1052
Test name
Test status
Simulation time 57803986 ps
CPU time 0.9 seconds
Started Aug 25 06:54:10 AM UTC 24
Finished Aug 25 06:54:15 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170639795 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.4170639795
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/16.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/16.edn_same_csr_outstanding.4115663070
Short name T1060
Test name
Test status
Simulation time 19775983 ps
CPU time 1.39 seconds
Started Aug 25 06:54:10 AM UTC 24
Finished Aug 25 06:54:15 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115663070 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_outstanding.4115663070
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/16.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_errors.2582842073
Short name T1076
Test name
Test status
Simulation time 86343840 ps
CPU time 2.7 seconds
Started Aug 25 06:54:10 AM UTC 24
Finished Aug 25 06:54:16 AM UTC 24
Peak memory 231896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582842073 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.2582842073
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/16.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_intg_err.1040257202
Short name T1049
Test name
Test status
Simulation time 73388626 ps
CPU time 2.31 seconds
Started Aug 25 06:54:10 AM UTC 24
Finished Aug 25 06:54:13 AM UTC 24
Peak memory 217504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040257202 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1040257202
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/16.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.457827185
Short name T1067
Test name
Test status
Simulation time 97165607 ps
CPU time 1.36 seconds
Started Aug 25 06:54:10 AM UTC 24
Finished Aug 25 06:54:16 AM UTC 24
Peak memory 225564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=457827185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.457827185
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_rw.1142935687
Short name T1055
Test name
Test status
Simulation time 12570273 ps
CPU time 0.86 seconds
Started Aug 25 06:54:10 AM UTC 24
Finished Aug 25 06:54:15 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142935687 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1142935687
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/17.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/17.edn_intr_test.3825665685
Short name T1058
Test name
Test status
Simulation time 16783761 ps
CPU time 1.1 seconds
Started Aug 25 06:54:10 AM UTC 24
Finished Aug 25 06:54:15 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825665685 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.3825665685
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/17.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/17.edn_same_csr_outstanding.2340580072
Short name T1054
Test name
Test status
Simulation time 29247782 ps
CPU time 0.97 seconds
Started Aug 25 06:54:10 AM UTC 24
Finished Aug 25 06:54:15 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340580072 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_outstanding.2340580072
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/17.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_errors.1053810429
Short name T1078
Test name
Test status
Simulation time 393522575 ps
CPU time 3.11 seconds
Started Aug 25 06:54:10 AM UTC 24
Finished Aug 25 06:54:17 AM UTC 24
Peak memory 227792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053810429 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.1053810429
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/17.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_intg_err.4148774938
Short name T1069
Test name
Test status
Simulation time 66004647 ps
CPU time 1.72 seconds
Started Aug 25 06:54:10 AM UTC 24
Finished Aug 25 06:54:16 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148774938 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.4148774938
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/17.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.541946602
Short name T1074
Test name
Test status
Simulation time 28164783 ps
CPU time 1.7 seconds
Started Aug 25 06:54:10 AM UTC 24
Finished Aug 25 06:54:16 AM UTC 24
Peak memory 227744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=541946602 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.541946602
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_rw.2276543290
Short name T288
Test name
Test status
Simulation time 24801116 ps
CPU time 1.05 seconds
Started Aug 25 06:54:10 AM UTC 24
Finished Aug 25 06:54:12 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276543290 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.2276543290
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/18.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/18.edn_intr_test.4076533916
Short name T1053
Test name
Test status
Simulation time 31851231 ps
CPU time 0.9 seconds
Started Aug 25 06:54:10 AM UTC 24
Finished Aug 25 06:54:15 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076533916 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.4076533916
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/18.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/18.edn_same_csr_outstanding.781797476
Short name T1059
Test name
Test status
Simulation time 20835146 ps
CPU time 1.09 seconds
Started Aug 25 06:54:10 AM UTC 24
Finished Aug 25 06:54:15 AM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781797476 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_outstanding.781797476
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/18.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_errors.3587083804
Short name T1077
Test name
Test status
Simulation time 71692954 ps
CPU time 2.66 seconds
Started Aug 25 06:54:10 AM UTC 24
Finished Aug 25 06:54:17 AM UTC 24
Peak memory 227796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587083804 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3587083804
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/18.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_intg_err.308412068
Short name T1075
Test name
Test status
Simulation time 645983689 ps
CPU time 1.8 seconds
Started Aug 25 06:54:10 AM UTC 24
Finished Aug 25 06:54:16 AM UTC 24
Peak memory 225632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308412068 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.308412068
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/18.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.4124771052
Short name T1091
Test name
Test status
Simulation time 184007613 ps
CPU time 1.6 seconds
Started Aug 25 06:54:11 AM UTC 24
Finished Aug 25 06:54:27 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4124771052 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.4124771052
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_rw.883876072
Short name T1085
Test name
Test status
Simulation time 17603564 ps
CPU time 1.17 seconds
Started Aug 25 06:54:11 AM UTC 24
Finished Aug 25 06:54:27 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883876072 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.883876072
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/19.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/19.edn_intr_test.914867773
Short name T1087
Test name
Test status
Simulation time 14681840 ps
CPU time 1.16 seconds
Started Aug 25 06:54:11 AM UTC 24
Finished Aug 25 06:54:27 AM UTC 24
Peak memory 215376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914867773 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.914867773
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/19.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/19.edn_same_csr_outstanding.3854046797
Short name T1086
Test name
Test status
Simulation time 50818619 ps
CPU time 1.05 seconds
Started Aug 25 06:54:11 AM UTC 24
Finished Aug 25 06:54:27 AM UTC 24
Peak memory 215440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854046797 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_outstanding.3854046797
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/19.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_errors.2328640960
Short name T1079
Test name
Test status
Simulation time 506874205 ps
CPU time 2.77 seconds
Started Aug 25 06:54:10 AM UTC 24
Finished Aug 25 06:54:17 AM UTC 24
Peak memory 231892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328640960 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2328640960
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/19.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_intg_err.2289050544
Short name T1102
Test name
Test status
Simulation time 111587868 ps
CPU time 3.95 seconds
Started Aug 25 06:54:11 AM UTC 24
Finished Aug 25 06:54:34 AM UTC 24
Peak memory 217420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289050544 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.2289050544
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/19.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_aliasing.3530105719
Short name T275
Test name
Test status
Simulation time 29368187 ps
CPU time 1.2 seconds
Started Aug 25 06:53:59 AM UTC 24
Finished Aug 25 06:54:01 AM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530105719 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.3530105719
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/2.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_bit_bash.572069362
Short name T284
Test name
Test status
Simulation time 487693107 ps
CPU time 3.35 seconds
Started Aug 25 06:53:46 AM UTC 24
Finished Aug 25 06:54:04 AM UTC 24
Peak memory 216880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572069362 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.572069362
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/2.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_hw_reset.2506155397
Short name T274
Test name
Test status
Simulation time 76753382 ps
CPU time 0.74 seconds
Started Aug 25 06:53:46 AM UTC 24
Finished Aug 25 06:54:01 AM UTC 24
Peak memory 214236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506155397 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2506155397
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/2.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3417410591
Short name T986
Test name
Test status
Simulation time 76573102 ps
CPU time 1.64 seconds
Started Aug 25 06:54:01 AM UTC 24
Finished Aug 25 06:54:04 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3417410591 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3417410591
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_rw.3843870342
Short name T977
Test name
Test status
Simulation time 14459361 ps
CPU time 0.93 seconds
Started Aug 25 06:53:46 AM UTC 24
Finished Aug 25 06:54:01 AM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843870342 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3843870342
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/2.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/2.edn_intr_test.1567731733
Short name T975
Test name
Test status
Simulation time 45321321 ps
CPU time 0.74 seconds
Started Aug 25 06:53:46 AM UTC 24
Finished Aug 25 06:54:01 AM UTC 24
Peak memory 215388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567731733 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1567731733
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/2.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/2.edn_same_csr_outstanding.1130379439
Short name T292
Test name
Test status
Simulation time 22482230 ps
CPU time 1.52 seconds
Started Aug 25 06:54:01 AM UTC 24
Finished Aug 25 06:54:04 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130379439 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_outstanding.1130379439
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/2.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/2.edn_tl_errors.1567536218
Short name T979
Test name
Test status
Simulation time 82229462 ps
CPU time 1.47 seconds
Started Aug 25 06:53:43 AM UTC 24
Finished Aug 25 06:54:02 AM UTC 24
Peak memory 229724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567536218 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1567536218
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/2.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/2.edn_tl_intg_err.3769359140
Short name T987
Test name
Test status
Simulation time 285415696 ps
CPU time 2.29 seconds
Started Aug 25 06:53:44 AM UTC 24
Finished Aug 25 06:54:05 AM UTC 24
Peak memory 227948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769359140 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3769359140
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/2.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/20.edn_intr_test.3206973764
Short name T1090
Test name
Test status
Simulation time 26857726 ps
CPU time 1.23 seconds
Started Aug 25 06:54:11 AM UTC 24
Finished Aug 25 06:54:27 AM UTC 24
Peak memory 215368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206973764 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3206973764
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/20.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/21.edn_intr_test.2426594484
Short name T1088
Test name
Test status
Simulation time 12880611 ps
CPU time 1.09 seconds
Started Aug 25 06:54:12 AM UTC 24
Finished Aug 25 06:54:27 AM UTC 24
Peak memory 215356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426594484 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.2426594484
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/21.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/22.edn_intr_test.1356762225
Short name T1050
Test name
Test status
Simulation time 20877575 ps
CPU time 0.89 seconds
Started Aug 25 06:54:12 AM UTC 24
Finished Aug 25 06:54:15 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356762225 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1356762225
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/22.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/23.edn_intr_test.3649770831
Short name T1092
Test name
Test status
Simulation time 14207564 ps
CPU time 1.01 seconds
Started Aug 25 06:54:12 AM UTC 24
Finished Aug 25 06:54:30 AM UTC 24
Peak memory 215004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649770831 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3649770831
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/23.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/24.edn_intr_test.1646378934
Short name T1095
Test name
Test status
Simulation time 47315698 ps
CPU time 1.14 seconds
Started Aug 25 06:54:12 AM UTC 24
Finished Aug 25 06:54:30 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646378934 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.1646378934
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/24.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/25.edn_intr_test.1141423986
Short name T1089
Test name
Test status
Simulation time 26172061 ps
CPU time 1.03 seconds
Started Aug 25 06:54:12 AM UTC 24
Finished Aug 25 06:54:27 AM UTC 24
Peak memory 214928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141423986 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1141423986
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/25.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/26.edn_intr_test.3656944296
Short name T1093
Test name
Test status
Simulation time 31107230 ps
CPU time 1 seconds
Started Aug 25 06:54:12 AM UTC 24
Finished Aug 25 06:54:30 AM UTC 24
Peak memory 215328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656944296 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3656944296
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/26.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/27.edn_intr_test.1321461863
Short name T1099
Test name
Test status
Simulation time 15326445 ps
CPU time 1.31 seconds
Started Aug 25 06:54:12 AM UTC 24
Finished Aug 25 06:54:31 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321461863 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1321461863
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/27.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/28.edn_intr_test.1578989199
Short name T1097
Test name
Test status
Simulation time 14316858 ps
CPU time 1.12 seconds
Started Aug 25 06:54:12 AM UTC 24
Finished Aug 25 06:54:30 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578989199 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.1578989199
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/28.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/29.edn_intr_test.1081147674
Short name T1101
Test name
Test status
Simulation time 32830864 ps
CPU time 1.29 seconds
Started Aug 25 06:54:12 AM UTC 24
Finished Aug 25 06:54:31 AM UTC 24
Peak memory 215124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081147674 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1081147674
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/29.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_aliasing.3222243103
Short name T988
Test name
Test status
Simulation time 23956941 ps
CPU time 1.03 seconds
Started Aug 25 06:54:02 AM UTC 24
Finished Aug 25 06:54:05 AM UTC 24
Peak memory 215440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222243103 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3222243103
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/3.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_bit_bash.190097484
Short name T286
Test name
Test status
Simulation time 645284001 ps
CPU time 2.9 seconds
Started Aug 25 06:54:02 AM UTC 24
Finished Aug 25 06:54:07 AM UTC 24
Peak memory 217436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190097484 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.190097484
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/3.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2262847137
Short name T995
Test name
Test status
Simulation time 201303160 ps
CPU time 2.25 seconds
Started Aug 25 06:54:04 AM UTC 24
Finished Aug 25 06:54:07 AM UTC 24
Peak memory 227792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2262847137 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2262847137
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_rw.4065826667
Short name T293
Test name
Test status
Simulation time 24092080 ps
CPU time 1.02 seconds
Started Aug 25 06:54:02 AM UTC 24
Finished Aug 25 06:54:05 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065826667 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.4065826667
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/3.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/3.edn_intr_test.4016164166
Short name T985
Test name
Test status
Simulation time 34125771 ps
CPU time 1 seconds
Started Aug 25 06:54:01 AM UTC 24
Finished Aug 25 06:54:04 AM UTC 24
Peak memory 215448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016164166 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.4016164166
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/3.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/3.edn_same_csr_outstanding.3523335886
Short name T294
Test name
Test status
Simulation time 45050640 ps
CPU time 1.17 seconds
Started Aug 25 06:54:02 AM UTC 24
Finished Aug 25 06:54:05 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523335886 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_outstanding.3523335886
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/3.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_errors.108942978
Short name T989
Test name
Test status
Simulation time 135260662 ps
CPU time 2.48 seconds
Started Aug 25 06:54:01 AM UTC 24
Finished Aug 25 06:54:05 AM UTC 24
Peak memory 227796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108942978 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.108942978
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/3.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_intg_err.2762581786
Short name T314
Test name
Test status
Simulation time 174910507 ps
CPU time 2.09 seconds
Started Aug 25 06:54:01 AM UTC 24
Finished Aug 25 06:54:05 AM UTC 24
Peak memory 217492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762581786 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2762581786
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/3.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/30.edn_intr_test.3888080240
Short name T1098
Test name
Test status
Simulation time 19770031 ps
CPU time 1.17 seconds
Started Aug 25 06:54:12 AM UTC 24
Finished Aug 25 06:54:31 AM UTC 24
Peak memory 215272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888080240 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.3888080240
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/30.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/31.edn_intr_test.3058866914
Short name T1094
Test name
Test status
Simulation time 26460685 ps
CPU time 0.92 seconds
Started Aug 25 06:54:12 AM UTC 24
Finished Aug 25 06:54:30 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058866914 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3058866914
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/31.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/32.edn_intr_test.4063715748
Short name T1096
Test name
Test status
Simulation time 21669285 ps
CPU time 1.06 seconds
Started Aug 25 06:54:12 AM UTC 24
Finished Aug 25 06:54:30 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063715748 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.4063715748
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/32.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/33.edn_intr_test.1493072979
Short name T1100
Test name
Test status
Simulation time 36350847 ps
CPU time 1.17 seconds
Started Aug 25 06:54:12 AM UTC 24
Finished Aug 25 06:54:31 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493072979 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.1493072979
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/33.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/34.edn_intr_test.171628873
Short name T1082
Test name
Test status
Simulation time 53491943 ps
CPU time 0.9 seconds
Started Aug 25 06:54:13 AM UTC 24
Finished Aug 25 06:54:26 AM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171628873 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.171628873
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/34.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/35.edn_intr_test.4174937838
Short name T1081
Test name
Test status
Simulation time 30782961 ps
CPU time 0.74 seconds
Started Aug 25 06:54:13 AM UTC 24
Finished Aug 25 06:54:26 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174937838 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.4174937838
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/35.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/36.edn_intr_test.3193342883
Short name T1083
Test name
Test status
Simulation time 18828113 ps
CPU time 0.96 seconds
Started Aug 25 06:54:13 AM UTC 24
Finished Aug 25 06:54:27 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193342883 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3193342883
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/36.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/37.edn_intr_test.928294364
Short name T1084
Test name
Test status
Simulation time 15311322 ps
CPU time 0.95 seconds
Started Aug 25 06:54:13 AM UTC 24
Finished Aug 25 06:54:27 AM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928294364 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.928294364
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/37.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/38.edn_intr_test.3966041567
Short name T1062
Test name
Test status
Simulation time 24791127 ps
CPU time 1.03 seconds
Started Aug 25 06:54:13 AM UTC 24
Finished Aug 25 06:54:16 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966041567 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3966041567
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/38.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/39.edn_intr_test.1208238445
Short name T1056
Test name
Test status
Simulation time 18861464 ps
CPU time 0.93 seconds
Started Aug 25 06:54:13 AM UTC 24
Finished Aug 25 06:54:15 AM UTC 24
Peak memory 215208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208238445 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.1208238445
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/39.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_aliasing.345402186
Short name T280
Test name
Test status
Simulation time 37542433 ps
CPU time 1.15 seconds
Started Aug 25 06:54:04 AM UTC 24
Finished Aug 25 06:54:06 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345402186 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.345402186
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/4.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_bit_bash.3519666426
Short name T1031
Test name
Test status
Simulation time 426902321 ps
CPU time 6.45 seconds
Started Aug 25 06:54:04 AM UTC 24
Finished Aug 25 06:54:11 AM UTC 24
Peak memory 217440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519666426 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.3519666426
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/4.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_hw_reset.3824857087
Short name T991
Test name
Test status
Simulation time 206428479 ps
CPU time 1.06 seconds
Started Aug 25 06:54:04 AM UTC 24
Finished Aug 25 06:54:06 AM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824857087 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3824857087
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/4.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.433954712
Short name T992
Test name
Test status
Simulation time 31243499 ps
CPU time 1.24 seconds
Started Aug 25 06:54:04 AM UTC 24
Finished Aug 25 06:54:06 AM UTC 24
Peak memory 225704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=433954712 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.433954712
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_rw.2201774457
Short name T295
Test name
Test status
Simulation time 113598362 ps
CPU time 1.18 seconds
Started Aug 25 06:54:04 AM UTC 24
Finished Aug 25 06:54:06 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201774457 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2201774457
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/4.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/4.edn_intr_test.1270385288
Short name T990
Test name
Test status
Simulation time 31037617 ps
CPU time 0.9 seconds
Started Aug 25 06:54:04 AM UTC 24
Finished Aug 25 06:54:06 AM UTC 24
Peak memory 215216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270385288 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1270385288
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/4.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/4.edn_same_csr_outstanding.3283826870
Short name T296
Test name
Test status
Simulation time 37513826 ps
CPU time 1.29 seconds
Started Aug 25 06:54:04 AM UTC 24
Finished Aug 25 06:54:06 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283826870 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_outstanding.3283826870
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/4.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_errors.4077184901
Short name T996
Test name
Test status
Simulation time 89221928 ps
CPU time 2.42 seconds
Started Aug 25 06:54:04 AM UTC 24
Finished Aug 25 06:54:07 AM UTC 24
Peak memory 227848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077184901 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.4077184901
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/4.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_intg_err.2411200537
Short name T318
Test name
Test status
Simulation time 205555772 ps
CPU time 1.81 seconds
Started Aug 25 06:54:04 AM UTC 24
Finished Aug 25 06:54:07 AM UTC 24
Peak memory 215268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411200537 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2411200537
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/4.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/40.edn_intr_test.2881577954
Short name T1061
Test name
Test status
Simulation time 13461576 ps
CPU time 0.93 seconds
Started Aug 25 06:54:13 AM UTC 24
Finished Aug 25 06:54:16 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881577954 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.2881577954
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/40.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/41.edn_intr_test.3524005195
Short name T1063
Test name
Test status
Simulation time 25988174 ps
CPU time 0.83 seconds
Started Aug 25 06:54:13 AM UTC 24
Finished Aug 25 06:54:16 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524005195 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.3524005195
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/41.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/42.edn_intr_test.4034639934
Short name T1066
Test name
Test status
Simulation time 25018286 ps
CPU time 1.05 seconds
Started Aug 25 06:54:13 AM UTC 24
Finished Aug 25 06:54:16 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034639934 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.4034639934
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/42.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/43.edn_intr_test.2446244407
Short name T1064
Test name
Test status
Simulation time 14587203 ps
CPU time 0.86 seconds
Started Aug 25 06:54:13 AM UTC 24
Finished Aug 25 06:54:16 AM UTC 24
Peak memory 215256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446244407 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2446244407
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/43.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/44.edn_intr_test.2682174080
Short name T1070
Test name
Test status
Simulation time 54016168 ps
CPU time 1.14 seconds
Started Aug 25 06:54:13 AM UTC 24
Finished Aug 25 06:54:16 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682174080 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2682174080
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/44.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/45.edn_intr_test.2077251059
Short name T1072
Test name
Test status
Simulation time 13417290 ps
CPU time 1.19 seconds
Started Aug 25 06:54:13 AM UTC 24
Finished Aug 25 06:54:16 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077251059 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2077251059
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/45.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/46.edn_intr_test.737329886
Short name T1071
Test name
Test status
Simulation time 12244427 ps
CPU time 1.01 seconds
Started Aug 25 06:54:13 AM UTC 24
Finished Aug 25 06:54:16 AM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737329886 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.737329886
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/46.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/47.edn_intr_test.2369755831
Short name T1065
Test name
Test status
Simulation time 11814231 ps
CPU time 0.87 seconds
Started Aug 25 06:54:13 AM UTC 24
Finished Aug 25 06:54:16 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369755831 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2369755831
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/47.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/48.edn_intr_test.375546042
Short name T1068
Test name
Test status
Simulation time 27965072 ps
CPU time 0.81 seconds
Started Aug 25 06:54:14 AM UTC 24
Finished Aug 25 06:54:16 AM UTC 24
Peak memory 215364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375546042 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.375546042
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/48.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/49.edn_intr_test.1730099818
Short name T1073
Test name
Test status
Simulation time 45424560 ps
CPU time 1.2 seconds
Started Aug 25 06:54:14 AM UTC 24
Finished Aug 25 06:54:16 AM UTC 24
Peak memory 215348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730099818 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1730099818
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/49.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.162308626
Short name T994
Test name
Test status
Simulation time 213889087 ps
CPU time 1.48 seconds
Started Aug 25 06:54:04 AM UTC 24
Finished Aug 25 06:54:07 AM UTC 24
Peak memory 225704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=162308626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.162308626
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_rw.2846165580
Short name T281
Test name
Test status
Simulation time 17417033 ps
CPU time 1.05 seconds
Started Aug 25 06:54:04 AM UTC 24
Finished Aug 25 06:54:06 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846165580 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2846165580
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/5.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/5.edn_intr_test.3052832742
Short name T993
Test name
Test status
Simulation time 42063566 ps
CPU time 1.18 seconds
Started Aug 25 06:54:04 AM UTC 24
Finished Aug 25 06:54:06 AM UTC 24
Peak memory 215448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052832742 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.3052832742
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/5.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/5.edn_same_csr_outstanding.3006210247
Short name T297
Test name
Test status
Simulation time 14145360 ps
CPU time 1.13 seconds
Started Aug 25 06:54:04 AM UTC 24
Finished Aug 25 06:54:06 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006210247 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_outstanding.3006210247
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/5.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_errors.2993099916
Short name T1002
Test name
Test status
Simulation time 36485311 ps
CPU time 2.83 seconds
Started Aug 25 06:54:04 AM UTC 24
Finished Aug 25 06:54:08 AM UTC 24
Peak memory 227872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993099916 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2993099916
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/5.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2259477845
Short name T1006
Test name
Test status
Simulation time 91085526 ps
CPU time 1.36 seconds
Started Aug 25 06:54:05 AM UTC 24
Finished Aug 25 06:54:08 AM UTC 24
Peak memory 225492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2259477845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.2259477845
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_rw.2210420926
Short name T999
Test name
Test status
Simulation time 22739396 ps
CPU time 0.99 seconds
Started Aug 25 06:54:05 AM UTC 24
Finished Aug 25 06:54:08 AM UTC 24
Peak memory 214272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210420926 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2210420926
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/6.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/6.edn_intr_test.1274704361
Short name T997
Test name
Test status
Simulation time 30991322 ps
CPU time 0.8 seconds
Started Aug 25 06:54:05 AM UTC 24
Finished Aug 25 06:54:07 AM UTC 24
Peak memory 215448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274704361 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.1274704361
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/6.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/6.edn_same_csr_outstanding.2989413557
Short name T298
Test name
Test status
Simulation time 16335746 ps
CPU time 1.09 seconds
Started Aug 25 06:54:05 AM UTC 24
Finished Aug 25 06:54:08 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989413557 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_outstanding.2989413557
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/6.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_errors.3202264469
Short name T1018
Test name
Test status
Simulation time 134086982 ps
CPU time 2.65 seconds
Started Aug 25 06:54:05 AM UTC 24
Finished Aug 25 06:54:09 AM UTC 24
Peak memory 227848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202264469 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3202264469
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/6.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_intg_err.4232886990
Short name T316
Test name
Test status
Simulation time 113960081 ps
CPU time 2.76 seconds
Started Aug 25 06:54:05 AM UTC 24
Finished Aug 25 06:54:09 AM UTC 24
Peak memory 217428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232886990 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.4232886990
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/6.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3121673145
Short name T1003
Test name
Test status
Simulation time 39479199 ps
CPU time 1.13 seconds
Started Aug 25 06:54:06 AM UTC 24
Finished Aug 25 06:54:08 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3121673145 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3121673145
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_rw.1702098269
Short name T1005
Test name
Test status
Simulation time 14958227 ps
CPU time 1.03 seconds
Started Aug 25 06:54:06 AM UTC 24
Finished Aug 25 06:54:08 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702098269 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1702098269
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/7.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/7.edn_intr_test.2676144409
Short name T998
Test name
Test status
Simulation time 28703866 ps
CPU time 0.83 seconds
Started Aug 25 06:54:06 AM UTC 24
Finished Aug 25 06:54:08 AM UTC 24
Peak memory 214456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676144409 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2676144409
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/7.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/7.edn_same_csr_outstanding.142605584
Short name T1000
Test name
Test status
Simulation time 27178477 ps
CPU time 0.96 seconds
Started Aug 25 06:54:06 AM UTC 24
Finished Aug 25 06:54:08 AM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142605584 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_outstanding.142605584
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/7.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_errors.1242459624
Short name T1017
Test name
Test status
Simulation time 105342397 ps
CPU time 2.26 seconds
Started Aug 25 06:54:06 AM UTC 24
Finished Aug 25 06:54:09 AM UTC 24
Peak memory 227616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242459624 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.1242459624
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/7.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_intg_err.4018918720
Short name T1014
Test name
Test status
Simulation time 82837605 ps
CPU time 2.17 seconds
Started Aug 25 06:54:06 AM UTC 24
Finished Aug 25 06:54:09 AM UTC 24
Peak memory 217496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018918720 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.4018918720
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/7.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2740400630
Short name T1010
Test name
Test status
Simulation time 49611606 ps
CPU time 1.27 seconds
Started Aug 25 06:54:06 AM UTC 24
Finished Aug 25 06:54:09 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2740400630 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.2740400630
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_rw.3341528316
Short name T1007
Test name
Test status
Simulation time 19606847 ps
CPU time 1.07 seconds
Started Aug 25 06:54:06 AM UTC 24
Finished Aug 25 06:54:08 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341528316 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.3341528316
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/8.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/8.edn_intr_test.804456415
Short name T1008
Test name
Test status
Simulation time 25998286 ps
CPU time 1.14 seconds
Started Aug 25 06:54:06 AM UTC 24
Finished Aug 25 06:54:08 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804456415 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.804456415
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/8.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/8.edn_same_csr_outstanding.3838888027
Short name T1013
Test name
Test status
Simulation time 26661192 ps
CPU time 1.52 seconds
Started Aug 25 06:54:06 AM UTC 24
Finished Aug 25 06:54:09 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838888027 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_outstanding.3838888027
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/8.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_errors.1749934909
Short name T1015
Test name
Test status
Simulation time 230461581 ps
CPU time 1.97 seconds
Started Aug 25 06:54:06 AM UTC 24
Finished Aug 25 06:54:09 AM UTC 24
Peak memory 225688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749934909 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1749934909
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/8.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_intg_err.3567823362
Short name T309
Test name
Test status
Simulation time 94816838 ps
CPU time 2.55 seconds
Started Aug 25 06:54:06 AM UTC 24
Finished Aug 25 06:54:10 AM UTC 24
Peak memory 217428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567823362 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.3567823362
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/8.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3684239107
Short name T1019
Test name
Test status
Simulation time 36085155 ps
CPU time 2.31 seconds
Started Aug 25 06:54:06 AM UTC 24
Finished Aug 25 06:54:10 AM UTC 24
Peak memory 227688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3684239107 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.3684239107
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_rw.318226757
Short name T1009
Test name
Test status
Simulation time 41988936 ps
CPU time 1.09 seconds
Started Aug 25 06:54:06 AM UTC 24
Finished Aug 25 06:54:09 AM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318226757 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.318226757
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/9.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/9.edn_intr_test.4094924440
Short name T1012
Test name
Test status
Simulation time 44156841 ps
CPU time 1.19 seconds
Started Aug 25 06:54:06 AM UTC 24
Finished Aug 25 06:54:09 AM UTC 24
Peak memory 215448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094924440 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.4094924440
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/9.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/9.edn_same_csr_outstanding.4257664246
Short name T1011
Test name
Test status
Simulation time 26133755 ps
CPU time 1.05 seconds
Started Aug 25 06:54:06 AM UTC 24
Finished Aug 25 06:54:09 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257664246 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_outstanding.4257664246
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/9.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_errors.825028062
Short name T1016
Test name
Test status
Simulation time 58495902 ps
CPU time 1.92 seconds
Started Aug 25 06:54:06 AM UTC 24
Finished Aug 25 06:54:09 AM UTC 24
Peak memory 225632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825028062 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.825028062
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/9.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_intg_err.3310637974
Short name T319
Test name
Test status
Simulation time 57218453 ps
CPU time 1.65 seconds
Started Aug 25 06:54:06 AM UTC 24
Finished Aug 25 06:54:09 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310637974 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3310637974
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/9.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/0.edn_disable.2600640788
Short name T1
Test name
Test status
Simulation time 13044716 ps
CPU time 0.83 seconds
Started Aug 25 06:49:43 AM UTC 24
Finished Aug 25 06:49:45 AM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600640788 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2600640788
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/0.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/0.edn_err.3993646269
Short name T5
Test name
Test status
Simulation time 21830820 ps
CPU time 1.22 seconds
Started Aug 25 06:49:42 AM UTC 24
Finished Aug 25 06:49:52 AM UTC 24
Peak memory 237336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993646269 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 0.edn_err.3993646269
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/0.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/0.edn_genbits.2293634685
Short name T7
Test name
Test status
Simulation time 137584404 ps
CPU time 1.27 seconds
Started Aug 25 06:49:42 AM UTC 24
Finished Aug 25 06:49:52 AM UTC 24
Peak memory 228328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293634685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2293634685
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/0.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/0.edn_intr.3014866016
Short name T4
Test name
Test status
Simulation time 19924997 ps
CPU time 1.11 seconds
Started Aug 25 06:49:42 AM UTC 24
Finished Aug 25 06:49:52 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014866016 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 0.edn_intr.3014866016
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/0.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/0.edn_regwen.2361962477
Short name T3
Test name
Test status
Simulation time 18886994 ps
CPU time 1.06 seconds
Started Aug 25 06:49:42 AM UTC 24
Finished Aug 25 06:49:52 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361962477 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 0.edn_regwen.2361962477
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/0.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/0.edn_stress_all_with_rand_reset.1634244393
Short name T40
Test name
Test status
Simulation time 4853411592 ps
CPU time 49.53 seconds
Started Aug 25 06:49:42 AM UTC 24
Finished Aug 25 06:50:41 AM UTC 24
Peak memory 229832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1634244393 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_
with_rand_reset.1634244393
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/1.edn_alert_test.889532530
Short name T70
Test name
Test status
Simulation time 20888074 ps
CPU time 0.94 seconds
Started Aug 25 06:49:53 AM UTC 24
Finished Aug 25 06:49:57 AM UTC 24
Peak memory 216080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889532530 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.889532530
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/1.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/1.edn_disable_auto_req_mode.4160997756
Short name T20
Test name
Test status
Simulation time 206220014 ps
CPU time 0.98 seconds
Started Aug 25 06:49:53 AM UTC 24
Finished Aug 25 06:49:56 AM UTC 24
Peak memory 226448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160997756 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable_auto_req_mode.4160997756
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/1.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/1.edn_err.1573923469
Short name T8
Test name
Test status
Simulation time 79040620 ps
CPU time 1.17 seconds
Started Aug 25 06:49:53 AM UTC 24
Finished Aug 25 06:49:57 AM UTC 24
Peak memory 230364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573923469 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 1.edn_err.1573923469
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/1.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/1.edn_intr.3673589046
Short name T63
Test name
Test status
Simulation time 31986539 ps
CPU time 1.03 seconds
Started Aug 25 06:49:53 AM UTC 24
Finished Aug 25 06:49:57 AM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673589046 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 1.edn_intr.3673589046
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/1.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/1.edn_regwen.1097095395
Short name T75
Test name
Test status
Simulation time 18057251 ps
CPU time 1.04 seconds
Started Aug 25 06:49:51 AM UTC 24
Finished Aug 25 06:49:57 AM UTC 24
Peak memory 216004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097095395 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 1.edn_regwen.1097095395
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/1.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/1.edn_sec_cm.989436595
Short name T19
Test name
Test status
Simulation time 1082294370 ps
CPU time 4.23 seconds
Started Aug 25 06:49:53 AM UTC 24
Finished Aug 25 06:50:00 AM UTC 24
Peak memory 262492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989436595 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.989436595
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/1.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/1.edn_smoke.3467360322
Short name T74
Test name
Test status
Simulation time 26446921 ps
CPU time 1.12 seconds
Started Aug 25 06:49:51 AM UTC 24
Finished Aug 25 06:49:56 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467360322 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 1.edn_smoke.3467360322
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/1.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/1.edn_stress_all.2299179771
Short name T62
Test name
Test status
Simulation time 150644558 ps
CPU time 3.59 seconds
Started Aug 25 06:49:51 AM UTC 24
Finished Aug 25 06:49:59 AM UTC 24
Peak memory 229476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299179771 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2299179771
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/1.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/10.edn_alert_test.2832843710
Short name T300
Test name
Test status
Simulation time 27863320 ps
CPU time 1.08 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:50:17 AM UTC 24
Peak memory 226984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832843710 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2832843710
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/10.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/10.edn_disable.1830911340
Short name T94
Test name
Test status
Simulation time 116228837 ps
CPU time 0.77 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:50:10 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830911340 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1830911340
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/10.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/10.edn_err.2042758794
Short name T182
Test name
Test status
Simulation time 36436411 ps
CPU time 0.92 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:50:10 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042758794 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 10.edn_err.2042758794
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/10.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/10.edn_intr.2797896742
Short name T85
Test name
Test status
Simulation time 36050789 ps
CPU time 0.88 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:50:07 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797896742 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 10.edn_intr.2797896742
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/10.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/10.edn_smoke.2628721174
Short name T369
Test name
Test status
Simulation time 53363992 ps
CPU time 0.92 seconds
Started Aug 25 06:50:04 AM UTC 24
Finished Aug 25 06:50:07 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628721174 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 10.edn_smoke.2628721174
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/10.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/10.edn_stress_all.2618073843
Short name T370
Test name
Test status
Simulation time 30206602 ps
CPU time 1.13 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:50:07 AM UTC 24
Peak memory 216668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618073843 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.2618073843
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/10.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/10.edn_stress_all_with_rand_reset.3413024371
Short name T581
Test name
Test status
Simulation time 4485397022 ps
CPU time 109.27 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:52:07 AM UTC 24
Peak memory 229948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3413024371 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all
_with_rand_reset.3413024371
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/10.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/100.edn_alert.1426116695
Short name T678
Test name
Test status
Simulation time 22690987 ps
CPU time 1.51 seconds
Started Aug 25 06:52:21 AM UTC 24
Finished Aug 25 06:52:25 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426116695 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 100.edn_alert.1426116695
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/100.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/100.edn_genbits.1876388795
Short name T710
Test name
Test status
Simulation time 52906857 ps
CPU time 2.21 seconds
Started Aug 25 06:52:21 AM UTC 24
Finished Aug 25 06:52:28 AM UTC 24
Peak memory 231680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876388795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 100.edn_genbits.1876388795
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/100.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/101.edn_genbits.2090638625
Short name T682
Test name
Test status
Simulation time 32798830 ps
CPU time 1.73 seconds
Started Aug 25 06:52:23 AM UTC 24
Finished Aug 25 06:52:26 AM UTC 24
Peak memory 226508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090638625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 101.edn_genbits.2090638625
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/101.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/102.edn_alert.2223394526
Short name T684
Test name
Test status
Simulation time 81290504 ps
CPU time 1.62 seconds
Started Aug 25 06:52:23 AM UTC 24
Finished Aug 25 06:52:26 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223394526 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 102.edn_alert.2223394526
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/102.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/102.edn_genbits.1853939554
Short name T688
Test name
Test status
Simulation time 59536520 ps
CPU time 2 seconds
Started Aug 25 06:52:23 AM UTC 24
Finished Aug 25 06:52:27 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853939554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 102.edn_genbits.1853939554
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/102.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/104.edn_alert.3751156244
Short name T686
Test name
Test status
Simulation time 84993726 ps
CPU time 1.67 seconds
Started Aug 25 06:52:23 AM UTC 24
Finished Aug 25 06:52:27 AM UTC 24
Peak memory 230380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751156244 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 104.edn_alert.3751156244
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/104.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/104.edn_genbits.3528362891
Short name T685
Test name
Test status
Simulation time 51831338 ps
CPU time 1.57 seconds
Started Aug 25 06:52:23 AM UTC 24
Finished Aug 25 06:52:27 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528362891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 104.edn_genbits.3528362891
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/104.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/105.edn_genbits.1632790240
Short name T689
Test name
Test status
Simulation time 32651457 ps
CPU time 1.73 seconds
Started Aug 25 06:52:23 AM UTC 24
Finished Aug 25 06:52:27 AM UTC 24
Peak memory 228004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632790240 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1632790240
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/105.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/106.edn_alert.17131524
Short name T712
Test name
Test status
Simulation time 80900408 ps
CPU time 1.76 seconds
Started Aug 25 06:52:23 AM UTC 24
Finished Aug 25 06:52:28 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17131524 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 106.edn_alert.17131524
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/106.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/106.edn_genbits.2191893098
Short name T705
Test name
Test status
Simulation time 133743091 ps
CPU time 2.44 seconds
Started Aug 25 06:52:23 AM UTC 24
Finished Aug 25 06:52:28 AM UTC 24
Peak memory 231760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191893098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 106.edn_genbits.2191893098
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/106.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/107.edn_alert.2713986758
Short name T695
Test name
Test status
Simulation time 29152811 ps
CPU time 1.76 seconds
Started Aug 25 06:52:24 AM UTC 24
Finished Aug 25 06:52:27 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713986758 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 107.edn_alert.2713986758
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/107.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/107.edn_genbits.7302077
Short name T693
Test name
Test status
Simulation time 58523777 ps
CPU time 1.83 seconds
Started Aug 25 06:52:24 AM UTC 24
Finished Aug 25 06:52:27 AM UTC 24
Peak memory 228332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7302077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_
genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 107.edn_genbits.7302077
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/107.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/108.edn_alert.313521873
Short name T692
Test name
Test status
Simulation time 62347456 ps
CPU time 1.65 seconds
Started Aug 25 06:52:24 AM UTC 24
Finished Aug 25 06:52:27 AM UTC 24
Peak memory 228388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313521873 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 108.edn_alert.313521873
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/108.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/108.edn_genbits.3805468286
Short name T708
Test name
Test status
Simulation time 46892225 ps
CPU time 2.32 seconds
Started Aug 25 06:52:24 AM UTC 24
Finished Aug 25 06:52:28 AM UTC 24
Peak memory 231768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805468286 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3805468286
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/108.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/109.edn_alert.156330797
Short name T694
Test name
Test status
Simulation time 117114914 ps
CPU time 1.6 seconds
Started Aug 25 06:52:24 AM UTC 24
Finished Aug 25 06:52:27 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156330797 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 109.edn_alert.156330797
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/109.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/109.edn_genbits.365912685
Short name T719
Test name
Test status
Simulation time 156986149 ps
CPU time 3.54 seconds
Started Aug 25 06:52:24 AM UTC 24
Finished Aug 25 06:52:29 AM UTC 24
Peak memory 231732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365912685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 109.edn_genbits.365912685
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/109.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/11.edn_alert.2631073368
Short name T93
Test name
Test status
Simulation time 355921607 ps
CPU time 1.45 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:50:18 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631073368 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 11.edn_alert.2631073368
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/11.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/11.edn_alert_test.3403944011
Short name T371
Test name
Test status
Simulation time 75407297 ps
CPU time 0.78 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:50:15 AM UTC 24
Peak memory 216912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403944011 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3403944011
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/11.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/11.edn_disable.1917834900
Short name T193
Test name
Test status
Simulation time 40564896 ps
CPU time 0.81 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:50:17 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917834900 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.1917834900
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/11.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/11.edn_smoke.513223354
Short name T303
Test name
Test status
Simulation time 50474520 ps
CPU time 0.9 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:50:17 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513223354 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 11.edn_smoke.513223354
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/11.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/11.edn_stress_all.1385519402
Short name T265
Test name
Test status
Simulation time 1304083695 ps
CPU time 3.59 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:50:20 AM UTC 24
Peak memory 229516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385519402 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1385519402
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/11.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/110.edn_alert.2576633928
Short name T697
Test name
Test status
Simulation time 148847958 ps
CPU time 1.56 seconds
Started Aug 25 06:52:24 AM UTC 24
Finished Aug 25 06:52:27 AM UTC 24
Peak memory 226356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576633928 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 110.edn_alert.2576633928
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/110.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/110.edn_genbits.2529444590
Short name T691
Test name
Test status
Simulation time 161346795 ps
CPU time 1.44 seconds
Started Aug 25 06:52:24 AM UTC 24
Finished Aug 25 06:52:27 AM UTC 24
Peak memory 228120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529444590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2529444590
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/110.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/111.edn_alert.3236998750
Short name T154
Test name
Test status
Simulation time 29160926 ps
CPU time 1.81 seconds
Started Aug 25 06:52:25 AM UTC 24
Finished Aug 25 06:52:28 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236998750 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 111.edn_alert.3236998750
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/111.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/111.edn_genbits.2120169171
Short name T701
Test name
Test status
Simulation time 374337785 ps
CPU time 1.7 seconds
Started Aug 25 06:52:24 AM UTC 24
Finished Aug 25 06:52:28 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120169171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 111.edn_genbits.2120169171
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/111.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/112.edn_alert.4237116008
Short name T704
Test name
Test status
Simulation time 44058937 ps
CPU time 1.66 seconds
Started Aug 25 06:52:25 AM UTC 24
Finished Aug 25 06:52:28 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237116008 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 112.edn_alert.4237116008
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/112.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/112.edn_genbits.1055283726
Short name T698
Test name
Test status
Simulation time 65553571 ps
CPU time 1.5 seconds
Started Aug 25 06:52:25 AM UTC 24
Finished Aug 25 06:52:27 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055283726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1055283726
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/112.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/113.edn_alert.3639555677
Short name T706
Test name
Test status
Simulation time 25557416 ps
CPU time 1.64 seconds
Started Aug 25 06:52:25 AM UTC 24
Finished Aug 25 06:52:28 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639555677 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 113.edn_alert.3639555677
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/113.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/113.edn_genbits.2443394908
Short name T703
Test name
Test status
Simulation time 23827699 ps
CPU time 1.62 seconds
Started Aug 25 06:52:25 AM UTC 24
Finished Aug 25 06:52:28 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443394908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 113.edn_genbits.2443394908
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/113.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/114.edn_alert.1300995609
Short name T709
Test name
Test status
Simulation time 309829345 ps
CPU time 1.82 seconds
Started Aug 25 06:52:25 AM UTC 24
Finished Aug 25 06:52:28 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300995609 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 114.edn_alert.1300995609
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/114.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/115.edn_alert.231505607
Short name T713
Test name
Test status
Simulation time 44042589 ps
CPU time 1.44 seconds
Started Aug 25 06:52:26 AM UTC 24
Finished Aug 25 06:52:28 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231505607 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 115.edn_alert.231505607
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/115.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/115.edn_genbits.1688855030
Short name T726
Test name
Test status
Simulation time 420758400 ps
CPU time 2.9 seconds
Started Aug 25 06:52:26 AM UTC 24
Finished Aug 25 06:52:30 AM UTC 24
Peak memory 231404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688855030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1688855030
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/115.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/116.edn_alert.3109283166
Short name T716
Test name
Test status
Simulation time 31987051 ps
CPU time 1.71 seconds
Started Aug 25 06:52:26 AM UTC 24
Finished Aug 25 06:52:29 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109283166 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 116.edn_alert.3109283166
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/116.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/116.edn_genbits.2508580460
Short name T714
Test name
Test status
Simulation time 83513306 ps
CPU time 1.59 seconds
Started Aug 25 06:52:26 AM UTC 24
Finished Aug 25 06:52:29 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508580460 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 116.edn_genbits.2508580460
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/116.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/117.edn_alert.1330030747
Short name T718
Test name
Test status
Simulation time 46027755 ps
CPU time 1.72 seconds
Started Aug 25 06:52:26 AM UTC 24
Finished Aug 25 06:52:29 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330030747 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 117.edn_alert.1330030747
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/117.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/117.edn_genbits.2692027473
Short name T720
Test name
Test status
Simulation time 54663239 ps
CPU time 1.85 seconds
Started Aug 25 06:52:26 AM UTC 24
Finished Aug 25 06:52:29 AM UTC 24
Peak memory 228544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692027473 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 117.edn_genbits.2692027473
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/117.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/118.edn_alert.3214442689
Short name T715
Test name
Test status
Simulation time 109318552 ps
CPU time 1.41 seconds
Started Aug 25 06:52:26 AM UTC 24
Finished Aug 25 06:52:29 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214442689 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 118.edn_alert.3214442689
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/118.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/118.edn_genbits.1533055855
Short name T723
Test name
Test status
Simulation time 52481298 ps
CPU time 2.02 seconds
Started Aug 25 06:52:26 AM UTC 24
Finished Aug 25 06:52:29 AM UTC 24
Peak memory 229520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533055855 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1533055855
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/118.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/119.edn_alert.521746451
Short name T717
Test name
Test status
Simulation time 189679784 ps
CPU time 1.49 seconds
Started Aug 25 06:52:26 AM UTC 24
Finished Aug 25 06:52:29 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521746451 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 119.edn_alert.521746451
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/119.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/119.edn_genbits.854692555
Short name T721
Test name
Test status
Simulation time 36185638 ps
CPU time 1.69 seconds
Started Aug 25 06:52:26 AM UTC 24
Finished Aug 25 06:52:29 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854692555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 119.edn_genbits.854692555
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/119.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/12.edn_alert.3363512611
Short name T127
Test name
Test status
Simulation time 28192470 ps
CPU time 1.19 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:50:15 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363512611 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 12.edn_alert.3363512611
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/12.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/12.edn_alert_test.2250667125
Short name T374
Test name
Test status
Simulation time 23726891 ps
CPU time 0.86 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:50:18 AM UTC 24
Peak memory 226524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250667125 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2250667125
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/12.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/12.edn_disable_auto_req_mode.2005850780
Short name T114
Test name
Test status
Simulation time 101272577 ps
CPU time 1.35 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:50:18 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005850780 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable_auto_req_mode.2005850780
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/12.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/12.edn_err.3035365655
Short name T229
Test name
Test status
Simulation time 21634617 ps
CPU time 0.94 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:50:18 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035365655 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 12.edn_err.3035365655
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/12.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/12.edn_genbits.2932616164
Short name T50
Test name
Test status
Simulation time 75942876 ps
CPU time 1.19 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:50:15 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932616164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2932616164
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/12.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/12.edn_smoke.1657514602
Short name T372
Test name
Test status
Simulation time 21807843 ps
CPU time 0.89 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:50:15 AM UTC 24
Peak memory 226072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657514602 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 12.edn_smoke.1657514602
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/12.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/12.edn_stress_all.2667606654
Short name T107
Test name
Test status
Simulation time 548601113 ps
CPU time 2.68 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:50:17 AM UTC 24
Peak memory 231580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667606654 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2667606654
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/12.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/12.edn_stress_all_with_rand_reset.3644962531
Short name T241
Test name
Test status
Simulation time 3874973764 ps
CPU time 80.01 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:51:35 AM UTC 24
Peak memory 229580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3644962531 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all
_with_rand_reset.3644962531
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/12.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/120.edn_alert.2346088404
Short name T731
Test name
Test status
Simulation time 27620691 ps
CPU time 1.81 seconds
Started Aug 25 06:52:28 AM UTC 24
Finished Aug 25 06:52:31 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346088404 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 120.edn_alert.2346088404
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/120.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/120.edn_genbits.2278597206
Short name T722
Test name
Test status
Simulation time 94195297 ps
CPU time 1.72 seconds
Started Aug 25 06:52:26 AM UTC 24
Finished Aug 25 06:52:29 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278597206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 120.edn_genbits.2278597206
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/120.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/121.edn_alert.2645509223
Short name T727
Test name
Test status
Simulation time 25040850 ps
CPU time 1.53 seconds
Started Aug 25 06:52:28 AM UTC 24
Finished Aug 25 06:52:30 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645509223 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 121.edn_alert.2645509223
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/121.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/121.edn_genbits.2187501656
Short name T728
Test name
Test status
Simulation time 34255620 ps
CPU time 1.69 seconds
Started Aug 25 06:52:28 AM UTC 24
Finished Aug 25 06:52:30 AM UTC 24
Peak memory 230604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187501656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 121.edn_genbits.2187501656
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/121.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/122.edn_alert.1147173354
Short name T650
Test name
Test status
Simulation time 28602555 ps
CPU time 1.69 seconds
Started Aug 25 06:52:28 AM UTC 24
Finished Aug 25 06:52:31 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147173354 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 122.edn_alert.1147173354
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/122.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/122.edn_genbits.2742547442
Short name T659
Test name
Test status
Simulation time 45885702 ps
CPU time 1.83 seconds
Started Aug 25 06:52:28 AM UTC 24
Finished Aug 25 06:52:31 AM UTC 24
Peak memory 230604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742547442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 122.edn_genbits.2742547442
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/122.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/123.edn_alert.3134931315
Short name T655
Test name
Test status
Simulation time 32891583 ps
CPU time 1.6 seconds
Started Aug 25 06:52:28 AM UTC 24
Finished Aug 25 06:52:31 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134931315 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 123.edn_alert.3134931315
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/123.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/123.edn_genbits.3703719953
Short name T679
Test name
Test status
Simulation time 121886661 ps
CPU time 1.77 seconds
Started Aug 25 06:52:28 AM UTC 24
Finished Aug 25 06:52:31 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703719953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 123.edn_genbits.3703719953
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/123.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/124.edn_alert.1416190105
Short name T733
Test name
Test status
Simulation time 48234483 ps
CPU time 1.74 seconds
Started Aug 25 06:52:28 AM UTC 24
Finished Aug 25 06:52:31 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416190105 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 124.edn_alert.1416190105
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/124.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/124.edn_genbits.3674859825
Short name T730
Test name
Test status
Simulation time 59650046 ps
CPU time 1.46 seconds
Started Aug 25 06:52:28 AM UTC 24
Finished Aug 25 06:52:31 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674859825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3674859825
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/124.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/125.edn_alert.4195934910
Short name T729
Test name
Test status
Simulation time 148395698 ps
CPU time 1.29 seconds
Started Aug 25 06:52:28 AM UTC 24
Finished Aug 25 06:52:31 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195934910 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 125.edn_alert.4195934910
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/125.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/125.edn_genbits.4055992853
Short name T735
Test name
Test status
Simulation time 84128941 ps
CPU time 2.08 seconds
Started Aug 25 06:52:28 AM UTC 24
Finished Aug 25 06:52:31 AM UTC 24
Peak memory 231580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055992853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 125.edn_genbits.4055992853
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/125.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/126.edn_alert.1543905913
Short name T683
Test name
Test status
Simulation time 31126227 ps
CPU time 1.54 seconds
Started Aug 25 06:52:28 AM UTC 24
Finished Aug 25 06:52:31 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543905913 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 126.edn_alert.1543905913
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/126.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/126.edn_genbits.1077426456
Short name T734
Test name
Test status
Simulation time 106130329 ps
CPU time 1.92 seconds
Started Aug 25 06:52:28 AM UTC 24
Finished Aug 25 06:52:31 AM UTC 24
Peak memory 228356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077426456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1077426456
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/126.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/127.edn_alert.1139794502
Short name T737
Test name
Test status
Simulation time 41079068 ps
CPU time 1.17 seconds
Started Aug 25 06:52:29 AM UTC 24
Finished Aug 25 06:52:32 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139794502 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 127.edn_alert.1139794502
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/127.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/127.edn_genbits.3791545899
Short name T736
Test name
Test status
Simulation time 251565409 ps
CPU time 2.05 seconds
Started Aug 25 06:52:28 AM UTC 24
Finished Aug 25 06:52:31 AM UTC 24
Peak memory 231772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791545899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 127.edn_genbits.3791545899
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/127.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/128.edn_genbits.1796406136
Short name T792
Test name
Test status
Simulation time 36765516 ps
CPU time 1.03 seconds
Started Aug 25 06:52:29 AM UTC 24
Finished Aug 25 06:53:02 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796406136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 128.edn_genbits.1796406136
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/128.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/129.edn_alert.951354104
Short name T749
Test name
Test status
Simulation time 48685009 ps
CPU time 1.49 seconds
Started Aug 25 06:52:29 AM UTC 24
Finished Aug 25 06:52:55 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951354104 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 129.edn_alert.951354104
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/129.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/129.edn_genbits.475151818
Short name T746
Test name
Test status
Simulation time 41339843 ps
CPU time 1.43 seconds
Started Aug 25 06:52:29 AM UTC 24
Finished Aug 25 06:52:55 AM UTC 24
Peak memory 228472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475151818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 129.edn_genbits.475151818
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/129.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/13.edn_alert.215187754
Short name T156
Test name
Test status
Simulation time 37913211 ps
CPU time 1.19 seconds
Started Aug 25 06:50:06 AM UTC 24
Finished Aug 25 06:50:18 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215187754 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 13.edn_alert.215187754
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/13.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/13.edn_alert_test.3827748651
Short name T377
Test name
Test status
Simulation time 39224490 ps
CPU time 0.91 seconds
Started Aug 25 06:50:06 AM UTC 24
Finished Aug 25 06:50:18 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827748651 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3827748651
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/13.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/13.edn_disable.1305897633
Short name T84
Test name
Test status
Simulation time 18221740 ps
CPU time 0.94 seconds
Started Aug 25 06:50:06 AM UTC 24
Finished Aug 25 06:50:18 AM UTC 24
Peak memory 226368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305897633 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1305897633
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/13.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/13.edn_err.1954479458
Short name T323
Test name
Test status
Simulation time 27898149 ps
CPU time 0.97 seconds
Started Aug 25 06:50:06 AM UTC 24
Finished Aug 25 06:50:18 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954479458 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 13.edn_err.1954479458
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/13.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/13.edn_intr.3022711333
Short name T133
Test name
Test status
Simulation time 61592565 ps
CPU time 1.05 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:50:18 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022711333 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 13.edn_intr.3022711333
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/13.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/13.edn_smoke.2376492777
Short name T375
Test name
Test status
Simulation time 24463740 ps
CPU time 0.84 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:50:18 AM UTC 24
Peak memory 226248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376492777 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 13.edn_smoke.2376492777
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/13.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/13.edn_stress_all.1312458638
Short name T379
Test name
Test status
Simulation time 66749735 ps
CPU time 1.52 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:50:19 AM UTC 24
Peak memory 226672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312458638 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1312458638
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/13.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/13.edn_stress_all_with_rand_reset.3195276881
Short name T240
Test name
Test status
Simulation time 13578121955 ps
CPU time 71.7 seconds
Started Aug 25 06:50:05 AM UTC 24
Finished Aug 25 06:51:29 AM UTC 24
Peak memory 229936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3195276881 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all
_with_rand_reset.3195276881
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/13.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/130.edn_genbits.1255035789
Short name T738
Test name
Test status
Simulation time 29878435 ps
CPU time 1.08 seconds
Started Aug 25 06:52:29 AM UTC 24
Finished Aug 25 06:52:35 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255035789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1255035789
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/130.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/131.edn_alert.181238033
Short name T745
Test name
Test status
Simulation time 28505563 ps
CPU time 1.22 seconds
Started Aug 25 06:52:30 AM UTC 24
Finished Aug 25 06:52:55 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181238033 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 131.edn_alert.181238033
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/131.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/131.edn_genbits.4225600165
Short name T751
Test name
Test status
Simulation time 69713005 ps
CPU time 1.54 seconds
Started Aug 25 06:52:30 AM UTC 24
Finished Aug 25 06:52:55 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225600165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 131.edn_genbits.4225600165
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/131.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/132.edn_alert.2945127675
Short name T748
Test name
Test status
Simulation time 78514722 ps
CPU time 1.15 seconds
Started Aug 25 06:52:30 AM UTC 24
Finished Aug 25 06:52:55 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945127675 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 132.edn_alert.2945127675
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/132.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/132.edn_genbits.3171557641
Short name T747
Test name
Test status
Simulation time 141554463 ps
CPU time 1.23 seconds
Started Aug 25 06:52:30 AM UTC 24
Finished Aug 25 06:52:55 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171557641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3171557641
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/132.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/133.edn_alert.315075634
Short name T750
Test name
Test status
Simulation time 44550579 ps
CPU time 1.3 seconds
Started Aug 25 06:52:30 AM UTC 24
Finished Aug 25 06:52:55 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315075634 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 133.edn_alert.315075634
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/133.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/133.edn_genbits.392523783
Short name T354
Test name
Test status
Simulation time 175754752 ps
CPU time 2.53 seconds
Started Aug 25 06:52:30 AM UTC 24
Finished Aug 25 06:52:56 AM UTC 24
Peak memory 231520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392523783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 133.edn_genbits.392523783
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/133.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/134.edn_alert.2085836690
Short name T753
Test name
Test status
Simulation time 29669937 ps
CPU time 1.48 seconds
Started Aug 25 06:52:30 AM UTC 24
Finished Aug 25 06:52:55 AM UTC 24
Peak memory 226356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085836690 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 134.edn_alert.2085836690
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/134.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/134.edn_genbits.2388411350
Short name T765
Test name
Test status
Simulation time 105038969 ps
CPU time 2.22 seconds
Started Aug 25 06:52:30 AM UTC 24
Finished Aug 25 06:52:56 AM UTC 24
Peak memory 231772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388411350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2388411350
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/134.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/135.edn_alert.1868981816
Short name T916
Test name
Test status
Simulation time 75202524 ps
CPU time 1.2 seconds
Started Aug 25 06:52:30 AM UTC 24
Finished Aug 25 06:53:40 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868981816 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 135.edn_alert.1868981816
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/135.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/135.edn_genbits.1097524764
Short name T797
Test name
Test status
Simulation time 45943472 ps
CPU time 1.49 seconds
Started Aug 25 06:52:30 AM UTC 24
Finished Aug 25 06:53:06 AM UTC 24
Peak memory 230556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097524764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 135.edn_genbits.1097524764
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/135.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/136.edn_alert.2444867438
Short name T762
Test name
Test status
Simulation time 26983301 ps
CPU time 1.81 seconds
Started Aug 25 06:52:30 AM UTC 24
Finished Aug 25 06:52:56 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444867438 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 136.edn_alert.2444867438
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/136.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/136.edn_genbits.1895877243
Short name T752
Test name
Test status
Simulation time 64552348 ps
CPU time 1.36 seconds
Started Aug 25 06:52:30 AM UTC 24
Finished Aug 25 06:52:55 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895877243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 136.edn_genbits.1895877243
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/136.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/137.edn_alert.1697330819
Short name T756
Test name
Test status
Simulation time 22462607 ps
CPU time 1.43 seconds
Started Aug 25 06:52:30 AM UTC 24
Finished Aug 25 06:52:56 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697330819 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 137.edn_alert.1697330819
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/137.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/137.edn_genbits.1917106185
Short name T760
Test name
Test status
Simulation time 46386511 ps
CPU time 1.51 seconds
Started Aug 25 06:52:30 AM UTC 24
Finished Aug 25 06:52:56 AM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917106185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1917106185
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/137.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/138.edn_alert.804713884
Short name T786
Test name
Test status
Simulation time 89651034 ps
CPU time 1.36 seconds
Started Aug 25 06:52:31 AM UTC 24
Finished Aug 25 06:53:01 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804713884 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 138.edn_alert.804713884
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/138.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/138.edn_genbits.62034177
Short name T757
Test name
Test status
Simulation time 54626539 ps
CPU time 1.37 seconds
Started Aug 25 06:52:30 AM UTC 24
Finished Aug 25 06:52:56 AM UTC 24
Peak memory 230608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62034177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 138.edn_genbits.62034177
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/138.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/139.edn_alert.4238126161
Short name T784
Test name
Test status
Simulation time 46567536 ps
CPU time 1.18 seconds
Started Aug 25 06:52:31 AM UTC 24
Finished Aug 25 06:53:01 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238126161 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 139.edn_alert.4238126161
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/139.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/139.edn_genbits.493041674
Short name T794
Test name
Test status
Simulation time 332252495 ps
CPU time 3 seconds
Started Aug 25 06:52:31 AM UTC 24
Finished Aug 25 06:53:03 AM UTC 24
Peak memory 231532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493041674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 139.edn_genbits.493041674
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/139.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/14.edn_alert.3735919754
Short name T185
Test name
Test status
Simulation time 330881142 ps
CPU time 1.44 seconds
Started Aug 25 06:50:06 AM UTC 24
Finished Aug 25 06:50:22 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735919754 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 14.edn_alert.3735919754
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/14.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/14.edn_alert_test.3793198719
Short name T376
Test name
Test status
Simulation time 45236680 ps
CPU time 0.8 seconds
Started Aug 25 06:50:07 AM UTC 24
Finished Aug 25 06:50:18 AM UTC 24
Peak memory 216360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793198719 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3793198719
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/14.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/14.edn_disable.3216575097
Short name T327
Test name
Test status
Simulation time 34969872 ps
CPU time 0.9 seconds
Started Aug 25 06:50:06 AM UTC 24
Finished Aug 25 06:50:21 AM UTC 24
Peak memory 216128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216575097 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3216575097
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/14.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/14.edn_disable_auto_req_mode.2179160196
Short name T141
Test name
Test status
Simulation time 55817082 ps
CPU time 0.93 seconds
Started Aug 25 06:50:07 AM UTC 24
Finished Aug 25 06:50:18 AM UTC 24
Peak memory 225988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179160196 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable_auto_req_mode.2179160196
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/14.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/14.edn_err.3429512656
Short name T162
Test name
Test status
Simulation time 88382787 ps
CPU time 1.16 seconds
Started Aug 25 06:50:06 AM UTC 24
Finished Aug 25 06:50:22 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429512656 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 14.edn_err.3429512656
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/14.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/14.edn_genbits.2357252356
Short name T312
Test name
Test status
Simulation time 107354678 ps
CPU time 1.18 seconds
Started Aug 25 06:50:06 AM UTC 24
Finished Aug 25 06:50:22 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357252356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2357252356
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/14.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/14.edn_intr.1027759744
Short name T391
Test name
Test status
Simulation time 23507534 ps
CPU time 1.08 seconds
Started Aug 25 06:50:06 AM UTC 24
Finished Aug 25 06:50:22 AM UTC 24
Peak memory 226292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027759744 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 14.edn_intr.1027759744
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/14.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/14.edn_smoke.445499912
Short name T382
Test name
Test status
Simulation time 23733283 ps
CPU time 0.83 seconds
Started Aug 25 06:50:06 AM UTC 24
Finished Aug 25 06:50:21 AM UTC 24
Peak memory 216016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445499912 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 14.edn_smoke.445499912
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/14.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/14.edn_stress_all.3128339631
Short name T393
Test name
Test status
Simulation time 143180006 ps
CPU time 1.88 seconds
Started Aug 25 06:50:06 AM UTC 24
Finished Aug 25 06:50:22 AM UTC 24
Peak memory 230396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128339631 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3128339631
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/14.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/140.edn_alert.2825800905
Short name T770
Test name
Test status
Simulation time 88990570 ps
CPU time 1.36 seconds
Started Aug 25 06:52:31 AM UTC 24
Finished Aug 25 06:53:00 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825800905 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 140.edn_alert.2825800905
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/140.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/140.edn_genbits.2217138362
Short name T767
Test name
Test status
Simulation time 35483712 ps
CPU time 1.39 seconds
Started Aug 25 06:52:31 AM UTC 24
Finished Aug 25 06:52:57 AM UTC 24
Peak memory 228560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217138362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2217138362
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/140.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/141.edn_alert.854429000
Short name T769
Test name
Test status
Simulation time 69588669 ps
CPU time 1.06 seconds
Started Aug 25 06:52:31 AM UTC 24
Finished Aug 25 06:53:00 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854429000 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 141.edn_alert.854429000
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/141.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/141.edn_genbits.666950798
Short name T768
Test name
Test status
Simulation time 66370699 ps
CPU time 1.18 seconds
Started Aug 25 06:52:31 AM UTC 24
Finished Aug 25 06:52:57 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666950798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 141.edn_genbits.666950798
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/141.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/142.edn_alert.3879380879
Short name T775
Test name
Test status
Simulation time 28814815 ps
CPU time 1.26 seconds
Started Aug 25 06:52:32 AM UTC 24
Finished Aug 25 06:53:00 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879380879 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 142.edn_alert.3879380879
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/142.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/142.edn_genbits.4269294952
Short name T793
Test name
Test status
Simulation time 130696820 ps
CPU time 2.81 seconds
Started Aug 25 06:52:32 AM UTC 24
Finished Aug 25 06:53:02 AM UTC 24
Peak memory 231760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269294952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 142.edn_genbits.4269294952
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/142.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/143.edn_alert.3671566850
Short name T782
Test name
Test status
Simulation time 57880625 ps
CPU time 1.7 seconds
Started Aug 25 06:52:32 AM UTC 24
Finished Aug 25 06:53:01 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671566850 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 143.edn_alert.3671566850
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/143.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/143.edn_genbits.142570707
Short name T779
Test name
Test status
Simulation time 83099649 ps
CPU time 1.66 seconds
Started Aug 25 06:52:32 AM UTC 24
Finished Aug 25 06:53:01 AM UTC 24
Peak memory 230420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142570707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 143.edn_genbits.142570707
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/143.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/145.edn_alert.796337830
Short name T778
Test name
Test status
Simulation time 72889884 ps
CPU time 1.23 seconds
Started Aug 25 06:52:32 AM UTC 24
Finished Aug 25 06:53:01 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796337830 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 145.edn_alert.796337830
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/145.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/145.edn_genbits.4231093416
Short name T771
Test name
Test status
Simulation time 89034498 ps
CPU time 1.11 seconds
Started Aug 25 06:52:32 AM UTC 24
Finished Aug 25 06:53:00 AM UTC 24
Peak memory 228340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231093416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 145.edn_genbits.4231093416
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/145.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/146.edn_alert.3911569480
Short name T785
Test name
Test status
Simulation time 82216793 ps
CPU time 1.39 seconds
Started Aug 25 06:52:32 AM UTC 24
Finished Aug 25 06:53:01 AM UTC 24
Peak memory 228224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911569480 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 146.edn_alert.3911569480
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/146.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/146.edn_genbits.2587632406
Short name T872
Test name
Test status
Simulation time 38885698 ps
CPU time 1.52 seconds
Started Aug 25 06:52:32 AM UTC 24
Finished Aug 25 06:53:32 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587632406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2587632406
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/146.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/147.edn_alert.2800467286
Short name T783
Test name
Test status
Simulation time 247316651 ps
CPU time 1.38 seconds
Started Aug 25 06:52:32 AM UTC 24
Finished Aug 25 06:53:01 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800467286 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 147.edn_alert.2800467286
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/147.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/147.edn_genbits.3553413938
Short name T787
Test name
Test status
Simulation time 220103850 ps
CPU time 1.58 seconds
Started Aug 25 06:52:32 AM UTC 24
Finished Aug 25 06:53:01 AM UTC 24
Peak memory 230524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553413938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3553413938
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/147.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/148.edn_genbits.2080562357
Short name T828
Test name
Test status
Simulation time 86956955 ps
CPU time 1.48 seconds
Started Aug 25 06:52:32 AM UTC 24
Finished Aug 25 06:53:28 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080562357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2080562357
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/148.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/149.edn_alert.3611043128
Short name T795
Test name
Test status
Simulation time 23726392 ps
CPU time 1 seconds
Started Aug 25 06:52:32 AM UTC 24
Finished Aug 25 06:53:05 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611043128 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 149.edn_alert.3611043128
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/149.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/15.edn_alert_test.2426453833
Short name T389
Test name
Test status
Simulation time 16039244 ps
CPU time 1.06 seconds
Started Aug 25 06:50:09 AM UTC 24
Finished Aug 25 06:50:22 AM UTC 24
Peak memory 216688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426453833 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2426453833
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/15.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/15.edn_disable.2657904988
Short name T87
Test name
Test status
Simulation time 12067703 ps
CPU time 1 seconds
Started Aug 25 06:50:09 AM UTC 24
Finished Aug 25 06:50:22 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657904988 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.2657904988
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/15.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/15.edn_disable_auto_req_mode.3680128239
Short name T390
Test name
Test status
Simulation time 28595902 ps
CPU time 1.17 seconds
Started Aug 25 06:50:09 AM UTC 24
Finished Aug 25 06:50:22 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680128239 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable_auto_req_mode.3680128239
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/15.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/15.edn_err.475737786
Short name T197
Test name
Test status
Simulation time 23442294 ps
CPU time 0.81 seconds
Started Aug 25 06:50:09 AM UTC 24
Finished Aug 25 06:50:21 AM UTC 24
Peak memory 228352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475737786 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 15.edn_err.475737786
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/15.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/15.edn_genbits.3672256912
Short name T378
Test name
Test status
Simulation time 38118217 ps
CPU time 1.09 seconds
Started Aug 25 06:50:09 AM UTC 24
Finished Aug 25 06:50:18 AM UTC 24
Peak memory 228352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672256912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_genbits.3672256912
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/15.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/15.edn_smoke.134707618
Short name T108
Test name
Test status
Simulation time 119877226 ps
CPU time 1.01 seconds
Started Aug 25 06:50:08 AM UTC 24
Finished Aug 25 06:50:18 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134707618 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 15.edn_smoke.134707618
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/15.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/15.edn_stress_all.4281165974
Short name T249
Test name
Test status
Simulation time 256853968 ps
CPU time 3.26 seconds
Started Aug 25 06:50:09 AM UTC 24
Finished Aug 25 06:50:20 AM UTC 24
Peak memory 229520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281165974 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.4281165974
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/15.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/150.edn_alert.3412885426
Short name T759
Test name
Test status
Simulation time 29444640 ps
CPU time 1.56 seconds
Started Aug 25 06:52:33 AM UTC 24
Finished Aug 25 06:52:56 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412885426 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 150.edn_alert.3412885426
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/150.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/151.edn_alert.2634246410
Short name T755
Test name
Test status
Simulation time 122845592 ps
CPU time 1.28 seconds
Started Aug 25 06:52:33 AM UTC 24
Finished Aug 25 06:52:56 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634246410 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 151.edn_alert.2634246410
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/151.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/151.edn_genbits.549982068
Short name T761
Test name
Test status
Simulation time 71332580 ps
CPU time 1.77 seconds
Started Aug 25 06:52:33 AM UTC 24
Finished Aug 25 06:52:56 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549982068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 151.edn_genbits.549982068
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/151.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/152.edn_alert.2045375943
Short name T754
Test name
Test status
Simulation time 77797676 ps
CPU time 1.14 seconds
Started Aug 25 06:52:33 AM UTC 24
Finished Aug 25 06:52:56 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045375943 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 152.edn_alert.2045375943
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/152.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/152.edn_genbits.4116873955
Short name T758
Test name
Test status
Simulation time 47689139 ps
CPU time 1.41 seconds
Started Aug 25 06:52:33 AM UTC 24
Finished Aug 25 06:52:56 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116873955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 152.edn_genbits.4116873955
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/152.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/153.edn_alert.3274006124
Short name T832
Test name
Test status
Simulation time 72219144 ps
CPU time 1.41 seconds
Started Aug 25 06:52:35 AM UTC 24
Finished Aug 25 06:53:29 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274006124 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 153.edn_alert.3274006124
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/153.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/153.edn_genbits.2510877883
Short name T764
Test name
Test status
Simulation time 121675298 ps
CPU time 1.65 seconds
Started Aug 25 06:52:33 AM UTC 24
Finished Aug 25 06:52:56 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510877883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2510877883
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/153.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/154.edn_alert.224902826
Short name T766
Test name
Test status
Simulation time 42579837 ps
CPU time 1.13 seconds
Started Aug 25 06:52:45 AM UTC 24
Finished Aug 25 06:52:57 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224902826 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 154.edn_alert.224902826
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/154.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/154.edn_genbits.2909252938
Short name T789
Test name
Test status
Simulation time 34071809 ps
CPU time 1.48 seconds
Started Aug 25 06:52:38 AM UTC 24
Finished Aug 25 06:53:01 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909252938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2909252938
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/154.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/155.edn_alert.2746036898
Short name T774
Test name
Test status
Simulation time 29783704 ps
CPU time 1.17 seconds
Started Aug 25 06:52:48 AM UTC 24
Finished Aug 25 06:53:00 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746036898 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 155.edn_alert.2746036898
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/155.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/155.edn_genbits.4099516790
Short name T833
Test name
Test status
Simulation time 63387142 ps
CPU time 1.39 seconds
Started Aug 25 06:52:46 AM UTC 24
Finished Aug 25 06:53:29 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099516790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 155.edn_genbits.4099516790
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/155.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/156.edn_alert.3758542724
Short name T763
Test name
Test status
Simulation time 85179175 ps
CPU time 1.12 seconds
Started Aug 25 06:52:51 AM UTC 24
Finished Aug 25 06:52:56 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758542724 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 156.edn_alert.3758542724
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/156.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/156.edn_genbits.3979780798
Short name T906
Test name
Test status
Simulation time 57277295 ps
CPU time 1.48 seconds
Started Aug 25 06:52:50 AM UTC 24
Finished Aug 25 06:53:36 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979780798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3979780798
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/156.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/157.edn_alert.889725234
Short name T873
Test name
Test status
Simulation time 219450408 ps
CPU time 1.68 seconds
Started Aug 25 06:52:56 AM UTC 24
Finished Aug 25 06:53:32 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889725234 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 157.edn_alert.889725234
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/157.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/157.edn_genbits.2856963970
Short name T342
Test name
Test status
Simulation time 186197188 ps
CPU time 2.43 seconds
Started Aug 25 06:52:56 AM UTC 24
Finished Aug 25 06:53:30 AM UTC 24
Peak memory 231508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856963970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 157.edn_genbits.2856963970
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/157.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/158.edn_alert.3067923716
Short name T865
Test name
Test status
Simulation time 39662540 ps
CPU time 1.12 seconds
Started Aug 25 06:52:56 AM UTC 24
Finished Aug 25 06:53:32 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067923716 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 158.edn_alert.3067923716
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/158.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/158.edn_genbits.2094480042
Short name T840
Test name
Test status
Simulation time 58118595 ps
CPU time 1.09 seconds
Started Aug 25 06:52:56 AM UTC 24
Finished Aug 25 06:53:29 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094480042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2094480042
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/158.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/159.edn_alert.2277969609
Short name T801
Test name
Test status
Simulation time 83882173 ps
CPU time 1.12 seconds
Started Aug 25 06:52:56 AM UTC 24
Finished Aug 25 06:53:15 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277969609 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 159.edn_alert.2277969609
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/159.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/159.edn_genbits.468709946
Short name T871
Test name
Test status
Simulation time 45936558 ps
CPU time 1.38 seconds
Started Aug 25 06:52:56 AM UTC 24
Finished Aug 25 06:53:32 AM UTC 24
Peak memory 228344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468709946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 159.edn_genbits.468709946
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/159.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/16.edn_alert_test.3797135630
Short name T299
Test name
Test status
Simulation time 16751190 ps
CPU time 0.77 seconds
Started Aug 25 06:50:12 AM UTC 24
Finished Aug 25 06:50:17 AM UTC 24
Peak memory 226868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797135630 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3797135630
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/16.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/16.edn_disable.4089576245
Short name T95
Test name
Test status
Simulation time 29183697 ps
CPU time 0.82 seconds
Started Aug 25 06:50:12 AM UTC 24
Finished Aug 25 06:50:17 AM UTC 24
Peak memory 226292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089576245 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.4089576245
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/16.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/16.edn_disable_auto_req_mode.70804810
Short name T302
Test name
Test status
Simulation time 41567519 ps
CPU time 0.94 seconds
Started Aug 25 06:50:12 AM UTC 24
Finished Aug 25 06:50:17 AM UTC 24
Peak memory 226248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70804810 -assert nopostproc +UVM_TESTNAME=edn_disab
le_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable_auto_req_mode.70804810
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/16.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/16.edn_err.2368900340
Short name T159
Test name
Test status
Simulation time 99574454 ps
CPU time 0.85 seconds
Started Aug 25 06:50:12 AM UTC 24
Finished Aug 25 06:50:17 AM UTC 24
Peak memory 244396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368900340 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 16.edn_err.2368900340
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/16.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/16.edn_genbits.1048724748
Short name T89
Test name
Test status
Simulation time 20559301 ps
CPU time 1.4 seconds
Started Aug 25 06:50:09 AM UTC 24
Finished Aug 25 06:50:22 AM UTC 24
Peak memory 228212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048724748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_genbits.1048724748
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/16.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/16.edn_intr.3102214402
Short name T479
Test name
Test status
Simulation time 33895787 ps
CPU time 1.31 seconds
Started Aug 25 06:50:10 AM UTC 24
Finished Aug 25 06:51:30 AM UTC 24
Peak memory 237412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102214402 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 16.edn_intr.3102214402
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/16.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/16.edn_smoke.4160215330
Short name T394
Test name
Test status
Simulation time 16212475 ps
CPU time 1.03 seconds
Started Aug 25 06:50:09 AM UTC 24
Finished Aug 25 06:50:25 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160215330 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 16.edn_smoke.4160215330
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/16.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/16.edn_stress_all.2033892726
Short name T383
Test name
Test status
Simulation time 82643262 ps
CPU time 1.82 seconds
Started Aug 25 06:50:09 AM UTC 24
Finished Aug 25 06:50:22 AM UTC 24
Peak memory 228004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033892726 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2033892726
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/16.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/16.edn_stress_all_with_rand_reset.3508950446
Short name T648
Test name
Test status
Simulation time 10075114214 ps
CPU time 119.93 seconds
Started Aug 25 06:50:09 AM UTC 24
Finished Aug 25 06:52:22 AM UTC 24
Peak memory 229652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3508950446 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all
_with_rand_reset.3508950446
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/16.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/160.edn_alert.3472177411
Short name T802
Test name
Test status
Simulation time 44524626 ps
CPU time 1.19 seconds
Started Aug 25 06:52:56 AM UTC 24
Finished Aug 25 06:53:15 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472177411 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 160.edn_alert.3472177411
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/160.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/161.edn_alert.3571431904
Short name T781
Test name
Test status
Simulation time 39892723 ps
CPU time 1.28 seconds
Started Aug 25 06:52:57 AM UTC 24
Finished Aug 25 06:53:01 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571431904 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 161.edn_alert.3571431904
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/161.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/161.edn_genbits.1789881127
Short name T816
Test name
Test status
Simulation time 118398505 ps
CPU time 1.48 seconds
Started Aug 25 06:52:56 AM UTC 24
Finished Aug 25 06:53:26 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789881127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1789881127
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/161.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/162.edn_alert.3705560465
Short name T777
Test name
Test status
Simulation time 71404510 ps
CPU time 1.11 seconds
Started Aug 25 06:52:57 AM UTC 24
Finished Aug 25 06:53:01 AM UTC 24
Peak memory 230348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705560465 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 162.edn_alert.3705560465
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/162.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/162.edn_genbits.4146710099
Short name T780
Test name
Test status
Simulation time 82823684 ps
CPU time 1.32 seconds
Started Aug 25 06:52:57 AM UTC 24
Finished Aug 25 06:53:01 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146710099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 162.edn_genbits.4146710099
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/162.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/163.edn_alert.1908282759
Short name T776
Test name
Test status
Simulation time 43011712 ps
CPU time 1.05 seconds
Started Aug 25 06:52:57 AM UTC 24
Finished Aug 25 06:53:01 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908282759 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 163.edn_alert.1908282759
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/163.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/163.edn_genbits.2372948870
Short name T788
Test name
Test status
Simulation time 38617267 ps
CPU time 1.51 seconds
Started Aug 25 06:52:57 AM UTC 24
Finished Aug 25 06:53:01 AM UTC 24
Peak memory 228292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372948870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2372948870
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/163.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/164.edn_alert.1452381570
Short name T790
Test name
Test status
Simulation time 25075000 ps
CPU time 1.53 seconds
Started Aug 25 06:52:57 AM UTC 24
Finished Aug 25 06:53:01 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452381570 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 164.edn_alert.1452381570
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/164.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/165.edn_alert.3865909035
Short name T791
Test name
Test status
Simulation time 56844034 ps
CPU time 1.39 seconds
Started Aug 25 06:52:57 AM UTC 24
Finished Aug 25 06:53:01 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865909035 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 165.edn_alert.3865909035
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/165.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/165.edn_genbits.2794281238
Short name T847
Test name
Test status
Simulation time 39720828 ps
CPU time 1.87 seconds
Started Aug 25 06:52:57 AM UTC 24
Finished Aug 25 06:53:29 AM UTC 24
Peak memory 226572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794281238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 165.edn_genbits.2794281238
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/165.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/166.edn_alert.1090480860
Short name T830
Test name
Test status
Simulation time 26545013 ps
CPU time 1.29 seconds
Started Aug 25 06:52:57 AM UTC 24
Finished Aug 25 06:53:28 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090480860 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 166.edn_alert.1090480860
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/166.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/166.edn_genbits.1681190745
Short name T352
Test name
Test status
Simulation time 232428957 ps
CPU time 1.58 seconds
Started Aug 25 06:52:57 AM UTC 24
Finished Aug 25 06:53:29 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681190745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 166.edn_genbits.1681190745
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/166.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/167.edn_alert.3976285940
Short name T834
Test name
Test status
Simulation time 87059325 ps
CPU time 1.41 seconds
Started Aug 25 06:52:58 AM UTC 24
Finished Aug 25 06:53:29 AM UTC 24
Peak memory 228380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976285940 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 167.edn_alert.3976285940
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/167.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/167.edn_genbits.55133081
Short name T846
Test name
Test status
Simulation time 126251678 ps
CPU time 1.65 seconds
Started Aug 25 06:52:58 AM UTC 24
Finished Aug 25 06:53:29 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55133081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 167.edn_genbits.55133081
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/167.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/168.edn_alert.1433905323
Short name T831
Test name
Test status
Simulation time 24334233 ps
CPU time 1.38 seconds
Started Aug 25 06:52:58 AM UTC 24
Finished Aug 25 06:53:29 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433905323 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 168.edn_alert.1433905323
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/168.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/168.edn_genbits.4247718856
Short name T843
Test name
Test status
Simulation time 61659248 ps
CPU time 1.73 seconds
Started Aug 25 06:52:58 AM UTC 24
Finished Aug 25 06:53:29 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247718856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 168.edn_genbits.4247718856
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/168.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/169.edn_alert.1511789489
Short name T837
Test name
Test status
Simulation time 91607798 ps
CPU time 1.21 seconds
Started Aug 25 06:52:58 AM UTC 24
Finished Aug 25 06:53:29 AM UTC 24
Peak memory 230460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511789489 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 169.edn_alert.1511789489
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/169.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/169.edn_genbits.1786163363
Short name T845
Test name
Test status
Simulation time 79303347 ps
CPU time 1.38 seconds
Started Aug 25 06:52:58 AM UTC 24
Finished Aug 25 06:53:29 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786163363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 169.edn_genbits.1786163363
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/169.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/17.edn_alert_test.3274313804
Short name T251
Test name
Test status
Simulation time 30001773 ps
CPU time 0.95 seconds
Started Aug 25 06:50:19 AM UTC 24
Finished Aug 25 06:50:21 AM UTC 24
Peak memory 216688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274313804 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3274313804
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/17.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/17.edn_disable.815591856
Short name T247
Test name
Test status
Simulation time 21723843 ps
CPU time 0.89 seconds
Started Aug 25 06:50:18 AM UTC 24
Finished Aug 25 06:50:20 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815591856 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.815591856
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/17.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/17.edn_disable_auto_req_mode.3720303915
Short name T150
Test name
Test status
Simulation time 69379639 ps
CPU time 1.23 seconds
Started Aug 25 06:50:19 AM UTC 24
Finished Aug 25 06:50:21 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720303915 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable_auto_req_mode.3720303915
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/17.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/17.edn_genbits.2492023279
Short name T380
Test name
Test status
Simulation time 69788407 ps
CPU time 1.28 seconds
Started Aug 25 06:50:16 AM UTC 24
Finished Aug 25 06:50:26 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492023279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2492023279
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/17.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/17.edn_intr.23959116
Short name T373
Test name
Test status
Simulation time 37029151 ps
CPU time 0.83 seconds
Started Aug 25 06:50:16 AM UTC 24
Finished Aug 25 06:50:26 AM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23959116 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_in
tr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 17.edn_intr.23959116
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/17.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/17.edn_smoke.1807044541
Short name T301
Test name
Test status
Simulation time 35800288 ps
CPU time 0.95 seconds
Started Aug 25 06:50:16 AM UTC 24
Finished Aug 25 06:50:26 AM UTC 24
Peak memory 226148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807044541 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 17.edn_smoke.1807044541
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/17.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/17.edn_stress_all.3807548778
Short name T399
Test name
Test status
Simulation time 101843784 ps
CPU time 2.32 seconds
Started Aug 25 06:50:16 AM UTC 24
Finished Aug 25 06:50:27 AM UTC 24
Peak memory 229452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807548778 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.3807548778
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/17.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/17.edn_stress_all_with_rand_reset.741970764
Short name T623
Test name
Test status
Simulation time 25005181528 ps
CPU time 105.86 seconds
Started Aug 25 06:50:16 AM UTC 24
Finished Aug 25 06:52:12 AM UTC 24
Peak memory 229728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=741970764 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_
with_rand_reset.741970764
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/17.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/170.edn_alert.244083457
Short name T825
Test name
Test status
Simulation time 29077158 ps
CPU time 1.4 seconds
Started Aug 25 06:53:01 AM UTC 24
Finished Aug 25 06:53:27 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244083457 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 170.edn_alert.244083457
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/170.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/170.edn_genbits.703318840
Short name T844
Test name
Test status
Simulation time 71539549 ps
CPU time 1.25 seconds
Started Aug 25 06:52:59 AM UTC 24
Finished Aug 25 06:53:29 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703318840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 170.edn_genbits.703318840
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/170.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/171.edn_alert.3511201394
Short name T820
Test name
Test status
Simulation time 49824900 ps
CPU time 1.25 seconds
Started Aug 25 06:53:01 AM UTC 24
Finished Aug 25 06:53:27 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511201394 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 171.edn_alert.3511201394
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/171.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/171.edn_genbits.3628993362
Short name T823
Test name
Test status
Simulation time 46671675 ps
CPU time 1.4 seconds
Started Aug 25 06:53:01 AM UTC 24
Finished Aug 25 06:53:27 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628993362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 171.edn_genbits.3628993362
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/171.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/172.edn_alert.584731885
Short name T822
Test name
Test status
Simulation time 73017323 ps
CPU time 1.17 seconds
Started Aug 25 06:53:01 AM UTC 24
Finished Aug 25 06:53:27 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584731885 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 172.edn_alert.584731885
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/172.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/172.edn_genbits.1480863609
Short name T827
Test name
Test status
Simulation time 36013141 ps
CPU time 1.46 seconds
Started Aug 25 06:53:01 AM UTC 24
Finished Aug 25 06:53:27 AM UTC 24
Peak memory 230608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480863609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 172.edn_genbits.1480863609
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/172.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/173.edn_alert.3992850244
Short name T800
Test name
Test status
Simulation time 27571046 ps
CPU time 1.1 seconds
Started Aug 25 06:53:01 AM UTC 24
Finished Aug 25 06:53:10 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992850244 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 173.edn_alert.3992850244
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/173.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/173.edn_genbits.729533904
Short name T826
Test name
Test status
Simulation time 36130993 ps
CPU time 1.5 seconds
Started Aug 25 06:53:01 AM UTC 24
Finished Aug 25 06:53:27 AM UTC 24
Peak memory 230128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729533904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 173.edn_genbits.729533904
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/173.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/174.edn_alert.893964798
Short name T796
Test name
Test status
Simulation time 24287492 ps
CPU time 1.07 seconds
Started Aug 25 06:53:02 AM UTC 24
Finished Aug 25 06:53:05 AM UTC 24
Peak memory 230384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893964798 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 174.edn_alert.893964798
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/174.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/174.edn_genbits.584341603
Short name T821
Test name
Test status
Simulation time 36713759 ps
CPU time 1.27 seconds
Started Aug 25 06:53:01 AM UTC 24
Finished Aug 25 06:53:27 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584341603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 174.edn_genbits.584341603
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/174.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/175.edn_alert.948619954
Short name T803
Test name
Test status
Simulation time 27219398 ps
CPU time 1.2 seconds
Started Aug 25 06:53:02 AM UTC 24
Finished Aug 25 06:53:15 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948619954 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 175.edn_alert.948619954
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/175.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/175.edn_genbits.3644295482
Short name T807
Test name
Test status
Simulation time 228476467 ps
CPU time 2.86 seconds
Started Aug 25 06:53:02 AM UTC 24
Finished Aug 25 06:53:17 AM UTC 24
Peak memory 229404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644295482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 175.edn_genbits.3644295482
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/175.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/176.edn_alert.1629329519
Short name T814
Test name
Test status
Simulation time 40095430 ps
CPU time 1.29 seconds
Started Aug 25 06:53:02 AM UTC 24
Finished Aug 25 06:53:26 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629329519 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 176.edn_alert.1629329519
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/176.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/176.edn_genbits.2283981388
Short name T810
Test name
Test status
Simulation time 59749360 ps
CPU time 1.25 seconds
Started Aug 25 06:53:02 AM UTC 24
Finished Aug 25 06:53:26 AM UTC 24
Peak memory 230600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283981388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2283981388
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/176.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/177.edn_alert.2559929596
Short name T805
Test name
Test status
Simulation time 27727716 ps
CPU time 1.11 seconds
Started Aug 25 06:53:02 AM UTC 24
Finished Aug 25 06:53:16 AM UTC 24
Peak memory 230436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559929596 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 177.edn_alert.2559929596
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/177.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/177.edn_genbits.3593652518
Short name T804
Test name
Test status
Simulation time 50796474 ps
CPU time 1.03 seconds
Started Aug 25 06:53:02 AM UTC 24
Finished Aug 25 06:53:15 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593652518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 177.edn_genbits.3593652518
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/177.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/178.edn_alert.3139986434
Short name T773
Test name
Test status
Simulation time 154485410 ps
CPU time 1.43 seconds
Started Aug 25 06:53:02 AM UTC 24
Finished Aug 25 06:53:26 AM UTC 24
Peak memory 228320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139986434 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 178.edn_alert.3139986434
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/178.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/178.edn_genbits.1127303639
Short name T808
Test name
Test status
Simulation time 35455532 ps
CPU time 1.44 seconds
Started Aug 25 06:53:02 AM UTC 24
Finished Aug 25 06:53:18 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127303639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1127303639
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/178.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/179.edn_alert.760256080
Short name T806
Test name
Test status
Simulation time 329112576 ps
CPU time 1.13 seconds
Started Aug 25 06:53:02 AM UTC 24
Finished Aug 25 06:53:16 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760256080 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 179.edn_alert.760256080
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/179.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/179.edn_genbits.2931907799
Short name T813
Test name
Test status
Simulation time 34094323 ps
CPU time 1.26 seconds
Started Aug 25 06:53:02 AM UTC 24
Finished Aug 25 06:53:26 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931907799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2931907799
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/179.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/18.edn_alert.2093109008
Short name T164
Test name
Test status
Simulation time 25868727 ps
CPU time 1.14 seconds
Started Aug 25 06:50:19 AM UTC 24
Finished Aug 25 06:50:21 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093109008 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 18.edn_alert.2093109008
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/18.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/18.edn_alert_test.1419551865
Short name T381
Test name
Test status
Simulation time 54474256 ps
CPU time 1.07 seconds
Started Aug 25 06:50:19 AM UTC 24
Finished Aug 25 06:50:21 AM UTC 24
Peak memory 217108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419551865 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.1419551865
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/18.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/18.edn_disable.2392929288
Short name T388
Test name
Test status
Simulation time 139984168 ps
CPU time 1.13 seconds
Started Aug 25 06:50:19 AM UTC 24
Finished Aug 25 06:50:21 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392929288 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2392929288
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/18.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/18.edn_disable_auto_req_mode.3423582383
Short name T86
Test name
Test status
Simulation time 97718410 ps
CPU time 1.05 seconds
Started Aug 25 06:50:19 AM UTC 24
Finished Aug 25 06:50:21 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423582383 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable_auto_req_mode.3423582383
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/18.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/18.edn_err.333380599
Short name T139
Test name
Test status
Simulation time 43669605 ps
CPU time 1.3 seconds
Started Aug 25 06:50:19 AM UTC 24
Finished Aug 25 06:50:21 AM UTC 24
Peak memory 244220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333380599 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 18.edn_err.333380599
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/18.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/18.edn_genbits.3262288407
Short name T253
Test name
Test status
Simulation time 82348141 ps
CPU time 1.22 seconds
Started Aug 25 06:50:19 AM UTC 24
Finished Aug 25 06:50:21 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262288407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_genbits.3262288407
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/18.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/18.edn_intr.1214522661
Short name T97
Test name
Test status
Simulation time 22587313 ps
CPU time 1.55 seconds
Started Aug 25 06:50:19 AM UTC 24
Finished Aug 25 06:50:22 AM UTC 24
Peak memory 237360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214522661 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 18.edn_intr.1214522661
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/18.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/18.edn_smoke.3238893650
Short name T252
Test name
Test status
Simulation time 94686410 ps
CPU time 0.97 seconds
Started Aug 25 06:50:19 AM UTC 24
Finished Aug 25 06:50:21 AM UTC 24
Peak memory 226100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238893650 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 18.edn_smoke.3238893650
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/18.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/18.edn_stress_all.326412289
Short name T250
Test name
Test status
Simulation time 499983115 ps
CPU time 4.68 seconds
Started Aug 25 06:50:19 AM UTC 24
Finished Aug 25 06:50:25 AM UTC 24
Peak memory 227704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326412289 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.326412289
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/18.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/180.edn_alert.2089370518
Short name T817
Test name
Test status
Simulation time 24875747 ps
CPU time 1.23 seconds
Started Aug 25 06:53:02 AM UTC 24
Finished Aug 25 06:53:26 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089370518 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 180.edn_alert.2089370518
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/180.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/180.edn_genbits.1888417054
Short name T744
Test name
Test status
Simulation time 37367654 ps
CPU time 1.41 seconds
Started Aug 25 06:53:02 AM UTC 24
Finished Aug 25 06:53:26 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888417054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 180.edn_genbits.1888417054
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/180.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/181.edn_genbits.1173340972
Short name T811
Test name
Test status
Simulation time 52507358 ps
CPU time 1.06 seconds
Started Aug 25 06:53:02 AM UTC 24
Finished Aug 25 06:53:26 AM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173340972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 181.edn_genbits.1173340972
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/181.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/182.edn_alert.2789304117
Short name T812
Test name
Test status
Simulation time 22907873 ps
CPU time 1.06 seconds
Started Aug 25 06:53:03 AM UTC 24
Finished Aug 25 06:53:26 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789304117 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 182.edn_alert.2789304117
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/182.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/182.edn_genbits.3589155786
Short name T809
Test name
Test status
Simulation time 35837507 ps
CPU time 0.9 seconds
Started Aug 25 06:53:03 AM UTC 24
Finished Aug 25 06:53:26 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589155786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 182.edn_genbits.3589155786
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/182.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/183.edn_alert.1165129452
Short name T711
Test name
Test status
Simulation time 29106102 ps
CPU time 1.61 seconds
Started Aug 25 06:53:04 AM UTC 24
Finished Aug 25 06:53:27 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165129452 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 183.edn_alert.1165129452
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/183.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/183.edn_genbits.158823291
Short name T818
Test name
Test status
Simulation time 118324976 ps
CPU time 1.22 seconds
Started Aug 25 06:53:03 AM UTC 24
Finished Aug 25 06:53:26 AM UTC 24
Peak memory 230288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158823291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 183.edn_genbits.158823291
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/183.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/184.edn_alert.2986444565
Short name T836
Test name
Test status
Simulation time 313198480 ps
CPU time 1.45 seconds
Started Aug 25 06:53:06 AM UTC 24
Finished Aug 25 06:53:29 AM UTC 24
Peak memory 228076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986444565 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 184.edn_alert.2986444565
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/184.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/184.edn_genbits.3537452347
Short name T841
Test name
Test status
Simulation time 49268777 ps
CPU time 1.57 seconds
Started Aug 25 06:53:06 AM UTC 24
Finished Aug 25 06:53:29 AM UTC 24
Peak memory 227984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537452347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3537452347
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/184.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/185.edn_alert.69719085
Short name T322
Test name
Test status
Simulation time 71903242 ps
CPU time 1.23 seconds
Started Aug 25 06:53:07 AM UTC 24
Finished Aug 25 06:53:26 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69719085 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 185.edn_alert.69719085
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/185.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/185.edn_genbits.2941356446
Short name T839
Test name
Test status
Simulation time 112560955 ps
CPU time 1.64 seconds
Started Aug 25 06:53:06 AM UTC 24
Finished Aug 25 06:53:29 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941356446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2941356446
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/185.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/186.edn_alert.3652546039
Short name T815
Test name
Test status
Simulation time 30524370 ps
CPU time 1.14 seconds
Started Aug 25 06:53:11 AM UTC 24
Finished Aug 25 06:53:26 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652546039 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 186.edn_alert.3652546039
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/186.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/186.edn_genbits.164253806
Short name T345
Test name
Test status
Simulation time 55192944 ps
CPU time 1.44 seconds
Started Aug 25 06:53:09 AM UTC 24
Finished Aug 25 06:53:29 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164253806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 186.edn_genbits.164253806
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/186.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/187.edn_alert.1319927206
Short name T819
Test name
Test status
Simulation time 65957484 ps
CPU time 1.24 seconds
Started Aug 25 06:53:11 AM UTC 24
Finished Aug 25 06:53:27 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319927206 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 187.edn_alert.1319927206
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/187.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/187.edn_genbits.1291880737
Short name T824
Test name
Test status
Simulation time 36282045 ps
CPU time 1.5 seconds
Started Aug 25 06:53:11 AM UTC 24
Finished Aug 25 06:53:27 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291880737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 187.edn_genbits.1291880737
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/187.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/188.edn_alert.2340738329
Short name T838
Test name
Test status
Simulation time 26433122 ps
CPU time 1.15 seconds
Started Aug 25 06:53:16 AM UTC 24
Finished Aug 25 06:53:29 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340738329 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 188.edn_alert.2340738329
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/188.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/188.edn_genbits.3455019573
Short name T848
Test name
Test status
Simulation time 54395574 ps
CPU time 1.44 seconds
Started Aug 25 06:53:16 AM UTC 24
Finished Aug 25 06:53:29 AM UTC 24
Peak memory 228344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455019573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3455019573
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/188.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/189.edn_alert.1129065025
Short name T842
Test name
Test status
Simulation time 25126653 ps
CPU time 1.24 seconds
Started Aug 25 06:53:16 AM UTC 24
Finished Aug 25 06:53:29 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129065025 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 189.edn_alert.1129065025
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/189.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/189.edn_genbits.1214972599
Short name T850
Test name
Test status
Simulation time 58354755 ps
CPU time 1.87 seconds
Started Aug 25 06:53:16 AM UTC 24
Finished Aug 25 06:53:29 AM UTC 24
Peak memory 228556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214972599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 189.edn_genbits.1214972599
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/189.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/19.edn_err.3836443171
Short name T140
Test name
Test status
Simulation time 213088491 ps
CPU time 1.37 seconds
Started Aug 25 06:50:19 AM UTC 24
Finished Aug 25 06:50:22 AM UTC 24
Peak memory 230180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836443171 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 19.edn_err.3836443171
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/19.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/19.edn_genbits.1544616537
Short name T88
Test name
Test status
Simulation time 61701380 ps
CPU time 1.66 seconds
Started Aug 25 06:50:19 AM UTC 24
Finished Aug 25 06:50:22 AM UTC 24
Peak memory 228264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544616537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_genbits.1544616537
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/19.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/19.edn_intr.3301663805
Short name T392
Test name
Test status
Simulation time 23141587 ps
CPU time 1.56 seconds
Started Aug 25 06:50:19 AM UTC 24
Finished Aug 25 06:50:22 AM UTC 24
Peak memory 237300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301663805 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 19.edn_intr.3301663805
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/19.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/19.edn_smoke.983465699
Short name T385
Test name
Test status
Simulation time 46467545 ps
CPU time 0.98 seconds
Started Aug 25 06:50:19 AM UTC 24
Finished Aug 25 06:50:21 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983465699 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 19.edn_smoke.983465699
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/19.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/19.edn_stress_all.767217857
Short name T386
Test name
Test status
Simulation time 168914806 ps
CPU time 2.3 seconds
Started Aug 25 06:50:19 AM UTC 24
Finished Aug 25 06:50:23 AM UTC 24
Peak memory 229512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767217857 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.767217857
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/19.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/190.edn_alert.3679477560
Short name T849
Test name
Test status
Simulation time 51099147 ps
CPU time 1.45 seconds
Started Aug 25 06:53:16 AM UTC 24
Finished Aug 25 06:53:29 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679477560 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 190.edn_alert.3679477560
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/190.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/190.edn_genbits.172912336
Short name T835
Test name
Test status
Simulation time 74828409 ps
CPU time 1.09 seconds
Started Aug 25 06:53:16 AM UTC 24
Finished Aug 25 06:53:29 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172912336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 190.edn_genbits.172912336
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/190.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/191.edn_alert.10328919
Short name T877
Test name
Test status
Simulation time 22549616 ps
CPU time 1.08 seconds
Started Aug 25 06:53:19 AM UTC 24
Finished Aug 25 06:53:32 AM UTC 24
Peak memory 230312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10328919 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 191.edn_alert.10328919
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/191.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/191.edn_genbits.2621580636
Short name T829
Test name
Test status
Simulation time 123649023 ps
CPU time 1.67 seconds
Started Aug 25 06:53:18 AM UTC 24
Finished Aug 25 06:53:28 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621580636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2621580636
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/191.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/192.edn_alert.55659197
Short name T886
Test name
Test status
Simulation time 56974163 ps
CPU time 1.68 seconds
Started Aug 25 06:53:26 AM UTC 24
Finished Aug 25 06:53:33 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55659197 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 192.edn_alert.55659197
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/192.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/192.edn_genbits.3284699868
Short name T883
Test name
Test status
Simulation time 50746158 ps
CPU time 1.61 seconds
Started Aug 25 06:53:26 AM UTC 24
Finished Aug 25 06:53:32 AM UTC 24
Peak memory 226508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284699868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 192.edn_genbits.3284699868
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/192.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/193.edn_alert.2293120358
Short name T851
Test name
Test status
Simulation time 344545815 ps
CPU time 1.07 seconds
Started Aug 25 06:53:27 AM UTC 24
Finished Aug 25 06:53:31 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293120358 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 193.edn_alert.2293120358
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/193.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/193.edn_genbits.1413685184
Short name T880
Test name
Test status
Simulation time 70817416 ps
CPU time 2.38 seconds
Started Aug 25 06:53:27 AM UTC 24
Finished Aug 25 06:53:32 AM UTC 24
Peak memory 229700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413685184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 193.edn_genbits.1413685184
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/193.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/194.edn_alert.3471194821
Short name T852
Test name
Test status
Simulation time 151074853 ps
CPU time 1.05 seconds
Started Aug 25 06:53:27 AM UTC 24
Finished Aug 25 06:53:31 AM UTC 24
Peak memory 230452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471194821 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 194.edn_alert.3471194821
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/194.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/195.edn_alert.341233657
Short name T859
Test name
Test status
Simulation time 45433798 ps
CPU time 1.21 seconds
Started Aug 25 06:53:27 AM UTC 24
Finished Aug 25 06:53:31 AM UTC 24
Peak memory 230400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341233657 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 195.edn_alert.341233657
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/195.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/195.edn_genbits.2799270542
Short name T858
Test name
Test status
Simulation time 99783879 ps
CPU time 1.4 seconds
Started Aug 25 06:53:27 AM UTC 24
Finished Aug 25 06:53:31 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799270542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 195.edn_genbits.2799270542
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/195.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/196.edn_alert.915074807
Short name T863
Test name
Test status
Simulation time 28887466 ps
CPU time 1.52 seconds
Started Aug 25 06:53:28 AM UTC 24
Finished Aug 25 06:53:32 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915074807 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 196.edn_alert.915074807
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/196.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/196.edn_genbits.3892662916
Short name T972
Test name
Test status
Simulation time 9113820346 ps
CPU time 99.45 seconds
Started Aug 25 06:53:27 AM UTC 24
Finished Aug 25 06:55:11 AM UTC 24
Peak memory 231880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892662916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3892662916
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/196.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/197.edn_alert.1398420003
Short name T868
Test name
Test status
Simulation time 30627546 ps
CPU time 1.59 seconds
Started Aug 25 06:53:28 AM UTC 24
Finished Aug 25 06:53:32 AM UTC 24
Peak memory 230464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398420003 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 197.edn_alert.1398420003
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/197.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/197.edn_genbits.1414750765
Short name T860
Test name
Test status
Simulation time 48704889 ps
CPU time 1.45 seconds
Started Aug 25 06:53:28 AM UTC 24
Finished Aug 25 06:53:32 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414750765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1414750765
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/197.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/198.edn_alert.812566950
Short name T874
Test name
Test status
Simulation time 52717892 ps
CPU time 1.8 seconds
Started Aug 25 06:53:28 AM UTC 24
Finished Aug 25 06:53:32 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812566950 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 198.edn_alert.812566950
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/198.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/198.edn_genbits.3754378707
Short name T854
Test name
Test status
Simulation time 36035823 ps
CPU time 1.1 seconds
Started Aug 25 06:53:28 AM UTC 24
Finished Aug 25 06:53:31 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754378707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3754378707
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/198.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/199.edn_alert.3058296929
Short name T862
Test name
Test status
Simulation time 28387920 ps
CPU time 1.44 seconds
Started Aug 25 06:53:28 AM UTC 24
Finished Aug 25 06:53:32 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058296929 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 199.edn_alert.3058296929
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/199.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/199.edn_genbits.1641980705
Short name T867
Test name
Test status
Simulation time 62001842 ps
CPU time 1.47 seconds
Started Aug 25 06:53:28 AM UTC 24
Finished Aug 25 06:53:32 AM UTC 24
Peak memory 228348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641980705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1641980705
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/199.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/2.edn_alert_test.2503809000
Short name T60
Test name
Test status
Simulation time 45872922 ps
CPU time 0.83 seconds
Started Aug 25 06:49:53 AM UTC 24
Finished Aug 25 06:49:55 AM UTC 24
Peak memory 217052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503809000 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2503809000
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/2.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/2.edn_disable_auto_req_mode.4242376232
Short name T11
Test name
Test status
Simulation time 26919216 ps
CPU time 1 seconds
Started Aug 25 06:49:53 AM UTC 24
Finished Aug 25 06:49:55 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242376232 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable_auto_req_mode.4242376232
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/2.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/2.edn_err.2023631313
Short name T31
Test name
Test status
Simulation time 30726074 ps
CPU time 1.12 seconds
Started Aug 25 06:49:53 AM UTC 24
Finished Aug 25 06:49:56 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023631313 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 2.edn_err.2023631313
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/2.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/2.edn_genbits.2877115523
Short name T113
Test name
Test status
Simulation time 62313863 ps
CPU time 1.71 seconds
Started Aug 25 06:49:53 AM UTC 24
Finished Aug 25 06:49:58 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877115523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_genbits.2877115523
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/2.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/2.edn_intr.3687480973
Short name T64
Test name
Test status
Simulation time 45996796 ps
CPU time 1.46 seconds
Started Aug 25 06:49:53 AM UTC 24
Finished Aug 25 06:49:57 AM UTC 24
Peak memory 243756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687480973 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 2.edn_intr.3687480973
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/2.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/2.edn_regwen.3325656426
Short name T324
Test name
Test status
Simulation time 33609610 ps
CPU time 0.88 seconds
Started Aug 25 06:49:53 AM UTC 24
Finished Aug 25 06:49:57 AM UTC 24
Peak memory 215800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325656426 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 2.edn_regwen.3325656426
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/2.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/2.edn_sec_cm.1238102221
Short name T18
Test name
Test status
Simulation time 679710638 ps
CPU time 4.58 seconds
Started Aug 25 06:49:53 AM UTC 24
Finished Aug 25 06:49:59 AM UTC 24
Peak memory 260364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238102221 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1238102221
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/2.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/2.edn_smoke.1920165439
Short name T111
Test name
Test status
Simulation time 16698227 ps
CPU time 0.93 seconds
Started Aug 25 06:49:53 AM UTC 24
Finished Aug 25 06:49:57 AM UTC 24
Peak memory 226136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920165439 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 2.edn_smoke.1920165439
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/2.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/2.edn_stress_all.2027356582
Short name T61
Test name
Test status
Simulation time 436820536 ps
CPU time 2.57 seconds
Started Aug 25 06:49:53 AM UTC 24
Finished Aug 25 06:49:59 AM UTC 24
Peak memory 227316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027356582 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2027356582
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/2.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/20.edn_alert.3922092179
Short name T196
Test name
Test status
Simulation time 53980817 ps
CPU time 1.41 seconds
Started Aug 25 06:50:21 AM UTC 24
Finished Aug 25 06:50:57 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922092179 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 20.edn_alert.3922092179
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/20.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/20.edn_alert_test.2882312058
Short name T412
Test name
Test status
Simulation time 80521946 ps
CPU time 1.07 seconds
Started Aug 25 06:50:22 AM UTC 24
Finished Aug 25 06:50:57 AM UTC 24
Peak memory 216924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882312058 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2882312058
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/20.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/20.edn_disable_auto_req_mode.1137940539
Short name T416
Test name
Test status
Simulation time 54517521 ps
CPU time 1.44 seconds
Started Aug 25 06:50:22 AM UTC 24
Finished Aug 25 06:50:58 AM UTC 24
Peak memory 226248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137940539 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable_auto_req_mode.1137940539
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/20.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/20.edn_err.3608385523
Short name T160
Test name
Test status
Simulation time 57283052 ps
CPU time 1.1 seconds
Started Aug 25 06:50:22 AM UTC 24
Finished Aug 25 06:50:37 AM UTC 24
Peak memory 243796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608385523 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 20.edn_err.3608385523
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/20.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/20.edn_intr.4017253511
Short name T405
Test name
Test status
Simulation time 24793754 ps
CPU time 1.01 seconds
Started Aug 25 06:50:21 AM UTC 24
Finished Aug 25 06:50:37 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017253511 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 20.edn_intr.4017253511
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/20.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/20.edn_stress_all.1915081851
Short name T403
Test name
Test status
Simulation time 94005383 ps
CPU time 2.17 seconds
Started Aug 25 06:50:21 AM UTC 24
Finished Aug 25 06:50:31 AM UTC 24
Peak memory 229444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915081851 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1915081851
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/20.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/20.edn_stress_all_with_rand_reset.665452294
Short name T254
Test name
Test status
Simulation time 28263817759 ps
CPU time 78.81 seconds
Started Aug 25 06:50:21 AM UTC 24
Finished Aug 25 06:52:05 AM UTC 24
Peak memory 231844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=665452294 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_
with_rand_reset.665452294
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/20.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/200.edn_genbits.327399602
Short name T890
Test name
Test status
Simulation time 43517450 ps
CPU time 2.18 seconds
Started Aug 25 06:53:28 AM UTC 24
Finished Aug 25 06:53:33 AM UTC 24
Peak memory 229520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327399602 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 200.edn_genbits.327399602
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/200.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/201.edn_genbits.3613830843
Short name T870
Test name
Test status
Simulation time 81938567 ps
CPU time 1.59 seconds
Started Aug 25 06:53:28 AM UTC 24
Finished Aug 25 06:53:32 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613830843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 201.edn_genbits.3613830843
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/201.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/203.edn_genbits.2519056066
Short name T884
Test name
Test status
Simulation time 102104431 ps
CPU time 1.75 seconds
Started Aug 25 06:53:28 AM UTC 24
Finished Aug 25 06:53:32 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519056066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2519056066
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/203.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/204.edn_genbits.2634226654
Short name T876
Test name
Test status
Simulation time 64087602 ps
CPU time 1.53 seconds
Started Aug 25 06:53:28 AM UTC 24
Finished Aug 25 06:53:32 AM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634226654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 204.edn_genbits.2634226654
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/204.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/205.edn_genbits.3525102364
Short name T869
Test name
Test status
Simulation time 56566158 ps
CPU time 1.25 seconds
Started Aug 25 06:53:28 AM UTC 24
Finished Aug 25 06:53:32 AM UTC 24
Peak memory 228332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525102364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3525102364
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/205.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/206.edn_genbits.4288218157
Short name T896
Test name
Test status
Simulation time 50629913 ps
CPU time 2.19 seconds
Started Aug 25 06:53:28 AM UTC 24
Finished Aug 25 06:53:33 AM UTC 24
Peak memory 229704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288218157 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 206.edn_genbits.4288218157
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/206.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/207.edn_genbits.2047539657
Short name T879
Test name
Test status
Simulation time 57834513 ps
CPU time 1.59 seconds
Started Aug 25 06:53:28 AM UTC 24
Finished Aug 25 06:53:32 AM UTC 24
Peak memory 228352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047539657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 207.edn_genbits.2047539657
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/207.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/208.edn_genbits.4165252704
Short name T891
Test name
Test status
Simulation time 43306196 ps
CPU time 1.68 seconds
Started Aug 25 06:53:29 AM UTC 24
Finished Aug 25 06:53:33 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165252704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 208.edn_genbits.4165252704
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/208.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/209.edn_genbits.865319590
Short name T889
Test name
Test status
Simulation time 75882402 ps
CPU time 1.42 seconds
Started Aug 25 06:53:29 AM UTC 24
Finished Aug 25 06:53:33 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865319590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 209.edn_genbits.865319590
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/209.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/21.edn_alert.3390780529
Short name T144
Test name
Test status
Simulation time 98750344 ps
CPU time 1.54 seconds
Started Aug 25 06:50:22 AM UTC 24
Finished Aug 25 06:50:58 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390780529 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 21.edn_alert.3390780529
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/21.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/21.edn_alert_test.38595211
Short name T387
Test name
Test status
Simulation time 26931693 ps
CPU time 1.07 seconds
Started Aug 25 06:50:24 AM UTC 24
Finished Aug 25 06:50:26 AM UTC 24
Peak memory 217168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38595211 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.38595211
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/21.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/21.edn_disable.1293283291
Short name T207
Test name
Test status
Simulation time 19032652 ps
CPU time 0.99 seconds
Started Aug 25 06:50:22 AM UTC 24
Finished Aug 25 06:50:58 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293283291 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1293283291
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/21.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/21.edn_disable_auto_req_mode.1628241552
Short name T151
Test name
Test status
Simulation time 97296630 ps
CPU time 1.03 seconds
Started Aug 25 06:50:24 AM UTC 24
Finished Aug 25 06:50:26 AM UTC 24
Peak memory 226096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628241552 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable_auto_req_mode.1628241552
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/21.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/21.edn_err.4230056486
Short name T415
Test name
Test status
Simulation time 36305436 ps
CPU time 0.87 seconds
Started Aug 25 06:50:22 AM UTC 24
Finished Aug 25 06:50:57 AM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230056486 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 21.edn_err.4230056486
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/21.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/21.edn_genbits.1839824561
Short name T90
Test name
Test status
Simulation time 59616731 ps
CPU time 1.5 seconds
Started Aug 25 06:50:22 AM UTC 24
Finished Aug 25 06:50:58 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839824561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_genbits.1839824561
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/21.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/21.edn_intr.1146189272
Short name T413
Test name
Test status
Simulation time 57611824 ps
CPU time 0.96 seconds
Started Aug 25 06:50:22 AM UTC 24
Finished Aug 25 06:50:57 AM UTC 24
Peak memory 225908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146189272 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 21.edn_intr.1146189272
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/21.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/21.edn_smoke.4099893839
Short name T406
Test name
Test status
Simulation time 46576606 ps
CPU time 0.97 seconds
Started Aug 25 06:50:22 AM UTC 24
Finished Aug 25 06:50:57 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099893839 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 21.edn_smoke.4099893839
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/21.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/21.edn_stress_all.2918255248
Short name T310
Test name
Test status
Simulation time 560145679 ps
CPU time 6.21 seconds
Started Aug 25 06:50:22 AM UTC 24
Finished Aug 25 06:51:03 AM UTC 24
Peak memory 228696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918255248 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2918255248
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/21.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/21.edn_stress_all_with_rand_reset.3523672233
Short name T742
Test name
Test status
Simulation time 5150370743 ps
CPU time 111.23 seconds
Started Aug 25 06:50:22 AM UTC 24
Finished Aug 25 06:52:49 AM UTC 24
Peak memory 234260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3523672233 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all
_with_rand_reset.3523672233
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/21.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/210.edn_genbits.530453980
Short name T892
Test name
Test status
Simulation time 61839548 ps
CPU time 1.85 seconds
Started Aug 25 06:53:29 AM UTC 24
Finished Aug 25 06:53:33 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530453980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 210.edn_genbits.530453980
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/210.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/211.edn_genbits.3447327319
Short name T875
Test name
Test status
Simulation time 43556754 ps
CPU time 1.32 seconds
Started Aug 25 06:53:29 AM UTC 24
Finished Aug 25 06:53:32 AM UTC 24
Peak memory 226068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447327319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 211.edn_genbits.3447327319
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/211.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/212.edn_genbits.1250001950
Short name T893
Test name
Test status
Simulation time 66220999 ps
CPU time 1.61 seconds
Started Aug 25 06:53:29 AM UTC 24
Finished Aug 25 06:53:33 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250001950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1250001950
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/212.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/213.edn_genbits.775821412
Short name T887
Test name
Test status
Simulation time 111935595 ps
CPU time 1.4 seconds
Started Aug 25 06:53:29 AM UTC 24
Finished Aug 25 06:53:33 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775821412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 213.edn_genbits.775821412
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/213.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/214.edn_genbits.2013393852
Short name T895
Test name
Test status
Simulation time 39759244 ps
CPU time 1.74 seconds
Started Aug 25 06:53:29 AM UTC 24
Finished Aug 25 06:53:33 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013393852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 214.edn_genbits.2013393852
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/214.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/215.edn_genbits.592263863
Short name T878
Test name
Test status
Simulation time 68424427 ps
CPU time 1.15 seconds
Started Aug 25 06:53:29 AM UTC 24
Finished Aug 25 06:53:32 AM UTC 24
Peak memory 227568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592263863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 215.edn_genbits.592263863
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/215.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/216.edn_genbits.1189126709
Short name T888
Test name
Test status
Simulation time 158638330 ps
CPU time 1.35 seconds
Started Aug 25 06:53:29 AM UTC 24
Finished Aug 25 06:53:33 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189126709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1189126709
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/216.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/217.edn_genbits.3401469040
Short name T885
Test name
Test status
Simulation time 33082301 ps
CPU time 1.28 seconds
Started Aug 25 06:53:29 AM UTC 24
Finished Aug 25 06:53:32 AM UTC 24
Peak memory 230604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401469040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 217.edn_genbits.3401469040
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/217.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/218.edn_genbits.859848900
Short name T894
Test name
Test status
Simulation time 192875487 ps
CPU time 1.5 seconds
Started Aug 25 06:53:29 AM UTC 24
Finished Aug 25 06:53:33 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859848900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 218.edn_genbits.859848900
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/218.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/219.edn_genbits.2875325045
Short name T903
Test name
Test status
Simulation time 37070308 ps
CPU time 1.39 seconds
Started Aug 25 06:53:29 AM UTC 24
Finished Aug 25 06:53:36 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875325045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 219.edn_genbits.2875325045
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/219.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/22.edn_alert.2750441729
Short name T194
Test name
Test status
Simulation time 125403325 ps
CPU time 1.34 seconds
Started Aug 25 06:50:24 AM UTC 24
Finished Aug 25 06:50:27 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750441729 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 22.edn_alert.2750441729
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/22.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/22.edn_alert_test.3779208037
Short name T396
Test name
Test status
Simulation time 13469040 ps
CPU time 1.22 seconds
Started Aug 25 06:50:24 AM UTC 24
Finished Aug 25 06:50:27 AM UTC 24
Peak memory 216688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779208037 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.3779208037
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/22.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/22.edn_disable.3672543098
Short name T395
Test name
Test status
Simulation time 41962451 ps
CPU time 1.14 seconds
Started Aug 25 06:50:24 AM UTC 24
Finished Aug 25 06:50:27 AM UTC 24
Peak memory 216000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672543098 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3672543098
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/22.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/22.edn_disable_auto_req_mode.3323650283
Short name T168
Test name
Test status
Simulation time 87729488 ps
CPU time 1.42 seconds
Started Aug 25 06:50:24 AM UTC 24
Finished Aug 25 06:50:27 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323650283 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable_auto_req_mode.3323650283
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/22.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/22.edn_err.200062494
Short name T246
Test name
Test status
Simulation time 19016589 ps
CPU time 1.18 seconds
Started Aug 25 06:50:24 AM UTC 24
Finished Aug 25 06:50:27 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200062494 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 22.edn_err.200062494
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/22.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/22.edn_genbits.3600542955
Short name T398
Test name
Test status
Simulation time 42619772 ps
CPU time 1.54 seconds
Started Aug 25 06:50:24 AM UTC 24
Finished Aug 25 06:50:27 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600542955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3600542955
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/22.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/22.edn_intr.1393901734
Short name T248
Test name
Test status
Simulation time 55984320 ps
CPU time 0.85 seconds
Started Aug 25 06:50:24 AM UTC 24
Finished Aug 25 06:50:26 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393901734 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 22.edn_intr.1393901734
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/22.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/22.edn_smoke.284324810
Short name T384
Test name
Test status
Simulation time 51601743 ps
CPU time 1.12 seconds
Started Aug 25 06:50:24 AM UTC 24
Finished Aug 25 06:50:26 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284324810 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 22.edn_smoke.284324810
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/22.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/22.edn_stress_all.1774654896
Short name T401
Test name
Test status
Simulation time 302913060 ps
CPU time 3.13 seconds
Started Aug 25 06:50:24 AM UTC 24
Finished Aug 25 06:50:29 AM UTC 24
Peak memory 227472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774654896 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.1774654896
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/22.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/220.edn_genbits.2141324868
Short name T856
Test name
Test status
Simulation time 56252357 ps
CPU time 1.98 seconds
Started Aug 25 06:53:29 AM UTC 24
Finished Aug 25 06:53:36 AM UTC 24
Peak memory 229708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141324868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 220.edn_genbits.2141324868
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/220.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/221.edn_genbits.98419813
Short name T915
Test name
Test status
Simulation time 677169759 ps
CPU time 4.9 seconds
Started Aug 25 06:53:30 AM UTC 24
Finished Aug 25 06:53:39 AM UTC 24
Peak memory 229516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98419813 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 221.edn_genbits.98419813
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/221.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/222.edn_genbits.3144349075
Short name T897
Test name
Test status
Simulation time 141113543 ps
CPU time 1.96 seconds
Started Aug 25 06:53:30 AM UTC 24
Finished Aug 25 06:53:33 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144349075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3144349075
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/222.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/223.edn_genbits.1786990654
Short name T902
Test name
Test status
Simulation time 150411879 ps
CPU time 1.21 seconds
Started Aug 25 06:53:30 AM UTC 24
Finished Aug 25 06:53:36 AM UTC 24
Peak memory 225624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786990654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 223.edn_genbits.1786990654
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/223.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/224.edn_genbits.2984556407
Short name T899
Test name
Test status
Simulation time 248718490 ps
CPU time 1.04 seconds
Started Aug 25 06:53:30 AM UTC 24
Finished Aug 25 06:53:35 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984556407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2984556407
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/224.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/225.edn_genbits.116514456
Short name T907
Test name
Test status
Simulation time 121443784 ps
CPU time 1.51 seconds
Started Aug 25 06:53:30 AM UTC 24
Finished Aug 25 06:53:36 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116514456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 225.edn_genbits.116514456
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/225.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/226.edn_genbits.1776772260
Short name T353
Test name
Test status
Simulation time 55186302 ps
CPU time 1.18 seconds
Started Aug 25 06:53:30 AM UTC 24
Finished Aug 25 06:53:36 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776772260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 226.edn_genbits.1776772260
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/226.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/227.edn_genbits.3261456400
Short name T957
Test name
Test status
Simulation time 105941217 ps
CPU time 1.65 seconds
Started Aug 25 06:53:31 AM UTC 24
Finished Aug 25 06:54:04 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261456400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3261456400
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/227.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/228.edn_genbits.4133737189
Short name T955
Test name
Test status
Simulation time 42313530 ps
CPU time 1.66 seconds
Started Aug 25 06:53:31 AM UTC 24
Finished Aug 25 06:54:04 AM UTC 24
Peak memory 228132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133737189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 228.edn_genbits.4133737189
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/228.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/229.edn_genbits.3759098520
Short name T954
Test name
Test status
Simulation time 72264269 ps
CPU time 1.61 seconds
Started Aug 25 06:53:31 AM UTC 24
Finished Aug 25 06:54:04 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759098520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3759098520
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/229.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/23.edn_alert.1331329338
Short name T269
Test name
Test status
Simulation time 33170445 ps
CPU time 1.61 seconds
Started Aug 25 06:50:24 AM UTC 24
Finished Aug 25 06:50:27 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331329338 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 23.edn_alert.1331329338
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/23.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/23.edn_alert_test.3195887712
Short name T409
Test name
Test status
Simulation time 32322848 ps
CPU time 0.99 seconds
Started Aug 25 06:50:25 AM UTC 24
Finished Aug 25 06:50:57 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195887712 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3195887712
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/23.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/23.edn_disable.1475699548
Short name T263
Test name
Test status
Simulation time 192101831 ps
CPU time 0.88 seconds
Started Aug 25 06:50:24 AM UTC 24
Finished Aug 25 06:50:57 AM UTC 24
Peak memory 216132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475699548 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.1475699548
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/23.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/23.edn_disable_auto_req_mode.3294695251
Short name T175
Test name
Test status
Simulation time 33584985 ps
CPU time 1.36 seconds
Started Aug 25 06:50:25 AM UTC 24
Finished Aug 25 06:50:57 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294695251 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable_auto_req_mode.3294695251
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/23.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/23.edn_err.3514813828
Short name T129
Test name
Test status
Simulation time 33742676 ps
CPU time 1.2 seconds
Started Aug 25 06:50:24 AM UTC 24
Finished Aug 25 06:50:27 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514813828 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 23.edn_err.3514813828
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/23.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/23.edn_genbits.2602509140
Short name T355
Test name
Test status
Simulation time 120472940 ps
CPU time 2.1 seconds
Started Aug 25 06:50:24 AM UTC 24
Finished Aug 25 06:50:28 AM UTC 24
Peak memory 231368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602509140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2602509140
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/23.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/23.edn_intr.3140534118
Short name T134
Test name
Test status
Simulation time 36550729 ps
CPU time 1.15 seconds
Started Aug 25 06:50:24 AM UTC 24
Finished Aug 25 06:50:27 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140534118 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 23.edn_intr.3140534118
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/23.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/23.edn_smoke.1383717151
Short name T397
Test name
Test status
Simulation time 18715839 ps
CPU time 1.25 seconds
Started Aug 25 06:50:24 AM UTC 24
Finished Aug 25 06:50:27 AM UTC 24
Peak memory 226128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383717151 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 23.edn_smoke.1383717151
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/23.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/23.edn_stress_all.2797974724
Short name T400
Test name
Test status
Simulation time 264481932 ps
CPU time 1.91 seconds
Started Aug 25 06:50:24 AM UTC 24
Finished Aug 25 06:50:28 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797974724 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.2797974724
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/23.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/230.edn_genbits.233670442
Short name T967
Test name
Test status
Simulation time 46567288 ps
CPU time 1.94 seconds
Started Aug 25 06:53:31 AM UTC 24
Finished Aug 25 06:54:05 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233670442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 230.edn_genbits.233670442
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/230.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/231.edn_genbits.3504303529
Short name T866
Test name
Test status
Simulation time 56482198 ps
CPU time 1.26 seconds
Started Aug 25 06:53:31 AM UTC 24
Finished Aug 25 06:53:37 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504303529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3504303529
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/231.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/232.edn_genbits.219180063
Short name T951
Test name
Test status
Simulation time 23537760 ps
CPU time 1.61 seconds
Started Aug 25 06:53:31 AM UTC 24
Finished Aug 25 06:54:04 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219180063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 232.edn_genbits.219180063
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/232.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/233.edn_genbits.1921993639
Short name T966
Test name
Test status
Simulation time 46947171 ps
CPU time 1.89 seconds
Started Aug 25 06:53:31 AM UTC 24
Finished Aug 25 06:54:05 AM UTC 24
Peak memory 228436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921993639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1921993639
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/233.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/234.edn_genbits.86018378
Short name T348
Test name
Test status
Simulation time 68013962 ps
CPU time 1.46 seconds
Started Aug 25 06:53:31 AM UTC 24
Finished Aug 25 06:53:37 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86018378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 234.edn_genbits.86018378
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/234.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/235.edn_genbits.573676783
Short name T900
Test name
Test status
Simulation time 25644345 ps
CPU time 1.24 seconds
Started Aug 25 06:53:32 AM UTC 24
Finished Aug 25 06:53:35 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573676783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 235.edn_genbits.573676783
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/235.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/236.edn_genbits.3991041055
Short name T925
Test name
Test status
Simulation time 131182452 ps
CPU time 1.14 seconds
Started Aug 25 06:53:32 AM UTC 24
Finished Aug 25 06:53:41 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991041055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3991041055
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/236.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/237.edn_genbits.1091216273
Short name T857
Test name
Test status
Simulation time 64861485 ps
CPU time 2.18 seconds
Started Aug 25 06:53:32 AM UTC 24
Finished Aug 25 06:53:36 AM UTC 24
Peak memory 231580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091216273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1091216273
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/237.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/238.edn_genbits.2198253299
Short name T909
Test name
Test status
Simulation time 112532857 ps
CPU time 1.56 seconds
Started Aug 25 06:53:32 AM UTC 24
Finished Aug 25 06:53:36 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198253299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 238.edn_genbits.2198253299
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/238.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/239.edn_genbits.863775538
Short name T904
Test name
Test status
Simulation time 45735564 ps
CPU time 1.29 seconds
Started Aug 25 06:53:32 AM UTC 24
Finished Aug 25 06:53:36 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863775538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 239.edn_genbits.863775538
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/239.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/24.edn_alert.3943584497
Short name T195
Test name
Test status
Simulation time 29977980 ps
CPU time 1.17 seconds
Started Aug 25 06:50:27 AM UTC 24
Finished Aug 25 06:50:56 AM UTC 24
Peak memory 226360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943584497 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 24.edn_alert.3943584497
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/24.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/24.edn_alert_test.342538374
Short name T411
Test name
Test status
Simulation time 26314702 ps
CPU time 0.87 seconds
Started Aug 25 06:50:28 AM UTC 24
Finished Aug 25 06:50:57 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342538374 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.342538374
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/24.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/24.edn_disable.4094190418
Short name T179
Test name
Test status
Simulation time 14249073 ps
CPU time 1.11 seconds
Started Aug 25 06:50:28 AM UTC 24
Finished Aug 25 06:50:58 AM UTC 24
Peak memory 226368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094190418 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.4094190418
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/24.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/24.edn_disable_auto_req_mode.2626603832
Short name T417
Test name
Test status
Simulation time 58345452 ps
CPU time 1.27 seconds
Started Aug 25 06:50:28 AM UTC 24
Finished Aug 25 06:50:58 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626603832 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable_auto_req_mode.2626603832
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/24.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/24.edn_err.379377470
Short name T172
Test name
Test status
Simulation time 21409043 ps
CPU time 1.03 seconds
Started Aug 25 06:50:27 AM UTC 24
Finished Aug 25 06:50:56 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379377470 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 24.edn_err.379377470
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/24.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/24.edn_genbits.260801180
Short name T358
Test name
Test status
Simulation time 39212448 ps
CPU time 1.27 seconds
Started Aug 25 06:50:25 AM UTC 24
Finished Aug 25 06:50:57 AM UTC 24
Peak memory 230608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260801180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.edn_genbits.260801180
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/24.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/24.edn_intr.2416263279
Short name T261
Test name
Test status
Simulation time 140446079 ps
CPU time 0.88 seconds
Started Aug 25 06:50:27 AM UTC 24
Finished Aug 25 06:50:56 AM UTC 24
Peak memory 226324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416263279 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 24.edn_intr.2416263279
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/24.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/24.edn_smoke.237750585
Short name T407
Test name
Test status
Simulation time 18795620 ps
CPU time 1.04 seconds
Started Aug 25 06:50:25 AM UTC 24
Finished Aug 25 06:50:57 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237750585 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 24.edn_smoke.237750585
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/24.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/24.edn_stress_all.2196370239
Short name T414
Test name
Test status
Simulation time 64394697 ps
CPU time 1.24 seconds
Started Aug 25 06:50:25 AM UTC 24
Finished Aug 25 06:50:57 AM UTC 24
Peak memory 228308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196370239 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2196370239
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/24.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/24.edn_stress_all_with_rand_reset.1591614606
Short name T258
Test name
Test status
Simulation time 11586280424 ps
CPU time 119.46 seconds
Started Aug 25 06:50:27 AM UTC 24
Finished Aug 25 06:52:56 AM UTC 24
Peak memory 231860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1591614606 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all
_with_rand_reset.1591614606
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/24.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/240.edn_genbits.407602815
Short name T855
Test name
Test status
Simulation time 47493176 ps
CPU time 1.73 seconds
Started Aug 25 06:53:32 AM UTC 24
Finished Aug 25 06:53:36 AM UTC 24
Peak memory 230612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407602815 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 240.edn_genbits.407602815
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/240.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/241.edn_genbits.3151802035
Short name T912
Test name
Test status
Simulation time 85614434 ps
CPU time 2.18 seconds
Started Aug 25 06:53:32 AM UTC 24
Finished Aug 25 06:53:37 AM UTC 24
Peak memory 231700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151802035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3151802035
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/241.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/242.edn_genbits.3884936919
Short name T905
Test name
Test status
Simulation time 26205313 ps
CPU time 1.23 seconds
Started Aug 25 06:53:33 AM UTC 24
Finished Aug 25 06:53:36 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884936919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 242.edn_genbits.3884936919
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/242.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/243.edn_genbits.3227152943
Short name T908
Test name
Test status
Simulation time 73097776 ps
CPU time 1.31 seconds
Started Aug 25 06:53:33 AM UTC 24
Finished Aug 25 06:53:36 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227152943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3227152943
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/243.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/244.edn_genbits.2850501070
Short name T911
Test name
Test status
Simulation time 95193353 ps
CPU time 1.46 seconds
Started Aug 25 06:53:33 AM UTC 24
Finished Aug 25 06:53:36 AM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850501070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 244.edn_genbits.2850501070
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/244.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/245.edn_genbits.193511763
Short name T910
Test name
Test status
Simulation time 145649069 ps
CPU time 1.32 seconds
Started Aug 25 06:53:33 AM UTC 24
Finished Aug 25 06:53:36 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193511763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 245.edn_genbits.193511763
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/245.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/246.edn_genbits.1581896850
Short name T901
Test name
Test status
Simulation time 59243340 ps
CPU time 1.94 seconds
Started Aug 25 06:53:34 AM UTC 24
Finished Aug 25 06:53:37 AM UTC 24
Peak memory 230604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581896850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1581896850
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/246.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/247.edn_genbits.3651568366
Short name T942
Test name
Test status
Simulation time 37774526 ps
CPU time 1.48 seconds
Started Aug 25 06:53:34 AM UTC 24
Finished Aug 25 06:54:03 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651568366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 247.edn_genbits.3651568366
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/247.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/248.edn_genbits.548214847
Short name T943
Test name
Test status
Simulation time 93447716 ps
CPU time 1.47 seconds
Started Aug 25 06:53:34 AM UTC 24
Finished Aug 25 06:54:03 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548214847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 248.edn_genbits.548214847
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/248.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/249.edn_genbits.4191042632
Short name T947
Test name
Test status
Simulation time 58535371 ps
CPU time 1.61 seconds
Started Aug 25 06:53:34 AM UTC 24
Finished Aug 25 06:54:04 AM UTC 24
Peak memory 228468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191042632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 249.edn_genbits.4191042632
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/249.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/25.edn_alert.2757933549
Short name T132
Test name
Test status
Simulation time 28031750 ps
CPU time 1.5 seconds
Started Aug 25 06:50:28 AM UTC 24
Finished Aug 25 06:51:01 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757933549 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 25.edn_alert.2757933549
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/25.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/25.edn_alert_test.1838471733
Short name T425
Test name
Test status
Simulation time 21249710 ps
CPU time 1.25 seconds
Started Aug 25 06:50:28 AM UTC 24
Finished Aug 25 06:51:01 AM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838471733 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1838471733
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/25.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/25.edn_disable_auto_req_mode.2867877328
Short name T427
Test name
Test status
Simulation time 96055008 ps
CPU time 1.37 seconds
Started Aug 25 06:50:28 AM UTC 24
Finished Aug 25 06:51:01 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867877328 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable_auto_req_mode.2867877328
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/25.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/25.edn_err.1081840500
Short name T233
Test name
Test status
Simulation time 23443984 ps
CPU time 1.26 seconds
Started Aug 25 06:50:28 AM UTC 24
Finished Aug 25 06:51:01 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081840500 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 25.edn_err.1081840500
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/25.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/25.edn_genbits.2996822361
Short name T418
Test name
Test status
Simulation time 48585783 ps
CPU time 1.36 seconds
Started Aug 25 06:50:28 AM UTC 24
Finished Aug 25 06:50:58 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996822361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_genbits.2996822361
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/25.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/25.edn_intr.3144913291
Short name T419
Test name
Test status
Simulation time 66384620 ps
CPU time 1.05 seconds
Started Aug 25 06:50:28 AM UTC 24
Finished Aug 25 06:51:00 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144913291 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 25.edn_intr.3144913291
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/25.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/25.edn_smoke.3772407618
Short name T402
Test name
Test status
Simulation time 30487288 ps
CPU time 0.93 seconds
Started Aug 25 06:50:28 AM UTC 24
Finished Aug 25 06:50:30 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772407618 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 25.edn_smoke.3772407618
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/25.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/25.edn_stress_all.3093277673
Short name T428
Test name
Test status
Simulation time 87533152 ps
CPU time 2.22 seconds
Started Aug 25 06:50:28 AM UTC 24
Finished Aug 25 06:51:01 AM UTC 24
Peak memory 231504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093277673 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.3093277673
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/25.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/25.edn_stress_all_with_rand_reset.1636142568
Short name T242
Test name
Test status
Simulation time 6295743406 ps
CPU time 41.62 seconds
Started Aug 25 06:50:28 AM UTC 24
Finished Aug 25 06:51:41 AM UTC 24
Peak memory 229868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1636142568 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all
_with_rand_reset.1636142568
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/25.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/250.edn_genbits.3904595261
Short name T853
Test name
Test status
Simulation time 39846647 ps
CPU time 1.35 seconds
Started Aug 25 06:53:34 AM UTC 24
Finished Aug 25 06:53:36 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904595261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3904595261
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/250.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/251.edn_genbits.3160391720
Short name T349
Test name
Test status
Simulation time 49433578 ps
CPU time 1.73 seconds
Started Aug 25 06:53:34 AM UTC 24
Finished Aug 25 06:54:04 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160391720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 251.edn_genbits.3160391720
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/251.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/252.edn_genbits.4013856553
Short name T945
Test name
Test status
Simulation time 42418097 ps
CPU time 1.48 seconds
Started Aug 25 06:53:34 AM UTC 24
Finished Aug 25 06:54:04 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013856553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 252.edn_genbits.4013856553
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/252.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/253.edn_genbits.1814610320
Short name T946
Test name
Test status
Simulation time 67549975 ps
CPU time 1.37 seconds
Started Aug 25 06:53:34 AM UTC 24
Finished Aug 25 06:54:04 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814610320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 253.edn_genbits.1814610320
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/253.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/254.edn_genbits.2946102385
Short name T861
Test name
Test status
Simulation time 29600932 ps
CPU time 1.41 seconds
Started Aug 25 06:53:34 AM UTC 24
Finished Aug 25 06:53:37 AM UTC 24
Peak memory 230604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946102385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2946102385
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/254.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/255.edn_genbits.874286771
Short name T944
Test name
Test status
Simulation time 68332608 ps
CPU time 1.35 seconds
Started Aug 25 06:53:34 AM UTC 24
Finished Aug 25 06:54:04 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874286771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 255.edn_genbits.874286771
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/255.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/256.edn_genbits.1994658991
Short name T952
Test name
Test status
Simulation time 40524852 ps
CPU time 1.95 seconds
Started Aug 25 06:53:34 AM UTC 24
Finished Aug 25 06:54:04 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994658991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1994658991
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/256.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/257.edn_genbits.3307155110
Short name T949
Test name
Test status
Simulation time 74263333 ps
CPU time 1.61 seconds
Started Aug 25 06:53:34 AM UTC 24
Finished Aug 25 06:54:04 AM UTC 24
Peak memory 230392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307155110 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 257.edn_genbits.3307155110
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/257.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/258.edn_genbits.209645188
Short name T898
Test name
Test status
Simulation time 115631570 ps
CPU time 1.44 seconds
Started Aug 25 06:53:34 AM UTC 24
Finished Aug 25 06:53:37 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209645188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 258.edn_genbits.209645188
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/258.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/259.edn_genbits.2961649197
Short name T948
Test name
Test status
Simulation time 67529622 ps
CPU time 1.37 seconds
Started Aug 25 06:53:34 AM UTC 24
Finished Aug 25 06:54:04 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961649197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 259.edn_genbits.2961649197
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/259.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/26.edn_alert.669298324
Short name T138
Test name
Test status
Simulation time 27598424 ps
CPU time 1.09 seconds
Started Aug 25 06:50:29 AM UTC 24
Finished Aug 25 06:51:05 AM UTC 24
Peak memory 229984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669298324 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 26.edn_alert.669298324
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/26.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/26.edn_alert_test.2424618321
Short name T259
Test name
Test status
Simulation time 65107991 ps
CPU time 0.85 seconds
Started Aug 25 06:50:33 AM UTC 24
Finished Aug 25 06:50:56 AM UTC 24
Peak memory 226752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424618321 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2424618321
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/26.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/26.edn_disable.1694487596
Short name T235
Test name
Test status
Simulation time 11824191 ps
CPU time 0.93 seconds
Started Aug 25 06:50:31 AM UTC 24
Finished Aug 25 06:50:56 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694487596 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1694487596
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/26.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/26.edn_disable_auto_req_mode.1980909851
Short name T404
Test name
Test status
Simulation time 96847265 ps
CPU time 0.95 seconds
Started Aug 25 06:50:31 AM UTC 24
Finished Aug 25 06:50:36 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980909851 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable_auto_req_mode.1980909851
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/26.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/26.edn_err.3252018650
Short name T218
Test name
Test status
Simulation time 24749221 ps
CPU time 1.16 seconds
Started Aug 25 06:50:29 AM UTC 24
Finished Aug 25 06:51:01 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252018650 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 26.edn_err.3252018650
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/26.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/26.edn_genbits.4172425730
Short name T328
Test name
Test status
Simulation time 31623375 ps
CPU time 1.26 seconds
Started Aug 25 06:50:28 AM UTC 24
Finished Aug 25 06:51:01 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172425730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_genbits.4172425730
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/26.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/26.edn_intr.1365787413
Short name T426
Test name
Test status
Simulation time 37739510 ps
CPU time 1.23 seconds
Started Aug 25 06:50:29 AM UTC 24
Finished Aug 25 06:51:01 AM UTC 24
Peak memory 237404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365787413 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 26.edn_intr.1365787413
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/26.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/26.edn_smoke.1963558391
Short name T424
Test name
Test status
Simulation time 143568782 ps
CPU time 1.18 seconds
Started Aug 25 06:50:28 AM UTC 24
Finished Aug 25 06:51:01 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963558391 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 26.edn_smoke.1963558391
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/26.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/26.edn_stress_all.549289924
Short name T357
Test name
Test status
Simulation time 260043631 ps
CPU time 5.1 seconds
Started Aug 25 06:50:28 AM UTC 24
Finished Aug 25 06:51:05 AM UTC 24
Peak memory 227140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549289924 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.549289924
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/26.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/26.edn_stress_all_with_rand_reset.3109103203
Short name T256
Test name
Test status
Simulation time 4128576933 ps
CPU time 86.3 seconds
Started Aug 25 06:50:29 AM UTC 24
Finished Aug 25 06:52:31 AM UTC 24
Peak memory 230036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3109103203 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all
_with_rand_reset.3109103203
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/26.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/260.edn_genbits.839590358
Short name T956
Test name
Test status
Simulation time 50100933 ps
CPU time 1.68 seconds
Started Aug 25 06:53:34 AM UTC 24
Finished Aug 25 06:54:04 AM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839590358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 260.edn_genbits.839590358
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/260.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/261.edn_genbits.2056177313
Short name T958
Test name
Test status
Simulation time 43680245 ps
CPU time 1.6 seconds
Started Aug 25 06:53:34 AM UTC 24
Finished Aug 25 06:54:04 AM UTC 24
Peak memory 230096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056177313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 261.edn_genbits.2056177313
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/261.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/262.edn_genbits.340861522
Short name T953
Test name
Test status
Simulation time 87447317 ps
CPU time 1.48 seconds
Started Aug 25 06:53:34 AM UTC 24
Finished Aug 25 06:54:04 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340861522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 262.edn_genbits.340861522
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/262.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/263.edn_genbits.1004895943
Short name T969
Test name
Test status
Simulation time 37244653 ps
CPU time 1.91 seconds
Started Aug 25 06:53:34 AM UTC 24
Finished Aug 25 06:54:05 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004895943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1004895943
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/263.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/264.edn_genbits.861383663
Short name T960
Test name
Test status
Simulation time 127737423 ps
CPU time 1.61 seconds
Started Aug 25 06:53:34 AM UTC 24
Finished Aug 25 06:54:04 AM UTC 24
Peak memory 228188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861383663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 264.edn_genbits.861383663
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/264.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/265.edn_genbits.3297410163
Short name T964
Test name
Test status
Simulation time 36037146 ps
CPU time 1.84 seconds
Started Aug 25 06:53:34 AM UTC 24
Finished Aug 25 06:54:05 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297410163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3297410163
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/265.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/266.edn_genbits.2400619076
Short name T913
Test name
Test status
Simulation time 50855008 ps
CPU time 1.75 seconds
Started Aug 25 06:53:34 AM UTC 24
Finished Aug 25 06:53:37 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400619076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2400619076
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/266.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/267.edn_genbits.258799943
Short name T959
Test name
Test status
Simulation time 127709224 ps
CPU time 1.7 seconds
Started Aug 25 06:53:34 AM UTC 24
Finished Aug 25 06:54:04 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258799943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 267.edn_genbits.258799943
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/267.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/268.edn_genbits.4238776227
Short name T965
Test name
Test status
Simulation time 49424532 ps
CPU time 1.81 seconds
Started Aug 25 06:53:34 AM UTC 24
Finished Aug 25 06:54:05 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238776227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 268.edn_genbits.4238776227
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/268.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/269.edn_genbits.3897148824
Short name T961
Test name
Test status
Simulation time 70025189 ps
CPU time 1.58 seconds
Started Aug 25 06:53:34 AM UTC 24
Finished Aug 25 06:54:04 AM UTC 24
Peak memory 230308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897148824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3897148824
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/269.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/27.edn_alert.1906809905
Short name T423
Test name
Test status
Simulation time 53682091 ps
CPU time 1.83 seconds
Started Aug 25 06:50:57 AM UTC 24
Finished Aug 25 06:51:01 AM UTC 24
Peak memory 226356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906809905 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 27.edn_alert.1906809905
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/27.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/27.edn_alert_test.1669026301
Short name T421
Test name
Test status
Simulation time 17383669 ps
CPU time 1.32 seconds
Started Aug 25 06:50:57 AM UTC 24
Finished Aug 25 06:51:01 AM UTC 24
Peak memory 226728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669026301 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1669026301
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/27.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/27.edn_disable_auto_req_mode.3946798388
Short name T420
Test name
Test status
Simulation time 54506193 ps
CPU time 1.23 seconds
Started Aug 25 06:50:57 AM UTC 24
Finished Aug 25 06:51:01 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946798388 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable_auto_req_mode.3946798388
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/27.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/27.edn_err.120905741
Short name T222
Test name
Test status
Simulation time 132207784 ps
CPU time 1.52 seconds
Started Aug 25 06:50:57 AM UTC 24
Finished Aug 25 06:51:01 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120905741 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 27.edn_err.120905741
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/27.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/27.edn_genbits.2290074576
Short name T438
Test name
Test status
Simulation time 116205367 ps
CPU time 1.27 seconds
Started Aug 25 06:50:39 AM UTC 24
Finished Aug 25 06:51:11 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290074576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2290074576
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/27.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/27.edn_intr.3951500483
Short name T410
Test name
Test status
Simulation time 21072161 ps
CPU time 0.96 seconds
Started Aug 25 06:50:45 AM UTC 24
Finished Aug 25 06:50:57 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951500483 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 27.edn_intr.3951500483
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/27.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/27.edn_smoke.2095286863
Short name T260
Test name
Test status
Simulation time 44729311 ps
CPU time 0.81 seconds
Started Aug 25 06:50:37 AM UTC 24
Finished Aug 25 06:50:56 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095286863 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 27.edn_smoke.2095286863
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/27.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/27.edn_stress_all.3996016178
Short name T429
Test name
Test status
Simulation time 171671751 ps
CPU time 2.3 seconds
Started Aug 25 06:50:39 AM UTC 24
Finished Aug 25 06:51:02 AM UTC 24
Peak memory 229668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996016178 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3996016178
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/27.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/27.edn_stress_all_with_rand_reset.1702357379
Short name T245
Test name
Test status
Simulation time 2883948371 ps
CPU time 69.46 seconds
Started Aug 25 06:50:43 AM UTC 24
Finished Aug 25 06:52:05 AM UTC 24
Peak memory 229984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1702357379 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all
_with_rand_reset.1702357379
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/27.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/270.edn_genbits.1585360533
Short name T950
Test name
Test status
Simulation time 49470070 ps
CPU time 1.23 seconds
Started Aug 25 06:53:34 AM UTC 24
Finished Aug 25 06:54:04 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585360533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 270.edn_genbits.1585360533
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/270.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/271.edn_genbits.950272124
Short name T970
Test name
Test status
Simulation time 59922468 ps
CPU time 2.14 seconds
Started Aug 25 06:53:34 AM UTC 24
Finished Aug 25 06:54:05 AM UTC 24
Peak memory 229736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950272124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 271.edn_genbits.950272124
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/271.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/272.edn_genbits.1059841178
Short name T971
Test name
Test status
Simulation time 115112507 ps
CPU time 2.31 seconds
Started Aug 25 06:53:34 AM UTC 24
Finished Aug 25 06:54:05 AM UTC 24
Peak memory 231568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059841178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1059841178
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/272.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/273.edn_genbits.2694492137
Short name T963
Test name
Test status
Simulation time 53094203 ps
CPU time 1.45 seconds
Started Aug 25 06:53:34 AM UTC 24
Finished Aug 25 06:54:04 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694492137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2694492137
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/273.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/274.edn_genbits.1603699769
Short name T962
Test name
Test status
Simulation time 186042990 ps
CPU time 1.34 seconds
Started Aug 25 06:53:34 AM UTC 24
Finished Aug 25 06:54:04 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603699769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 274.edn_genbits.1603699769
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/274.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/275.edn_genbits.2809179938
Short name T968
Test name
Test status
Simulation time 124234147 ps
CPU time 1.64 seconds
Started Aug 25 06:53:34 AM UTC 24
Finished Aug 25 06:54:05 AM UTC 24
Peak memory 230612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809179938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2809179938
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/275.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/276.edn_genbits.3057735492
Short name T914
Test name
Test status
Simulation time 29419421 ps
CPU time 1.14 seconds
Started Aug 25 06:53:35 AM UTC 24
Finished Aug 25 06:53:38 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057735492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3057735492
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/276.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/277.edn_genbits.2958451338
Short name T932
Test name
Test status
Simulation time 39837143 ps
CPU time 1.27 seconds
Started Aug 25 06:53:37 AM UTC 24
Finished Aug 25 06:53:45 AM UTC 24
Peak memory 228556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958451338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2958451338
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/277.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/278.edn_genbits.3006718119
Short name T931
Test name
Test status
Simulation time 67154501 ps
CPU time 1.03 seconds
Started Aug 25 06:53:37 AM UTC 24
Finished Aug 25 06:53:45 AM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006718119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3006718119
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/278.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/279.edn_genbits.227262230
Short name T927
Test name
Test status
Simulation time 29101721 ps
CPU time 1.2 seconds
Started Aug 25 06:53:37 AM UTC 24
Finished Aug 25 06:53:42 AM UTC 24
Peak memory 230612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227262230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 279.edn_genbits.227262230
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/279.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/28.edn_alert.3632375595
Short name T476
Test name
Test status
Simulation time 147899492 ps
CPU time 1.58 seconds
Started Aug 25 06:51:00 AM UTC 24
Finished Aug 25 06:51:30 AM UTC 24
Peak memory 230440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632375595 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 28.edn_alert.3632375595
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/28.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/28.edn_alert_test.1139120642
Short name T469
Test name
Test status
Simulation time 15606232 ps
CPU time 1.29 seconds
Started Aug 25 06:51:00 AM UTC 24
Finished Aug 25 06:51:30 AM UTC 24
Peak memory 226912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139120642 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.1139120642
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/28.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/28.edn_disable.136507605
Short name T439
Test name
Test status
Simulation time 12208480 ps
CPU time 0.95 seconds
Started Aug 25 06:51:00 AM UTC 24
Finished Aug 25 06:51:15 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136507605 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.136507605
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/28.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/28.edn_disable_auto_req_mode.2768406330
Short name T468
Test name
Test status
Simulation time 112429018 ps
CPU time 1.33 seconds
Started Aug 25 06:51:00 AM UTC 24
Finished Aug 25 06:51:30 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768406330 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable_auto_req_mode.2768406330
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/28.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/28.edn_err.720198284
Short name T198
Test name
Test status
Simulation time 18937898 ps
CPU time 1.46 seconds
Started Aug 25 06:51:00 AM UTC 24
Finished Aug 25 06:51:30 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720198284 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 28.edn_err.720198284
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/28.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/28.edn_genbits.3393108650
Short name T91
Test name
Test status
Simulation time 41908881 ps
CPU time 1.67 seconds
Started Aug 25 06:50:57 AM UTC 24
Finished Aug 25 06:51:01 AM UTC 24
Peak memory 230612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393108650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3393108650
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/28.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/28.edn_intr.2060361274
Short name T464
Test name
Test status
Simulation time 39244787 ps
CPU time 1.02 seconds
Started Aug 25 06:50:59 AM UTC 24
Finished Aug 25 06:51:29 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060361274 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 28.edn_intr.2060361274
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/28.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/28.edn_smoke.63013352
Short name T422
Test name
Test status
Simulation time 38627574 ps
CPU time 1.31 seconds
Started Aug 25 06:50:57 AM UTC 24
Finished Aug 25 06:51:01 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63013352 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 28.edn_smoke.63013352
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/28.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/28.edn_stress_all.3464026021
Short name T266
Test name
Test status
Simulation time 815122006 ps
CPU time 4.54 seconds
Started Aug 25 06:50:57 AM UTC 24
Finished Aug 25 06:51:04 AM UTC 24
Peak memory 227380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464026021 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3464026021
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/28.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/28.edn_stress_all_with_rand_reset.774029802
Short name T743
Test name
Test status
Simulation time 3640596519 ps
CPU time 80.1 seconds
Started Aug 25 06:50:59 AM UTC 24
Finished Aug 25 06:52:49 AM UTC 24
Peak memory 229800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=774029802 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_
with_rand_reset.774029802
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/28.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/280.edn_genbits.1989818500
Short name T929
Test name
Test status
Simulation time 55382984 ps
CPU time 1.16 seconds
Started Aug 25 06:53:37 AM UTC 24
Finished Aug 25 06:53:42 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989818500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1989818500
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/280.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/281.edn_genbits.683437616
Short name T928
Test name
Test status
Simulation time 138754035 ps
CPU time 1.1 seconds
Started Aug 25 06:53:37 AM UTC 24
Finished Aug 25 06:53:42 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683437616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 281.edn_genbits.683437616
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/281.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/282.edn_genbits.3147184437
Short name T939
Test name
Test status
Simulation time 39373599 ps
CPU time 1.58 seconds
Started Aug 25 06:53:37 AM UTC 24
Finished Aug 25 06:54:02 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147184437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3147184437
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/282.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/283.edn_genbits.3539234301
Short name T941
Test name
Test status
Simulation time 41237177 ps
CPU time 1.56 seconds
Started Aug 25 06:53:37 AM UTC 24
Finished Aug 25 06:54:03 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539234301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 283.edn_genbits.3539234301
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/283.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/284.edn_genbits.2721504387
Short name T933
Test name
Test status
Simulation time 36009849 ps
CPU time 1.24 seconds
Started Aug 25 06:53:37 AM UTC 24
Finished Aug 25 06:53:45 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721504387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2721504387
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/284.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/285.edn_genbits.1097459364
Short name T921
Test name
Test status
Simulation time 45893351 ps
CPU time 1.6 seconds
Started Aug 25 06:53:37 AM UTC 24
Finished Aug 25 06:53:41 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097459364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 285.edn_genbits.1097459364
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/285.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/286.edn_genbits.1984790977
Short name T938
Test name
Test status
Simulation time 49777558 ps
CPU time 1.29 seconds
Started Aug 25 06:53:37 AM UTC 24
Finished Aug 25 06:54:02 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984790977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 286.edn_genbits.1984790977
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/286.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/287.edn_genbits.2126729621
Short name T937
Test name
Test status
Simulation time 69410749 ps
CPU time 1.1 seconds
Started Aug 25 06:53:37 AM UTC 24
Finished Aug 25 06:54:02 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126729621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2126729621
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/287.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/288.edn_genbits.1885592319
Short name T926
Test name
Test status
Simulation time 164121182 ps
CPU time 2.96 seconds
Started Aug 25 06:53:37 AM UTC 24
Finished Aug 25 06:53:42 AM UTC 24
Peak memory 231580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885592319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 288.edn_genbits.1885592319
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/288.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/289.edn_genbits.144379646
Short name T935
Test name
Test status
Simulation time 100419095 ps
CPU time 0.95 seconds
Started Aug 25 06:53:37 AM UTC 24
Finished Aug 25 06:54:02 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144379646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 289.edn_genbits.144379646
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/289.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/29.edn_alert.3687232906
Short name T480
Test name
Test status
Simulation time 26961143 ps
CPU time 1.6 seconds
Started Aug 25 06:51:00 AM UTC 24
Finished Aug 25 06:51:31 AM UTC 24
Peak memory 230224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687232906 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 29.edn_alert.3687232906
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/29.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/29.edn_alert_test.1633668562
Short name T478
Test name
Test status
Simulation time 28361264 ps
CPU time 1.15 seconds
Started Aug 25 06:51:00 AM UTC 24
Finished Aug 25 06:51:30 AM UTC 24
Peak memory 216752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633668562 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1633668562
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/29.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/29.edn_disable.172056578
Short name T408
Test name
Test status
Simulation time 12766561 ps
CPU time 0.94 seconds
Started Aug 25 06:51:00 AM UTC 24
Finished Aug 25 06:51:25 AM UTC 24
Peak memory 216132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172056578 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.172056578
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/29.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/29.edn_disable_auto_req_mode.1742980257
Short name T477
Test name
Test status
Simulation time 60524972 ps
CPU time 1.32 seconds
Started Aug 25 06:51:00 AM UTC 24
Finished Aug 25 06:51:30 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742980257 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable_auto_req_mode.1742980257
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/29.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/29.edn_err.3050874132
Short name T163
Test name
Test status
Simulation time 146771639 ps
CPU time 1.17 seconds
Started Aug 25 06:51:00 AM UTC 24
Finished Aug 25 06:51:15 AM UTC 24
Peak memory 236812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050874132 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 29.edn_err.3050874132
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/29.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/29.edn_genbits.3424499841
Short name T481
Test name
Test status
Simulation time 52211496 ps
CPU time 2.04 seconds
Started Aug 25 06:51:00 AM UTC 24
Finished Aug 25 06:51:31 AM UTC 24
Peak memory 229532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424499841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3424499841
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/29.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/29.edn_intr.2429574792
Short name T104
Test name
Test status
Simulation time 20337286 ps
CPU time 1.17 seconds
Started Aug 25 06:51:00 AM UTC 24
Finished Aug 25 06:51:30 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429574792 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 29.edn_intr.2429574792
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/29.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/29.edn_smoke.1716872257
Short name T472
Test name
Test status
Simulation time 16706177 ps
CPU time 1.34 seconds
Started Aug 25 06:51:00 AM UTC 24
Finished Aug 25 06:51:30 AM UTC 24
Peak memory 226208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716872257 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 29.edn_smoke.1716872257
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/29.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/29.edn_stress_all.4166100242
Short name T491
Test name
Test status
Simulation time 255644394 ps
CPU time 3.66 seconds
Started Aug 25 06:51:00 AM UTC 24
Finished Aug 25 06:51:32 AM UTC 24
Peak memory 229540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166100242 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.4166100242
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/29.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/290.edn_genbits.3744246611
Short name T936
Test name
Test status
Simulation time 50869814 ps
CPU time 0.99 seconds
Started Aug 25 06:53:37 AM UTC 24
Finished Aug 25 06:54:02 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744246611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 290.edn_genbits.3744246611
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/290.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/291.edn_genbits.2413424898
Short name T940
Test name
Test status
Simulation time 27608858 ps
CPU time 1.25 seconds
Started Aug 25 06:53:37 AM UTC 24
Finished Aug 25 06:54:03 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413424898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2413424898
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/291.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/292.edn_genbits.1335003494
Short name T930
Test name
Test status
Simulation time 74104446 ps
CPU time 2.16 seconds
Started Aug 25 06:53:38 AM UTC 24
Finished Aug 25 06:53:42 AM UTC 24
Peak memory 231576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335003494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 292.edn_genbits.1335003494
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/292.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/293.edn_genbits.3524222571
Short name T923
Test name
Test status
Simulation time 288326648 ps
CPU time 1.03 seconds
Started Aug 25 06:53:38 AM UTC 24
Finished Aug 25 06:53:41 AM UTC 24
Peak memory 228008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524222571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 293.edn_genbits.3524222571
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/293.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/294.edn_genbits.1668551807
Short name T919
Test name
Test status
Simulation time 37916950 ps
CPU time 1.27 seconds
Started Aug 25 06:53:38 AM UTC 24
Finished Aug 25 06:53:40 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668551807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1668551807
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/294.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/295.edn_genbits.3112204113
Short name T917
Test name
Test status
Simulation time 64603393 ps
CPU time 0.84 seconds
Started Aug 25 06:53:38 AM UTC 24
Finished Aug 25 06:53:40 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112204113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 295.edn_genbits.3112204113
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/295.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/296.edn_genbits.4076188739
Short name T924
Test name
Test status
Simulation time 81543187 ps
CPU time 1.15 seconds
Started Aug 25 06:53:38 AM UTC 24
Finished Aug 25 06:53:41 AM UTC 24
Peak memory 230012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076188739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 296.edn_genbits.4076188739
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/296.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/297.edn_genbits.849985694
Short name T918
Test name
Test status
Simulation time 72643712 ps
CPU time 0.99 seconds
Started Aug 25 06:53:38 AM UTC 24
Finished Aug 25 06:53:40 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849985694 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 297.edn_genbits.849985694
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/297.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/298.edn_genbits.603729119
Short name T922
Test name
Test status
Simulation time 41736937 ps
CPU time 1.64 seconds
Started Aug 25 06:53:38 AM UTC 24
Finished Aug 25 06:53:41 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603729119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 298.edn_genbits.603729119
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/298.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/299.edn_genbits.3424137525
Short name T920
Test name
Test status
Simulation time 58515915 ps
CPU time 1.08 seconds
Started Aug 25 06:53:38 AM UTC 24
Finished Aug 25 06:53:40 AM UTC 24
Peak memory 230600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424137525 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3424137525
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/299.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/3.edn_alert_test.3753101659
Short name T71
Test name
Test status
Simulation time 15370365 ps
CPU time 0.82 seconds
Started Aug 25 06:49:55 AM UTC 24
Finished Aug 25 06:49:57 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753101659 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3753101659
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/3.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/3.edn_disable.139189163
Short name T57
Test name
Test status
Simulation time 11585212 ps
CPU time 1.07 seconds
Started Aug 25 06:49:54 AM UTC 24
Finished Aug 25 06:49:56 AM UTC 24
Peak memory 224700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139189163 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.139189163
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/3.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/3.edn_disable_auto_req_mode.1068081656
Short name T12
Test name
Test status
Simulation time 117003989 ps
CPU time 1.02 seconds
Started Aug 25 06:49:54 AM UTC 24
Finished Aug 25 06:49:56 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068081656 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable_auto_req_mode.1068081656
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/3.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/3.edn_err.2685635706
Short name T17
Test name
Test status
Simulation time 19401999 ps
CPU time 1.09 seconds
Started Aug 25 06:49:54 AM UTC 24
Finished Aug 25 06:49:56 AM UTC 24
Peak memory 237088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685635706 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 3.edn_err.2685635706
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/3.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/3.edn_intr.2289086302
Short name T58
Test name
Test status
Simulation time 21701113 ps
CPU time 1.18 seconds
Started Aug 25 06:49:53 AM UTC 24
Finished Aug 25 06:49:56 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289086302 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 3.edn_intr.2289086302
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/3.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/3.edn_regwen.21495329
Short name T27
Test name
Test status
Simulation time 52428151 ps
CPU time 1.09 seconds
Started Aug 25 06:49:53 AM UTC 24
Finished Aug 25 06:49:56 AM UTC 24
Peak memory 216012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21495329 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 3.edn_regwen.21495329
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/3.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/3.edn_sec_cm.147453153
Short name T65
Test name
Test status
Simulation time 517792186 ps
CPU time 4.11 seconds
Started Aug 25 06:49:55 AM UTC 24
Finished Aug 25 06:50:01 AM UTC 24
Peak memory 260576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147453153 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.147453153
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/3.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/3.edn_smoke.4068286181
Short name T38
Test name
Test status
Simulation time 67644506 ps
CPU time 0.94 seconds
Started Aug 25 06:49:53 AM UTC 24
Finished Aug 25 06:49:56 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068286181 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 3.edn_smoke.4068286181
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/3.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/3.edn_stress_all_with_rand_reset.2918029801
Short name T41
Test name
Test status
Simulation time 7271510785 ps
CPU time 77.81 seconds
Started Aug 25 06:49:53 AM UTC 24
Finished Aug 25 06:51:13 AM UTC 24
Peak memory 234040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2918029801 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_
with_rand_reset.2918029801
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/3.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/30.edn_alert.2778231831
Short name T176
Test name
Test status
Simulation time 25596074 ps
CPU time 1.31 seconds
Started Aug 25 06:51:03 AM UTC 24
Finished Aug 25 06:51:26 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778231831 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 30.edn_alert.2778231831
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/30.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/30.edn_alert_test.804063303
Short name T446
Test name
Test status
Simulation time 34715442 ps
CPU time 0.89 seconds
Started Aug 25 06:51:03 AM UTC 24
Finished Aug 25 06:51:26 AM UTC 24
Peak memory 216268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804063303 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.804063303
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/30.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/30.edn_disable_auto_req_mode.3560089862
Short name T448
Test name
Test status
Simulation time 24927749 ps
CPU time 1.47 seconds
Started Aug 25 06:51:03 AM UTC 24
Finished Aug 25 06:51:26 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560089862 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable_auto_req_mode.3560089862
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/30.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/30.edn_err.2880378853
Short name T187
Test name
Test status
Simulation time 23847217 ps
CPU time 1.21 seconds
Started Aug 25 06:51:03 AM UTC 24
Finished Aug 25 06:51:26 AM UTC 24
Peak memory 236948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880378853 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 30.edn_err.2880378853
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/30.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/30.edn_genbits.2490005904
Short name T313
Test name
Test status
Simulation time 46894130 ps
CPU time 1.29 seconds
Started Aug 25 06:51:00 AM UTC 24
Finished Aug 25 06:51:06 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490005904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2490005904
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/30.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/30.edn_intr.2563674182
Short name T445
Test name
Test status
Simulation time 34509090 ps
CPU time 1 seconds
Started Aug 25 06:51:02 AM UTC 24
Finished Aug 25 06:51:26 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563674182 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 30.edn_intr.2563674182
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/30.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/30.edn_smoke.907910883
Short name T430
Test name
Test status
Simulation time 29445028 ps
CPU time 1.06 seconds
Started Aug 25 06:51:00 AM UTC 24
Finished Aug 25 06:51:05 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907910883 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 30.edn_smoke.907910883
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/30.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/30.edn_stress_all.2006763
Short name T461
Test name
Test status
Simulation time 170202295 ps
CPU time 3.99 seconds
Started Aug 25 06:51:02 AM UTC 24
Finished Aug 25 06:51:29 AM UTC 24
Peak memory 229644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006763 -assert nopostproc +UVM_TESTNAME=edn_st
ress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.2006763
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/30.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/31.edn_alert.44252919
Short name T452
Test name
Test status
Simulation time 54459361 ps
CPU time 1.73 seconds
Started Aug 25 06:51:03 AM UTC 24
Finished Aug 25 06:51:27 AM UTC 24
Peak memory 226356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44252919 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 31.edn_alert.44252919
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/31.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/31.edn_alert_test.1573892685
Short name T449
Test name
Test status
Simulation time 15963477 ps
CPU time 1.14 seconds
Started Aug 25 06:51:03 AM UTC 24
Finished Aug 25 06:51:26 AM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573892685 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.1573892685
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/31.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/31.edn_disable.625988595
Short name T431
Test name
Test status
Simulation time 36264311 ps
CPU time 0.88 seconds
Started Aug 25 06:51:03 AM UTC 24
Finished Aug 25 06:51:06 AM UTC 24
Peak memory 216132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625988595 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.625988595
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/31.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/31.edn_disable_auto_req_mode.2662101512
Short name T432
Test name
Test status
Simulation time 43859034 ps
CPU time 0.98 seconds
Started Aug 25 06:51:03 AM UTC 24
Finished Aug 25 06:51:06 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662101512 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable_auto_req_mode.2662101512
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/31.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/31.edn_err.1243347759
Short name T440
Test name
Test status
Simulation time 51970455 ps
CPU time 0.94 seconds
Started Aug 25 06:51:03 AM UTC 24
Finished Aug 25 06:51:15 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243347759 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 31.edn_err.1243347759
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/31.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/31.edn_genbits.23726638
Short name T434
Test name
Test status
Simulation time 93029853 ps
CPU time 1.42 seconds
Started Aug 25 06:51:03 AM UTC 24
Finished Aug 25 06:51:06 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23726638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 31.edn_genbits.23726638
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/31.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/31.edn_intr.3662884016
Short name T447
Test name
Test status
Simulation time 27496586 ps
CPU time 1.06 seconds
Started Aug 25 06:51:03 AM UTC 24
Finished Aug 25 06:51:26 AM UTC 24
Peak memory 226324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662884016 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 31.edn_intr.3662884016
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/31.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/31.edn_smoke.3973380162
Short name T433
Test name
Test status
Simulation time 34488053 ps
CPU time 1.24 seconds
Started Aug 25 06:51:03 AM UTC 24
Finished Aug 25 06:51:06 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973380162 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 31.edn_smoke.3973380162
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/31.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/31.edn_stress_all.3802574716
Short name T454
Test name
Test status
Simulation time 696515598 ps
CPU time 2.34 seconds
Started Aug 25 06:51:03 AM UTC 24
Finished Aug 25 06:51:27 AM UTC 24
Peak memory 227524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802574716 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3802574716
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/31.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/32.edn_alert.921139771
Short name T441
Test name
Test status
Simulation time 47592291 ps
CPU time 1.06 seconds
Started Aug 25 06:51:03 AM UTC 24
Finished Aug 25 06:51:15 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921139771 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 32.edn_alert.921139771
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/32.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/32.edn_alert_test.970650121
Short name T435
Test name
Test status
Simulation time 13496985 ps
CPU time 0.93 seconds
Started Aug 25 06:51:05 AM UTC 24
Finished Aug 25 06:51:07 AM UTC 24
Peak memory 216688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970650121 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.970650121
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/32.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/32.edn_disable.3771756601
Short name T239
Test name
Test status
Simulation time 21525319 ps
CPU time 0.98 seconds
Started Aug 25 06:51:05 AM UTC 24
Finished Aug 25 06:51:11 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771756601 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3771756601
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/32.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/32.edn_disable_auto_req_mode.1019952063
Short name T443
Test name
Test status
Simulation time 51544373 ps
CPU time 1.3 seconds
Started Aug 25 06:51:05 AM UTC 24
Finished Aug 25 06:51:21 AM UTC 24
Peak memory 230340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019952063 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable_auto_req_mode.1019952063
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/32.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/32.edn_err.3486992346
Short name T190
Test name
Test status
Simulation time 23219758 ps
CPU time 0.87 seconds
Started Aug 25 06:51:03 AM UTC 24
Finished Aug 25 06:51:05 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486992346 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 32.edn_err.3486992346
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/32.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/32.edn_genbits.2344663224
Short name T453
Test name
Test status
Simulation time 46519766 ps
CPU time 1.52 seconds
Started Aug 25 06:51:03 AM UTC 24
Finished Aug 25 06:51:27 AM UTC 24
Peak memory 228640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344663224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2344663224
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/32.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/32.edn_intr.3360092964
Short name T437
Test name
Test status
Simulation time 29186511 ps
CPU time 1 seconds
Started Aug 25 06:51:03 AM UTC 24
Finished Aug 25 06:51:25 AM UTC 24
Peak memory 237344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360092964 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 32.edn_intr.3360092964
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/32.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/32.edn_smoke.2757626401
Short name T450
Test name
Test status
Simulation time 51879432 ps
CPU time 1.15 seconds
Started Aug 25 06:51:03 AM UTC 24
Finished Aug 25 06:51:26 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757626401 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 32.edn_smoke.2757626401
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/32.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/32.edn_stress_all.2798534692
Short name T456
Test name
Test status
Simulation time 660254496 ps
CPU time 2.48 seconds
Started Aug 25 06:51:03 AM UTC 24
Finished Aug 25 06:51:28 AM UTC 24
Peak memory 227648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798534692 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.2798534692
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/32.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/33.edn_alert.944275643
Short name T270
Test name
Test status
Simulation time 49176488 ps
CPU time 1.31 seconds
Started Aug 25 06:51:08 AM UTC 24
Finished Aug 25 06:51:27 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944275643 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 33.edn_alert.944275643
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/33.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/33.edn_alert_test.3387689926
Short name T458
Test name
Test status
Simulation time 19715620 ps
CPU time 0.93 seconds
Started Aug 25 06:51:08 AM UTC 24
Finished Aug 25 06:51:28 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387689926 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.3387689926
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/33.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/33.edn_disable_auto_req_mode.2887192926
Short name T459
Test name
Test status
Simulation time 66280420 ps
CPU time 1.51 seconds
Started Aug 25 06:51:08 AM UTC 24
Finished Aug 25 06:51:29 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887192926 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable_auto_req_mode.2887192926
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/33.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/33.edn_err.3784911467
Short name T460
Test name
Test status
Simulation time 111084958 ps
CPU time 1.72 seconds
Started Aug 25 06:51:08 AM UTC 24
Finished Aug 25 06:51:29 AM UTC 24
Peak memory 242144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784911467 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 33.edn_err.3784911467
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/33.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/33.edn_genbits.816410823
Short name T329
Test name
Test status
Simulation time 126430160 ps
CPU time 1.32 seconds
Started Aug 25 06:51:08 AM UTC 24
Finished Aug 25 06:51:28 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816410823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.edn_genbits.816410823
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/33.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/33.edn_intr.102756538
Short name T451
Test name
Test status
Simulation time 39806731 ps
CPU time 0.87 seconds
Started Aug 25 06:51:08 AM UTC 24
Finished Aug 25 06:51:27 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102756538 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 33.edn_intr.102756538
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/33.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/33.edn_smoke.946994777
Short name T442
Test name
Test status
Simulation time 36953048 ps
CPU time 0.86 seconds
Started Aug 25 06:51:05 AM UTC 24
Finished Aug 25 06:51:20 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946994777 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 33.edn_smoke.946994777
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/33.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/33.edn_stress_all.3712109715
Short name T267
Test name
Test status
Simulation time 189246685 ps
CPU time 1.68 seconds
Started Aug 25 06:51:08 AM UTC 24
Finished Aug 25 06:51:28 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712109715 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3712109715
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/33.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/33.edn_stress_all_with_rand_reset.1242047565
Short name T798
Test name
Test status
Simulation time 57100313337 ps
CPU time 100.16 seconds
Started Aug 25 06:51:08 AM UTC 24
Finished Aug 25 06:53:08 AM UTC 24
Peak memory 232060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1242047565 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all
_with_rand_reset.1242047565
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/33.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/34.edn_alert.617506722
Short name T216
Test name
Test status
Simulation time 29736656 ps
CPU time 1.55 seconds
Started Aug 25 06:51:14 AM UTC 24
Finished Aug 25 06:51:27 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617506722 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 34.edn_alert.617506722
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/34.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/34.edn_alert_test.2204350114
Short name T262
Test name
Test status
Simulation time 56632112 ps
CPU time 1.21 seconds
Started Aug 25 06:51:16 AM UTC 24
Finished Aug 25 06:51:26 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204350114 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.2204350114
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/34.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/34.edn_disable.3550261013
Short name T199
Test name
Test status
Simulation time 19536270 ps
CPU time 0.76 seconds
Started Aug 25 06:51:16 AM UTC 24
Finished Aug 25 06:51:25 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550261013 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3550261013
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/34.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/34.edn_disable_auto_req_mode.3672567380
Short name T142
Test name
Test status
Simulation time 93225813 ps
CPU time 1.1 seconds
Started Aug 25 06:51:16 AM UTC 24
Finished Aug 25 06:51:25 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672567380 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable_auto_req_mode.3672567380
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/34.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/34.edn_err.733772065
Short name T183
Test name
Test status
Simulation time 21369459 ps
CPU time 0.92 seconds
Started Aug 25 06:51:16 AM UTC 24
Finished Aug 25 06:51:25 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733772065 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 34.edn_err.733772065
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/34.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/34.edn_genbits.3610421370
Short name T455
Test name
Test status
Simulation time 43569528 ps
CPU time 1.48 seconds
Started Aug 25 06:51:12 AM UTC 24
Finished Aug 25 06:51:28 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610421370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3610421370
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/34.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/34.edn_intr.1075148152
Short name T102
Test name
Test status
Simulation time 26544922 ps
CPU time 0.97 seconds
Started Aug 25 06:51:12 AM UTC 24
Finished Aug 25 06:51:15 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075148152 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 34.edn_intr.1075148152
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/34.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/34.edn_smoke.2118584723
Short name T436
Test name
Test status
Simulation time 17901273 ps
CPU time 0.95 seconds
Started Aug 25 06:51:08 AM UTC 24
Finished Aug 25 06:51:10 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118584723 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 34.edn_smoke.2118584723
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/34.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/34.edn_stress_all.2579964493
Short name T488
Test name
Test status
Simulation time 424596073 ps
CPU time 4.71 seconds
Started Aug 25 06:51:12 AM UTC 24
Finished Aug 25 06:51:32 AM UTC 24
Peak memory 227612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579964493 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.2579964493
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/34.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/35.edn_alert.1192969762
Short name T474
Test name
Test status
Simulation time 78486250 ps
CPU time 1.67 seconds
Started Aug 25 06:51:27 AM UTC 24
Finished Aug 25 06:51:30 AM UTC 24
Peak memory 228412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192969762 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 35.edn_alert.1192969762
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/35.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/35.edn_alert_test.2599915080
Short name T470
Test name
Test status
Simulation time 21914263 ps
CPU time 1.15 seconds
Started Aug 25 06:51:27 AM UTC 24
Finished Aug 25 06:51:30 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599915080 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.2599915080
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/35.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/35.edn_disable.1024604251
Short name T465
Test name
Test status
Simulation time 40459437 ps
CPU time 1.22 seconds
Started Aug 25 06:51:27 AM UTC 24
Finished Aug 25 06:51:30 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024604251 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1024604251
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/35.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/35.edn_disable_auto_req_mode.562146049
Short name T467
Test name
Test status
Simulation time 39788900 ps
CPU time 1.27 seconds
Started Aug 25 06:51:27 AM UTC 24
Finished Aug 25 06:51:30 AM UTC 24
Peak memory 230348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562146049 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable_auto_req_mode.562146049
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/35.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/35.edn_err.3749962144
Short name T466
Test name
Test status
Simulation time 120767881 ps
CPU time 1.46 seconds
Started Aug 25 06:51:27 AM UTC 24
Finished Aug 25 06:51:30 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749962144 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 35.edn_err.3749962144
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/35.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/35.edn_genbits.3080277875
Short name T356
Test name
Test status
Simulation time 39607245 ps
CPU time 1.05 seconds
Started Aug 25 06:51:22 AM UTC 24
Finished Aug 25 06:51:26 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080277875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3080277875
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/35.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/35.edn_intr.1028756198
Short name T462
Test name
Test status
Simulation time 24833618 ps
CPU time 1.11 seconds
Started Aug 25 06:51:27 AM UTC 24
Finished Aug 25 06:51:29 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028756198 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 35.edn_intr.1028756198
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/35.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/35.edn_smoke.1568260327
Short name T444
Test name
Test status
Simulation time 17379542 ps
CPU time 1.11 seconds
Started Aug 25 06:51:16 AM UTC 24
Finished Aug 25 06:51:25 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568260327 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 35.edn_smoke.1568260327
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/35.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/35.edn_stress_all.1872677093
Short name T463
Test name
Test status
Simulation time 1110285630 ps
CPU time 4.4 seconds
Started Aug 25 06:51:22 AM UTC 24
Finished Aug 25 06:51:29 AM UTC 24
Peak memory 229528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872677093 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1872677093
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/35.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/35.edn_stress_all_with_rand_reset.4181680718
Short name T799
Test name
Test status
Simulation time 15863567915 ps
CPU time 100.17 seconds
Started Aug 25 06:51:26 AM UTC 24
Finished Aug 25 06:53:10 AM UTC 24
Peak memory 229684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=4181680718 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all
_with_rand_reset.4181680718
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/35.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/36.edn_alert.2089388446
Short name T320
Test name
Test status
Simulation time 22681754 ps
CPU time 1.41 seconds
Started Aug 25 06:51:27 AM UTC 24
Finished Aug 25 06:51:30 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089388446 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 36.edn_alert.2089388446
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/36.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/36.edn_alert_test.467347995
Short name T482
Test name
Test status
Simulation time 37185479 ps
CPU time 1.22 seconds
Started Aug 25 06:51:29 AM UTC 24
Finished Aug 25 06:51:32 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467347995 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.467347995
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/36.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/36.edn_err.2459225116
Short name T166
Test name
Test status
Simulation time 26104805 ps
CPU time 1.44 seconds
Started Aug 25 06:51:27 AM UTC 24
Finished Aug 25 06:51:30 AM UTC 24
Peak memory 243916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459225116 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 36.edn_err.2459225116
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/36.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/36.edn_genbits.4119384330
Short name T475
Test name
Test status
Simulation time 49124917 ps
CPU time 1.46 seconds
Started Aug 25 06:51:27 AM UTC 24
Finished Aug 25 06:51:30 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119384330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_genbits.4119384330
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/36.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/36.edn_intr.3707721039
Short name T471
Test name
Test status
Simulation time 29431537 ps
CPU time 1.04 seconds
Started Aug 25 06:51:27 AM UTC 24
Finished Aug 25 06:51:30 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707721039 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 36.edn_intr.3707721039
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/36.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/36.edn_smoke.3726715726
Short name T473
Test name
Test status
Simulation time 42590265 ps
CPU time 1.22 seconds
Started Aug 25 06:51:27 AM UTC 24
Finished Aug 25 06:51:30 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726715726 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 36.edn_smoke.3726715726
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/36.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/36.edn_stress_all.3378925438
Short name T493
Test name
Test status
Simulation time 579201456 ps
CPU time 4.01 seconds
Started Aug 25 06:51:27 AM UTC 24
Finished Aug 25 06:51:33 AM UTC 24
Peak memory 227464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378925438 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.3378925438
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/36.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/36.edn_stress_all_with_rand_reset.1931290616
Short name T244
Test name
Test status
Simulation time 1403367939 ps
CPU time 30.78 seconds
Started Aug 25 06:51:27 AM UTC 24
Finished Aug 25 06:52:00 AM UTC 24
Peak memory 229648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1931290616 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all
_with_rand_reset.1931290616
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/36.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/37.edn_alert.1394568476
Short name T490
Test name
Test status
Simulation time 27958835 ps
CPU time 1.69 seconds
Started Aug 25 06:51:29 AM UTC 24
Finished Aug 25 06:51:32 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394568476 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 37.edn_alert.1394568476
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/37.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/37.edn_alert_test.1267468370
Short name T486
Test name
Test status
Simulation time 22404492 ps
CPU time 1.17 seconds
Started Aug 25 06:51:30 AM UTC 24
Finished Aug 25 06:51:32 AM UTC 24
Peak memory 216988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267468370 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.1267468370
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/37.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/37.edn_disable.3806902967
Short name T485
Test name
Test status
Simulation time 35732043 ps
CPU time 1.23 seconds
Started Aug 25 06:51:29 AM UTC 24
Finished Aug 25 06:51:32 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806902967 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.3806902967
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/37.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/37.edn_disable_auto_req_mode.3745836057
Short name T492
Test name
Test status
Simulation time 24456006 ps
CPU time 1.57 seconds
Started Aug 25 06:51:30 AM UTC 24
Finished Aug 25 06:51:33 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745836057 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable_auto_req_mode.3745836057
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/37.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/37.edn_err.836795061
Short name T484
Test name
Test status
Simulation time 64768786 ps
CPU time 1.25 seconds
Started Aug 25 06:51:29 AM UTC 24
Finished Aug 25 06:51:32 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836795061 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 37.edn_err.836795061
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/37.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/37.edn_genbits.1088332770
Short name T311
Test name
Test status
Simulation time 62858005 ps
CPU time 1.38 seconds
Started Aug 25 06:51:29 AM UTC 24
Finished Aug 25 06:51:32 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088332770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1088332770
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/37.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/37.edn_intr.1527980407
Short name T101
Test name
Test status
Simulation time 34187423 ps
CPU time 1.19 seconds
Started Aug 25 06:51:29 AM UTC 24
Finished Aug 25 06:51:32 AM UTC 24
Peak memory 228548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527980407 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 37.edn_intr.1527980407
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/37.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/37.edn_smoke.3631944127
Short name T483
Test name
Test status
Simulation time 17925454 ps
CPU time 1.48 seconds
Started Aug 25 06:51:29 AM UTC 24
Finished Aug 25 06:51:32 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631944127 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 37.edn_smoke.3631944127
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/37.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/37.edn_stress_all.115190306
Short name T501
Test name
Test status
Simulation time 542208642 ps
CPU time 6.74 seconds
Started Aug 25 06:51:29 AM UTC 24
Finished Aug 25 06:51:37 AM UTC 24
Peak memory 229524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115190306 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.115190306
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/37.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/37.edn_stress_all_with_rand_reset.662673643
Short name T243
Test name
Test status
Simulation time 778223027 ps
CPU time 19.48 seconds
Started Aug 25 06:51:29 AM UTC 24
Finished Aug 25 06:51:50 AM UTC 24
Peak memory 229732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=662673643 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_
with_rand_reset.662673643
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/37.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/38.edn_alert.945142173
Short name T204
Test name
Test status
Simulation time 95503867 ps
CPU time 1.77 seconds
Started Aug 25 06:51:30 AM UTC 24
Finished Aug 25 06:51:33 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945142173 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 38.edn_alert.945142173
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/38.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/38.edn_alert_test.1896129641
Short name T498
Test name
Test status
Simulation time 18053899 ps
CPU time 1.38 seconds
Started Aug 25 06:51:31 AM UTC 24
Finished Aug 25 06:51:34 AM UTC 24
Peak memory 217184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896129641 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1896129641
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/38.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/38.edn_disable.4235358618
Short name T494
Test name
Test status
Simulation time 46111862 ps
CPU time 1.01 seconds
Started Aug 25 06:51:31 AM UTC 24
Finished Aug 25 06:51:33 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235358618 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.4235358618
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/38.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/38.edn_disable_auto_req_mode.3632628796
Short name T226
Test name
Test status
Simulation time 32761993 ps
CPU time 1.77 seconds
Started Aug 25 06:51:31 AM UTC 24
Finished Aug 25 06:51:34 AM UTC 24
Peak memory 226228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632628796 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable_auto_req_mode.3632628796
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/38.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/38.edn_err.1941652409
Short name T223
Test name
Test status
Simulation time 24828053 ps
CPU time 1.38 seconds
Started Aug 25 06:51:31 AM UTC 24
Finished Aug 25 06:51:34 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941652409 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 38.edn_err.1941652409
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/38.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/38.edn_genbits.4125268185
Short name T15
Test name
Test status
Simulation time 44247397 ps
CPU time 1.57 seconds
Started Aug 25 06:51:30 AM UTC 24
Finished Aug 25 06:51:33 AM UTC 24
Peak memory 230632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125268185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_genbits.4125268185
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/38.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/38.edn_intr.3528464101
Short name T487
Test name
Test status
Simulation time 34947273 ps
CPU time 1.06 seconds
Started Aug 25 06:51:30 AM UTC 24
Finished Aug 25 06:51:32 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528464101 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 38.edn_intr.3528464101
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/38.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/38.edn_smoke.2960781884
Short name T489
Test name
Test status
Simulation time 15303798 ps
CPU time 1.42 seconds
Started Aug 25 06:51:30 AM UTC 24
Finished Aug 25 06:51:32 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960781884 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 38.edn_smoke.2960781884
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/38.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/38.edn_stress_all.984322404
Short name T509
Test name
Test status
Simulation time 297956288 ps
CPU time 6.38 seconds
Started Aug 25 06:51:30 AM UTC 24
Finished Aug 25 06:51:37 AM UTC 24
Peak memory 231516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984322404 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.984322404
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/38.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/38.edn_stress_all_with_rand_reset.1416240582
Short name T337
Test name
Test status
Simulation time 1965391898 ps
CPU time 51.74 seconds
Started Aug 25 06:51:30 AM UTC 24
Finished Aug 25 06:52:23 AM UTC 24
Peak memory 231700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1416240582 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all
_with_rand_reset.1416240582
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/38.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/39.edn_alert.2453025268
Short name T496
Test name
Test status
Simulation time 60373893 ps
CPU time 1.14 seconds
Started Aug 25 06:51:31 AM UTC 24
Finished Aug 25 06:51:34 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453025268 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 39.edn_alert.2453025268
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/39.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/39.edn_alert_test.104785990
Short name T497
Test name
Test status
Simulation time 56999487 ps
CPU time 1.14 seconds
Started Aug 25 06:51:32 AM UTC 24
Finished Aug 25 06:51:34 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104785990 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.104785990
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/39.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/39.edn_disable.870472462
Short name T221
Test name
Test status
Simulation time 47428986 ps
CPU time 1.19 seconds
Started Aug 25 06:51:32 AM UTC 24
Finished Aug 25 06:51:34 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870472462 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.870472462
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/39.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/39.edn_disable_auto_req_mode.2457573785
Short name T504
Test name
Test status
Simulation time 132917827 ps
CPU time 1.67 seconds
Started Aug 25 06:51:32 AM UTC 24
Finished Aug 25 06:51:36 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457573785 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable_auto_req_mode.2457573785
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/39.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/39.edn_err.450409261
Short name T234
Test name
Test status
Simulation time 50791819 ps
CPU time 1.44 seconds
Started Aug 25 06:51:32 AM UTC 24
Finished Aug 25 06:51:34 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450409261 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 39.edn_err.450409261
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/39.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/39.edn_genbits.875082881
Short name T344
Test name
Test status
Simulation time 57773664 ps
CPU time 1.7 seconds
Started Aug 25 06:51:31 AM UTC 24
Finished Aug 25 06:51:34 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875082881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.edn_genbits.875082881
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/39.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/39.edn_intr.4161444543
Short name T500
Test name
Test status
Simulation time 21299669 ps
CPU time 1.6 seconds
Started Aug 25 06:51:31 AM UTC 24
Finished Aug 25 06:51:35 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161444543 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 39.edn_intr.4161444543
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/39.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/39.edn_smoke.2612120419
Short name T499
Test name
Test status
Simulation time 19288266 ps
CPU time 1.51 seconds
Started Aug 25 06:51:31 AM UTC 24
Finished Aug 25 06:51:34 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612120419 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 39.edn_smoke.2612120419
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/39.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/39.edn_stress_all.1925788599
Short name T502
Test name
Test status
Simulation time 127985355 ps
CPU time 3.1 seconds
Started Aug 25 06:51:31 AM UTC 24
Finished Aug 25 06:51:36 AM UTC 24
Peak memory 229464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925788599 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.1925788599
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/39.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/39.edn_stress_all_with_rand_reset.3593280575
Short name T881
Test name
Test status
Simulation time 15649472859 ps
CPU time 118.28 seconds
Started Aug 25 06:51:31 AM UTC 24
Finished Aug 25 06:53:32 AM UTC 24
Peak memory 233788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3593280575 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all
_with_rand_reset.3593280575
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/39.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/4.edn_alert_test.408358208
Short name T361
Test name
Test status
Simulation time 25584372 ps
CPU time 0.81 seconds
Started Aug 25 06:50:00 AM UTC 24
Finished Aug 25 06:50:02 AM UTC 24
Peak memory 217108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408358208 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.408358208
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/4.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/4.edn_disable.2807029278
Short name T56
Test name
Test status
Simulation time 12202943 ps
CPU time 0.77 seconds
Started Aug 25 06:50:00 AM UTC 24
Finished Aug 25 06:50:02 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807029278 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.2807029278
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/4.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/4.edn_disable_auto_req_mode.1468539871
Short name T47
Test name
Test status
Simulation time 56512914 ps
CPU time 1.6 seconds
Started Aug 25 06:50:00 AM UTC 24
Finished Aug 25 06:50:03 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468539871 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable_auto_req_mode.1468539871
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/4.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/4.edn_err.1353637724
Short name T189
Test name
Test status
Simulation time 19308282 ps
CPU time 0.92 seconds
Started Aug 25 06:50:00 AM UTC 24
Finished Aug 25 06:50:02 AM UTC 24
Peak memory 227908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353637724 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 4.edn_err.1353637724
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/4.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/4.edn_genbits.3700194915
Short name T51
Test name
Test status
Simulation time 45581970 ps
CPU time 1.38 seconds
Started Aug 25 06:49:55 AM UTC 24
Finished Aug 25 06:49:58 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700194915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_genbits.3700194915
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/4.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/4.edn_intr.3901693241
Short name T220
Test name
Test status
Simulation time 20897472 ps
CPU time 0.93 seconds
Started Aug 25 06:49:55 AM UTC 24
Finished Aug 25 06:49:58 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901693241 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 4.edn_intr.3901693241
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/4.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/4.edn_regwen.1894892786
Short name T268
Test name
Test status
Simulation time 18554579 ps
CPU time 0.99 seconds
Started Aug 25 06:49:55 AM UTC 24
Finished Aug 25 06:49:58 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894892786 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 4.edn_regwen.1894892786
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/4.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/4.edn_sec_cm.4130376975
Short name T68
Test name
Test status
Simulation time 1237903311 ps
CPU time 9.19 seconds
Started Aug 25 06:50:00 AM UTC 24
Finished Aug 25 06:50:11 AM UTC 24
Peak memory 262524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130376975 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.4130376975
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/4.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/4.edn_smoke.3454436922
Short name T121
Test name
Test status
Simulation time 32050092 ps
CPU time 0.87 seconds
Started Aug 25 06:49:55 AM UTC 24
Finished Aug 25 06:49:58 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454436922 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 4.edn_smoke.3454436922
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/4.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/4.edn_stress_all.3168405429
Short name T112
Test name
Test status
Simulation time 1254016287 ps
CPU time 3.26 seconds
Started Aug 25 06:49:55 AM UTC 24
Finished Aug 25 06:50:00 AM UTC 24
Peak memory 231660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168405429 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.3168405429
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/4.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/40.edn_alert.2074217122
Short name T210
Test name
Test status
Simulation time 29134759 ps
CPU time 1.68 seconds
Started Aug 25 06:51:32 AM UTC 24
Finished Aug 25 06:51:37 AM UTC 24
Peak memory 226356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074217122 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 40.edn_alert.2074217122
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/40.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/40.edn_alert_test.493898057
Short name T508
Test name
Test status
Simulation time 14686353 ps
CPU time 1.42 seconds
Started Aug 25 06:51:32 AM UTC 24
Finished Aug 25 06:51:37 AM UTC 24
Peak memory 226860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493898057 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.493898057
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/40.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/40.edn_disable.3681234818
Short name T506
Test name
Test status
Simulation time 11051157 ps
CPU time 1.23 seconds
Started Aug 25 06:51:32 AM UTC 24
Finished Aug 25 06:51:37 AM UTC 24
Peak memory 226332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681234818 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.3681234818
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/40.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/40.edn_disable_auto_req_mode.824116222
Short name T237
Test name
Test status
Simulation time 44707803 ps
CPU time 1.52 seconds
Started Aug 25 06:51:32 AM UTC 24
Finished Aug 25 06:51:37 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824116222 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable_auto_req_mode.824116222
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/40.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/40.edn_err.3397253697
Short name T167
Test name
Test status
Simulation time 36481056 ps
CPU time 1.55 seconds
Started Aug 25 06:51:32 AM UTC 24
Finished Aug 25 06:51:36 AM UTC 24
Peak memory 243736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397253697 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 40.edn_err.3397253697
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/40.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/40.edn_genbits.699969508
Short name T505
Test name
Test status
Simulation time 28985842 ps
CPU time 1.84 seconds
Started Aug 25 06:51:32 AM UTC 24
Finished Aug 25 06:51:36 AM UTC 24
Peak memory 230612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699969508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.edn_genbits.699969508
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/40.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/40.edn_intr.2109303893
Short name T103
Test name
Test status
Simulation time 25106561 ps
CPU time 1.25 seconds
Started Aug 25 06:51:32 AM UTC 24
Finished Aug 25 06:51:36 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109303893 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 40.edn_intr.2109303893
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/40.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/40.edn_smoke.4260825276
Short name T503
Test name
Test status
Simulation time 27488831 ps
CPU time 1.43 seconds
Started Aug 25 06:51:32 AM UTC 24
Finished Aug 25 06:51:36 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260825276 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 40.edn_smoke.4260825276
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/40.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/40.edn_stress_all.2079964824
Short name T495
Test name
Test status
Simulation time 833561384 ps
CPU time 4.91 seconds
Started Aug 25 06:51:32 AM UTC 24
Finished Aug 25 06:51:40 AM UTC 24
Peak memory 229552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079964824 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2079964824
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/40.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/40.edn_stress_all_with_rand_reset.2122692026
Short name T739
Test name
Test status
Simulation time 5320073809 ps
CPU time 62.13 seconds
Started Aug 25 06:51:32 AM UTC 24
Finished Aug 25 06:52:38 AM UTC 24
Peak memory 229720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2122692026 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all
_with_rand_reset.2122692026
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/40.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/41.edn_alert.941455008
Short name T145
Test name
Test status
Simulation time 46778151 ps
CPU time 1.69 seconds
Started Aug 25 06:51:33 AM UTC 24
Finished Aug 25 06:51:56 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941455008 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 41.edn_alert.941455008
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/41.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/41.edn_alert_test.3066193142
Short name T507
Test name
Test status
Simulation time 43547363 ps
CPU time 1.19 seconds
Started Aug 25 06:51:34 AM UTC 24
Finished Aug 25 06:51:37 AM UTC 24
Peak memory 216244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066193142 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3066193142
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/41.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/41.edn_disable.2732322622
Short name T519
Test name
Test status
Simulation time 30951284 ps
CPU time 1.2 seconds
Started Aug 25 06:51:34 AM UTC 24
Finished Aug 25 06:51:57 AM UTC 24
Peak memory 215020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732322622 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2732322622
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/41.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/41.edn_disable_auto_req_mode.2493006749
Short name T529
Test name
Test status
Simulation time 38771427 ps
CPU time 1.88 seconds
Started Aug 25 06:51:34 AM UTC 24
Finished Aug 25 06:51:57 AM UTC 24
Peak memory 225976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493006749 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable_auto_req_mode.2493006749
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/41.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/41.edn_err.3219321895
Short name T522
Test name
Test status
Simulation time 19158551 ps
CPU time 1.58 seconds
Started Aug 25 06:51:33 AM UTC 24
Finished Aug 25 06:51:57 AM UTC 24
Peak memory 237168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219321895 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 41.edn_err.3219321895
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/41.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/41.edn_genbits.4045973933
Short name T523
Test name
Test status
Simulation time 48530668 ps
CPU time 2.29 seconds
Started Aug 25 06:51:33 AM UTC 24
Finished Aug 25 06:51:57 AM UTC 24
Peak memory 229704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045973933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_genbits.4045973933
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/41.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/41.edn_intr.1298885450
Short name T525
Test name
Test status
Simulation time 22486292 ps
CPU time 1.7 seconds
Started Aug 25 06:51:33 AM UTC 24
Finished Aug 25 06:51:57 AM UTC 24
Peak memory 237836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298885450 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 41.edn_intr.1298885450
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/41.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/41.edn_smoke.1459741433
Short name T518
Test name
Test status
Simulation time 18359266 ps
CPU time 1.29 seconds
Started Aug 25 06:51:32 AM UTC 24
Finished Aug 25 06:51:46 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459741433 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 41.edn_smoke.1459741433
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/41.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/41.edn_stress_all.143582633
Short name T543
Test name
Test status
Simulation time 595628939 ps
CPU time 4.16 seconds
Started Aug 25 06:51:33 AM UTC 24
Finished Aug 25 06:51:59 AM UTC 24
Peak memory 229604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143582633 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.143582633
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/41.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/41.edn_stress_all_with_rand_reset.806153657
Short name T740
Test name
Test status
Simulation time 8930364723 ps
CPU time 59.15 seconds
Started Aug 25 06:51:33 AM UTC 24
Finished Aug 25 06:52:44 AM UTC 24
Peak memory 229980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=806153657 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_
with_rand_reset.806153657
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/41.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/42.edn_alert.3884620781
Short name T514
Test name
Test status
Simulation time 65810024 ps
CPU time 1.64 seconds
Started Aug 25 06:51:34 AM UTC 24
Finished Aug 25 06:51:41 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884620781 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 42.edn_alert.3884620781
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/42.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/42.edn_alert_test.1685184392
Short name T511
Test name
Test status
Simulation time 40379818 ps
CPU time 1.11 seconds
Started Aug 25 06:51:34 AM UTC 24
Finished Aug 25 06:51:40 AM UTC 24
Peak memory 216780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685184392 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1685184392
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/42.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/42.edn_disable.2094521492
Short name T520
Test name
Test status
Simulation time 119157874 ps
CPU time 1.28 seconds
Started Aug 25 06:51:34 AM UTC 24
Finished Aug 25 06:51:57 AM UTC 24
Peak memory 226352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094521492 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.2094521492
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/42.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/42.edn_disable_auto_req_mode.383675225
Short name T515
Test name
Test status
Simulation time 28423988 ps
CPU time 1.6 seconds
Started Aug 25 06:51:34 AM UTC 24
Finished Aug 25 06:51:41 AM UTC 24
Peak memory 226448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383675225 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable_auto_req_mode.383675225
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/42.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/42.edn_genbits.758826458
Short name T513
Test name
Test status
Simulation time 27684618 ps
CPU time 1.69 seconds
Started Aug 25 06:51:34 AM UTC 24
Finished Aug 25 06:51:40 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758826458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.edn_genbits.758826458
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/42.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/42.edn_intr.1728877568
Short name T510
Test name
Test status
Simulation time 30568574 ps
CPU time 1.3 seconds
Started Aug 25 06:51:34 AM UTC 24
Finished Aug 25 06:51:40 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728877568 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 42.edn_intr.1728877568
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/42.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/42.edn_smoke.2629250689
Short name T512
Test name
Test status
Simulation time 24824275 ps
CPU time 1.39 seconds
Started Aug 25 06:51:34 AM UTC 24
Finished Aug 25 06:51:40 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629250689 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 42.edn_smoke.2629250689
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/42.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/42.edn_stress_all.3505153138
Short name T516
Test name
Test status
Simulation time 2789520316 ps
CPU time 4.42 seconds
Started Aug 25 06:51:34 AM UTC 24
Finished Aug 25 06:51:43 AM UTC 24
Peak memory 229468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505153138 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.3505153138
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/42.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/42.edn_stress_all_with_rand_reset.4019431666
Short name T255
Test name
Test status
Simulation time 2536441347 ps
CPU time 49.79 seconds
Started Aug 25 06:51:34 AM UTC 24
Finished Aug 25 06:52:29 AM UTC 24
Peak memory 229940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=4019431666 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all
_with_rand_reset.4019431666
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/42.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/43.edn_alert.2997077419
Short name T305
Test name
Test status
Simulation time 59354168 ps
CPU time 1.76 seconds
Started Aug 25 06:51:35 AM UTC 24
Finished Aug 25 06:51:59 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997077419 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 43.edn_alert.2997077419
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/43.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/43.edn_alert_test.2048333223
Short name T537
Test name
Test status
Simulation time 116611796 ps
CPU time 1.21 seconds
Started Aug 25 06:51:35 AM UTC 24
Finished Aug 25 06:51:58 AM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048333223 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2048333223
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/43.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/43.edn_disable_auto_req_mode.3043015146
Short name T535
Test name
Test status
Simulation time 77963045 ps
CPU time 1.31 seconds
Started Aug 25 06:51:35 AM UTC 24
Finished Aug 25 06:51:58 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043015146 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable_auto_req_mode.3043015146
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/43.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/43.edn_err.3025646140
Short name T540
Test name
Test status
Simulation time 107280995 ps
CPU time 1.48 seconds
Started Aug 25 06:51:35 AM UTC 24
Finished Aug 25 06:51:58 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025646140 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 43.edn_err.3025646140
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/43.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/43.edn_genbits.4052440278
Short name T545
Test name
Test status
Simulation time 310631255 ps
CPU time 2.65 seconds
Started Aug 25 06:51:35 AM UTC 24
Finished Aug 25 06:51:59 AM UTC 24
Peak memory 229096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052440278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_genbits.4052440278
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/43.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/43.edn_smoke.1228238506
Short name T534
Test name
Test status
Simulation time 45103359 ps
CPU time 1.34 seconds
Started Aug 25 06:51:35 AM UTC 24
Finished Aug 25 06:51:58 AM UTC 24
Peak memory 225612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228238506 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 43.edn_smoke.1228238506
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/43.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/43.edn_stress_all.3938919577
Short name T559
Test name
Test status
Simulation time 270220528 ps
CPU time 5.53 seconds
Started Aug 25 06:51:35 AM UTC 24
Finished Aug 25 06:52:02 AM UTC 24
Peak memory 229296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938919577 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3938919577
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/43.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/44.edn_alert.1960146892
Short name T170
Test name
Test status
Simulation time 33869251 ps
CPU time 1.79 seconds
Started Aug 25 06:51:38 AM UTC 24
Finished Aug 25 06:51:58 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960146892 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 44.edn_alert.1960146892
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/44.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/44.edn_alert_test.2226723861
Short name T533
Test name
Test status
Simulation time 36294710 ps
CPU time 1.44 seconds
Started Aug 25 06:51:38 AM UTC 24
Finished Aug 25 06:51:58 AM UTC 24
Peak memory 226728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226723861 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2226723861
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/44.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/44.edn_disable.3368569735
Short name T528
Test name
Test status
Simulation time 19211086 ps
CPU time 1.15 seconds
Started Aug 25 06:51:38 AM UTC 24
Finished Aug 25 06:51:57 AM UTC 24
Peak memory 226368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368569735 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3368569735
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/44.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/44.edn_disable_auto_req_mode.1605555618
Short name T304
Test name
Test status
Simulation time 25398605 ps
CPU time 1.58 seconds
Started Aug 25 06:51:38 AM UTC 24
Finished Aug 25 06:51:58 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605555618 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable_auto_req_mode.1605555618
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/44.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/44.edn_err.752818782
Short name T536
Test name
Test status
Simulation time 27036788 ps
CPU time 1.85 seconds
Started Aug 25 06:51:38 AM UTC 24
Finished Aug 25 06:51:58 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752818782 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 44.edn_err.752818782
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/44.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/44.edn_genbits.3538770729
Short name T330
Test name
Test status
Simulation time 45179769 ps
CPU time 2.57 seconds
Started Aug 25 06:51:36 AM UTC 24
Finished Aug 25 06:52:00 AM UTC 24
Peak memory 229724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538770729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3538770729
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/44.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/44.edn_intr.3371342192
Short name T521
Test name
Test status
Simulation time 20840285 ps
CPU time 1.68 seconds
Started Aug 25 06:51:37 AM UTC 24
Finished Aug 25 06:51:57 AM UTC 24
Peak memory 237824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371342192 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 44.edn_intr.3371342192
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/44.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/44.edn_smoke.3637639929
Short name T539
Test name
Test status
Simulation time 25569476 ps
CPU time 1.34 seconds
Started Aug 25 06:51:36 AM UTC 24
Finished Aug 25 06:51:58 AM UTC 24
Peak memory 226240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637639929 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 44.edn_smoke.3637639929
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/44.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/44.edn_stress_all.2915115991
Short name T555
Test name
Test status
Simulation time 238964417 ps
CPU time 6.48 seconds
Started Aug 25 06:51:37 AM UTC 24
Finished Aug 25 06:52:02 AM UTC 24
Peak memory 227628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915115991 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2915115991
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/44.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/44.edn_stress_all_with_rand_reset.2708530953
Short name T257
Test name
Test status
Simulation time 10120998534 ps
CPU time 51.27 seconds
Started Aug 25 06:51:37 AM UTC 24
Finished Aug 25 06:52:47 AM UTC 24
Peak memory 229724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2708530953 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all
_with_rand_reset.2708530953
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/44.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/45.edn_alert.1705968054
Short name T186
Test name
Test status
Simulation time 327413949 ps
CPU time 1.73 seconds
Started Aug 25 06:51:40 AM UTC 24
Finished Aug 25 06:51:46 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705968054 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 45.edn_alert.1705968054
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/45.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/45.edn_alert_test.787343293
Short name T526
Test name
Test status
Simulation time 27108333 ps
CPU time 1.3 seconds
Started Aug 25 06:51:41 AM UTC 24
Finished Aug 25 06:51:57 AM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787343293 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.787343293
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/45.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/45.edn_disable.2825896370
Short name T538
Test name
Test status
Simulation time 74873494 ps
CPU time 1.25 seconds
Started Aug 25 06:51:41 AM UTC 24
Finished Aug 25 06:51:58 AM UTC 24
Peak memory 216132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825896370 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2825896370
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/45.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/45.edn_disable_auto_req_mode.3682958931
Short name T541
Test name
Test status
Simulation time 40088279 ps
CPU time 1.85 seconds
Started Aug 25 06:51:41 AM UTC 24
Finished Aug 25 06:51:59 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682958931 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable_auto_req_mode.3682958931
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/45.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/45.edn_err.3761670329
Short name T188
Test name
Test status
Simulation time 35425935 ps
CPU time 1.39 seconds
Started Aug 25 06:51:41 AM UTC 24
Finished Aug 25 06:51:58 AM UTC 24
Peak memory 236912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761670329 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 45.edn_err.3761670329
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/45.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/45.edn_genbits.672432312
Short name T340
Test name
Test status
Simulation time 33558012 ps
CPU time 1.8 seconds
Started Aug 25 06:51:38 AM UTC 24
Finished Aug 25 06:51:58 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672432312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_genbits.672432312
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/45.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/45.edn_intr.2045261063
Short name T105
Test name
Test status
Simulation time 26799966 ps
CPU time 1.17 seconds
Started Aug 25 06:51:38 AM UTC 24
Finished Aug 25 06:51:58 AM UTC 24
Peak memory 228488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045261063 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 45.edn_intr.2045261063
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/45.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/45.edn_smoke.2914211633
Short name T531
Test name
Test status
Simulation time 50270317 ps
CPU time 1.26 seconds
Started Aug 25 06:51:38 AM UTC 24
Finished Aug 25 06:51:58 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914211633 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 45.edn_smoke.2914211633
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/45.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/45.edn_stress_all.376954805
Short name T544
Test name
Test status
Simulation time 159654081 ps
CPU time 2.88 seconds
Started Aug 25 06:51:38 AM UTC 24
Finished Aug 25 06:51:59 AM UTC 24
Peak memory 229524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376954805 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.376954805
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/45.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/46.edn_alert.1546925323
Short name T200
Test name
Test status
Simulation time 38522254 ps
CPU time 1.65 seconds
Started Aug 25 06:51:47 AM UTC 24
Finished Aug 25 06:51:57 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546925323 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 46.edn_alert.1546925323
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/46.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/46.edn_alert_test.2750795313
Short name T542
Test name
Test status
Simulation time 15022407 ps
CPU time 1.23 seconds
Started Aug 25 06:51:57 AM UTC 24
Finished Aug 25 06:51:59 AM UTC 24
Peak memory 217108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750795313 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2750795313
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/46.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/46.edn_disable_auto_req_mode.3211114666
Short name T271
Test name
Test status
Simulation time 54325196 ps
CPU time 1.41 seconds
Started Aug 25 06:51:51 AM UTC 24
Finished Aug 25 06:51:57 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211114666 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable_auto_req_mode.3211114666
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/46.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/46.edn_err.2034932711
Short name T130
Test name
Test status
Simulation time 25789657 ps
CPU time 1.61 seconds
Started Aug 25 06:51:47 AM UTC 24
Finished Aug 25 06:51:57 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034932711 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 46.edn_err.2034932711
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/46.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/46.edn_genbits.3391021389
Short name T532
Test name
Test status
Simulation time 39970575 ps
CPU time 1.8 seconds
Started Aug 25 06:51:41 AM UTC 24
Finished Aug 25 06:51:58 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391021389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_genbits.3391021389
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/46.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/46.edn_intr.4178728753
Short name T517
Test name
Test status
Simulation time 31564577 ps
CPU time 0.83 seconds
Started Aug 25 06:51:44 AM UTC 24
Finished Aug 25 06:51:46 AM UTC 24
Peak memory 226248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178728753 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 46.edn_intr.4178728753
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/46.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/46.edn_smoke.3372611739
Short name T527
Test name
Test status
Simulation time 19136387 ps
CPU time 1.49 seconds
Started Aug 25 06:51:41 AM UTC 24
Finished Aug 25 06:51:57 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372611739 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 46.edn_smoke.3372611739
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/46.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/46.edn_stress_all.3112877636
Short name T546
Test name
Test status
Simulation time 525100054 ps
CPU time 4.03 seconds
Started Aug 25 06:51:42 AM UTC 24
Finished Aug 25 06:52:00 AM UTC 24
Peak memory 229604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112877636 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.3112877636
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/46.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/46.edn_stress_all_with_rand_reset.1096586639
Short name T732
Test name
Test status
Simulation time 1327006529 ps
CPU time 35.66 seconds
Started Aug 25 06:51:43 AM UTC 24
Finished Aug 25 06:52:31 AM UTC 24
Peak memory 229800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1096586639 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all
_with_rand_reset.1096586639
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/46.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/47.edn_alert_test.1911528289
Short name T550
Test name
Test status
Simulation time 23245262 ps
CPU time 1.22 seconds
Started Aug 25 06:51:58 AM UTC 24
Finished Aug 25 06:52:01 AM UTC 24
Peak memory 215812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911528289 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1911528289
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/47.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/47.edn_disable.1402262899
Short name T549
Test name
Test status
Simulation time 10287307 ps
CPU time 1.19 seconds
Started Aug 25 06:51:58 AM UTC 24
Finished Aug 25 06:52:01 AM UTC 24
Peak memory 216120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402262899 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1402262899
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/47.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/47.edn_disable_auto_req_mode.3192464760
Short name T553
Test name
Test status
Simulation time 27890256 ps
CPU time 1.55 seconds
Started Aug 25 06:51:58 AM UTC 24
Finished Aug 25 06:52:01 AM UTC 24
Peak memory 226240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192464760 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable_auto_req_mode.3192464760
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/47.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/47.edn_err.4235053318
Short name T552
Test name
Test status
Simulation time 25368745 ps
CPU time 1.53 seconds
Started Aug 25 06:51:58 AM UTC 24
Finished Aug 25 06:52:01 AM UTC 24
Peak memory 246620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235053318 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 47.edn_err.4235053318
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/47.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/47.edn_genbits.3847559752
Short name T359
Test name
Test status
Simulation time 34726049 ps
CPU time 1.96 seconds
Started Aug 25 06:51:58 AM UTC 24
Finished Aug 25 06:52:01 AM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847559752 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3847559752
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/47.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/47.edn_intr.1912803542
Short name T548
Test name
Test status
Simulation time 94698873 ps
CPU time 1.28 seconds
Started Aug 25 06:51:58 AM UTC 24
Finished Aug 25 06:52:01 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912803542 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 47.edn_intr.1912803542
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/47.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/47.edn_smoke.4019655972
Short name T547
Test name
Test status
Simulation time 94085862 ps
CPU time 1.38 seconds
Started Aug 25 06:51:58 AM UTC 24
Finished Aug 25 06:52:00 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019655972 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 47.edn_smoke.4019655972
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/47.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/47.edn_stress_all.2552128818
Short name T575
Test name
Test status
Simulation time 210238651 ps
CPU time 5.88 seconds
Started Aug 25 06:51:58 AM UTC 24
Finished Aug 25 06:52:05 AM UTC 24
Peak memory 229540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552128818 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.2552128818
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/47.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/48.edn_alert.2936433934
Short name T158
Test name
Test status
Simulation time 42024283 ps
CPU time 1.74 seconds
Started Aug 25 06:52:00 AM UTC 24
Finished Aug 25 06:52:03 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936433934 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 48.edn_alert.2936433934
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/48.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/48.edn_alert_test.1974304327
Short name T561
Test name
Test status
Simulation time 46679398 ps
CPU time 1.28 seconds
Started Aug 25 06:52:00 AM UTC 24
Finished Aug 25 06:52:02 AM UTC 24
Peak memory 216888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974304327 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1974304327
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/48.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/48.edn_disable.3113161494
Short name T557
Test name
Test status
Simulation time 110168962 ps
CPU time 1.25 seconds
Started Aug 25 06:52:00 AM UTC 24
Finished Aug 25 06:52:02 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113161494 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3113161494
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/48.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/48.edn_disable_auto_req_mode.957535352
Short name T562
Test name
Test status
Simulation time 57233556 ps
CPU time 1.73 seconds
Started Aug 25 06:52:00 AM UTC 24
Finished Aug 25 06:52:03 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957535352 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable_auto_req_mode.957535352
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/48.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/48.edn_err.2914237288
Short name T224
Test name
Test status
Simulation time 18977586 ps
CPU time 1.44 seconds
Started Aug 25 06:52:00 AM UTC 24
Finished Aug 25 06:52:03 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914237288 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 48.edn_err.2914237288
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/48.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/48.edn_genbits.661413989
Short name T556
Test name
Test status
Simulation time 43241454 ps
CPU time 2.41 seconds
Started Aug 25 06:51:59 AM UTC 24
Finished Aug 25 06:52:02 AM UTC 24
Peak memory 229732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661413989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.edn_genbits.661413989
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/48.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/48.edn_intr.3849376679
Short name T554
Test name
Test status
Simulation time 54622790 ps
CPU time 1.33 seconds
Started Aug 25 06:51:59 AM UTC 24
Finished Aug 25 06:52:01 AM UTC 24
Peak memory 236968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849376679 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 48.edn_intr.3849376679
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/48.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/48.edn_smoke.235076377
Short name T551
Test name
Test status
Simulation time 88342571 ps
CPU time 1.26 seconds
Started Aug 25 06:51:58 AM UTC 24
Finished Aug 25 06:52:01 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235076377 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 48.edn_smoke.235076377
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/48.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/48.edn_stress_all.1330068684
Short name T571
Test name
Test status
Simulation time 378072756 ps
CPU time 4.92 seconds
Started Aug 25 06:51:59 AM UTC 24
Finished Aug 25 06:52:05 AM UTC 24
Peak memory 229392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330068684 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1330068684
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/48.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/48.edn_stress_all_with_rand_reset.3861535998
Short name T934
Test name
Test status
Simulation time 10723001536 ps
CPU time 117.65 seconds
Started Aug 25 06:51:59 AM UTC 24
Finished Aug 25 06:53:59 AM UTC 24
Peak memory 229796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3861535998 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all
_with_rand_reset.3861535998
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/48.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/49.edn_alert.4244789236
Short name T565
Test name
Test status
Simulation time 25396213 ps
CPU time 1.58 seconds
Started Aug 25 06:52:00 AM UTC 24
Finished Aug 25 06:52:03 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244789236 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 49.edn_alert.4244789236
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/49.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/49.edn_alert_test.677275141
Short name T564
Test name
Test status
Simulation time 131415291 ps
CPU time 1.37 seconds
Started Aug 25 06:52:00 AM UTC 24
Finished Aug 25 06:52:03 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677275141 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.677275141
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/49.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/49.edn_disable.385655993
Short name T231
Test name
Test status
Simulation time 78727327 ps
CPU time 1.29 seconds
Started Aug 25 06:52:00 AM UTC 24
Finished Aug 25 06:52:03 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385655993 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.385655993
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/49.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/49.edn_disable_auto_req_mode.1418557212
Short name T567
Test name
Test status
Simulation time 55781343 ps
CPU time 1.79 seconds
Started Aug 25 06:52:00 AM UTC 24
Finished Aug 25 06:52:03 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418557212 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable_auto_req_mode.1418557212
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/49.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/49.edn_err.4094454003
Short name T131
Test name
Test status
Simulation time 33037681 ps
CPU time 1.52 seconds
Started Aug 25 06:52:00 AM UTC 24
Finished Aug 25 06:52:03 AM UTC 24
Peak memory 226232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094454003 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 49.edn_err.4094454003
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/49.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/49.edn_genbits.2325063373
Short name T335
Test name
Test status
Simulation time 87515618 ps
CPU time 1.75 seconds
Started Aug 25 06:52:00 AM UTC 24
Finished Aug 25 06:52:03 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325063373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2325063373
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/49.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/49.edn_intr.156382167
Short name T563
Test name
Test status
Simulation time 20705031 ps
CPU time 1.57 seconds
Started Aug 25 06:52:00 AM UTC 24
Finished Aug 25 06:52:03 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156382167 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 49.edn_intr.156382167
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/49.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/49.edn_smoke.1500468077
Short name T560
Test name
Test status
Simulation time 35169699 ps
CPU time 1.17 seconds
Started Aug 25 06:52:00 AM UTC 24
Finished Aug 25 06:52:02 AM UTC 24
Peak memory 226172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500468077 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 49.edn_smoke.1500468077
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/49.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/49.edn_stress_all.1697446279
Short name T568
Test name
Test status
Simulation time 196255891 ps
CPU time 2.4 seconds
Started Aug 25 06:52:00 AM UTC 24
Finished Aug 25 06:52:04 AM UTC 24
Peak memory 229728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697446279 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1697446279
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/49.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/49.edn_stress_all_with_rand_reset.2855508621
Short name T725
Test name
Test status
Simulation time 1164197754 ps
CPU time 27.9 seconds
Started Aug 25 06:52:00 AM UTC 24
Finished Aug 25 06:52:30 AM UTC 24
Peak memory 231648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2855508621 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all
_with_rand_reset.2855508621
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/49.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/5.edn_alert.2827750140
Short name T117
Test name
Test status
Simulation time 73463446 ps
CPU time 1.04 seconds
Started Aug 25 06:50:00 AM UTC 24
Finished Aug 25 06:50:03 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827750140 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 5.edn_alert.2827750140
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/5.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/5.edn_alert_test.4001473353
Short name T363
Test name
Test status
Simulation time 17010721 ps
CPU time 0.91 seconds
Started Aug 25 06:50:01 AM UTC 24
Finished Aug 25 06:50:03 AM UTC 24
Peak memory 226912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001473353 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.4001473353
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/5.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/5.edn_disable.509880599
Short name T77
Test name
Test status
Simulation time 12894384 ps
CPU time 0.98 seconds
Started Aug 25 06:50:00 AM UTC 24
Finished Aug 25 06:50:03 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509880599 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.509880599
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/5.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/5.edn_disable_auto_req_mode.2812629106
Short name T98
Test name
Test status
Simulation time 37360776 ps
CPU time 1.44 seconds
Started Aug 25 06:50:01 AM UTC 24
Finished Aug 25 06:50:03 AM UTC 24
Peak memory 230348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812629106 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable_auto_req_mode.2812629106
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/5.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/5.edn_err.1203753630
Short name T9
Test name
Test status
Simulation time 22742054 ps
CPU time 1.04 seconds
Started Aug 25 06:50:00 AM UTC 24
Finished Aug 25 06:50:03 AM UTC 24
Peak memory 227976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203753630 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 5.edn_err.1203753630
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/5.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/5.edn_genbits.1576153106
Short name T46
Test name
Test status
Simulation time 97321750 ps
CPU time 1.2 seconds
Started Aug 25 06:50:00 AM UTC 24
Finished Aug 25 06:50:03 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576153106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1576153106
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/5.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/5.edn_intr.3009802534
Short name T35
Test name
Test status
Simulation time 29768108 ps
CPU time 1.06 seconds
Started Aug 25 06:50:00 AM UTC 24
Finished Aug 25 06:50:03 AM UTC 24
Peak memory 228328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009802534 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 5.edn_intr.3009802534
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/5.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/5.edn_regwen.2880625734
Short name T325
Test name
Test status
Simulation time 29133552 ps
CPU time 0.93 seconds
Started Aug 25 06:50:00 AM UTC 24
Finished Aug 25 06:50:03 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880625734 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 5.edn_regwen.2880625734
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/5.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/5.edn_smoke.1538748340
Short name T362
Test name
Test status
Simulation time 17595092 ps
CPU time 0.91 seconds
Started Aug 25 06:50:00 AM UTC 24
Finished Aug 25 06:50:02 AM UTC 24
Peak memory 226192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538748340 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 5.edn_smoke.1538748340
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/5.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/5.edn_stress_all.1926458626
Short name T120
Test name
Test status
Simulation time 122551695 ps
CPU time 2.65 seconds
Started Aug 25 06:50:00 AM UTC 24
Finished Aug 25 06:50:05 AM UTC 24
Peak memory 227468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926458626 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1926458626
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/5.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/50.edn_alert.1140501810
Short name T321
Test name
Test status
Simulation time 58314841 ps
CPU time 1.58 seconds
Started Aug 25 06:52:01 AM UTC 24
Finished Aug 25 06:52:03 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140501810 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 50.edn_alert.1140501810
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/50.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/50.edn_err.2713939180
Short name T206
Test name
Test status
Simulation time 22631664 ps
CPU time 1.31 seconds
Started Aug 25 06:52:01 AM UTC 24
Finished Aug 25 06:52:03 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713939180 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 50.edn_err.2713939180
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/50.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/50.edn_genbits.1610142853
Short name T360
Test name
Test status
Simulation time 221774737 ps
CPU time 1.7 seconds
Started Aug 25 06:52:00 AM UTC 24
Finished Aug 25 06:52:03 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610142853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1610142853
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/50.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/51.edn_alert.3839066911
Short name T205
Test name
Test status
Simulation time 46889484 ps
CPU time 1.71 seconds
Started Aug 25 06:52:01 AM UTC 24
Finished Aug 25 06:52:04 AM UTC 24
Peak memory 230176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839066911 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 51.edn_alert.3839066911
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/51.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/51.edn_err.1257449512
Short name T219
Test name
Test status
Simulation time 28199065 ps
CPU time 1.19 seconds
Started Aug 25 06:52:01 AM UTC 24
Finished Aug 25 06:52:03 AM UTC 24
Peak memory 230076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257449512 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 51.edn_err.1257449512
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/51.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/51.edn_genbits.1004423797
Short name T566
Test name
Test status
Simulation time 39671858 ps
CPU time 1.28 seconds
Started Aug 25 06:52:01 AM UTC 24
Finished Aug 25 06:52:03 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004423797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 51.edn_genbits.1004423797
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/51.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/52.edn_alert.3589303774
Short name T169
Test name
Test status
Simulation time 26902175 ps
CPU time 1.81 seconds
Started Aug 25 06:52:02 AM UTC 24
Finished Aug 25 06:52:05 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589303774 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 52.edn_alert.3589303774
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/52.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/52.edn_err.4119297969
Short name T569
Test name
Test status
Simulation time 49795175 ps
CPU time 1.29 seconds
Started Aug 25 06:52:02 AM UTC 24
Finished Aug 25 06:52:04 AM UTC 24
Peak memory 228172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119297969 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 52.edn_err.4119297969
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/52.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/52.edn_genbits.1119529188
Short name T570
Test name
Test status
Simulation time 90544908 ps
CPU time 1.64 seconds
Started Aug 25 06:52:02 AM UTC 24
Finished Aug 25 06:52:05 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119529188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1119529188
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/52.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/53.edn_alert.2257119616
Short name T180
Test name
Test status
Simulation time 103503997 ps
CPU time 1.62 seconds
Started Aug 25 06:52:02 AM UTC 24
Finished Aug 25 06:52:05 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257119616 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 53.edn_alert.2257119616
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/53.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/53.edn_err.2404321401
Short name T178
Test name
Test status
Simulation time 145580588 ps
CPU time 1.82 seconds
Started Aug 25 06:52:02 AM UTC 24
Finished Aug 25 06:52:05 AM UTC 24
Peak memory 242068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404321401 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 53.edn_err.2404321401
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/53.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/53.edn_genbits.171013873
Short name T524
Test name
Test status
Simulation time 50868633 ps
CPU time 1.54 seconds
Started Aug 25 06:52:02 AM UTC 24
Finished Aug 25 06:52:05 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171013873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 53.edn_genbits.171013873
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/53.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/54.edn_alert.1991178462
Short name T573
Test name
Test status
Simulation time 90245084 ps
CPU time 1.78 seconds
Started Aug 25 06:52:02 AM UTC 24
Finished Aug 25 06:52:05 AM UTC 24
Peak memory 228388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991178462 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 54.edn_alert.1991178462
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/54.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/54.edn_err.3349428728
Short name T530
Test name
Test status
Simulation time 27985601 ps
CPU time 1.63 seconds
Started Aug 25 06:52:02 AM UTC 24
Finished Aug 25 06:52:05 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349428728 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 54.edn_err.3349428728
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/54.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/54.edn_genbits.1195741212
Short name T558
Test name
Test status
Simulation time 58821692 ps
CPU time 1.75 seconds
Started Aug 25 06:52:02 AM UTC 24
Finished Aug 25 06:52:05 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195741212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1195741212
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/54.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/55.edn_alert.4067434472
Short name T576
Test name
Test status
Simulation time 29496990 ps
CPU time 1.83 seconds
Started Aug 25 06:52:02 AM UTC 24
Finished Aug 25 06:52:05 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067434472 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 55.edn_alert.4067434472
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/55.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/55.edn_err.3351573925
Short name T572
Test name
Test status
Simulation time 20597709 ps
CPU time 1.55 seconds
Started Aug 25 06:52:02 AM UTC 24
Finished Aug 25 06:52:05 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351573925 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 55.edn_err.3351573925
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/55.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/56.edn_alert.3847478565
Short name T201
Test name
Test status
Simulation time 23983250 ps
CPU time 1.69 seconds
Started Aug 25 06:52:02 AM UTC 24
Finished Aug 25 06:52:05 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847478565 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 56.edn_alert.3847478565
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/56.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/56.edn_err.1292104155
Short name T577
Test name
Test status
Simulation time 20743133 ps
CPU time 1.25 seconds
Started Aug 25 06:52:04 AM UTC 24
Finished Aug 25 06:52:06 AM UTC 24
Peak memory 228272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292104155 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 56.edn_err.1292104155
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/56.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/56.edn_genbits.3267823299
Short name T574
Test name
Test status
Simulation time 73491595 ps
CPU time 1.62 seconds
Started Aug 25 06:52:02 AM UTC 24
Finished Aug 25 06:52:05 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267823299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 56.edn_genbits.3267823299
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/56.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/57.edn_alert.3138272384
Short name T152
Test name
Test status
Simulation time 69444995 ps
CPU time 1.44 seconds
Started Aug 25 06:52:04 AM UTC 24
Finished Aug 25 06:52:06 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138272384 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 57.edn_alert.3138272384
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/57.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/57.edn_err.1170646165
Short name T578
Test name
Test status
Simulation time 34022705 ps
CPU time 1.26 seconds
Started Aug 25 06:52:04 AM UTC 24
Finished Aug 25 06:52:06 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170646165 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 57.edn_err.1170646165
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/57.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/57.edn_genbits.2460251539
Short name T586
Test name
Test status
Simulation time 36073468 ps
CPU time 2.39 seconds
Started Aug 25 06:52:04 AM UTC 24
Finished Aug 25 06:52:07 AM UTC 24
Peak memory 229340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460251539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2460251539
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/57.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/58.edn_alert.16483858
Short name T146
Test name
Test status
Simulation time 25569600 ps
CPU time 1.73 seconds
Started Aug 25 06:52:04 AM UTC 24
Finished Aug 25 06:52:07 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16483858 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 58.edn_alert.16483858
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/58.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/58.edn_err.2623896039
Short name T579
Test name
Test status
Simulation time 23920126 ps
CPU time 1.18 seconds
Started Aug 25 06:52:04 AM UTC 24
Finished Aug 25 06:52:06 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623896039 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 58.edn_err.2623896039
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/58.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/58.edn_genbits.1915353470
Short name T582
Test name
Test status
Simulation time 51571341 ps
CPU time 1.84 seconds
Started Aug 25 06:52:04 AM UTC 24
Finished Aug 25 06:52:07 AM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915353470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1915353470
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/58.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/59.edn_alert.1939900827
Short name T165
Test name
Test status
Simulation time 52553379 ps
CPU time 1.62 seconds
Started Aug 25 06:52:04 AM UTC 24
Finished Aug 25 06:52:07 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939900827 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 59.edn_alert.1939900827
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/59.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/59.edn_err.1572058810
Short name T583
Test name
Test status
Simulation time 55125400 ps
CPU time 1.69 seconds
Started Aug 25 06:52:04 AM UTC 24
Finished Aug 25 06:52:07 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572058810 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 59.edn_err.1572058810
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/59.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/59.edn_genbits.403323724
Short name T580
Test name
Test status
Simulation time 131198328 ps
CPU time 1.45 seconds
Started Aug 25 06:52:04 AM UTC 24
Finished Aug 25 06:52:07 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403323724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 59.edn_genbits.403323724
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/59.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/6.edn_alert.3462308978
Short name T81
Test name
Test status
Simulation time 52745941 ps
CPU time 1.17 seconds
Started Aug 25 06:50:01 AM UTC 24
Finished Aug 25 06:50:04 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462308978 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 6.edn_alert.3462308978
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/6.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/6.edn_alert_test.3614708787
Short name T365
Test name
Test status
Simulation time 17568611 ps
CPU time 0.98 seconds
Started Aug 25 06:50:01 AM UTC 24
Finished Aug 25 06:50:03 AM UTC 24
Peak memory 226912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614708787 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3614708787
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/6.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/6.edn_disable.3404418619
Short name T54
Test name
Test status
Simulation time 21281598 ps
CPU time 0.88 seconds
Started Aug 25 06:50:01 AM UTC 24
Finished Aug 25 06:50:03 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404418619 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.3404418619
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/6.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/6.edn_disable_auto_req_mode.2795991998
Short name T118
Test name
Test status
Simulation time 87650376 ps
CPU time 1.51 seconds
Started Aug 25 06:50:01 AM UTC 24
Finished Aug 25 06:50:04 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795991998 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable_auto_req_mode.2795991998
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/6.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/6.edn_err.970265647
Short name T66
Test name
Test status
Simulation time 38598740 ps
CPU time 1.22 seconds
Started Aug 25 06:50:01 AM UTC 24
Finished Aug 25 06:50:04 AM UTC 24
Peak memory 242188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970265647 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 6.edn_err.970265647
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/6.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/6.edn_genbits.519576788
Short name T59
Test name
Test status
Simulation time 80189763 ps
CPU time 1.32 seconds
Started Aug 25 06:50:01 AM UTC 24
Finished Aug 25 06:50:03 AM UTC 24
Peak memory 228356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519576788 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.edn_genbits.519576788
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/6.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/6.edn_intr.3597938813
Short name T32
Test name
Test status
Simulation time 22681743 ps
CPU time 1.02 seconds
Started Aug 25 06:50:01 AM UTC 24
Finished Aug 25 06:50:03 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597938813 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 6.edn_intr.3597938813
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/6.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/6.edn_regwen.4226237786
Short name T264
Test name
Test status
Simulation time 147490302 ps
CPU time 0.87 seconds
Started Aug 25 06:50:01 AM UTC 24
Finished Aug 25 06:50:03 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226237786 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 6.edn_regwen.4226237786
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/6.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/6.edn_smoke.2289179790
Short name T109
Test name
Test status
Simulation time 24750414 ps
CPU time 0.88 seconds
Started Aug 25 06:50:01 AM UTC 24
Finished Aug 25 06:50:03 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289179790 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 6.edn_smoke.2289179790
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/6.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/6.edn_stress_all.3497046931
Short name T124
Test name
Test status
Simulation time 392050158 ps
CPU time 4.22 seconds
Started Aug 25 06:50:01 AM UTC 24
Finished Aug 25 06:50:07 AM UTC 24
Peak memory 227412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497046931 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3497046931
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/6.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/60.edn_alert.2018500778
Short name T272
Test name
Test status
Simulation time 26745741 ps
CPU time 1.51 seconds
Started Aug 25 06:52:04 AM UTC 24
Finished Aug 25 06:52:07 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018500778 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 60.edn_alert.2018500778
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/60.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/60.edn_err.1751472586
Short name T191
Test name
Test status
Simulation time 29882740 ps
CPU time 1.3 seconds
Started Aug 25 06:52:04 AM UTC 24
Finished Aug 25 06:52:07 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751472586 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 60.edn_err.1751472586
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/60.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/60.edn_genbits.1608698919
Short name T587
Test name
Test status
Simulation time 98645553 ps
CPU time 1.85 seconds
Started Aug 25 06:52:04 AM UTC 24
Finished Aug 25 06:52:07 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608698919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1608698919
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/60.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/61.edn_alert.825783076
Short name T306
Test name
Test status
Simulation time 250104148 ps
CPU time 1.68 seconds
Started Aug 25 06:52:04 AM UTC 24
Finished Aug 25 06:52:07 AM UTC 24
Peak memory 230296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825783076 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 61.edn_alert.825783076
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/61.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/61.edn_err.4055971641
Short name T585
Test name
Test status
Simulation time 20568389 ps
CPU time 1.49 seconds
Started Aug 25 06:52:04 AM UTC 24
Finished Aug 25 06:52:07 AM UTC 24
Peak memory 245784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055971641 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 61.edn_err.4055971641
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/61.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/61.edn_genbits.494806844
Short name T588
Test name
Test status
Simulation time 44496249 ps
CPU time 2.01 seconds
Started Aug 25 06:52:04 AM UTC 24
Finished Aug 25 06:52:07 AM UTC 24
Peak memory 229784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494806844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 61.edn_genbits.494806844
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/61.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/62.edn_alert.333883162
Short name T584
Test name
Test status
Simulation time 77735682 ps
CPU time 1.36 seconds
Started Aug 25 06:52:04 AM UTC 24
Finished Aug 25 06:52:07 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333883162 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 62.edn_alert.333883162
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/62.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/62.edn_err.3602396220
Short name T155
Test name
Test status
Simulation time 24508211 ps
CPU time 1.06 seconds
Started Aug 25 06:52:06 AM UTC 24
Finished Aug 25 06:52:08 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602396220 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 62.edn_err.3602396220
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/62.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/62.edn_genbits.4262108957
Short name T589
Test name
Test status
Simulation time 123091842 ps
CPU time 2.37 seconds
Started Aug 25 06:52:04 AM UTC 24
Finished Aug 25 06:52:08 AM UTC 24
Peak memory 231784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262108957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 62.edn_genbits.4262108957
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/62.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/63.edn_alert.3940679701
Short name T591
Test name
Test status
Simulation time 55105005 ps
CPU time 1.63 seconds
Started Aug 25 06:52:06 AM UTC 24
Finished Aug 25 06:52:09 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940679701 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 63.edn_alert.3940679701
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/63.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/63.edn_err.3797891938
Short name T136
Test name
Test status
Simulation time 36590058 ps
CPU time 1.21 seconds
Started Aug 25 06:52:06 AM UTC 24
Finished Aug 25 06:52:08 AM UTC 24
Peak memory 230388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797891938 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 63.edn_err.3797891938
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/63.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/63.edn_genbits.4058734738
Short name T594
Test name
Test status
Simulation time 29824803 ps
CPU time 1.84 seconds
Started Aug 25 06:52:06 AM UTC 24
Finished Aug 25 06:52:09 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058734738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 63.edn_genbits.4058734738
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/63.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/64.edn_alert.841226087
Short name T595
Test name
Test status
Simulation time 82367249 ps
CPU time 1.66 seconds
Started Aug 25 06:52:06 AM UTC 24
Finished Aug 25 06:52:09 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841226087 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 64.edn_alert.841226087
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/64.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/64.edn_err.3036916502
Short name T590
Test name
Test status
Simulation time 32864360 ps
CPU time 1.05 seconds
Started Aug 25 06:52:06 AM UTC 24
Finished Aug 25 06:52:08 AM UTC 24
Peak memory 230364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036916502 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 64.edn_err.3036916502
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/64.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/64.edn_genbits.1026743455
Short name T596
Test name
Test status
Simulation time 36634783 ps
CPU time 1.91 seconds
Started Aug 25 06:52:06 AM UTC 24
Finished Aug 25 06:52:09 AM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026743455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 64.edn_genbits.1026743455
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/64.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/65.edn_alert.1248918790
Short name T597
Test name
Test status
Simulation time 275086485 ps
CPU time 1.82 seconds
Started Aug 25 06:52:06 AM UTC 24
Finished Aug 25 06:52:09 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248918790 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 65.edn_alert.1248918790
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/65.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/65.edn_err.3583363872
Short name T593
Test name
Test status
Simulation time 25087974 ps
CPU time 1.43 seconds
Started Aug 25 06:52:06 AM UTC 24
Finished Aug 25 06:52:09 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583363872 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 65.edn_err.3583363872
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/65.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/66.edn_alert.3309038826
Short name T598
Test name
Test status
Simulation time 111413536 ps
CPU time 1.66 seconds
Started Aug 25 06:52:06 AM UTC 24
Finished Aug 25 06:52:09 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309038826 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 66.edn_alert.3309038826
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/66.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/66.edn_err.4118122664
Short name T592
Test name
Test status
Simulation time 27288988 ps
CPU time 1.2 seconds
Started Aug 25 06:52:06 AM UTC 24
Finished Aug 25 06:52:09 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118122664 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 66.edn_err.4118122664
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/66.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/66.edn_genbits.3775749074
Short name T600
Test name
Test status
Simulation time 68015165 ps
CPU time 1.68 seconds
Started Aug 25 06:52:06 AM UTC 24
Finished Aug 25 06:52:09 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775749074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3775749074
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/66.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/67.edn_alert.4179463246
Short name T602
Test name
Test status
Simulation time 27932832 ps
CPU time 1.77 seconds
Started Aug 25 06:52:06 AM UTC 24
Finished Aug 25 06:52:09 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179463246 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 67.edn_alert.4179463246
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/67.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/67.edn_err.674889122
Short name T147
Test name
Test status
Simulation time 68257037 ps
CPU time 1.59 seconds
Started Aug 25 06:52:06 AM UTC 24
Finished Aug 25 06:52:09 AM UTC 24
Peak memory 244100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674889122 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 67.edn_err.674889122
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/67.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/67.edn_genbits.1802078527
Short name T601
Test name
Test status
Simulation time 74963247 ps
CPU time 1.62 seconds
Started Aug 25 06:52:06 AM UTC 24
Finished Aug 25 06:52:09 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802078527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 67.edn_genbits.1802078527
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/67.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/68.edn_alert.37006148
Short name T603
Test name
Test status
Simulation time 97791377 ps
CPU time 1.82 seconds
Started Aug 25 06:52:07 AM UTC 24
Finished Aug 25 06:52:09 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37006148 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 68.edn_alert.37006148
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/68.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/68.edn_err.403016804
Short name T173
Test name
Test status
Simulation time 23445448 ps
CPU time 1.64 seconds
Started Aug 25 06:52:07 AM UTC 24
Finished Aug 25 06:52:09 AM UTC 24
Peak memory 243736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403016804 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 68.edn_err.403016804
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/68.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/68.edn_genbits.2180756197
Short name T599
Test name
Test status
Simulation time 56331086 ps
CPU time 1.53 seconds
Started Aug 25 06:52:06 AM UTC 24
Finished Aug 25 06:52:09 AM UTC 24
Peak memory 228624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180756197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2180756197
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/68.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/69.edn_alert.1361102305
Short name T604
Test name
Test status
Simulation time 80266847 ps
CPU time 1.57 seconds
Started Aug 25 06:52:07 AM UTC 24
Finished Aug 25 06:52:09 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361102305 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 69.edn_alert.1361102305
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/69.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/69.edn_err.3391072631
Short name T608
Test name
Test status
Simulation time 22928122 ps
CPU time 1.64 seconds
Started Aug 25 06:52:08 AM UTC 24
Finished Aug 25 06:52:11 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391072631 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 69.edn_err.3391072631
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/69.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/69.edn_genbits.1146396962
Short name T331
Test name
Test status
Simulation time 72618726 ps
CPU time 2.44 seconds
Started Aug 25 06:52:07 AM UTC 24
Finished Aug 25 06:52:10 AM UTC 24
Peak memory 229520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146396962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1146396962
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/69.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/7.edn_alert.1992116182
Short name T83
Test name
Test status
Simulation time 25418360 ps
CPU time 1.32 seconds
Started Aug 25 06:50:01 AM UTC 24
Finished Aug 25 06:50:04 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992116182 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 7.edn_alert.1992116182
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/7.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/7.edn_alert_test.2021388354
Short name T69
Test name
Test status
Simulation time 32054936 ps
CPU time 1.1 seconds
Started Aug 25 06:50:01 AM UTC 24
Finished Aug 25 06:50:04 AM UTC 24
Peak memory 216856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021388354 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.2021388354
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/7.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/7.edn_disable.3372899721
Short name T55
Test name
Test status
Simulation time 13785421 ps
CPU time 0.9 seconds
Started Aug 25 06:50:01 AM UTC 24
Finished Aug 25 06:50:04 AM UTC 24
Peak memory 225976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372899721 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3372899721
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/7.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/7.edn_disable_auto_req_mode.1942510057
Short name T82
Test name
Test status
Simulation time 42597673 ps
CPU time 1.24 seconds
Started Aug 25 06:50:01 AM UTC 24
Finished Aug 25 06:50:04 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942510057 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable_auto_req_mode.1942510057
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/7.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/7.edn_err.535964504
Short name T10
Test name
Test status
Simulation time 34074954 ps
CPU time 0.97 seconds
Started Aug 25 06:50:01 AM UTC 24
Finished Aug 25 06:50:04 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535964504 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 7.edn_err.535964504
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/7.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/7.edn_intr.2604209189
Short name T72
Test name
Test status
Simulation time 33918525 ps
CPU time 1.14 seconds
Started Aug 25 06:50:01 AM UTC 24
Finished Aug 25 06:50:04 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604209189 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 7.edn_intr.2604209189
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/7.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/7.edn_regwen.4138367057
Short name T326
Test name
Test status
Simulation time 26458687 ps
CPU time 1.24 seconds
Started Aug 25 06:50:01 AM UTC 24
Finished Aug 25 06:50:04 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138367057 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 7.edn_regwen.4138367057
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/7.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/7.edn_smoke.382139637
Short name T364
Test name
Test status
Simulation time 51317645 ps
CPU time 0.84 seconds
Started Aug 25 06:50:01 AM UTC 24
Finished Aug 25 06:50:03 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382139637 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 7.edn_smoke.382139637
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/7.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/7.edn_stress_all.603666894
Short name T116
Test name
Test status
Simulation time 463635594 ps
CPU time 2.99 seconds
Started Aug 25 06:50:01 AM UTC 24
Finished Aug 25 06:50:06 AM UTC 24
Peak memory 229716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603666894 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.603666894
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/7.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/70.edn_err.247478421
Short name T606
Test name
Test status
Simulation time 38767542 ps
CPU time 1.14 seconds
Started Aug 25 06:52:08 AM UTC 24
Finished Aug 25 06:52:10 AM UTC 24
Peak memory 228448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247478421 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 70.edn_err.247478421
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/70.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/70.edn_genbits.1533017797
Short name T332
Test name
Test status
Simulation time 40620288 ps
CPU time 1.95 seconds
Started Aug 25 06:52:08 AM UTC 24
Finished Aug 25 06:52:11 AM UTC 24
Peak memory 230612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533017797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 70.edn_genbits.1533017797
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/70.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/71.edn_alert.1449666140
Short name T610
Test name
Test status
Simulation time 58192418 ps
CPU time 1.49 seconds
Started Aug 25 06:52:08 AM UTC 24
Finished Aug 25 06:52:11 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449666140 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 71.edn_alert.1449666140
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/71.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/71.edn_err.2074286527
Short name T614
Test name
Test status
Simulation time 108256189 ps
CPU time 1.91 seconds
Started Aug 25 06:52:08 AM UTC 24
Finished Aug 25 06:52:11 AM UTC 24
Peak memory 242668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074286527 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 71.edn_err.2074286527
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/71.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/71.edn_genbits.573099323
Short name T333
Test name
Test status
Simulation time 125625837 ps
CPU time 1.7 seconds
Started Aug 25 06:52:08 AM UTC 24
Finished Aug 25 06:52:11 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573099323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 71.edn_genbits.573099323
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/71.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/72.edn_alert.2310246758
Short name T612
Test name
Test status
Simulation time 90353196 ps
CPU time 1.63 seconds
Started Aug 25 06:52:08 AM UTC 24
Finished Aug 25 06:52:11 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310246758 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 72.edn_alert.2310246758
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/72.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/72.edn_err.3714892061
Short name T611
Test name
Test status
Simulation time 33542427 ps
CPU time 1.62 seconds
Started Aug 25 06:52:08 AM UTC 24
Finished Aug 25 06:52:11 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714892061 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 72.edn_err.3714892061
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/72.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/72.edn_genbits.2955310580
Short name T613
Test name
Test status
Simulation time 72791251 ps
CPU time 1.77 seconds
Started Aug 25 06:52:08 AM UTC 24
Finished Aug 25 06:52:11 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955310580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2955310580
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/72.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/73.edn_alert.950576541
Short name T620
Test name
Test status
Simulation time 32994555 ps
CPU time 1.93 seconds
Started Aug 25 06:52:08 AM UTC 24
Finished Aug 25 06:52:12 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950576541 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 73.edn_alert.950576541
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/73.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/73.edn_err.1166534310
Short name T174
Test name
Test status
Simulation time 21878435 ps
CPU time 1.73 seconds
Started Aug 25 06:52:08 AM UTC 24
Finished Aug 25 06:52:12 AM UTC 24
Peak memory 243736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166534310 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 73.edn_err.1166534310
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/73.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/73.edn_genbits.3464422785
Short name T615
Test name
Test status
Simulation time 27131992 ps
CPU time 1.84 seconds
Started Aug 25 06:52:08 AM UTC 24
Finished Aug 25 06:52:11 AM UTC 24
Peak memory 230284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464422785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 73.edn_genbits.3464422785
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/73.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/74.edn_alert.3751455327
Short name T616
Test name
Test status
Simulation time 22493222 ps
CPU time 1.69 seconds
Started Aug 25 06:52:08 AM UTC 24
Finished Aug 25 06:52:11 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751455327 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 74.edn_alert.3751455327
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/74.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/74.edn_err.2894255625
Short name T619
Test name
Test status
Simulation time 198446179 ps
CPU time 1.61 seconds
Started Aug 25 06:52:09 AM UTC 24
Finished Aug 25 06:52:12 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894255625 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 74.edn_err.2894255625
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/74.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/74.edn_genbits.3573504573
Short name T621
Test name
Test status
Simulation time 76108521 ps
CPU time 1.91 seconds
Started Aug 25 06:52:08 AM UTC 24
Finished Aug 25 06:52:12 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573504573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 74.edn_genbits.3573504573
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/74.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/75.edn_alert.630507751
Short name T618
Test name
Test status
Simulation time 23531865 ps
CPU time 1.71 seconds
Started Aug 25 06:52:09 AM UTC 24
Finished Aug 25 06:52:12 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630507751 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 75.edn_alert.630507751
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/75.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/75.edn_err.2367537918
Short name T617
Test name
Test status
Simulation time 32486959 ps
CPU time 1.48 seconds
Started Aug 25 06:52:09 AM UTC 24
Finished Aug 25 06:52:12 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367537918 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 75.edn_err.2367537918
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/75.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/76.edn_alert.1430440870
Short name T632
Test name
Test status
Simulation time 31312860 ps
CPU time 1.78 seconds
Started Aug 25 06:52:10 AM UTC 24
Finished Aug 25 06:52:13 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430440870 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 76.edn_alert.1430440870
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/76.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/76.edn_err.244970165
Short name T630
Test name
Test status
Simulation time 22562022 ps
CPU time 1.7 seconds
Started Aug 25 06:52:10 AM UTC 24
Finished Aug 25 06:52:13 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244970165 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 76.edn_err.244970165
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/76.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/76.edn_genbits.2703549423
Short name T624
Test name
Test status
Simulation time 56218952 ps
CPU time 1.79 seconds
Started Aug 25 06:52:09 AM UTC 24
Finished Aug 25 06:52:12 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703549423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2703549423
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/76.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/77.edn_alert.2830514388
Short name T626
Test name
Test status
Simulation time 65028673 ps
CPU time 1.52 seconds
Started Aug 25 06:52:10 AM UTC 24
Finished Aug 25 06:52:13 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830514388 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 77.edn_alert.2830514388
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/77.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/77.edn_err.1329510683
Short name T625
Test name
Test status
Simulation time 22538008 ps
CPU time 1.55 seconds
Started Aug 25 06:52:10 AM UTC 24
Finished Aug 25 06:52:13 AM UTC 24
Peak memory 237336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329510683 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 77.edn_err.1329510683
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/77.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/77.edn_genbits.247887853
Short name T627
Test name
Test status
Simulation time 24149933 ps
CPU time 1.61 seconds
Started Aug 25 06:52:10 AM UTC 24
Finished Aug 25 06:52:13 AM UTC 24
Peak memory 228140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247887853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 77.edn_genbits.247887853
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/77.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/78.edn_alert.496194762
Short name T629
Test name
Test status
Simulation time 23505680 ps
CPU time 1.48 seconds
Started Aug 25 06:52:10 AM UTC 24
Finished Aug 25 06:52:13 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496194762 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 78.edn_alert.496194762
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/78.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/78.edn_err.1616406178
Short name T628
Test name
Test status
Simulation time 24332252 ps
CPU time 1.35 seconds
Started Aug 25 06:52:10 AM UTC 24
Finished Aug 25 06:52:13 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616406178 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 78.edn_err.1616406178
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/78.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/78.edn_genbits.555143876
Short name T633
Test name
Test status
Simulation time 45824115 ps
CPU time 1.62 seconds
Started Aug 25 06:52:10 AM UTC 24
Finished Aug 25 06:52:13 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555143876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 78.edn_genbits.555143876
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/78.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/79.edn_alert.3034931813
Short name T637
Test name
Test status
Simulation time 28895684 ps
CPU time 1.87 seconds
Started Aug 25 06:52:10 AM UTC 24
Finished Aug 25 06:52:13 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034931813 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 79.edn_alert.3034931813
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/79.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/79.edn_err.4004561839
Short name T192
Test name
Test status
Simulation time 19500668 ps
CPU time 1.51 seconds
Started Aug 25 06:52:10 AM UTC 24
Finished Aug 25 06:52:13 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004561839 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 79.edn_err.4004561839
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/79.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/79.edn_genbits.3231977181
Short name T640
Test name
Test status
Simulation time 118010994 ps
CPU time 3.84 seconds
Started Aug 25 06:52:10 AM UTC 24
Finished Aug 25 06:52:15 AM UTC 24
Peak memory 231780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231977181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3231977181
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/79.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/8.edn_alert.764666297
Short name T79
Test name
Test status
Simulation time 40315666 ps
CPU time 1.2 seconds
Started Aug 25 06:50:01 AM UTC 24
Finished Aug 25 06:50:04 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764666297 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 8.edn_alert.764666297
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/8.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/8.edn_alert_test.861574734
Short name T366
Test name
Test status
Simulation time 36774854 ps
CPU time 0.9 seconds
Started Aug 25 06:50:01 AM UTC 24
Finished Aug 25 06:50:04 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861574734 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.861574734
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/8.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/8.edn_disable.860822451
Short name T52
Test name
Test status
Simulation time 21736392 ps
CPU time 0.8 seconds
Started Aug 25 06:50:01 AM UTC 24
Finished Aug 25 06:50:04 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860822451 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.860822451
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/8.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/8.edn_disable_auto_req_mode.2525167501
Short name T22
Test name
Test status
Simulation time 45120155 ps
CPU time 1.01 seconds
Started Aug 25 06:50:01 AM UTC 24
Finished Aug 25 06:50:04 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525167501 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable_auto_req_mode.2525167501
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/8.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/8.edn_err.2592459793
Short name T106
Test name
Test status
Simulation time 32195049 ps
CPU time 0.97 seconds
Started Aug 25 06:50:01 AM UTC 24
Finished Aug 25 06:50:04 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592459793 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 8.edn_err.2592459793
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/8.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/8.edn_genbits.1173854471
Short name T80
Test name
Test status
Simulation time 185643122 ps
CPU time 1.58 seconds
Started Aug 25 06:50:01 AM UTC 24
Finished Aug 25 06:50:05 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173854471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1173854471
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/8.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/8.edn_intr.945763272
Short name T67
Test name
Test status
Simulation time 27879759 ps
CPU time 1.09 seconds
Started Aug 25 06:50:01 AM UTC 24
Finished Aug 25 06:50:04 AM UTC 24
Peak memory 236760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945763272 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 8.edn_intr.945763272
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/8.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/8.edn_regwen.2577573662
Short name T73
Test name
Test status
Simulation time 42711283 ps
CPU time 1 seconds
Started Aug 25 06:50:01 AM UTC 24
Finished Aug 25 06:50:04 AM UTC 24
Peak memory 215736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577573662 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 8.edn_regwen.2577573662
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/8.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/8.edn_smoke.50702319
Short name T367
Test name
Test status
Simulation time 43987641 ps
CPU time 1.13 seconds
Started Aug 25 06:50:01 AM UTC 24
Finished Aug 25 06:50:04 AM UTC 24
Peak memory 226012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50702319 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 8.edn_smoke.50702319
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/8.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/8.edn_stress_all.1215644519
Short name T122
Test name
Test status
Simulation time 465201231 ps
CPU time 2.87 seconds
Started Aug 25 06:50:01 AM UTC 24
Finished Aug 25 06:50:06 AM UTC 24
Peak memory 227636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215644519 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.1215644519
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/8.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/80.edn_alert.1495663473
Short name T635
Test name
Test status
Simulation time 43887075 ps
CPU time 1.53 seconds
Started Aug 25 06:52:10 AM UTC 24
Finished Aug 25 06:52:13 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495663473 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 80.edn_alert.1495663473
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/80.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/80.edn_err.1547596000
Short name T631
Test name
Test status
Simulation time 24265243 ps
CPU time 1.27 seconds
Started Aug 25 06:52:10 AM UTC 24
Finished Aug 25 06:52:13 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547596000 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 80.edn_err.1547596000
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/80.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/80.edn_genbits.3055553069
Short name T634
Test name
Test status
Simulation time 67750989 ps
CPU time 1.4 seconds
Started Aug 25 06:52:10 AM UTC 24
Finished Aug 25 06:52:13 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055553069 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 80.edn_genbits.3055553069
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/80.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/81.edn_alert.393312113
Short name T202
Test name
Test status
Simulation time 40962350 ps
CPU time 1.62 seconds
Started Aug 25 06:52:11 AM UTC 24
Finished Aug 25 06:52:13 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393312113 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 81.edn_alert.393312113
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/81.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/81.edn_err.604736693
Short name T148
Test name
Test status
Simulation time 26357350 ps
CPU time 1.38 seconds
Started Aug 25 06:52:11 AM UTC 24
Finished Aug 25 06:52:13 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604736693 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 81.edn_err.604736693
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/81.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/81.edn_genbits.2832868563
Short name T636
Test name
Test status
Simulation time 287448601 ps
CPU time 1.47 seconds
Started Aug 25 06:52:10 AM UTC 24
Finished Aug 25 06:52:13 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832868563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 81.edn_genbits.2832868563
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/81.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/82.edn_alert.3637646565
Short name T638
Test name
Test status
Simulation time 51391359 ps
CPU time 1.55 seconds
Started Aug 25 06:52:11 AM UTC 24
Finished Aug 25 06:52:13 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637646565 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 82.edn_alert.3637646565
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/82.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/82.edn_err.3145234042
Short name T161
Test name
Test status
Simulation time 31064251 ps
CPU time 1.33 seconds
Started Aug 25 06:52:12 AM UTC 24
Finished Aug 25 06:52:15 AM UTC 24
Peak memory 246504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145234042 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 82.edn_err.3145234042
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/82.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/82.edn_genbits.3199117343
Short name T639
Test name
Test status
Simulation time 121529971 ps
CPU time 2.96 seconds
Started Aug 25 06:52:11 AM UTC 24
Finished Aug 25 06:52:15 AM UTC 24
Peak memory 231520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199117343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3199117343
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/82.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/83.edn_alert.4124601888
Short name T181
Test name
Test status
Simulation time 378110232 ps
CPU time 2.23 seconds
Started Aug 25 06:52:12 AM UTC 24
Finished Aug 25 06:52:16 AM UTC 24
Peak memory 232260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124601888 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 83.edn_alert.4124601888
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/83.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/83.edn_err.2704407444
Short name T213
Test name
Test status
Simulation time 24238332 ps
CPU time 1.53 seconds
Started Aug 25 06:52:12 AM UTC 24
Finished Aug 25 06:52:16 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704407444 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 83.edn_err.2704407444
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/83.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/83.edn_genbits.513895623
Short name T641
Test name
Test status
Simulation time 201152782 ps
CPU time 1.66 seconds
Started Aug 25 06:52:12 AM UTC 24
Finished Aug 25 06:52:15 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513895623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 83.edn_genbits.513895623
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/83.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/84.edn_alert.4255885950
Short name T651
Test name
Test status
Simulation time 104984904 ps
CPU time 1.64 seconds
Started Aug 25 06:52:12 AM UTC 24
Finished Aug 25 06:52:22 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255885950 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 84.edn_alert.4255885950
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/84.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/84.edn_err.2582174243
Short name T647
Test name
Test status
Simulation time 18337238 ps
CPU time 1.47 seconds
Started Aug 25 06:52:12 AM UTC 24
Finished Aug 25 06:52:22 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582174243 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 84.edn_err.2582174243
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/84.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/84.edn_genbits.3997845093
Short name T642
Test name
Test status
Simulation time 273426208 ps
CPU time 1.74 seconds
Started Aug 25 06:52:12 AM UTC 24
Finished Aug 25 06:52:16 AM UTC 24
Peak memory 228228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997845093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3997845093
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/84.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/85.edn_alert.1644659370
Short name T652
Test name
Test status
Simulation time 72407149 ps
CPU time 1.6 seconds
Started Aug 25 06:52:12 AM UTC 24
Finished Aug 25 06:52:22 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644659370 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 85.edn_alert.1644659370
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/85.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/85.edn_err.1259038956
Short name T653
Test name
Test status
Simulation time 181052400 ps
CPU time 1.55 seconds
Started Aug 25 06:52:12 AM UTC 24
Finished Aug 25 06:52:22 AM UTC 24
Peak memory 230040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259038956 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 85.edn_err.1259038956
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/85.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/85.edn_genbits.4033166249
Short name T649
Test name
Test status
Simulation time 34632824 ps
CPU time 1.47 seconds
Started Aug 25 06:52:12 AM UTC 24
Finished Aug 25 06:52:22 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033166249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 85.edn_genbits.4033166249
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/85.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/86.edn_alert.2216246394
Short name T654
Test name
Test status
Simulation time 25726913 ps
CPU time 1.8 seconds
Started Aug 25 06:52:12 AM UTC 24
Finished Aug 25 06:52:22 AM UTC 24
Peak memory 228332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216246394 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 86.edn_alert.2216246394
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/86.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/86.edn_err.510856363
Short name T660
Test name
Test status
Simulation time 19630920 ps
CPU time 1.48 seconds
Started Aug 25 06:52:12 AM UTC 24
Finished Aug 25 06:52:23 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510856363 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 86.edn_err.510856363
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/86.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/86.edn_genbits.1763104990
Short name T339
Test name
Test status
Simulation time 67636112 ps
CPU time 1.89 seconds
Started Aug 25 06:52:12 AM UTC 24
Finished Aug 25 06:52:22 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763104990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 86.edn_genbits.1763104990
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/86.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/87.edn_alert.3837011396
Short name T663
Test name
Test status
Simulation time 39515763 ps
CPU time 1.69 seconds
Started Aug 25 06:52:13 AM UTC 24
Finished Aug 25 06:52:24 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837011396 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 87.edn_alert.3837011396
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/87.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/87.edn_err.948193719
Short name T203
Test name
Test status
Simulation time 29295027 ps
CPU time 1.31 seconds
Started Aug 25 06:52:14 AM UTC 24
Finished Aug 25 06:52:23 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948193719 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 87.edn_err.948193719
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/87.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/87.edn_genbits.361437390
Short name T661
Test name
Test status
Simulation time 107499362 ps
CPU time 1.54 seconds
Started Aug 25 06:52:13 AM UTC 24
Finished Aug 25 06:52:23 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361437390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 87.edn_genbits.361437390
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/87.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/88.edn_alert.2725287766
Short name T662
Test name
Test status
Simulation time 111345808 ps
CPU time 1.5 seconds
Started Aug 25 06:52:14 AM UTC 24
Finished Aug 25 06:52:23 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725287766 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 88.edn_alert.2725287766
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/88.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/88.edn_err.4081918164
Short name T664
Test name
Test status
Simulation time 19885457 ps
CPU time 1.57 seconds
Started Aug 25 06:52:14 AM UTC 24
Finished Aug 25 06:52:24 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081918164 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 88.edn_err.4081918164
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/88.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/88.edn_genbits.1979540389
Short name T674
Test name
Test status
Simulation time 135729014 ps
CPU time 2.97 seconds
Started Aug 25 06:52:14 AM UTC 24
Finished Aug 25 06:52:25 AM UTC 24
Peak memory 229580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979540389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1979540389
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/88.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/89.edn_alert.913726970
Short name T669
Test name
Test status
Simulation time 48770742 ps
CPU time 1.77 seconds
Started Aug 25 06:52:14 AM UTC 24
Finished Aug 25 06:52:24 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913726970 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 89.edn_alert.913726970
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/89.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/89.edn_err.3388163625
Short name T666
Test name
Test status
Simulation time 50681112 ps
CPU time 1.62 seconds
Started Aug 25 06:52:14 AM UTC 24
Finished Aug 25 06:52:24 AM UTC 24
Peak memory 236932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388163625 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 89.edn_err.3388163625
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/89.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/89.edn_genbits.273995089
Short name T675
Test name
Test status
Simulation time 76121003 ps
CPU time 2.9 seconds
Started Aug 25 06:52:14 AM UTC 24
Finished Aug 25 06:52:25 AM UTC 24
Peak memory 231520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273995089 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 89.edn_genbits.273995089
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/89.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/9.edn_alert_test.2778579934
Short name T368
Test name
Test status
Simulation time 48887869 ps
CPU time 0.88 seconds
Started Aug 25 06:50:04 AM UTC 24
Finished Aug 25 06:50:07 AM UTC 24
Peak memory 216248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778579934 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.2778579934
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/9.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/9.edn_disable.1862115521
Short name T78
Test name
Test status
Simulation time 24622956 ps
CPU time 0.96 seconds
Started Aug 25 06:50:02 AM UTC 24
Finished Aug 25 06:50:04 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862115521 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1862115521
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/9.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/9.edn_disable_auto_req_mode.96895304
Short name T49
Test name
Test status
Simulation time 169768429 ps
CPU time 1.2 seconds
Started Aug 25 06:50:04 AM UTC 24
Finished Aug 25 06:50:07 AM UTC 24
Peak memory 230348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96895304 -assert nopostproc +UVM_TESTNAME=edn_disab
le_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable_auto_req_mode.96895304
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/9.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/9.edn_genbits.1540131321
Short name T13
Test name
Test status
Simulation time 53177899 ps
CPU time 1.13 seconds
Started Aug 25 06:50:02 AM UTC 24
Finished Aug 25 06:50:04 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540131321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1540131321
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/9.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/9.edn_intr.2851130203
Short name T33
Test name
Test status
Simulation time 35845242 ps
CPU time 1.02 seconds
Started Aug 25 06:50:02 AM UTC 24
Finished Aug 25 06:50:04 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851130203 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 9.edn_intr.2851130203
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/9.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/9.edn_regwen.4181138562
Short name T115
Test name
Test status
Simulation time 15729463 ps
CPU time 0.9 seconds
Started Aug 25 06:50:02 AM UTC 24
Finished Aug 25 06:50:04 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181138562 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 9.edn_regwen.4181138562
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/9.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/9.edn_smoke.2190005629
Short name T119
Test name
Test status
Simulation time 23929572 ps
CPU time 0.87 seconds
Started Aug 25 06:50:02 AM UTC 24
Finished Aug 25 06:50:04 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190005629 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 9.edn_smoke.2190005629
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/9.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/9.edn_stress_all.3755979838
Short name T125
Test name
Test status
Simulation time 348699852 ps
CPU time 6.16 seconds
Started Aug 25 06:50:02 AM UTC 24
Finished Aug 25 06:50:10 AM UTC 24
Peak memory 229444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755979838 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.3755979838
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/9.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/90.edn_alert.3925363170
Short name T667
Test name
Test status
Simulation time 106720437 ps
CPU time 1.56 seconds
Started Aug 25 06:52:14 AM UTC 24
Finished Aug 25 06:52:24 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925363170 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 90.edn_alert.3925363170
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/90.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/90.edn_err.791326196
Short name T671
Test name
Test status
Simulation time 45544869 ps
CPU time 1.66 seconds
Started Aug 25 06:52:14 AM UTC 24
Finished Aug 25 06:52:24 AM UTC 24
Peak memory 246088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791326196 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 90.edn_err.791326196
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/90.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/90.edn_genbits.3561440973
Short name T668
Test name
Test status
Simulation time 74050854 ps
CPU time 1.75 seconds
Started Aug 25 06:52:14 AM UTC 24
Finished Aug 25 06:52:24 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561440973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3561440973
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/90.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/91.edn_alert.2472166307
Short name T211
Test name
Test status
Simulation time 45237875 ps
CPU time 1.69 seconds
Started Aug 25 06:52:14 AM UTC 24
Finished Aug 25 06:52:24 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472166307 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 91.edn_alert.2472166307
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/91.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/91.edn_err.795828822
Short name T665
Test name
Test status
Simulation time 27854999 ps
CPU time 1.15 seconds
Started Aug 25 06:52:14 AM UTC 24
Finished Aug 25 06:52:24 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795828822 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 91.edn_err.795828822
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/91.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/91.edn_genbits.1593609923
Short name T672
Test name
Test status
Simulation time 30078551 ps
CPU time 1.7 seconds
Started Aug 25 06:52:14 AM UTC 24
Finished Aug 25 06:52:24 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593609923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 91.edn_genbits.1593609923
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/91.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/92.edn_alert.1910329526
Short name T702
Test name
Test status
Simulation time 25139412 ps
CPU time 1.77 seconds
Started Aug 25 06:52:14 AM UTC 24
Finished Aug 25 06:52:28 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910329526 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 92.edn_alert.1910329526
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/92.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/92.edn_err.3629370842
Short name T670
Test name
Test status
Simulation time 24712433 ps
CPU time 1.39 seconds
Started Aug 25 06:52:14 AM UTC 24
Finished Aug 25 06:52:24 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629370842 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 92.edn_err.3629370842
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/92.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/92.edn_genbits.2806968453
Short name T673
Test name
Test status
Simulation time 90464115 ps
CPU time 2.1 seconds
Started Aug 25 06:52:14 AM UTC 24
Finished Aug 25 06:52:25 AM UTC 24
Peak memory 229536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806968453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 92.edn_genbits.2806968453
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/92.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/93.edn_alert.2136971834
Short name T676
Test name
Test status
Simulation time 47486776 ps
CPU time 1.4 seconds
Started Aug 25 06:52:14 AM UTC 24
Finished Aug 25 06:52:25 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136971834 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 93.edn_alert.2136971834
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/93.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/93.edn_err.1219399667
Short name T700
Test name
Test status
Simulation time 21013836 ps
CPU time 1.65 seconds
Started Aug 25 06:52:14 AM UTC 24
Finished Aug 25 06:52:28 AM UTC 24
Peak memory 236892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219399667 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 93.edn_err.1219399667
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/93.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/93.edn_genbits.3356790037
Short name T724
Test name
Test status
Simulation time 100457387 ps
CPU time 3.73 seconds
Started Aug 25 06:52:14 AM UTC 24
Finished Aug 25 06:52:30 AM UTC 24
Peak memory 231568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356790037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 93.edn_genbits.3356790037
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/93.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/94.edn_alert.4056051994
Short name T696
Test name
Test status
Simulation time 79921936 ps
CPU time 1.38 seconds
Started Aug 25 06:52:14 AM UTC 24
Finished Aug 25 06:52:27 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056051994 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 94.edn_alert.4056051994
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/94.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/94.edn_err.532038964
Short name T677
Test name
Test status
Simulation time 23765137 ps
CPU time 1.33 seconds
Started Aug 25 06:52:14 AM UTC 24
Finished Aug 25 06:52:25 AM UTC 24
Peak memory 236964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532038964 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 94.edn_err.532038964
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/94.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/94.edn_genbits.1266010713
Short name T690
Test name
Test status
Simulation time 144383939 ps
CPU time 4.25 seconds
Started Aug 25 06:52:14 AM UTC 24
Finished Aug 25 06:52:27 AM UTC 24
Peak memory 231576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266010713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1266010713
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/94.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/95.edn_alert.3294721899
Short name T644
Test name
Test status
Simulation time 58243303 ps
CPU time 1.8 seconds
Started Aug 25 06:52:16 AM UTC 24
Finished Aug 25 06:52:22 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294721899 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 95.edn_alert.3294721899
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/95.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/95.edn_err.45962196
Short name T184
Test name
Test status
Simulation time 27829248 ps
CPU time 1.22 seconds
Started Aug 25 06:52:16 AM UTC 24
Finished Aug 25 06:52:21 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45962196 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 95.edn_err.45962196
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/95.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/95.edn_genbits.3192772853
Short name T622
Test name
Test status
Simulation time 120391253 ps
CPU time 1.29 seconds
Started Aug 25 06:52:16 AM UTC 24
Finished Aug 25 06:52:21 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192772853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 95.edn_genbits.3192772853
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/95.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/96.edn_alert.485092308
Short name T177
Test name
Test status
Simulation time 270419784 ps
CPU time 1.55 seconds
Started Aug 25 06:52:16 AM UTC 24
Finished Aug 25 06:52:22 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485092308 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 96.edn_alert.485092308
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/96.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/96.edn_err.810818427
Short name T645
Test name
Test status
Simulation time 24349910 ps
CPU time 1.68 seconds
Started Aug 25 06:52:16 AM UTC 24
Finished Aug 25 06:52:22 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810818427 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 96.edn_err.810818427
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/96.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/96.edn_genbits.1932745239
Short name T643
Test name
Test status
Simulation time 40823336 ps
CPU time 1.55 seconds
Started Aug 25 06:52:16 AM UTC 24
Finished Aug 25 06:52:21 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932745239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 96.edn_genbits.1932745239
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/96.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/97.edn_alert.573699948
Short name T658
Test name
Test status
Simulation time 75495905 ps
CPU time 1.66 seconds
Started Aug 25 06:52:17 AM UTC 24
Finished Aug 25 06:52:23 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573699948 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 97.edn_alert.573699948
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/97.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/97.edn_err.2965265955
Short name T656
Test name
Test status
Simulation time 23046134 ps
CPU time 1.35 seconds
Started Aug 25 06:52:17 AM UTC 24
Finished Aug 25 06:52:23 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965265955 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 97.edn_err.2965265955
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/97.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/97.edn_genbits.905514880
Short name T646
Test name
Test status
Simulation time 31669053 ps
CPU time 1.76 seconds
Started Aug 25 06:52:16 AM UTC 24
Finished Aug 25 06:52:22 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905514880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 97.edn_genbits.905514880
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/97.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/98.edn_alert.2345070419
Short name T607
Test name
Test status
Simulation time 107262638 ps
CPU time 1.27 seconds
Started Aug 25 06:52:17 AM UTC 24
Finished Aug 25 06:52:20 AM UTC 24
Peak memory 229984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345070419 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 98.edn_alert.2345070419
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/98.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/98.edn_err.1159866789
Short name T605
Test name
Test status
Simulation time 28202868 ps
CPU time 1.59 seconds
Started Aug 25 06:52:17 AM UTC 24
Finished Aug 25 06:52:21 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159866789 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 98.edn_err.1159866789
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/98.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/98.edn_genbits.2607500563
Short name T657
Test name
Test status
Simulation time 85989999 ps
CPU time 1.36 seconds
Started Aug 25 06:52:17 AM UTC 24
Finished Aug 25 06:52:23 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607500563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2607500563
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/98.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/99.edn_alert.3202401497
Short name T699
Test name
Test status
Simulation time 21745181 ps
CPU time 1.66 seconds
Started Aug 25 06:52:21 AM UTC 24
Finished Aug 25 06:52:27 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202401497 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 99.edn_alert.3202401497
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/99.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/99.edn_err.2008766793
Short name T214
Test name
Test status
Simulation time 40606707 ps
CPU time 1.43 seconds
Started Aug 25 06:52:21 AM UTC 24
Finished Aug 25 06:52:27 AM UTC 24
Peak memory 236896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008766793 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 99.edn_err.2008766793
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/99.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/default/99.edn_genbits.2320538260
Short name T609
Test name
Test status
Simulation time 85983432 ps
CPU time 1.52 seconds
Started Aug 25 06:52:17 AM UTC 24
Finished Aug 25 06:52:21 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320538260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2320538260
Directory /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/99.edn_genbits/latest
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