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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.75 98.25 93.97 97.02 91.86 96.37 99.77 92.99


Total test records in report: 1110
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T1012 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_errors.1698715982 Aug 27 09:18:46 AM UTC 24 Aug 27 09:18:51 AM UTC 24 152768668 ps
T1013 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.452207577 Aug 27 09:18:48 AM UTC 24 Aug 27 09:18:51 AM UTC 24 118801323 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_intg_err.2339087460 Aug 27 09:18:47 AM UTC 24 Aug 27 09:18:52 AM UTC 24 79175407 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_rw.51591142 Aug 27 09:18:50 AM UTC 24 Aug 27 09:18:52 AM UTC 24 73231887 ps
T1014 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/7.edn_intr_test.3908917293 Aug 27 09:18:50 AM UTC 24 Aug 27 09:18:52 AM UTC 24 68346992 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_intg_err.4266309541 Aug 27 09:18:49 AM UTC 24 Aug 27 09:18:52 AM UTC 24 98958377 ps
T1015 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/7.edn_same_csr_outstanding.1749546244 Aug 27 09:18:50 AM UTC 24 Aug 27 09:18:53 AM UTC 24 131603162 ps
T1016 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1922703331 Aug 27 09:18:50 AM UTC 24 Aug 27 09:18:53 AM UTC 24 26039830 ps
T1017 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_intg_err.3821764137 Aug 27 09:18:50 AM UTC 24 Aug 27 09:18:53 AM UTC 24 605213610 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_rw.4231348137 Aug 27 09:18:51 AM UTC 24 Aug 27 09:18:53 AM UTC 24 33851313 ps
T1018 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/8.edn_intr_test.1672336492 Aug 27 09:18:51 AM UTC 24 Aug 27 09:18:53 AM UTC 24 39937066 ps
T1019 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1734279360 Aug 27 09:18:51 AM UTC 24 Aug 27 09:18:54 AM UTC 24 19222241 ps
T1020 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/8.edn_same_csr_outstanding.1922671690 Aug 27 09:18:51 AM UTC 24 Aug 27 09:18:54 AM UTC 24 34494519 ps
T1021 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_errors.3560626182 Aug 27 09:18:50 AM UTC 24 Aug 27 09:18:54 AM UTC 24 63609821 ps
T1022 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/9.edn_intr_test.1629117228 Aug 27 09:18:53 AM UTC 24 Aug 27 09:18:55 AM UTC 24 22260282 ps
T1023 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_rw.4193597821 Aug 27 09:18:53 AM UTC 24 Aug 27 09:18:55 AM UTC 24 81819699 ps
T1024 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_intg_err.2023986597 Aug 27 09:18:51 AM UTC 24 Aug 27 09:18:55 AM UTC 24 124636683 ps
T1025 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_errors.970619071 Aug 27 09:18:48 AM UTC 24 Aug 27 09:18:55 AM UTC 24 221832625 ps
T1026 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/9.edn_same_csr_outstanding.949687827 Aug 27 09:18:53 AM UTC 24 Aug 27 09:18:55 AM UTC 24 14908956 ps
T1027 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/10.edn_intr_test.4292319512 Aug 27 09:18:54 AM UTC 24 Aug 27 09:18:56 AM UTC 24 18702608 ps
T1028 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2415372186 Aug 27 09:18:53 AM UTC 24 Aug 27 09:18:56 AM UTC 24 28599872 ps
T1029 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_intg_err.1706334777 Aug 27 09:18:53 AM UTC 24 Aug 27 09:18:56 AM UTC 24 160058101 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_rw.1501137072 Aug 27 09:18:54 AM UTC 24 Aug 27 09:18:57 AM UTC 24 119607843 ps
T1030 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/11.edn_intr_test.2582317314 Aug 27 09:18:55 AM UTC 24 Aug 27 09:18:57 AM UTC 24 19228160 ps
T1031 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/10.edn_same_csr_outstanding.3623683180 Aug 27 09:18:54 AM UTC 24 Aug 27 09:18:57 AM UTC 24 20828753 ps
T1032 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2396165311 Aug 27 09:18:54 AM UTC 24 Aug 27 09:18:57 AM UTC 24 137531710 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_rw.1509230729 Aug 27 09:18:56 AM UTC 24 Aug 27 09:18:58 AM UTC 24 36300455 ps
T1033 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_errors.3368525046 Aug 27 09:18:53 AM UTC 24 Aug 27 09:18:58 AM UTC 24 193715277 ps
T1034 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/12.edn_intr_test.3838932800 Aug 27 09:18:56 AM UTC 24 Aug 27 09:18:58 AM UTC 24 78061636 ps
T1035 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_intg_err.2973124853 Aug 27 09:18:55 AM UTC 24 Aug 27 09:18:58 AM UTC 24 876193867 ps
T1036 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/11.edn_same_csr_outstanding.4281122739 Aug 27 09:18:56 AM UTC 24 Aug 27 09:18:59 AM UTC 24 27725812 ps
T1037 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.433972957 Aug 27 09:18:56 AM UTC 24 Aug 27 09:18:59 AM UTC 24 32893428 ps
T1038 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_errors.805844903 Aug 27 09:18:56 AM UTC 24 Aug 27 09:18:59 AM UTC 24 86190822 ps
T1039 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_intg_err.87169620 Aug 27 09:18:56 AM UTC 24 Aug 27 09:18:59 AM UTC 24 459946670 ps
T1040 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_rw.845766015 Aug 27 09:18:58 AM UTC 24 Aug 27 09:19:00 AM UTC 24 67428059 ps
T1041 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/13.edn_intr_test.780420789 Aug 27 09:18:58 AM UTC 24 Aug 27 09:19:00 AM UTC 24 14909308 ps
T1042 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_errors.2298800799 Aug 27 09:18:55 AM UTC 24 Aug 27 09:19:00 AM UTC 24 207194960 ps
T1043 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_rw.4221941391 Aug 27 09:18:58 AM UTC 24 Aug 27 09:19:00 AM UTC 24 45074571 ps
T1044 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/13.edn_same_csr_outstanding.1889982962 Aug 27 09:18:58 AM UTC 24 Aug 27 09:19:00 AM UTC 24 41489283 ps
T1045 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/12.edn_same_csr_outstanding.2337610461 Aug 27 09:18:58 AM UTC 24 Aug 27 09:19:00 AM UTC 24 30172306 ps
T1046 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.4134805860 Aug 27 09:18:58 AM UTC 24 Aug 27 09:19:01 AM UTC 24 47113449 ps
T1047 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/14.edn_intr_test.1137410189 Aug 27 09:18:59 AM UTC 24 Aug 27 09:19:01 AM UTC 24 37577734 ps
T1048 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_intg_err.1973362963 Aug 27 09:18:58 AM UTC 24 Aug 27 09:19:01 AM UTC 24 95804362 ps
T1049 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1316355751 Aug 27 09:18:59 AM UTC 24 Aug 27 09:19:01 AM UTC 24 37888408 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_rw.489278398 Aug 27 09:18:59 AM UTC 24 Aug 27 09:19:02 AM UTC 24 26024586 ps
T1050 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_errors.3537701590 Aug 27 09:18:58 AM UTC 24 Aug 27 09:19:02 AM UTC 24 224096421 ps
T1051 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/14.edn_same_csr_outstanding.1383963727 Aug 27 09:18:59 AM UTC 24 Aug 27 09:19:02 AM UTC 24 33846486 ps
T1052 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_intg_err.3758938554 Aug 27 09:18:59 AM UTC 24 Aug 27 09:19:02 AM UTC 24 46084904 ps
T1053 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3969057316 Aug 27 09:19:01 AM UTC 24 Aug 27 09:19:03 AM UTC 24 17407718 ps
T1054 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/15.edn_same_csr_outstanding.2180535873 Aug 27 09:19:01 AM UTC 24 Aug 27 09:19:03 AM UTC 24 15585833 ps
T1055 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_rw.964039825 Aug 27 09:19:01 AM UTC 24 Aug 27 09:19:03 AM UTC 24 25301969 ps
T1056 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/15.edn_intr_test.2564674264 Aug 27 09:19:01 AM UTC 24 Aug 27 09:19:03 AM UTC 24 17743666 ps
T1057 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_errors.458177019 Aug 27 09:18:59 AM UTC 24 Aug 27 09:19:03 AM UTC 24 58875968 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_intg_err.3611264654 Aug 27 09:19:01 AM UTC 24 Aug 27 09:19:04 AM UTC 24 129595029 ps
T1058 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_errors.2896686265 Aug 27 09:19:01 AM UTC 24 Aug 27 09:19:04 AM UTC 24 52586364 ps
T1059 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1284209101 Aug 27 09:19:01 AM UTC 24 Aug 27 09:19:04 AM UTC 24 107092146 ps
T1060 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_rw.1318016102 Aug 27 09:19:02 AM UTC 24 Aug 27 09:19:05 AM UTC 24 55299102 ps
T1061 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.675395536 Aug 27 09:19:03 AM UTC 24 Aug 27 09:19:05 AM UTC 24 21836258 ps
T1062 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/17.edn_intr_test.938835314 Aug 27 09:19:03 AM UTC 24 Aug 27 09:19:05 AM UTC 24 17188533 ps
T1063 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/16.edn_intr_test.441279905 Aug 27 09:19:02 AM UTC 24 Aug 27 09:19:05 AM UTC 24 18208054 ps
T1064 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/16.edn_same_csr_outstanding.2556229609 Aug 27 09:19:03 AM UTC 24 Aug 27 09:19:05 AM UTC 24 26540704 ps
T1065 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_errors.260995712 Aug 27 09:19:01 AM UTC 24 Aug 27 09:19:06 AM UTC 24 91605313 ps
T1066 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_intg_err.2672404929 Aug 27 09:19:02 AM UTC 24 Aug 27 09:19:06 AM UTC 24 293447966 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_intg_err.726687687 Aug 27 09:19:03 AM UTC 24 Aug 27 09:19:06 AM UTC 24 86725685 ps
T1067 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/17.edn_same_csr_outstanding.2674011457 Aug 27 09:19:04 AM UTC 24 Aug 27 09:19:06 AM UTC 24 89224395 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_rw.2797580341 Aug 27 09:19:04 AM UTC 24 Aug 27 09:19:06 AM UTC 24 18290871 ps
T1068 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3533398861 Aug 27 09:19:04 AM UTC 24 Aug 27 09:19:06 AM UTC 24 39728676 ps
T1069 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_rw.3339123150 Aug 27 09:19:06 AM UTC 24 Aug 27 09:19:08 AM UTC 24 11636896 ps
T1070 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_errors.3488918870 Aug 27 09:19:03 AM UTC 24 Aug 27 09:19:08 AM UTC 24 330143067 ps
T1071 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_intg_err.399473542 Aug 27 09:19:04 AM UTC 24 Aug 27 09:19:08 AM UTC 24 57830021 ps
T1072 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/18.edn_intr_test.1926414673 Aug 27 09:19:05 AM UTC 24 Aug 27 09:19:08 AM UTC 24 121853009 ps
T1073 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/19.edn_intr_test.3814643463 Aug 27 09:19:06 AM UTC 24 Aug 27 09:19:08 AM UTC 24 13258874 ps
T1074 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2304992351 Aug 27 09:19:06 AM UTC 24 Aug 27 09:19:08 AM UTC 24 44264999 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_rw.3399772373 Aug 27 09:19:06 AM UTC 24 Aug 27 09:19:08 AM UTC 24 42802732 ps
T1075 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_errors.652639644 Aug 27 09:19:04 AM UTC 24 Aug 27 09:19:08 AM UTC 24 867817465 ps
T1076 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/18.edn_same_csr_outstanding.1216354109 Aug 27 09:19:06 AM UTC 24 Aug 27 09:19:08 AM UTC 24 19832055 ps
T1077 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_intg_err.4101351258 Aug 27 09:19:06 AM UTC 24 Aug 27 09:19:08 AM UTC 24 77506620 ps
T1078 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/19.edn_same_csr_outstanding.28211106 Aug 27 09:19:06 AM UTC 24 Aug 27 09:19:09 AM UTC 24 88195021 ps
T1079 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_errors.2098476830 Aug 27 09:19:06 AM UTC 24 Aug 27 09:19:09 AM UTC 24 51822366 ps
T1080 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/20.edn_intr_test.2581781601 Aug 27 09:19:07 AM UTC 24 Aug 27 09:19:09 AM UTC 24 17411231 ps
T1081 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/21.edn_intr_test.312683229 Aug 27 09:19:07 AM UTC 24 Aug 27 09:19:09 AM UTC 24 25415475 ps
T1082 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/23.edn_intr_test.3519809940 Aug 27 09:19:07 AM UTC 24 Aug 27 09:19:09 AM UTC 24 11329901 ps
T1083 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/24.edn_intr_test.2383521770 Aug 27 09:19:07 AM UTC 24 Aug 27 09:19:10 AM UTC 24 12728251 ps
T1084 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.130832573 Aug 27 09:19:07 AM UTC 24 Aug 27 09:19:10 AM UTC 24 108310357 ps
T1085 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/22.edn_intr_test.702201763 Aug 27 09:19:07 AM UTC 24 Aug 27 09:19:10 AM UTC 24 101608048 ps
T1086 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/30.edn_intr_test.1476864344 Aug 27 09:19:09 AM UTC 24 Aug 27 09:19:11 AM UTC 24 21339526 ps
T1087 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/27.edn_intr_test.3191887387 Aug 27 09:19:09 AM UTC 24 Aug 27 09:19:11 AM UTC 24 48782007 ps
T1088 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/28.edn_intr_test.968507267 Aug 27 09:19:09 AM UTC 24 Aug 27 09:19:11 AM UTC 24 37023748 ps
T1089 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/25.edn_intr_test.2629641061 Aug 27 09:19:09 AM UTC 24 Aug 27 09:19:11 AM UTC 24 13132368 ps
T1090 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/26.edn_intr_test.246700275 Aug 27 09:19:09 AM UTC 24 Aug 27 09:19:11 AM UTC 24 12886020 ps
T1091 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/29.edn_intr_test.3382302378 Aug 27 09:19:09 AM UTC 24 Aug 27 09:19:11 AM UTC 24 17585710 ps
T1092 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/31.edn_intr_test.3784702677 Aug 27 09:19:09 AM UTC 24 Aug 27 09:19:11 AM UTC 24 11972837 ps
T1093 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/32.edn_intr_test.3611940425 Aug 27 09:19:10 AM UTC 24 Aug 27 09:19:12 AM UTC 24 16002996 ps
T1094 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/36.edn_intr_test.2046646972 Aug 27 09:19:11 AM UTC 24 Aug 27 09:19:13 AM UTC 24 15171892 ps
T1095 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/33.edn_intr_test.3353651740 Aug 27 09:19:10 AM UTC 24 Aug 27 09:19:13 AM UTC 24 66259950 ps
T1096 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/38.edn_intr_test.1642465793 Aug 27 09:19:11 AM UTC 24 Aug 27 09:19:13 AM UTC 24 53165060 ps
T1097 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/34.edn_intr_test.1515542355 Aug 27 09:19:11 AM UTC 24 Aug 27 09:19:13 AM UTC 24 50361974 ps
T1098 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/42.edn_intr_test.2942503270 Aug 27 09:19:11 AM UTC 24 Aug 27 09:19:13 AM UTC 24 11960463 ps
T1099 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/37.edn_intr_test.3522848658 Aug 27 09:19:11 AM UTC 24 Aug 27 09:19:13 AM UTC 24 15064072 ps
T1100 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/39.edn_intr_test.470102083 Aug 27 09:19:11 AM UTC 24 Aug 27 09:19:13 AM UTC 24 42366917 ps
T1101 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/40.edn_intr_test.4142120730 Aug 27 09:19:11 AM UTC 24 Aug 27 09:19:13 AM UTC 24 51131413 ps
T1102 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/35.edn_intr_test.2338749468 Aug 27 09:19:11 AM UTC 24 Aug 27 09:19:13 AM UTC 24 17105636 ps
T1103 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/41.edn_intr_test.3836157210 Aug 27 09:19:11 AM UTC 24 Aug 27 09:19:13 AM UTC 24 16921104 ps
T1104 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/43.edn_intr_test.2311081802 Aug 27 09:19:12 AM UTC 24 Aug 27 09:19:14 AM UTC 24 20950017 ps
T1105 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/45.edn_intr_test.820524345 Aug 27 09:19:12 AM UTC 24 Aug 27 09:19:14 AM UTC 24 12978229 ps
T1106 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/44.edn_intr_test.1741210312 Aug 27 09:19:12 AM UTC 24 Aug 27 09:19:14 AM UTC 24 29224468 ps
T1107 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/48.edn_intr_test.2828013645 Aug 27 09:19:12 AM UTC 24 Aug 27 09:19:15 AM UTC 24 32184149 ps
T1108 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/47.edn_intr_test.3612039066 Aug 27 09:19:12 AM UTC 24 Aug 27 09:19:15 AM UTC 24 36367273 ps
T1109 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/49.edn_intr_test.2722660401 Aug 27 09:19:12 AM UTC 24 Aug 27 09:19:15 AM UTC 24 85712099 ps
T1110 /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/46.edn_intr_test.1475069151 Aug 27 09:19:12 AM UTC 24 Aug 27 09:19:15 AM UTC 24 24142092 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/0.edn_disable_auto_req_mode.2891673461
Short name T9
Test name
Test status
Simulation time 25589419 ps
CPU time 1.48 seconds
Started Aug 27 09:10:45 AM UTC 24
Finished Aug 27 09:10:48 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891673461 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable_auto_req_mode.2891673461
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/0.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/0.edn_stress_all.1751443017
Short name T6
Test name
Test status
Simulation time 238176472 ps
CPU time 5.86 seconds
Started Aug 27 09:10:41 AM UTC 24
Finished Aug 27 09:10:48 AM UTC 24
Peak memory 229864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751443017 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.1751443017
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/0.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/7.edn_genbits.1833683310
Short name T46
Test name
Test status
Simulation time 58104251 ps
CPU time 1.73 seconds
Started Aug 27 09:11:25 AM UTC 24
Finished Aug 27 09:11:28 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833683310 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1833683310
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/7.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/0.edn_sec_cm.308831399
Short name T14
Test name
Test status
Simulation time 469919625 ps
CPU time 5.81 seconds
Started Aug 27 09:10:45 AM UTC 24
Finished Aug 27 09:10:52 AM UTC 24
Peak memory 262552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308831399 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.308831399
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/0.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/0.edn_alert.2387730267
Short name T23
Test name
Test status
Simulation time 22103255 ps
CPU time 1.51 seconds
Started Aug 27 09:10:43 AM UTC 24
Finished Aug 27 09:10:45 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387730267 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 0.edn_alert.2387730267
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/0.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/1.edn_stress_all_with_rand_reset.2829458433
Short name T38
Test name
Test status
Simulation time 31140096619 ps
CPU time 76.97 seconds
Started Aug 27 09:10:47 AM UTC 24
Finished Aug 27 09:12:05 AM UTC 24
Peak memory 233864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2829458433 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_
with_rand_reset.2829458433
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/1.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/3.edn_sec_cm.1909983457
Short name T19
Test name
Test status
Simulation time 2256848250 ps
CPU time 10.46 seconds
Started Aug 27 09:11:03 AM UTC 24
Finished Aug 27 09:11:14 AM UTC 24
Peak memory 262536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909983457 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.1909983457
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/3.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/8.edn_alert.4128041903
Short name T116
Test name
Test status
Simulation time 33283789 ps
CPU time 1.71 seconds
Started Aug 27 09:11:34 AM UTC 24
Finished Aug 27 09:11:37 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128041903 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 8.edn_alert.4128041903
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/8.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/5.edn_genbits.3670135584
Short name T18
Test name
Test status
Simulation time 75074760 ps
CPU time 2.22 seconds
Started Aug 27 09:11:12 AM UTC 24
Finished Aug 27 09:11:15 AM UTC 24
Peak memory 231576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670135584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3670135584
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/5.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/12.edn_intr.4263911494
Short name T31
Test name
Test status
Simulation time 45614927 ps
CPU time 1.32 seconds
Started Aug 27 09:12:00 AM UTC 24
Finished Aug 27 09:12:02 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263911494 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 12.edn_intr.4263911494
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/12.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/0.edn_disable.2762340051
Short name T22
Test name
Test status
Simulation time 43042880 ps
CPU time 1.2 seconds
Started Aug 27 09:10:43 AM UTC 24
Finished Aug 27 09:10:45 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762340051 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2762340051
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/0.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/5.edn_regwen.2678791711
Short name T110
Test name
Test status
Simulation time 44731742 ps
CPU time 1.09 seconds
Started Aug 27 09:11:12 AM UTC 24
Finished Aug 27 09:11:14 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678791711 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 5.edn_regwen.2678791711
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/5.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/1.edn_alert.2412115967
Short name T10
Test name
Test status
Simulation time 82102721 ps
CPU time 1.51 seconds
Started Aug 27 09:10:49 AM UTC 24
Finished Aug 27 09:10:51 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412115967 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 1.edn_alert.2412115967
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/1.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/14.edn_stress_all_with_rand_reset.619999913
Short name T237
Test name
Test status
Simulation time 2990227261 ps
CPU time 72.03 seconds
Started Aug 27 09:12:11 AM UTC 24
Finished Aug 27 09:13:25 AM UTC 24
Peak memory 229988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=619999913 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_
with_rand_reset.619999913
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/14.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_intg_err.2339087460
Short name T314
Test name
Test status
Simulation time 79175407 ps
CPU time 3.46 seconds
Started Aug 27 09:18:47 AM UTC 24
Finished Aug 27 09:18:52 AM UTC 24
Peak memory 217544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339087460 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.2339087460
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/6.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/2.edn_disable.3774766873
Short name T51
Test name
Test status
Simulation time 18717355 ps
CPU time 1.19 seconds
Started Aug 27 09:10:56 AM UTC 24
Finished Aug 27 09:10:58 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774766873 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.3774766873
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/2.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/28.edn_disable_auto_req_mode.257507201
Short name T131
Test name
Test status
Simulation time 73572483 ps
CPU time 1.49 seconds
Started Aug 27 09:13:30 AM UTC 24
Finished Aug 27 09:13:32 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257507201 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable_auto_req_mode.257507201
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/28.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/20.edn_alert.2122557072
Short name T172
Test name
Test status
Simulation time 23052197 ps
CPU time 1.65 seconds
Started Aug 27 09:12:49 AM UTC 24
Finished Aug 27 09:12:52 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122557072 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 20.edn_alert.2122557072
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/20.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/8.edn_err.1866183672
Short name T61
Test name
Test status
Simulation time 72014873 ps
CPU time 1.29 seconds
Started Aug 27 09:11:34 AM UTC 24
Finished Aug 27 09:11:37 AM UTC 24
Peak memory 236872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866183672 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 8.edn_err.1866183672
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/8.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/1.edn_genbits.1644403629
Short name T39
Test name
Test status
Simulation time 35506747 ps
CPU time 2.15 seconds
Started Aug 27 09:10:47 AM UTC 24
Finished Aug 27 09:10:50 AM UTC 24
Peak memory 229600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644403629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_genbits.1644403629
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/1.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/29.edn_disable.2593466944
Short name T195
Test name
Test status
Simulation time 18578080 ps
CPU time 1.11 seconds
Started Aug 27 09:13:34 AM UTC 24
Finished Aug 27 09:13:36 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593466944 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2593466944
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/29.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/40.edn_alert.330511505
Short name T145
Test name
Test status
Simulation time 58884830 ps
CPU time 1.52 seconds
Started Aug 27 09:15:00 AM UTC 24
Finished Aug 27 09:15:03 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330511505 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 40.edn_alert.330511505
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/40.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/73.edn_alert.98368031
Short name T166
Test name
Test status
Simulation time 38613899 ps
CPU time 1.59 seconds
Started Aug 27 09:16:40 AM UTC 24
Finished Aug 27 09:16:43 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98368031 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 73.edn_alert.98368031
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/73.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/130.edn_alert.3642825842
Short name T321
Test name
Test status
Simulation time 28737129 ps
CPU time 1.82 seconds
Started Aug 27 09:17:27 AM UTC 24
Finished Aug 27 09:17:29 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642825842 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 130.edn_alert.3642825842
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/130.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_aliasing.3400409412
Short name T274
Test name
Test status
Simulation time 124669399 ps
CPU time 2.01 seconds
Started Aug 27 09:18:35 AM UTC 24
Finished Aug 27 09:18:38 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400409412 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.3400409412
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/0.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/2.edn_intr.2865571723
Short name T29
Test name
Test status
Simulation time 19763177 ps
CPU time 1.55 seconds
Started Aug 27 09:10:53 AM UTC 24
Finished Aug 27 09:10:56 AM UTC 24
Peak memory 228480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865571723 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 2.edn_intr.2865571723
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/2.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/8.edn_disable_auto_req_mode.2129827136
Short name T20
Test name
Test status
Simulation time 109250688 ps
CPU time 1.61 seconds
Started Aug 27 09:11:36 AM UTC 24
Finished Aug 27 09:11:39 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129827136 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable_auto_req_mode.2129827136
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/8.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/99.edn_genbits.3343217225
Short name T338
Test name
Test status
Simulation time 138002012 ps
CPU time 3.01 seconds
Started Aug 27 09:17:07 AM UTC 24
Finished Aug 27 09:17:11 AM UTC 24
Peak memory 231568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343217225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3343217225
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/99.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/30.edn_alert.577009552
Short name T118
Test name
Test status
Simulation time 28941723 ps
CPU time 1.86 seconds
Started Aug 27 09:13:39 AM UTC 24
Finished Aug 27 09:13:42 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577009552 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 30.edn_alert.577009552
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/30.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/18.edn_disable.1652567995
Short name T76
Test name
Test status
Simulation time 32464585 ps
CPU time 1.07 seconds
Started Aug 27 09:12:40 AM UTC 24
Finished Aug 27 09:12:42 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652567995 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1652567995
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/18.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/104.edn_alert.346341691
Short name T729
Test name
Test status
Simulation time 68165980 ps
CPU time 1.58 seconds
Started Aug 27 09:17:11 AM UTC 24
Finished Aug 27 09:17:13 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346341691 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 104.edn_alert.346341691
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/104.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/16.edn_alert.3894676293
Short name T197
Test name
Test status
Simulation time 41859195 ps
CPU time 1.64 seconds
Started Aug 27 09:12:27 AM UTC 24
Finished Aug 27 09:12:29 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894676293 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 16.edn_alert.3894676293
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/16.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/20.edn_disable_auto_req_mode.3056733392
Short name T422
Test name
Test status
Simulation time 110110776 ps
CPU time 1.69 seconds
Started Aug 27 09:12:53 AM UTC 24
Finished Aug 27 09:12:55 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056733392 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable_auto_req_mode.3056733392
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/20.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/22.edn_alert.1343765554
Short name T133
Test name
Test status
Simulation time 80776039 ps
CPU time 1.49 seconds
Started Aug 27 09:13:00 AM UTC 24
Finished Aug 27 09:13:03 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343765554 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 22.edn_alert.1343765554
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/22.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/43.edn_alert.4258484329
Short name T151
Test name
Test status
Simulation time 85542937 ps
CPU time 1.66 seconds
Started Aug 27 09:15:20 AM UTC 24
Finished Aug 27 09:15:23 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258484329 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 43.edn_alert.4258484329
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/43.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/58.edn_alert.1241496070
Short name T143
Test name
Test status
Simulation time 44157781 ps
CPU time 1.76 seconds
Started Aug 27 09:16:19 AM UTC 24
Finished Aug 27 09:16:23 AM UTC 24
Peak memory 228296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241496070 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 58.edn_alert.1241496070
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/58.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/0.edn_alert_test.3605054098
Short name T24
Test name
Test status
Simulation time 62904715 ps
CPU time 0.95 seconds
Started Aug 27 09:10:45 AM UTC 24
Finished Aug 27 09:10:47 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605054098 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3605054098
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/0.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/27.edn_genbits.1710202462
Short name T310
Test name
Test status
Simulation time 64786087 ps
CPU time 1.51 seconds
Started Aug 27 09:13:22 AM UTC 24
Finished Aug 27 09:13:24 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710202462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_genbits.1710202462
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/27.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/156.edn_alert.2051375672
Short name T192
Test name
Test status
Simulation time 196682038 ps
CPU time 1.82 seconds
Started Aug 27 09:17:43 AM UTC 24
Finished Aug 27 09:17:46 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051375672 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 156.edn_alert.2051375672
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/156.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/25.edn_disable.149827480
Short name T171
Test name
Test status
Simulation time 33524558 ps
CPU time 1.06 seconds
Started Aug 27 09:13:14 AM UTC 24
Finished Aug 27 09:13:17 AM UTC 24
Peak memory 226088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149827480 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.149827480
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/25.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/7.edn_stress_all.2739667805
Short name T101
Test name
Test status
Simulation time 749501808 ps
CPU time 5.99 seconds
Started Aug 27 09:11:25 AM UTC 24
Finished Aug 27 09:11:32 AM UTC 24
Peak memory 229860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739667805 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.2739667805
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/7.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/13.edn_disable.1824848584
Short name T83
Test name
Test status
Simulation time 13194714 ps
CPU time 1.16 seconds
Started Aug 27 09:12:08 AM UTC 24
Finished Aug 27 09:12:10 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824848584 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1824848584
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/13.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/120.edn_alert.2530759083
Short name T188
Test name
Test status
Simulation time 26896316 ps
CPU time 1.66 seconds
Started Aug 27 09:17:22 AM UTC 24
Finished Aug 27 09:17:24 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530759083 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 120.edn_alert.2530759083
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/120.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/124.edn_alert.1323547169
Short name T184
Test name
Test status
Simulation time 74163547 ps
CPU time 1.65 seconds
Started Aug 27 09:17:23 AM UTC 24
Finished Aug 27 09:17:26 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323547169 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 124.edn_alert.1323547169
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/124.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/15.edn_disable.3744278480
Short name T94
Test name
Test status
Simulation time 22848477 ps
CPU time 1.35 seconds
Started Aug 27 09:12:22 AM UTC 24
Finished Aug 27 09:12:24 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744278480 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3744278480
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/15.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/16.edn_disable.3723739907
Short name T207
Test name
Test status
Simulation time 10840649 ps
CPU time 1.25 seconds
Started Aug 27 09:12:28 AM UTC 24
Finished Aug 27 09:12:30 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723739907 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.3723739907
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/16.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/21.edn_err.2223959428
Short name T202
Test name
Test status
Simulation time 23798610 ps
CPU time 1.59 seconds
Started Aug 27 09:12:55 AM UTC 24
Finished Aug 27 09:12:58 AM UTC 24
Peak memory 246084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223959428 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 21.edn_err.2223959428
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/21.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/25.edn_disable_auto_req_mode.4010821492
Short name T138
Test name
Test status
Simulation time 108666766 ps
CPU time 1.54 seconds
Started Aug 27 09:13:14 AM UTC 24
Finished Aug 27 09:13:17 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010821492 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable_auto_req_mode.4010821492
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/25.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/25.edn_err.576958828
Short name T199
Test name
Test status
Simulation time 26964635 ps
CPU time 1.34 seconds
Started Aug 27 09:13:13 AM UTC 24
Finished Aug 27 09:13:16 AM UTC 24
Peak memory 236964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576958828 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 25.edn_err.576958828
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/25.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/16.edn_genbits.2855780700
Short name T11
Test name
Test status
Simulation time 99255944 ps
CPU time 1.66 seconds
Started Aug 27 09:12:24 AM UTC 24
Finished Aug 27 09:12:27 AM UTC 24
Peak memory 230612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855780700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2855780700
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/16.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_bit_bash.1839488318
Short name T276
Test name
Test status
Simulation time 221690743 ps
CPU time 3.3 seconds
Started Aug 27 09:18:38 AM UTC 24
Finished Aug 27 09:18:42 AM UTC 24
Peak memory 217520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839488318 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.1839488318
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/1.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/55.edn_genbits.491951058
Short name T334
Test name
Test status
Simulation time 132845806 ps
CPU time 2.74 seconds
Started Aug 27 09:16:15 AM UTC 24
Finished Aug 27 09:16:18 AM UTC 24
Peak memory 231364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491951058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 55.edn_genbits.491951058
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/55.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/8.edn_stress_all.1539937979
Short name T105
Test name
Test status
Simulation time 597443571 ps
CPU time 5.2 seconds
Started Aug 27 09:11:32 AM UTC 24
Finished Aug 27 09:11:39 AM UTC 24
Peak memory 229516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539937979 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.1539937979
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/8.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/33.edn_intr.581897297
Short name T96
Test name
Test status
Simulation time 21402673 ps
CPU time 1.34 seconds
Started Aug 27 09:13:59 AM UTC 24
Finished Aug 27 09:14:01 AM UTC 24
Peak memory 228060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581897297 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 33.edn_intr.581897297
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/33.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/136.edn_genbits.3819982934
Short name T771
Test name
Test status
Simulation time 104786803 ps
CPU time 1.71 seconds
Started Aug 27 09:17:30 AM UTC 24
Finished Aug 27 09:17:33 AM UTC 24
Peak memory 230680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819982934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3819982934
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/136.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/170.edn_genbits.2095129880
Short name T346
Test name
Test status
Simulation time 49656337 ps
CPU time 1.77 seconds
Started Aug 27 09:17:50 AM UTC 24
Finished Aug 27 09:17:53 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095129880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2095129880
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/170.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_rw.3180897380
Short name T289
Test name
Test status
Simulation time 20384451 ps
CPU time 1.37 seconds
Started Aug 27 09:18:35 AM UTC 24
Finished Aug 27 09:18:38 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180897380 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3180897380
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/0.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/0.edn_regwen.2310896479
Short name T2
Test name
Test status
Simulation time 53667138 ps
CPU time 1.27 seconds
Started Aug 27 09:10:39 AM UTC 24
Finished Aug 27 09:10:42 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310896479 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 0.edn_regwen.2310896479
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/0.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/114.edn_genbits.1681456094
Short name T353
Test name
Test status
Simulation time 34707684 ps
CPU time 2 seconds
Started Aug 27 09:17:17 AM UTC 24
Finished Aug 27 09:17:20 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681456094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1681456094
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/114.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/115.edn_genbits.3506905508
Short name T263
Test name
Test status
Simulation time 48139737 ps
CPU time 2.05 seconds
Started Aug 27 09:17:18 AM UTC 24
Finished Aug 27 09:17:21 AM UTC 24
Peak memory 229580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506905508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 115.edn_genbits.3506905508
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/115.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/121.edn_genbits.3875670512
Short name T750
Test name
Test status
Simulation time 93748179 ps
CPU time 1.93 seconds
Started Aug 27 09:17:22 AM UTC 24
Finished Aug 27 09:17:24 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875670512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 121.edn_genbits.3875670512
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/121.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/13.edn_genbits.2053231962
Short name T362
Test name
Test status
Simulation time 41247469 ps
CPU time 1.47 seconds
Started Aug 27 09:12:04 AM UTC 24
Finished Aug 27 09:12:07 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053231962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2053231962
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/13.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/131.edn_genbits.1104183318
Short name T351
Test name
Test status
Simulation time 94197199 ps
CPU time 2.28 seconds
Started Aug 27 09:17:28 AM UTC 24
Finished Aug 27 09:17:31 AM UTC 24
Peak memory 229708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104183318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 131.edn_genbits.1104183318
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/131.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/147.edn_genbits.1002877221
Short name T349
Test name
Test status
Simulation time 148539032 ps
CPU time 3.16 seconds
Started Aug 27 09:17:38 AM UTC 24
Finished Aug 27 09:17:42 AM UTC 24
Peak memory 229572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002877221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 147.edn_genbits.1002877221
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/147.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/150.edn_genbits.4269167642
Short name T795
Test name
Test status
Simulation time 65387878 ps
CPU time 1.38 seconds
Started Aug 27 09:17:39 AM UTC 24
Finished Aug 27 09:17:41 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269167642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 150.edn_genbits.4269167642
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/150.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/159.edn_genbits.1979814892
Short name T341
Test name
Test status
Simulation time 57755699 ps
CPU time 1.81 seconds
Started Aug 27 09:17:44 AM UTC 24
Finished Aug 27 09:17:47 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979814892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1979814892
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/159.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/26.edn_intr.3861070582
Short name T99
Test name
Test status
Simulation time 21240785 ps
CPU time 1.5 seconds
Started Aug 27 09:13:18 AM UTC 24
Finished Aug 27 09:13:21 AM UTC 24
Peak memory 227712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861070582 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 26.edn_intr.3861070582
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/26.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/107.edn_alert.1449117894
Short name T732
Test name
Test status
Simulation time 27315810 ps
CPU time 1.64 seconds
Started Aug 27 09:17:12 AM UTC 24
Finished Aug 27 09:17:14 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449117894 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 107.edn_alert.1449117894
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/107.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/122.edn_alert.890912789
Short name T755
Test name
Test status
Simulation time 90827422 ps
CPU time 1.82 seconds
Started Aug 27 09:17:23 AM UTC 24
Finished Aug 27 09:17:26 AM UTC 24
Peak memory 226360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890912789 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 122.edn_alert.890912789
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/122.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/155.edn_alert.2669380102
Short name T122
Test name
Test status
Simulation time 36989604 ps
CPU time 1.58 seconds
Started Aug 27 09:17:43 AM UTC 24
Finished Aug 27 09:17:46 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669380102 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 155.edn_alert.2669380102
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/155.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/0.edn_err.957561880
Short name T5
Test name
Test status
Simulation time 33649890 ps
CPU time 1.36 seconds
Started Aug 27 09:10:43 AM UTC 24
Finished Aug 27 09:10:45 AM UTC 24
Peak memory 244580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957561880 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 0.edn_err.957561880
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/0.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_bit_bash.2784631500
Short name T985
Test name
Test status
Simulation time 887741408 ps
CPU time 3.34 seconds
Started Aug 27 09:18:35 AM UTC 24
Finished Aug 27 09:18:40 AM UTC 24
Peak memory 217628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784631500 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2784631500
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/0.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_hw_reset.3347876945
Short name T981
Test name
Test status
Simulation time 37559052 ps
CPU time 1.29 seconds
Started Aug 27 09:18:35 AM UTC 24
Finished Aug 27 09:18:38 AM UTC 24
Peak memory 215160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347876945 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.3347876945
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/0.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.71070875
Short name T986
Test name
Test status
Simulation time 99970877 ps
CPU time 2.3 seconds
Started Aug 27 09:18:37 AM UTC 24
Finished Aug 27 09:18:40 AM UTC 24
Peak memory 227880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=71070875 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.71070875
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/0.edn_intr_test.1304675911
Short name T980
Test name
Test status
Simulation time 27079154 ps
CPU time 1.31 seconds
Started Aug 27 09:18:35 AM UTC 24
Finished Aug 27 09:18:38 AM UTC 24
Peak memory 216672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304675911 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1304675911
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/0.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/0.edn_same_csr_outstanding.2160905382
Short name T288
Test name
Test status
Simulation time 50445701 ps
CPU time 1.07 seconds
Started Aug 27 09:18:35 AM UTC 24
Finished Aug 27 09:18:38 AM UTC 24
Peak memory 217128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160905382 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_outstanding.2160905382
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/0.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/0.edn_tl_errors.4000611314
Short name T982
Test name
Test status
Simulation time 63451375 ps
CPU time 3.7 seconds
Started Aug 27 09:18:34 AM UTC 24
Finished Aug 27 09:18:39 AM UTC 24
Peak memory 227796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000611314 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.4000611314
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/0.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/0.edn_tl_intg_err.17787215
Short name T298
Test name
Test status
Simulation time 280567415 ps
CPU time 3.9 seconds
Started Aug 27 09:18:34 AM UTC 24
Finished Aug 27 09:18:39 AM UTC 24
Peak memory 217820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17787215 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.17787215
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/0.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_aliasing.1850479550
Short name T275
Test name
Test status
Simulation time 70727893 ps
CPU time 2.25 seconds
Started Aug 27 09:18:39 AM UTC 24
Finished Aug 27 09:18:42 AM UTC 24
Peak memory 217508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850479550 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1850479550
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/1.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_hw_reset.559354069
Short name T984
Test name
Test status
Simulation time 26255266 ps
CPU time 1.27 seconds
Started Aug 27 09:18:37 AM UTC 24
Finished Aug 27 09:18:39 AM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559354069 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.559354069
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/1.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1590056710
Short name T989
Test name
Test status
Simulation time 26858768 ps
CPU time 1.69 seconds
Started Aug 27 09:18:39 AM UTC 24
Finished Aug 27 09:18:42 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1590056710 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.1590056710
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_rw.2359686536
Short name T290
Test name
Test status
Simulation time 16303496 ps
CPU time 1.48 seconds
Started Aug 27 09:18:38 AM UTC 24
Finished Aug 27 09:18:40 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359686536 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2359686536
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/1.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/1.edn_intr_test.4232340676
Short name T983
Test name
Test status
Simulation time 42843194 ps
CPU time 1.24 seconds
Started Aug 27 09:18:37 AM UTC 24
Finished Aug 27 09:18:39 AM UTC 24
Peak memory 214680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232340676 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.4232340676
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/1.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/1.edn_same_csr_outstanding.728808698
Short name T291
Test name
Test status
Simulation time 59410103 ps
CPU time 1.75 seconds
Started Aug 27 09:18:39 AM UTC 24
Finished Aug 27 09:18:42 AM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728808698 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_outstanding.728808698
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/1.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/1.edn_tl_errors.2006831049
Short name T987
Test name
Test status
Simulation time 247106984 ps
CPU time 3.4 seconds
Started Aug 27 09:18:37 AM UTC 24
Finished Aug 27 09:18:41 AM UTC 24
Peak memory 227860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006831049 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2006831049
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/1.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/1.edn_tl_intg_err.1781663576
Short name T299
Test name
Test status
Simulation time 174314586 ps
CPU time 2.13 seconds
Started Aug 27 09:18:37 AM UTC 24
Finished Aug 27 09:18:40 AM UTC 24
Peak memory 217408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781663576 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1781663576
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/1.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2396165311
Short name T1032
Test name
Test status
Simulation time 137531710 ps
CPU time 2.04 seconds
Started Aug 27 09:18:54 AM UTC 24
Finished Aug 27 09:18:57 AM UTC 24
Peak memory 227740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2396165311 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2396165311
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_rw.1501137072
Short name T283
Test name
Test status
Simulation time 119607843 ps
CPU time 1.2 seconds
Started Aug 27 09:18:54 AM UTC 24
Finished Aug 27 09:18:57 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501137072 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1501137072
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/10.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/10.edn_intr_test.4292319512
Short name T1027
Test name
Test status
Simulation time 18702608 ps
CPU time 1 seconds
Started Aug 27 09:18:54 AM UTC 24
Finished Aug 27 09:18:56 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292319512 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.4292319512
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/10.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/10.edn_same_csr_outstanding.3623683180
Short name T1031
Test name
Test status
Simulation time 20828753 ps
CPU time 1.5 seconds
Started Aug 27 09:18:54 AM UTC 24
Finished Aug 27 09:18:57 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623683180 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_outstanding.3623683180
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/10.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_errors.3368525046
Short name T1033
Test name
Test status
Simulation time 193715277 ps
CPU time 4.09 seconds
Started Aug 27 09:18:53 AM UTC 24
Finished Aug 27 09:18:58 AM UTC 24
Peak memory 227800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368525046 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3368525046
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/10.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_intg_err.1706334777
Short name T1029
Test name
Test status
Simulation time 160058101 ps
CPU time 2.43 seconds
Started Aug 27 09:18:53 AM UTC 24
Finished Aug 27 09:18:56 AM UTC 24
Peak memory 217548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706334777 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1706334777
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/10.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.433972957
Short name T1037
Test name
Test status
Simulation time 32893428 ps
CPU time 2.09 seconds
Started Aug 27 09:18:56 AM UTC 24
Finished Aug 27 09:18:59 AM UTC 24
Peak memory 227860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=433972957 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.433972957
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_rw.1509230729
Short name T284
Test name
Test status
Simulation time 36300455 ps
CPU time 1.19 seconds
Started Aug 27 09:18:56 AM UTC 24
Finished Aug 27 09:18:58 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509230729 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1509230729
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/11.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/11.edn_intr_test.2582317314
Short name T1030
Test name
Test status
Simulation time 19228160 ps
CPU time 1.1 seconds
Started Aug 27 09:18:55 AM UTC 24
Finished Aug 27 09:18:57 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582317314 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2582317314
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/11.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/11.edn_same_csr_outstanding.4281122739
Short name T1036
Test name
Test status
Simulation time 27725812 ps
CPU time 1.58 seconds
Started Aug 27 09:18:56 AM UTC 24
Finished Aug 27 09:18:59 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281122739 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_outstanding.4281122739
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/11.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_errors.2298800799
Short name T1042
Test name
Test status
Simulation time 207194960 ps
CPU time 4.49 seconds
Started Aug 27 09:18:55 AM UTC 24
Finished Aug 27 09:19:00 AM UTC 24
Peak memory 228068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298800799 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2298800799
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/11.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_intg_err.2973124853
Short name T1035
Test name
Test status
Simulation time 876193867 ps
CPU time 2.77 seconds
Started Aug 27 09:18:55 AM UTC 24
Finished Aug 27 09:18:58 AM UTC 24
Peak memory 217492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973124853 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2973124853
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/11.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.4134805860
Short name T1046
Test name
Test status
Simulation time 47113449 ps
CPU time 2.24 seconds
Started Aug 27 09:18:58 AM UTC 24
Finished Aug 27 09:19:01 AM UTC 24
Peak memory 227868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4134805860 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.4134805860
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_rw.845766015
Short name T1040
Test name
Test status
Simulation time 67428059 ps
CPU time 1.14 seconds
Started Aug 27 09:18:58 AM UTC 24
Finished Aug 27 09:19:00 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845766015 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.845766015
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/12.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/12.edn_intr_test.3838932800
Short name T1034
Test name
Test status
Simulation time 78061636 ps
CPU time 1.08 seconds
Started Aug 27 09:18:56 AM UTC 24
Finished Aug 27 09:18:58 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838932800 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3838932800
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/12.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/12.edn_same_csr_outstanding.2337610461
Short name T1045
Test name
Test status
Simulation time 30172306 ps
CPU time 1.91 seconds
Started Aug 27 09:18:58 AM UTC 24
Finished Aug 27 09:19:00 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337610461 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_outstanding.2337610461
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/12.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_errors.805844903
Short name T1038
Test name
Test status
Simulation time 86190822 ps
CPU time 2.33 seconds
Started Aug 27 09:18:56 AM UTC 24
Finished Aug 27 09:18:59 AM UTC 24
Peak memory 227840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805844903 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.805844903
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/12.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_intg_err.87169620
Short name T1039
Test name
Test status
Simulation time 459946670 ps
CPU time 2.32 seconds
Started Aug 27 09:18:56 AM UTC 24
Finished Aug 27 09:18:59 AM UTC 24
Peak memory 217676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87169620 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.87169620
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/12.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1316355751
Short name T1049
Test name
Test status
Simulation time 37888408 ps
CPU time 1.27 seconds
Started Aug 27 09:18:59 AM UTC 24
Finished Aug 27 09:19:01 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1316355751 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.1316355751
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_rw.4221941391
Short name T1043
Test name
Test status
Simulation time 45074571 ps
CPU time 1.24 seconds
Started Aug 27 09:18:58 AM UTC 24
Finished Aug 27 09:19:00 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221941391 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.4221941391
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/13.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/13.edn_intr_test.780420789
Short name T1041
Test name
Test status
Simulation time 14909308 ps
CPU time 1.17 seconds
Started Aug 27 09:18:58 AM UTC 24
Finished Aug 27 09:19:00 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780420789 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.780420789
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/13.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/13.edn_same_csr_outstanding.1889982962
Short name T1044
Test name
Test status
Simulation time 41489283 ps
CPU time 1.5 seconds
Started Aug 27 09:18:58 AM UTC 24
Finished Aug 27 09:19:00 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889982962 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_outstanding.1889982962
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/13.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_errors.3537701590
Short name T1050
Test name
Test status
Simulation time 224096421 ps
CPU time 3.1 seconds
Started Aug 27 09:18:58 AM UTC 24
Finished Aug 27 09:19:02 AM UTC 24
Peak memory 227804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537701590 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.3537701590
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/13.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_intg_err.1973362963
Short name T1048
Test name
Test status
Simulation time 95804362 ps
CPU time 2.63 seconds
Started Aug 27 09:18:58 AM UTC 24
Finished Aug 27 09:19:01 AM UTC 24
Peak memory 217692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973362963 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1973362963
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/13.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3969057316
Short name T1053
Test name
Test status
Simulation time 17407718 ps
CPU time 1.29 seconds
Started Aug 27 09:19:01 AM UTC 24
Finished Aug 27 09:19:03 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3969057316 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.3969057316
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_rw.489278398
Short name T285
Test name
Test status
Simulation time 26024586 ps
CPU time 1.26 seconds
Started Aug 27 09:18:59 AM UTC 24
Finished Aug 27 09:19:02 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489278398 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.489278398
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/14.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/14.edn_intr_test.1137410189
Short name T1047
Test name
Test status
Simulation time 37577734 ps
CPU time 1.06 seconds
Started Aug 27 09:18:59 AM UTC 24
Finished Aug 27 09:19:01 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137410189 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.1137410189
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/14.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/14.edn_same_csr_outstanding.1383963727
Short name T1051
Test name
Test status
Simulation time 33846486 ps
CPU time 1.63 seconds
Started Aug 27 09:18:59 AM UTC 24
Finished Aug 27 09:19:02 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383963727 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_outstanding.1383963727
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/14.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_errors.458177019
Short name T1057
Test name
Test status
Simulation time 58875968 ps
CPU time 3.26 seconds
Started Aug 27 09:18:59 AM UTC 24
Finished Aug 27 09:19:03 AM UTC 24
Peak memory 227848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458177019 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.458177019
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/14.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_intg_err.3758938554
Short name T1052
Test name
Test status
Simulation time 46084904 ps
CPU time 1.93 seconds
Started Aug 27 09:18:59 AM UTC 24
Finished Aug 27 09:19:02 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758938554 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.3758938554
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/14.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1284209101
Short name T1059
Test name
Test status
Simulation time 107092146 ps
CPU time 2.42 seconds
Started Aug 27 09:19:01 AM UTC 24
Finished Aug 27 09:19:04 AM UTC 24
Peak memory 228056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1284209101 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1284209101
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_rw.964039825
Short name T1055
Test name
Test status
Simulation time 25301969 ps
CPU time 1.32 seconds
Started Aug 27 09:19:01 AM UTC 24
Finished Aug 27 09:19:03 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964039825 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.964039825
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/15.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/15.edn_intr_test.2564674264
Short name T1056
Test name
Test status
Simulation time 17743666 ps
CPU time 1.43 seconds
Started Aug 27 09:19:01 AM UTC 24
Finished Aug 27 09:19:03 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564674264 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.2564674264
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/15.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/15.edn_same_csr_outstanding.2180535873
Short name T1054
Test name
Test status
Simulation time 15585833 ps
CPU time 1.25 seconds
Started Aug 27 09:19:01 AM UTC 24
Finished Aug 27 09:19:03 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180535873 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_outstanding.2180535873
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/15.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_errors.2896686265
Short name T1058
Test name
Test status
Simulation time 52586364 ps
CPU time 2.54 seconds
Started Aug 27 09:19:01 AM UTC 24
Finished Aug 27 09:19:04 AM UTC 24
Peak memory 227176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896686265 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2896686265
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/15.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_intg_err.3611264654
Short name T316
Test name
Test status
Simulation time 129595029 ps
CPU time 2.01 seconds
Started Aug 27 09:19:01 AM UTC 24
Finished Aug 27 09:19:04 AM UTC 24
Peak memory 217700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611264654 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.3611264654
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/15.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.675395536
Short name T1061
Test name
Test status
Simulation time 21836258 ps
CPU time 1.32 seconds
Started Aug 27 09:19:03 AM UTC 24
Finished Aug 27 09:19:05 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=675395536 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.675395536
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_rw.1318016102
Short name T1060
Test name
Test status
Simulation time 55299102 ps
CPU time 1.23 seconds
Started Aug 27 09:19:02 AM UTC 24
Finished Aug 27 09:19:05 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318016102 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1318016102
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/16.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/16.edn_intr_test.441279905
Short name T1063
Test name
Test status
Simulation time 18208054 ps
CPU time 1.39 seconds
Started Aug 27 09:19:02 AM UTC 24
Finished Aug 27 09:19:05 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441279905 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.441279905
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/16.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/16.edn_same_csr_outstanding.2556229609
Short name T1064
Test name
Test status
Simulation time 26540704 ps
CPU time 1.52 seconds
Started Aug 27 09:19:03 AM UTC 24
Finished Aug 27 09:19:05 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556229609 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_outstanding.2556229609
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/16.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_errors.260995712
Short name T1065
Test name
Test status
Simulation time 91605313 ps
CPU time 3.6 seconds
Started Aug 27 09:19:01 AM UTC 24
Finished Aug 27 09:19:06 AM UTC 24
Peak memory 227800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260995712 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.260995712
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/16.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_intg_err.2672404929
Short name T1066
Test name
Test status
Simulation time 293447966 ps
CPU time 2.46 seconds
Started Aug 27 09:19:02 AM UTC 24
Finished Aug 27 09:19:06 AM UTC 24
Peak memory 217492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672404929 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2672404929
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/16.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3533398861
Short name T1068
Test name
Test status
Simulation time 39728676 ps
CPU time 1.38 seconds
Started Aug 27 09:19:04 AM UTC 24
Finished Aug 27 09:19:06 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3533398861 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3533398861
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_rw.2797580341
Short name T286
Test name
Test status
Simulation time 18290871 ps
CPU time 1.45 seconds
Started Aug 27 09:19:04 AM UTC 24
Finished Aug 27 09:19:06 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797580341 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2797580341
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/17.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/17.edn_intr_test.938835314
Short name T1062
Test name
Test status
Simulation time 17188533 ps
CPU time 1.12 seconds
Started Aug 27 09:19:03 AM UTC 24
Finished Aug 27 09:19:05 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938835314 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.938835314
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/17.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/17.edn_same_csr_outstanding.2674011457
Short name T1067
Test name
Test status
Simulation time 89224395 ps
CPU time 1.37 seconds
Started Aug 27 09:19:04 AM UTC 24
Finished Aug 27 09:19:06 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674011457 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_outstanding.2674011457
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/17.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_errors.3488918870
Short name T1070
Test name
Test status
Simulation time 330143067 ps
CPU time 4.21 seconds
Started Aug 27 09:19:03 AM UTC 24
Finished Aug 27 09:19:08 AM UTC 24
Peak memory 227880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488918870 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3488918870
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/17.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_intg_err.726687687
Short name T317
Test name
Test status
Simulation time 86725685 ps
CPU time 2.58 seconds
Started Aug 27 09:19:03 AM UTC 24
Finished Aug 27 09:19:06 AM UTC 24
Peak memory 217416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726687687 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.726687687
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/17.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2304992351
Short name T1074
Test name
Test status
Simulation time 44264999 ps
CPU time 1.3 seconds
Started Aug 27 09:19:06 AM UTC 24
Finished Aug 27 09:19:08 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2304992351 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2304992351
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_rw.3339123150
Short name T1069
Test name
Test status
Simulation time 11636896 ps
CPU time 1.21 seconds
Started Aug 27 09:19:06 AM UTC 24
Finished Aug 27 09:19:08 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339123150 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.3339123150
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/18.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/18.edn_intr_test.1926414673
Short name T1072
Test name
Test status
Simulation time 121853009 ps
CPU time 1.37 seconds
Started Aug 27 09:19:05 AM UTC 24
Finished Aug 27 09:19:08 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926414673 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.1926414673
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/18.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/18.edn_same_csr_outstanding.1216354109
Short name T1076
Test name
Test status
Simulation time 19832055 ps
CPU time 1.77 seconds
Started Aug 27 09:19:06 AM UTC 24
Finished Aug 27 09:19:08 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216354109 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_outstanding.1216354109
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/18.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_errors.652639644
Short name T1075
Test name
Test status
Simulation time 867817465 ps
CPU time 3.11 seconds
Started Aug 27 09:19:04 AM UTC 24
Finished Aug 27 09:19:08 AM UTC 24
Peak memory 227792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652639644 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.652639644
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/18.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_intg_err.399473542
Short name T1071
Test name
Test status
Simulation time 57830021 ps
CPU time 2.63 seconds
Started Aug 27 09:19:04 AM UTC 24
Finished Aug 27 09:19:08 AM UTC 24
Peak memory 217496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399473542 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.399473542
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/18.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.130832573
Short name T1084
Test name
Test status
Simulation time 108310357 ps
CPU time 1.38 seconds
Started Aug 27 09:19:07 AM UTC 24
Finished Aug 27 09:19:10 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=130832573 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.130832573
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_rw.3399772373
Short name T287
Test name
Test status
Simulation time 42802732 ps
CPU time 1.3 seconds
Started Aug 27 09:19:06 AM UTC 24
Finished Aug 27 09:19:08 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399772373 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3399772373
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/19.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/19.edn_intr_test.3814643463
Short name T1073
Test name
Test status
Simulation time 13258874 ps
CPU time 1.18 seconds
Started Aug 27 09:19:06 AM UTC 24
Finished Aug 27 09:19:08 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814643463 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.3814643463
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/19.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/19.edn_same_csr_outstanding.28211106
Short name T1078
Test name
Test status
Simulation time 88195021 ps
CPU time 1.97 seconds
Started Aug 27 09:19:06 AM UTC 24
Finished Aug 27 09:19:09 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28211106 -assert nopostproc +UVM_T
ESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_outstanding.28211106
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/19.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_errors.2098476830
Short name T1079
Test name
Test status
Simulation time 51822366 ps
CPU time 2.44 seconds
Started Aug 27 09:19:06 AM UTC 24
Finished Aug 27 09:19:09 AM UTC 24
Peak memory 227880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098476830 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2098476830
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/19.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_intg_err.4101351258
Short name T1077
Test name
Test status
Simulation time 77506620 ps
CPU time 1.68 seconds
Started Aug 27 09:19:06 AM UTC 24
Finished Aug 27 09:19:08 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101351258 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.4101351258
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/19.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_aliasing.1779863899
Short name T278
Test name
Test status
Simulation time 135840505 ps
CPU time 1.63 seconds
Started Aug 27 09:18:40 AM UTC 24
Finished Aug 27 09:18:43 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779863899 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.1779863899
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/2.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_bit_bash.4252339827
Short name T259
Test name
Test status
Simulation time 3094613283 ps
CPU time 7.07 seconds
Started Aug 27 09:18:40 AM UTC 24
Finished Aug 27 09:18:48 AM UTC 24
Peak memory 217816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252339827 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.4252339827
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/2.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_hw_reset.3445086005
Short name T991
Test name
Test status
Simulation time 19470133 ps
CPU time 1.35 seconds
Started Aug 27 09:18:40 AM UTC 24
Finished Aug 27 09:18:43 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445086005 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3445086005
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/2.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3785417019
Short name T992
Test name
Test status
Simulation time 56692383 ps
CPU time 1.17 seconds
Started Aug 27 09:18:41 AM UTC 24
Finished Aug 27 09:18:43 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3785417019 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3785417019
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_rw.269901874
Short name T277
Test name
Test status
Simulation time 15103775 ps
CPU time 1.25 seconds
Started Aug 27 09:18:40 AM UTC 24
Finished Aug 27 09:18:43 AM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269901874 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.269901874
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/2.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/2.edn_intr_test.4077658658
Short name T988
Test name
Test status
Simulation time 23145433 ps
CPU time 1.16 seconds
Started Aug 27 09:18:39 AM UTC 24
Finished Aug 27 09:18:41 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077658658 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.4077658658
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/2.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/2.edn_same_csr_outstanding.2393846964
Short name T292
Test name
Test status
Simulation time 16429826 ps
CPU time 1.34 seconds
Started Aug 27 09:18:40 AM UTC 24
Finished Aug 27 09:18:43 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393846964 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_outstanding.2393846964
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/2.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/2.edn_tl_errors.4130160913
Short name T993
Test name
Test status
Simulation time 860675699 ps
CPU time 3.95 seconds
Started Aug 27 09:18:39 AM UTC 24
Finished Aug 27 09:18:44 AM UTC 24
Peak memory 227796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130160913 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.4130160913
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/2.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/2.edn_tl_intg_err.2667803967
Short name T300
Test name
Test status
Simulation time 85326859 ps
CPU time 3 seconds
Started Aug 27 09:18:39 AM UTC 24
Finished Aug 27 09:18:43 AM UTC 24
Peak memory 217300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667803967 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.2667803967
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/2.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/20.edn_intr_test.2581781601
Short name T1080
Test name
Test status
Simulation time 17411231 ps
CPU time 1.02 seconds
Started Aug 27 09:19:07 AM UTC 24
Finished Aug 27 09:19:09 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581781601 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.2581781601
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/20.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/21.edn_intr_test.312683229
Short name T1081
Test name
Test status
Simulation time 25415475 ps
CPU time 1.08 seconds
Started Aug 27 09:19:07 AM UTC 24
Finished Aug 27 09:19:09 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312683229 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.312683229
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/21.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/22.edn_intr_test.702201763
Short name T1085
Test name
Test status
Simulation time 101608048 ps
CPU time 1.36 seconds
Started Aug 27 09:19:07 AM UTC 24
Finished Aug 27 09:19:10 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702201763 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.702201763
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/22.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/23.edn_intr_test.3519809940
Short name T1082
Test name
Test status
Simulation time 11329901 ps
CPU time 1.1 seconds
Started Aug 27 09:19:07 AM UTC 24
Finished Aug 27 09:19:09 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519809940 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3519809940
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/23.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/24.edn_intr_test.2383521770
Short name T1083
Test name
Test status
Simulation time 12728251 ps
CPU time 1.22 seconds
Started Aug 27 09:19:07 AM UTC 24
Finished Aug 27 09:19:10 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383521770 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.2383521770
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/24.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/25.edn_intr_test.2629641061
Short name T1089
Test name
Test status
Simulation time 13132368 ps
CPU time 1.33 seconds
Started Aug 27 09:19:09 AM UTC 24
Finished Aug 27 09:19:11 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629641061 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2629641061
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/25.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/26.edn_intr_test.246700275
Short name T1090
Test name
Test status
Simulation time 12886020 ps
CPU time 1.22 seconds
Started Aug 27 09:19:09 AM UTC 24
Finished Aug 27 09:19:11 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246700275 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.246700275
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/26.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/27.edn_intr_test.3191887387
Short name T1087
Test name
Test status
Simulation time 48782007 ps
CPU time 1.18 seconds
Started Aug 27 09:19:09 AM UTC 24
Finished Aug 27 09:19:11 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191887387 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3191887387
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/27.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/28.edn_intr_test.968507267
Short name T1088
Test name
Test status
Simulation time 37023748 ps
CPU time 1.13 seconds
Started Aug 27 09:19:09 AM UTC 24
Finished Aug 27 09:19:11 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968507267 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.968507267
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/28.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/29.edn_intr_test.3382302378
Short name T1091
Test name
Test status
Simulation time 17585710 ps
CPU time 1.27 seconds
Started Aug 27 09:19:09 AM UTC 24
Finished Aug 27 09:19:11 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382302378 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3382302378
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/29.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_aliasing.3063797623
Short name T280
Test name
Test status
Simulation time 56680979 ps
CPU time 1.28 seconds
Started Aug 27 09:18:43 AM UTC 24
Finished Aug 27 09:18:45 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063797623 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3063797623
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/3.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_bit_bash.1592912615
Short name T999
Test name
Test status
Simulation time 71395020 ps
CPU time 2.28 seconds
Started Aug 27 09:18:43 AM UTC 24
Finished Aug 27 09:18:46 AM UTC 24
Peak memory 217496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592912615 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1592912615
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/3.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_hw_reset.2384073290
Short name T995
Test name
Test status
Simulation time 27472593 ps
CPU time 1.37 seconds
Started Aug 27 09:18:42 AM UTC 24
Finished Aug 27 09:18:44 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384073290 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2384073290
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/3.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3060315350
Short name T998
Test name
Test status
Simulation time 43710838 ps
CPU time 1.76 seconds
Started Aug 27 09:18:43 AM UTC 24
Finished Aug 27 09:18:46 AM UTC 24
Peak memory 229732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3060315350 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3060315350
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_rw.2629053792
Short name T279
Test name
Test status
Simulation time 19043709 ps
CPU time 1.1 seconds
Started Aug 27 09:18:43 AM UTC 24
Finished Aug 27 09:18:45 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629053792 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2629053792
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/3.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/3.edn_intr_test.1148255930
Short name T994
Test name
Test status
Simulation time 23278026 ps
CPU time 1.23 seconds
Started Aug 27 09:18:42 AM UTC 24
Finished Aug 27 09:18:44 AM UTC 24
Peak memory 215388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148255930 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1148255930
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/3.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/3.edn_same_csr_outstanding.3155671023
Short name T242
Test name
Test status
Simulation time 160505345 ps
CPU time 1.87 seconds
Started Aug 27 09:18:43 AM UTC 24
Finished Aug 27 09:18:46 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155671023 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_outstanding.3155671023
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/3.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_errors.3591725878
Short name T996
Test name
Test status
Simulation time 182737034 ps
CPU time 2.86 seconds
Started Aug 27 09:18:41 AM UTC 24
Finished Aug 27 09:18:44 AM UTC 24
Peak memory 227876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591725878 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3591725878
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/3.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_intg_err.3523742215
Short name T997
Test name
Test status
Simulation time 128472538 ps
CPU time 2.21 seconds
Started Aug 27 09:18:42 AM UTC 24
Finished Aug 27 09:18:45 AM UTC 24
Peak memory 217572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523742215 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3523742215
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/3.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/30.edn_intr_test.1476864344
Short name T1086
Test name
Test status
Simulation time 21339526 ps
CPU time 0.99 seconds
Started Aug 27 09:19:09 AM UTC 24
Finished Aug 27 09:19:11 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476864344 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1476864344
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/30.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/31.edn_intr_test.3784702677
Short name T1092
Test name
Test status
Simulation time 11972837 ps
CPU time 1.29 seconds
Started Aug 27 09:19:09 AM UTC 24
Finished Aug 27 09:19:11 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784702677 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3784702677
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/31.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/32.edn_intr_test.3611940425
Short name T1093
Test name
Test status
Simulation time 16002996 ps
CPU time 1.07 seconds
Started Aug 27 09:19:10 AM UTC 24
Finished Aug 27 09:19:12 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611940425 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3611940425
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/32.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/33.edn_intr_test.3353651740
Short name T1095
Test name
Test status
Simulation time 66259950 ps
CPU time 1.15 seconds
Started Aug 27 09:19:10 AM UTC 24
Finished Aug 27 09:19:13 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353651740 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3353651740
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/33.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/34.edn_intr_test.1515542355
Short name T1097
Test name
Test status
Simulation time 50361974 ps
CPU time 1.23 seconds
Started Aug 27 09:19:11 AM UTC 24
Finished Aug 27 09:19:13 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515542355 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1515542355
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/34.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/35.edn_intr_test.2338749468
Short name T1102
Test name
Test status
Simulation time 17105636 ps
CPU time 1.33 seconds
Started Aug 27 09:19:11 AM UTC 24
Finished Aug 27 09:19:13 AM UTC 24
Peak memory 215364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338749468 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2338749468
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/35.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/36.edn_intr_test.2046646972
Short name T1094
Test name
Test status
Simulation time 15171892 ps
CPU time 0.94 seconds
Started Aug 27 09:19:11 AM UTC 24
Finished Aug 27 09:19:13 AM UTC 24
Peak memory 215336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046646972 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.2046646972
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/36.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/37.edn_intr_test.3522848658
Short name T1099
Test name
Test status
Simulation time 15064072 ps
CPU time 1.21 seconds
Started Aug 27 09:19:11 AM UTC 24
Finished Aug 27 09:19:13 AM UTC 24
Peak memory 215304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522848658 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.3522848658
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/37.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/38.edn_intr_test.1642465793
Short name T1096
Test name
Test status
Simulation time 53165060 ps
CPU time 1.01 seconds
Started Aug 27 09:19:11 AM UTC 24
Finished Aug 27 09:19:13 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642465793 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1642465793
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/38.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/39.edn_intr_test.470102083
Short name T1100
Test name
Test status
Simulation time 42366917 ps
CPU time 1.15 seconds
Started Aug 27 09:19:11 AM UTC 24
Finished Aug 27 09:19:13 AM UTC 24
Peak memory 215308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470102083 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.470102083
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/39.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_aliasing.93503946
Short name T243
Test name
Test status
Simulation time 147274462 ps
CPU time 1.45 seconds
Started Aug 27 09:18:44 AM UTC 24
Finished Aug 27 09:18:47 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93503946 -assert nopostproc +UVM_TESTNAME=edn_
base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ed
n-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.93503946
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/4.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_bit_bash.1164313142
Short name T1007
Test name
Test status
Simulation time 369125703 ps
CPU time 3.82 seconds
Started Aug 27 09:18:44 AM UTC 24
Finished Aug 27 09:18:49 AM UTC 24
Peak memory 217436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164313142 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.1164313142
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/4.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_hw_reset.2284105896
Short name T1001
Test name
Test status
Simulation time 118383655 ps
CPU time 1.24 seconds
Started Aug 27 09:18:44 AM UTC 24
Finished Aug 27 09:18:47 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284105896 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.2284105896
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/4.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3719326558
Short name T1006
Test name
Test status
Simulation time 47613225 ps
CPU time 1.92 seconds
Started Aug 27 09:18:46 AM UTC 24
Finished Aug 27 09:18:49 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3719326558 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3719326558
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_rw.991976429
Short name T258
Test name
Test status
Simulation time 17475896 ps
CPU time 1.31 seconds
Started Aug 27 09:18:44 AM UTC 24
Finished Aug 27 09:18:47 AM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991976429 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.991976429
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/4.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/4.edn_intr_test.2547251709
Short name T1000
Test name
Test status
Simulation time 13271140 ps
CPU time 1.09 seconds
Started Aug 27 09:18:44 AM UTC 24
Finished Aug 27 09:18:46 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547251709 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2547251709
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/4.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/4.edn_same_csr_outstanding.2167460474
Short name T293
Test name
Test status
Simulation time 44204557 ps
CPU time 1.34 seconds
Started Aug 27 09:18:46 AM UTC 24
Finished Aug 27 09:18:48 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167460474 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_outstanding.2167460474
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/4.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_errors.3564307308
Short name T1003
Test name
Test status
Simulation time 81504361 ps
CPU time 3.99 seconds
Started Aug 27 09:18:43 AM UTC 24
Finished Aug 27 09:18:48 AM UTC 24
Peak memory 227796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564307308 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.3564307308
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/4.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_intg_err.2123900701
Short name T318
Test name
Test status
Simulation time 108087979 ps
CPU time 1.92 seconds
Started Aug 27 09:18:43 AM UTC 24
Finished Aug 27 09:18:46 AM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123900701 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2123900701
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/4.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/40.edn_intr_test.4142120730
Short name T1101
Test name
Test status
Simulation time 51131413 ps
CPU time 1.1 seconds
Started Aug 27 09:19:11 AM UTC 24
Finished Aug 27 09:19:13 AM UTC 24
Peak memory 215296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142120730 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.4142120730
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/40.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/41.edn_intr_test.3836157210
Short name T1103
Test name
Test status
Simulation time 16921104 ps
CPU time 1.21 seconds
Started Aug 27 09:19:11 AM UTC 24
Finished Aug 27 09:19:13 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836157210 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.3836157210
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/41.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/42.edn_intr_test.2942503270
Short name T1098
Test name
Test status
Simulation time 11960463 ps
CPU time 0.97 seconds
Started Aug 27 09:19:11 AM UTC 24
Finished Aug 27 09:19:13 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942503270 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2942503270
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/42.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/43.edn_intr_test.2311081802
Short name T1104
Test name
Test status
Simulation time 20950017 ps
CPU time 1 seconds
Started Aug 27 09:19:12 AM UTC 24
Finished Aug 27 09:19:14 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311081802 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2311081802
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/43.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/44.edn_intr_test.1741210312
Short name T1106
Test name
Test status
Simulation time 29224468 ps
CPU time 1.17 seconds
Started Aug 27 09:19:12 AM UTC 24
Finished Aug 27 09:19:14 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741210312 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.1741210312
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/44.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/45.edn_intr_test.820524345
Short name T1105
Test name
Test status
Simulation time 12978229 ps
CPU time 0.98 seconds
Started Aug 27 09:19:12 AM UTC 24
Finished Aug 27 09:19:14 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820524345 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.820524345
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/45.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/46.edn_intr_test.1475069151
Short name T1110
Test name
Test status
Simulation time 24142092 ps
CPU time 1.37 seconds
Started Aug 27 09:19:12 AM UTC 24
Finished Aug 27 09:19:15 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475069151 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1475069151
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/46.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/47.edn_intr_test.3612039066
Short name T1108
Test name
Test status
Simulation time 36367273 ps
CPU time 1.16 seconds
Started Aug 27 09:19:12 AM UTC 24
Finished Aug 27 09:19:15 AM UTC 24
Peak memory 215164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612039066 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.3612039066
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/47.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/48.edn_intr_test.2828013645
Short name T1107
Test name
Test status
Simulation time 32184149 ps
CPU time 1.18 seconds
Started Aug 27 09:19:12 AM UTC 24
Finished Aug 27 09:19:15 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828013645 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2828013645
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/48.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/49.edn_intr_test.2722660401
Short name T1109
Test name
Test status
Simulation time 85712099 ps
CPU time 1.19 seconds
Started Aug 27 09:19:12 AM UTC 24
Finished Aug 27 09:19:15 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722660401 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2722660401
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/49.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2050283261
Short name T244
Test name
Test status
Simulation time 386819114 ps
CPU time 1.44 seconds
Started Aug 27 09:18:47 AM UTC 24
Finished Aug 27 09:18:50 AM UTC 24
Peak memory 225636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2050283261 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2050283261
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_rw.3569161912
Short name T1004
Test name
Test status
Simulation time 48100758 ps
CPU time 1.34 seconds
Started Aug 27 09:18:46 AM UTC 24
Finished Aug 27 09:18:48 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569161912 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.3569161912
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/5.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/5.edn_intr_test.266527937
Short name T1002
Test name
Test status
Simulation time 66878965 ps
CPU time 0.86 seconds
Started Aug 27 09:18:46 AM UTC 24
Finished Aug 27 09:18:48 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266527937 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.266527937
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/5.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/5.edn_same_csr_outstanding.2851659352
Short name T245
Test name
Test status
Simulation time 38130778 ps
CPU time 2.02 seconds
Started Aug 27 09:18:47 AM UTC 24
Finished Aug 27 09:18:50 AM UTC 24
Peak memory 217688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851659352 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_outstanding.2851659352
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/5.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_errors.1698715982
Short name T1012
Test name
Test status
Simulation time 152768668 ps
CPU time 4.27 seconds
Started Aug 27 09:18:46 AM UTC 24
Finished Aug 27 09:18:51 AM UTC 24
Peak memory 228076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698715982 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.1698715982
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/5.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_intg_err.1951320812
Short name T1005
Test name
Test status
Simulation time 80783899 ps
CPU time 1.72 seconds
Started Aug 27 09:18:46 AM UTC 24
Finished Aug 27 09:18:49 AM UTC 24
Peak memory 225704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951320812 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1951320812
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/5.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.452207577
Short name T1013
Test name
Test status
Simulation time 118801323 ps
CPU time 1.87 seconds
Started Aug 27 09:18:48 AM UTC 24
Finished Aug 27 09:18:51 AM UTC 24
Peak memory 225696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=452207577 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.452207577
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_rw.909601561
Short name T1009
Test name
Test status
Simulation time 45698057 ps
CPU time 1.27 seconds
Started Aug 27 09:18:47 AM UTC 24
Finished Aug 27 09:18:50 AM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909601561 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.909601561
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/6.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/6.edn_intr_test.2533273409
Short name T1008
Test name
Test status
Simulation time 13382484 ps
CPU time 1.17 seconds
Started Aug 27 09:18:47 AM UTC 24
Finished Aug 27 09:18:50 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533273409 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.2533273409
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/6.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/6.edn_same_csr_outstanding.2045626528
Short name T1010
Test name
Test status
Simulation time 20388972 ps
CPU time 1.74 seconds
Started Aug 27 09:18:47 AM UTC 24
Finished Aug 27 09:18:50 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045626528 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_outstanding.2045626528
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/6.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_errors.2901545598
Short name T1011
Test name
Test status
Simulation time 63942231 ps
CPU time 2.38 seconds
Started Aug 27 09:18:47 AM UTC 24
Finished Aug 27 09:18:51 AM UTC 24
Peak memory 227860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901545598 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2901545598
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/6.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1922703331
Short name T1016
Test name
Test status
Simulation time 26039830 ps
CPU time 1.98 seconds
Started Aug 27 09:18:50 AM UTC 24
Finished Aug 27 09:18:53 AM UTC 24
Peak memory 229732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1922703331 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1922703331
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_rw.51591142
Short name T281
Test name
Test status
Simulation time 73231887 ps
CPU time 1.16 seconds
Started Aug 27 09:18:50 AM UTC 24
Finished Aug 27 09:18:52 AM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51591142 -assert nopostproc +UVM_TESTNAME=edn_base_t
est +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.51591142
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/7.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/7.edn_intr_test.3908917293
Short name T1014
Test name
Test status
Simulation time 68346992 ps
CPU time 1.18 seconds
Started Aug 27 09:18:50 AM UTC 24
Finished Aug 27 09:18:52 AM UTC 24
Peak memory 215252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908917293 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.3908917293
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/7.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/7.edn_same_csr_outstanding.1749546244
Short name T1015
Test name
Test status
Simulation time 131603162 ps
CPU time 1.55 seconds
Started Aug 27 09:18:50 AM UTC 24
Finished Aug 27 09:18:53 AM UTC 24
Peak memory 215216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749546244 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_outstanding.1749546244
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/7.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_errors.970619071
Short name T1025
Test name
Test status
Simulation time 221832625 ps
CPU time 5.78 seconds
Started Aug 27 09:18:48 AM UTC 24
Finished Aug 27 09:18:55 AM UTC 24
Peak memory 227524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970619071 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.970619071
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/7.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_intg_err.4266309541
Short name T315
Test name
Test status
Simulation time 98958377 ps
CPU time 2.6 seconds
Started Aug 27 09:18:49 AM UTC 24
Finished Aug 27 09:18:52 AM UTC 24
Peak memory 217500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266309541 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.4266309541
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/7.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1734279360
Short name T1019
Test name
Test status
Simulation time 19222241 ps
CPU time 1.31 seconds
Started Aug 27 09:18:51 AM UTC 24
Finished Aug 27 09:18:54 AM UTC 24
Peak memory 227684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1734279360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1734279360
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_rw.4231348137
Short name T282
Test name
Test status
Simulation time 33851313 ps
CPU time 0.97 seconds
Started Aug 27 09:18:51 AM UTC 24
Finished Aug 27 09:18:53 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231348137 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.4231348137
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/8.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/8.edn_intr_test.1672336492
Short name T1018
Test name
Test status
Simulation time 39937066 ps
CPU time 1.25 seconds
Started Aug 27 09:18:51 AM UTC 24
Finished Aug 27 09:18:53 AM UTC 24
Peak memory 215364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672336492 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1672336492
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/8.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/8.edn_same_csr_outstanding.1922671690
Short name T1020
Test name
Test status
Simulation time 34494519 ps
CPU time 1.43 seconds
Started Aug 27 09:18:51 AM UTC 24
Finished Aug 27 09:18:54 AM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922671690 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_outstanding.1922671690
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/8.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_errors.3560626182
Short name T1021
Test name
Test status
Simulation time 63609821 ps
CPU time 3.11 seconds
Started Aug 27 09:18:50 AM UTC 24
Finished Aug 27 09:18:54 AM UTC 24
Peak memory 227800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560626182 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3560626182
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/8.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_intg_err.3821764137
Short name T1017
Test name
Test status
Simulation time 605213610 ps
CPU time 2.08 seconds
Started Aug 27 09:18:50 AM UTC 24
Finished Aug 27 09:18:53 AM UTC 24
Peak memory 217508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821764137 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.3821764137
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/8.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2415372186
Short name T1028
Test name
Test status
Simulation time 28599872 ps
CPU time 2.45 seconds
Started Aug 27 09:18:53 AM UTC 24
Finished Aug 27 09:18:56 AM UTC 24
Peak memory 227460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2415372186 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.2415372186
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_rw.4193597821
Short name T1023
Test name
Test status
Simulation time 81819699 ps
CPU time 1.19 seconds
Started Aug 27 09:18:53 AM UTC 24
Finished Aug 27 09:18:55 AM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193597821 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.4193597821
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/9.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/9.edn_intr_test.1629117228
Short name T1022
Test name
Test status
Simulation time 22260282 ps
CPU time 1.17 seconds
Started Aug 27 09:18:53 AM UTC 24
Finished Aug 27 09:18:55 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629117228 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1629117228
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/9.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/9.edn_same_csr_outstanding.949687827
Short name T1026
Test name
Test status
Simulation time 14908956 ps
CPU time 1.38 seconds
Started Aug 27 09:18:53 AM UTC 24
Finished Aug 27 09:18:55 AM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949687827 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_outstanding.949687827
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/9.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_errors.3761736058
Short name T990
Test name
Test status
Simulation time 67831952 ps
CPU time 3.13 seconds
Started Aug 27 09:18:51 AM UTC 24
Finished Aug 27 09:18:56 AM UTC 24
Peak memory 227880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761736058 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3761736058
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/9.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_intg_err.2023986597
Short name T1024
Test name
Test status
Simulation time 124636683 ps
CPU time 2.7 seconds
Started Aug 27 09:18:51 AM UTC 24
Finished Aug 27 09:18:55 AM UTC 24
Peak memory 217484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023986597 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2023986597
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/9.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/0.edn_genbits.3667540268
Short name T3
Test name
Test status
Simulation time 42784042 ps
CPU time 2.38 seconds
Started Aug 27 09:10:39 AM UTC 24
Finished Aug 27 09:10:43 AM UTC 24
Peak memory 229532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667540268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_genbits.3667540268
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/0.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/0.edn_intr.2267636273
Short name T4
Test name
Test status
Simulation time 41740892 ps
CPU time 1.19 seconds
Started Aug 27 09:10:43 AM UTC 24
Finished Aug 27 09:10:45 AM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267636273 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 0.edn_intr.2267636273
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/0.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/0.edn_smoke.3122722060
Short name T1
Test name
Test status
Simulation time 52305967 ps
CPU time 1.25 seconds
Started Aug 27 09:10:39 AM UTC 24
Finished Aug 27 09:10:42 AM UTC 24
Peak memory 226812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122722060 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 0.edn_smoke.3122722060
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/0.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/0.edn_stress_all_with_rand_reset.1300989246
Short name T37
Test name
Test status
Simulation time 5250590398 ps
CPU time 68.7 seconds
Started Aug 27 09:10:41 AM UTC 24
Finished Aug 27 09:11:52 AM UTC 24
Peak memory 229720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1300989246 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_
with_rand_reset.1300989246
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/1.edn_alert_test.3646083898
Short name T63
Test name
Test status
Simulation time 17353839 ps
CPU time 1.23 seconds
Started Aug 27 09:10:51 AM UTC 24
Finished Aug 27 09:10:53 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646083898 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.3646083898
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/1.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/1.edn_disable.2939123319
Short name T62
Test name
Test status
Simulation time 13935631 ps
CPU time 1.08 seconds
Started Aug 27 09:10:49 AM UTC 24
Finished Aug 27 09:10:51 AM UTC 24
Peak memory 216136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939123319 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2939123319
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/1.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/1.edn_disable_auto_req_mode.3222835203
Short name T49
Test name
Test status
Simulation time 31309195 ps
CPU time 1.83 seconds
Started Aug 27 09:10:50 AM UTC 24
Finished Aug 27 09:10:53 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222835203 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable_auto_req_mode.3222835203
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/1.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/1.edn_err.2518436220
Short name T7
Test name
Test status
Simulation time 27152094 ps
CPU time 1.62 seconds
Started Aug 27 09:10:49 AM UTC 24
Finished Aug 27 09:10:51 AM UTC 24
Peak memory 243800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518436220 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 1.edn_err.2518436220
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/1.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/1.edn_intr.1875883173
Short name T30
Test name
Test status
Simulation time 39680560 ps
CPU time 1.17 seconds
Started Aug 27 09:10:48 AM UTC 24
Finished Aug 27 09:10:50 AM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875883173 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 1.edn_intr.1875883173
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/1.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/1.edn_regwen.1597306776
Short name T26
Test name
Test status
Simulation time 19472047 ps
CPU time 1.36 seconds
Started Aug 27 09:10:46 AM UTC 24
Finished Aug 27 09:10:49 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597306776 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 1.edn_regwen.1597306776
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/1.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/1.edn_sec_cm.2782149908
Short name T15
Test name
Test status
Simulation time 1005800767 ps
CPU time 6.46 seconds
Started Aug 27 09:10:51 AM UTC 24
Finished Aug 27 09:10:58 AM UTC 24
Peak memory 260444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782149908 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.2782149908
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/1.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/1.edn_smoke.1842781382
Short name T25
Test name
Test status
Simulation time 20105013 ps
CPU time 1.47 seconds
Started Aug 27 09:10:45 AM UTC 24
Finished Aug 27 09:10:48 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842781382 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 1.edn_smoke.1842781382
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/1.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/1.edn_stress_all.3707661976
Short name T57
Test name
Test status
Simulation time 96140095 ps
CPU time 3.41 seconds
Started Aug 27 09:10:47 AM UTC 24
Finished Aug 27 09:10:51 AM UTC 24
Peak memory 227572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707661976 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3707661976
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/1.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/10.edn_alert.858959191
Short name T125
Test name
Test status
Simulation time 41189349 ps
CPU time 1.71 seconds
Started Aug 27 09:11:46 AM UTC 24
Finished Aug 27 09:11:49 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858959191 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 10.edn_alert.858959191
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/10.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/10.edn_alert_test.633649642
Short name T386
Test name
Test status
Simulation time 41243938 ps
CPU time 1.16 seconds
Started Aug 27 09:11:51 AM UTC 24
Finished Aug 27 09:11:53 AM UTC 24
Peak memory 216252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633649642 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.633649642
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/10.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/10.edn_disable.2659822700
Short name T93
Test name
Test status
Simulation time 30466156 ps
CPU time 1.19 seconds
Started Aug 27 09:11:48 AM UTC 24
Finished Aug 27 09:11:50 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659822700 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2659822700
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/10.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/10.edn_disable_auto_req_mode.119214678
Short name T21
Test name
Test status
Simulation time 77124077 ps
CPU time 1.38 seconds
Started Aug 27 09:11:50 AM UTC 24
Finished Aug 27 09:11:52 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119214678 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable_auto_req_mode.119214678
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/10.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/10.edn_err.1437596978
Short name T148
Test name
Test status
Simulation time 102788559 ps
CPU time 1.26 seconds
Started Aug 27 09:11:48 AM UTC 24
Finished Aug 27 09:11:50 AM UTC 24
Peak memory 246084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437596978 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 10.edn_err.1437596978
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/10.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/10.edn_genbits.3040095742
Short name T384
Test name
Test status
Simulation time 35410428 ps
CPU time 1.77 seconds
Started Aug 27 09:11:44 AM UTC 24
Finished Aug 27 09:11:47 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040095742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3040095742
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/10.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/10.edn_intr.3660428483
Short name T111
Test name
Test status
Simulation time 20788172 ps
CPU time 1.47 seconds
Started Aug 27 09:11:46 AM UTC 24
Finished Aug 27 09:11:49 AM UTC 24
Peak memory 226020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660428483 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 10.edn_intr.3660428483
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/10.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/10.edn_smoke.4011171022
Short name T382
Test name
Test status
Simulation time 27978353 ps
CPU time 1.29 seconds
Started Aug 27 09:11:43 AM UTC 24
Finished Aug 27 09:11:45 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011171022 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 10.edn_smoke.4011171022
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/10.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/10.edn_stress_all.1485411594
Short name T256
Test name
Test status
Simulation time 3389897951 ps
CPU time 5.53 seconds
Started Aug 27 09:11:44 AM UTC 24
Finished Aug 27 09:11:51 AM UTC 24
Peak memory 229572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485411594 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1485411594
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/10.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/100.edn_alert.3914620421
Short name T722
Test name
Test status
Simulation time 31163267 ps
CPU time 1.75 seconds
Started Aug 27 09:17:08 AM UTC 24
Finished Aug 27 09:17:11 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914620421 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 100.edn_alert.3914620421
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/100.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/100.edn_genbits.173268872
Short name T721
Test name
Test status
Simulation time 26761602 ps
CPU time 1.68 seconds
Started Aug 27 09:17:08 AM UTC 24
Finished Aug 27 09:17:11 AM UTC 24
Peak memory 228084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173268872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 100.edn_genbits.173268872
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/100.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/101.edn_alert.954217788
Short name T191
Test name
Test status
Simulation time 220360396 ps
CPU time 1.84 seconds
Started Aug 27 09:17:08 AM UTC 24
Finished Aug 27 09:17:11 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954217788 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 101.edn_alert.954217788
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/101.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/101.edn_genbits.1659958949
Short name T724
Test name
Test status
Simulation time 29356115 ps
CPU time 1.82 seconds
Started Aug 27 09:17:08 AM UTC 24
Finished Aug 27 09:17:11 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659958949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 101.edn_genbits.1659958949
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/101.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/102.edn_alert.656811505
Short name T727
Test name
Test status
Simulation time 24275262 ps
CPU time 1.68 seconds
Started Aug 27 09:17:09 AM UTC 24
Finished Aug 27 09:17:12 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656811505 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 102.edn_alert.656811505
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/102.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/102.edn_genbits.2684977554
Short name T723
Test name
Test status
Simulation time 63775772 ps
CPU time 1.64 seconds
Started Aug 27 09:17:08 AM UTC 24
Finished Aug 27 09:17:11 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684977554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2684977554
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/102.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/103.edn_alert.3790570949
Short name T730
Test name
Test status
Simulation time 27274183 ps
CPU time 1.77 seconds
Started Aug 27 09:17:10 AM UTC 24
Finished Aug 27 09:17:13 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790570949 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 103.edn_alert.3790570949
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/103.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/103.edn_genbits.4111619659
Short name T725
Test name
Test status
Simulation time 62377977 ps
CPU time 1.42 seconds
Started Aug 27 09:17:09 AM UTC 24
Finished Aug 27 09:17:12 AM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111619659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 103.edn_genbits.4111619659
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/103.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/104.edn_genbits.1647522968
Short name T728
Test name
Test status
Simulation time 168456192 ps
CPU time 1.44 seconds
Started Aug 27 09:17:10 AM UTC 24
Finished Aug 27 09:17:13 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647522968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 104.edn_genbits.1647522968
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/104.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/105.edn_alert.100056494
Short name T731
Test name
Test status
Simulation time 25687589 ps
CPU time 1.58 seconds
Started Aug 27 09:17:12 AM UTC 24
Finished Aug 27 09:17:14 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100056494 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 105.edn_alert.100056494
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/105.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/105.edn_genbits.3609299914
Short name T344
Test name
Test status
Simulation time 95810679 ps
CPU time 1.66 seconds
Started Aug 27 09:17:12 AM UTC 24
Finished Aug 27 09:17:14 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609299914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 105.edn_genbits.3609299914
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/105.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/106.edn_alert.3713313231
Short name T734
Test name
Test status
Simulation time 50481668 ps
CPU time 1.75 seconds
Started Aug 27 09:17:12 AM UTC 24
Finished Aug 27 09:17:15 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713313231 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 106.edn_alert.3713313231
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/106.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/106.edn_genbits.1510378936
Short name T733
Test name
Test status
Simulation time 55696418 ps
CPU time 1.82 seconds
Started Aug 27 09:17:12 AM UTC 24
Finished Aug 27 09:17:15 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510378936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1510378936
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/106.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/107.edn_genbits.1329447187
Short name T978
Test name
Test status
Simulation time 4577420425 ps
CPU time 88.65 seconds
Started Aug 27 09:17:12 AM UTC 24
Finished Aug 27 09:18:42 AM UTC 24
Peak memory 229560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329447187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 107.edn_genbits.1329447187
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/107.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/108.edn_alert.193019685
Short name T737
Test name
Test status
Simulation time 225497841 ps
CPU time 1.8 seconds
Started Aug 27 09:17:13 AM UTC 24
Finished Aug 27 09:17:16 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193019685 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 108.edn_alert.193019685
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/108.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/108.edn_genbits.2297162569
Short name T735
Test name
Test status
Simulation time 81064169 ps
CPU time 1.34 seconds
Started Aug 27 09:17:13 AM UTC 24
Finished Aug 27 09:17:15 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297162569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2297162569
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/108.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/109.edn_alert.422604111
Short name T738
Test name
Test status
Simulation time 44960584 ps
CPU time 1.48 seconds
Started Aug 27 09:17:14 AM UTC 24
Finished Aug 27 09:17:17 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422604111 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 109.edn_alert.422604111
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/109.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/109.edn_genbits.4058681099
Short name T736
Test name
Test status
Simulation time 79678481 ps
CPU time 1.75 seconds
Started Aug 27 09:17:13 AM UTC 24
Finished Aug 27 09:17:16 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058681099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 109.edn_genbits.4058681099
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/109.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/11.edn_alert.390972027
Short name T90
Test name
Test status
Simulation time 29239550 ps
CPU time 1.84 seconds
Started Aug 27 09:11:54 AM UTC 24
Finished Aug 27 09:11:57 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390972027 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 11.edn_alert.390972027
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/11.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/11.edn_alert_test.3057734528
Short name T389
Test name
Test status
Simulation time 39719036 ps
CPU time 1.12 seconds
Started Aug 27 09:11:56 AM UTC 24
Finished Aug 27 09:11:59 AM UTC 24
Peak memory 216928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057734528 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3057734528
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/11.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/11.edn_disable.3741272601
Short name T41
Test name
Test status
Simulation time 84993507 ps
CPU time 1.14 seconds
Started Aug 27 09:11:54 AM UTC 24
Finished Aug 27 09:11:56 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741272601 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3741272601
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/11.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/11.edn_disable_auto_req_mode.3124539984
Short name T388
Test name
Test status
Simulation time 262978236 ps
CPU time 1.53 seconds
Started Aug 27 09:11:54 AM UTC 24
Finished Aug 27 09:11:57 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124539984 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable_auto_req_mode.3124539984
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/11.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/11.edn_err.1524539004
Short name T387
Test name
Test status
Simulation time 30097195 ps
CPU time 1.31 seconds
Started Aug 27 09:11:54 AM UTC 24
Finished Aug 27 09:11:57 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524539004 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 11.edn_err.1524539004
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/11.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/11.edn_genbits.2103802410
Short name T53
Test name
Test status
Simulation time 77180761 ps
CPU time 1.86 seconds
Started Aug 27 09:11:51 AM UTC 24
Finished Aug 27 09:11:54 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103802410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2103802410
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/11.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/11.edn_intr.1569371395
Short name T89
Test name
Test status
Simulation time 38385459 ps
CPU time 1.55 seconds
Started Aug 27 09:11:53 AM UTC 24
Finished Aug 27 09:11:56 AM UTC 24
Peak memory 236980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569371395 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 11.edn_intr.1569371395
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/11.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/11.edn_smoke.145403592
Short name T385
Test name
Test status
Simulation time 24427932 ps
CPU time 1.04 seconds
Started Aug 27 09:11:51 AM UTC 24
Finished Aug 27 09:11:53 AM UTC 24
Peak memory 215960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145403592 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 11.edn_smoke.145403592
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/11.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/11.edn_stress_all.13246314
Short name T303
Test name
Test status
Simulation time 339633747 ps
CPU time 6.86 seconds
Started Aug 27 09:11:52 AM UTC 24
Finished Aug 27 09:12:00 AM UTC 24
Peak memory 229452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13246314 -assert nopostproc +UVM_TESTNAME=edn_s
tress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.13246314
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/11.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/11.edn_stress_all_with_rand_reset.1569362657
Short name T229
Test name
Test status
Simulation time 8854872405 ps
CPU time 50.92 seconds
Started Aug 27 09:11:53 AM UTC 24
Finished Aug 27 09:12:45 AM UTC 24
Peak memory 229728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1569362657 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all
_with_rand_reset.1569362657
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/11.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/110.edn_alert.217932032
Short name T740
Test name
Test status
Simulation time 25114401 ps
CPU time 1.6 seconds
Started Aug 27 09:17:14 AM UTC 24
Finished Aug 27 09:17:17 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217932032 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 110.edn_alert.217932032
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/110.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/110.edn_genbits.2740807661
Short name T739
Test name
Test status
Simulation time 35733925 ps
CPU time 1.69 seconds
Started Aug 27 09:17:14 AM UTC 24
Finished Aug 27 09:17:17 AM UTC 24
Peak memory 228556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740807661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2740807661
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/110.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/111.edn_alert.3081059478
Short name T745
Test name
Test status
Simulation time 114618234 ps
CPU time 1.84 seconds
Started Aug 27 09:17:15 AM UTC 24
Finished Aug 27 09:17:18 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081059478 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 111.edn_alert.3081059478
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/111.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/111.edn_genbits.2235731486
Short name T743
Test name
Test status
Simulation time 89075183 ps
CPU time 1.69 seconds
Started Aug 27 09:17:15 AM UTC 24
Finished Aug 27 09:17:18 AM UTC 24
Peak memory 230604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235731486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 111.edn_genbits.2235731486
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/111.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/112.edn_alert.1124043499
Short name T744
Test name
Test status
Simulation time 91085761 ps
CPU time 1.61 seconds
Started Aug 27 09:17:16 AM UTC 24
Finished Aug 27 09:17:18 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124043499 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 112.edn_alert.1124043499
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/112.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/112.edn_genbits.3566433327
Short name T741
Test name
Test status
Simulation time 70255623 ps
CPU time 1.47 seconds
Started Aug 27 09:17:15 AM UTC 24
Finished Aug 27 09:17:18 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566433327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 112.edn_genbits.3566433327
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/112.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/113.edn_alert.3564067009
Short name T747
Test name
Test status
Simulation time 27468443 ps
CPU time 1.84 seconds
Started Aug 27 09:17:17 AM UTC 24
Finished Aug 27 09:17:20 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564067009 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 113.edn_alert.3564067009
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/113.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/113.edn_genbits.2424606469
Short name T742
Test name
Test status
Simulation time 77691213 ps
CPU time 1.41 seconds
Started Aug 27 09:17:16 AM UTC 24
Finished Aug 27 09:17:18 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424606469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 113.edn_genbits.2424606469
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/113.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/114.edn_alert.4030013229
Short name T746
Test name
Test status
Simulation time 308817952 ps
CPU time 1.4 seconds
Started Aug 27 09:17:17 AM UTC 24
Finished Aug 27 09:17:19 AM UTC 24
Peak memory 232516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030013229 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 114.edn_alert.4030013229
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/114.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/115.edn_alert.377772714
Short name T260
Test name
Test status
Simulation time 81775949 ps
CPU time 1.58 seconds
Started Aug 27 09:17:18 AM UTC 24
Finished Aug 27 09:17:20 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377772714 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 115.edn_alert.377772714
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/115.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/116.edn_alert.554641843
Short name T265
Test name
Test status
Simulation time 88276912 ps
CPU time 1.63 seconds
Started Aug 27 09:17:19 AM UTC 24
Finished Aug 27 09:17:22 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554641843 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 116.edn_alert.554641843
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/116.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/116.edn_genbits.1991020352
Short name T262
Test name
Test status
Simulation time 36293512 ps
CPU time 1.96 seconds
Started Aug 27 09:17:18 AM UTC 24
Finished Aug 27 09:17:21 AM UTC 24
Peak memory 228556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991020352 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1991020352
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/116.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/117.edn_alert.569049998
Short name T268
Test name
Test status
Simulation time 36719735 ps
CPU time 1.7 seconds
Started Aug 27 09:17:19 AM UTC 24
Finished Aug 27 09:17:22 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569049998 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 117.edn_alert.569049998
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/117.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/117.edn_genbits.1024459020
Short name T267
Test name
Test status
Simulation time 31908971 ps
CPU time 1.77 seconds
Started Aug 27 09:17:19 AM UTC 24
Finished Aug 27 09:17:22 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024459020 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 117.edn_genbits.1024459020
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/117.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/118.edn_alert.3187181501
Short name T266
Test name
Test status
Simulation time 27762745 ps
CPU time 1.57 seconds
Started Aug 27 09:17:19 AM UTC 24
Finished Aug 27 09:17:22 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187181501 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 118.edn_alert.3187181501
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/118.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/118.edn_genbits.122453051
Short name T264
Test name
Test status
Simulation time 75415060 ps
CPU time 1.59 seconds
Started Aug 27 09:17:19 AM UTC 24
Finished Aug 27 09:17:22 AM UTC 24
Peak memory 228296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122453051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 118.edn_genbits.122453051
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/118.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/119.edn_alert.3591599064
Short name T748
Test name
Test status
Simulation time 29268764 ps
CPU time 1.86 seconds
Started Aug 27 09:17:20 AM UTC 24
Finished Aug 27 09:17:23 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591599064 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 119.edn_alert.3591599064
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/119.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/119.edn_genbits.1311592135
Short name T269
Test name
Test status
Simulation time 103274249 ps
CPU time 1.56 seconds
Started Aug 27 09:17:20 AM UTC 24
Finished Aug 27 09:17:23 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311592135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 119.edn_genbits.1311592135
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/119.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/12.edn_alert.828822696
Short name T72
Test name
Test status
Simulation time 92002547 ps
CPU time 1.95 seconds
Started Aug 27 09:12:01 AM UTC 24
Finished Aug 27 09:12:04 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828822696 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 12.edn_alert.828822696
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/12.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/12.edn_alert_test.3252294208
Short name T392
Test name
Test status
Simulation time 57274195 ps
CPU time 1.23 seconds
Started Aug 27 09:12:03 AM UTC 24
Finished Aug 27 09:12:05 AM UTC 24
Peak memory 216244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252294208 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3252294208
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/12.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/12.edn_disable.885688771
Short name T206
Test name
Test status
Simulation time 17362985 ps
CPU time 1.21 seconds
Started Aug 27 09:12:01 AM UTC 24
Finished Aug 27 09:12:03 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885688771 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.885688771
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/12.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/12.edn_disable_auto_req_mode.645238965
Short name T73
Test name
Test status
Simulation time 34148644 ps
CPU time 1.63 seconds
Started Aug 27 09:12:03 AM UTC 24
Finished Aug 27 09:12:06 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645238965 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable_auto_req_mode.645238965
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/12.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/12.edn_err.1843310433
Short name T153
Test name
Test status
Simulation time 19732611 ps
CPU time 1.42 seconds
Started Aug 27 09:12:01 AM UTC 24
Finished Aug 27 09:12:03 AM UTC 24
Peak memory 237156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843310433 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 12.edn_err.1843310433
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/12.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/12.edn_genbits.4057564122
Short name T304
Test name
Test status
Simulation time 46664192 ps
CPU time 1.51 seconds
Started Aug 27 09:11:58 AM UTC 24
Finished Aug 27 09:12:00 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057564122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_genbits.4057564122
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/12.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/12.edn_smoke.1116057345
Short name T390
Test name
Test status
Simulation time 18206039 ps
CPU time 1.42 seconds
Started Aug 27 09:11:58 AM UTC 24
Finished Aug 27 09:12:00 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116057345 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 12.edn_smoke.1116057345
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/12.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/12.edn_stress_all.2540511252
Short name T391
Test name
Test status
Simulation time 204814753 ps
CPU time 5.5 seconds
Started Aug 27 09:11:58 AM UTC 24
Finished Aug 27 09:12:04 AM UTC 24
Peak memory 227236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540511252 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2540511252
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/12.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/12.edn_stress_all_with_rand_reset.1078921388
Short name T451
Test name
Test status
Simulation time 5232300191 ps
CPU time 78.9 seconds
Started Aug 27 09:11:58 AM UTC 24
Finished Aug 27 09:13:19 AM UTC 24
Peak memory 229856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1078921388 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all
_with_rand_reset.1078921388
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/12.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/120.edn_genbits.1895041295
Short name T751
Test name
Test status
Simulation time 163785455 ps
CPU time 3.43 seconds
Started Aug 27 09:17:20 AM UTC 24
Finished Aug 27 09:17:25 AM UTC 24
Peak memory 231504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895041295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 120.edn_genbits.1895041295
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/120.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/121.edn_alert.1266230819
Short name T749
Test name
Test status
Simulation time 22550894 ps
CPU time 1.65 seconds
Started Aug 27 09:17:22 AM UTC 24
Finished Aug 27 09:17:24 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266230819 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 121.edn_alert.1266230819
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/121.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/122.edn_genbits.3672882424
Short name T360
Test name
Test status
Simulation time 218878044 ps
CPU time 1.72 seconds
Started Aug 27 09:17:22 AM UTC 24
Finished Aug 27 09:17:24 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672882424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3672882424
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/122.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/123.edn_alert.2441282438
Short name T753
Test name
Test status
Simulation time 24537083 ps
CPU time 1.52 seconds
Started Aug 27 09:17:23 AM UTC 24
Finished Aug 27 09:17:25 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441282438 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 123.edn_alert.2441282438
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/123.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/123.edn_genbits.2633154527
Short name T754
Test name
Test status
Simulation time 91912353 ps
CPU time 1.71 seconds
Started Aug 27 09:17:23 AM UTC 24
Finished Aug 27 09:17:25 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633154527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2633154527
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/123.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/124.edn_genbits.2363610301
Short name T752
Test name
Test status
Simulation time 183586769 ps
CPU time 1.26 seconds
Started Aug 27 09:17:23 AM UTC 24
Finished Aug 27 09:17:25 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363610301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 124.edn_genbits.2363610301
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/124.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/125.edn_alert.1805740856
Short name T757
Test name
Test status
Simulation time 27471320 ps
CPU time 1.79 seconds
Started Aug 27 09:17:24 AM UTC 24
Finished Aug 27 09:17:27 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805740856 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 125.edn_alert.1805740856
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/125.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/125.edn_genbits.1070168293
Short name T756
Test name
Test status
Simulation time 82096531 ps
CPU time 1.55 seconds
Started Aug 27 09:17:24 AM UTC 24
Finished Aug 27 09:17:27 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070168293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 125.edn_genbits.1070168293
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/125.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/126.edn_alert.1389171049
Short name T760
Test name
Test status
Simulation time 34950993 ps
CPU time 1.64 seconds
Started Aug 27 09:17:25 AM UTC 24
Finished Aug 27 09:17:28 AM UTC 24
Peak memory 230404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389171049 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 126.edn_alert.1389171049
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/126.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/126.edn_genbits.1971977620
Short name T979
Test name
Test status
Simulation time 4583577911 ps
CPU time 88.51 seconds
Started Aug 27 09:17:25 AM UTC 24
Finished Aug 27 09:18:56 AM UTC 24
Peak memory 231832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971977620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1971977620
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/126.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/127.edn_alert.3898058636
Short name T320
Test name
Test status
Simulation time 41678241 ps
CPU time 1.76 seconds
Started Aug 27 09:17:25 AM UTC 24
Finished Aug 27 09:17:28 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898058636 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 127.edn_alert.3898058636
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/127.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/127.edn_genbits.147332058
Short name T758
Test name
Test status
Simulation time 167328995 ps
CPU time 1.49 seconds
Started Aug 27 09:17:25 AM UTC 24
Finished Aug 27 09:17:28 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147332058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 127.edn_genbits.147332058
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/127.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/128.edn_alert.3921764092
Short name T305
Test name
Test status
Simulation time 29358211 ps
CPU time 1.66 seconds
Started Aug 27 09:17:26 AM UTC 24
Finished Aug 27 09:17:29 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921764092 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 128.edn_alert.3921764092
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/128.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/128.edn_genbits.1287850190
Short name T761
Test name
Test status
Simulation time 223896410 ps
CPU time 1.64 seconds
Started Aug 27 09:17:25 AM UTC 24
Finished Aug 27 09:17:28 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287850190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 128.edn_genbits.1287850190
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/128.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/129.edn_alert.2927045493
Short name T764
Test name
Test status
Simulation time 82673225 ps
CPU time 1.72 seconds
Started Aug 27 09:17:27 AM UTC 24
Finished Aug 27 09:17:29 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927045493 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 129.edn_alert.2927045493
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/129.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/129.edn_genbits.1424168297
Short name T762
Test name
Test status
Simulation time 135684985 ps
CPU time 1.16 seconds
Started Aug 27 09:17:26 AM UTC 24
Finished Aug 27 09:17:29 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424168297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 129.edn_genbits.1424168297
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/129.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/13.edn_alert.1535950249
Short name T74
Test name
Test status
Simulation time 31283773 ps
CPU time 1.89 seconds
Started Aug 27 09:12:07 AM UTC 24
Finished Aug 27 09:12:09 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535950249 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 13.edn_alert.1535950249
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/13.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/13.edn_alert_test.691475669
Short name T394
Test name
Test status
Simulation time 21575944 ps
CPU time 1.35 seconds
Started Aug 27 09:12:08 AM UTC 24
Finished Aug 27 09:12:10 AM UTC 24
Peak memory 226904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691475669 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.691475669
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/13.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/13.edn_disable_auto_req_mode.2068089087
Short name T84
Test name
Test status
Simulation time 102636851 ps
CPU time 1.47 seconds
Started Aug 27 09:12:08 AM UTC 24
Finished Aug 27 09:12:10 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068089087 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable_auto_req_mode.2068089087
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/13.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/13.edn_err.4176821770
Short name T154
Test name
Test status
Simulation time 26177097 ps
CPU time 1.44 seconds
Started Aug 27 09:12:07 AM UTC 24
Finished Aug 27 09:12:09 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176821770 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 13.edn_err.4176821770
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/13.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/13.edn_intr.953247259
Short name T32
Test name
Test status
Simulation time 29104679 ps
CPU time 1.27 seconds
Started Aug 27 09:12:07 AM UTC 24
Finished Aug 27 09:12:09 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953247259 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 13.edn_intr.953247259
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/13.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/13.edn_smoke.2777754027
Short name T393
Test name
Test status
Simulation time 28903857 ps
CPU time 1.26 seconds
Started Aug 27 09:12:04 AM UTC 24
Finished Aug 27 09:12:07 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777754027 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 13.edn_smoke.2777754027
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/13.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/13.edn_stress_all.2815451909
Short name T257
Test name
Test status
Simulation time 39411454 ps
CPU time 1.75 seconds
Started Aug 27 09:12:04 AM UTC 24
Finished Aug 27 09:12:07 AM UTC 24
Peak memory 226672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815451909 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.2815451909
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/13.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/13.edn_stress_all_with_rand_reset.3930217449
Short name T232
Test name
Test status
Simulation time 7449786547 ps
CPU time 46.45 seconds
Started Aug 27 09:12:05 AM UTC 24
Finished Aug 27 09:12:53 AM UTC 24
Peak memory 233952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3930217449 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all
_with_rand_reset.3930217449
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/13.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/130.edn_genbits.2869804479
Short name T763
Test name
Test status
Simulation time 67970325 ps
CPU time 1.67 seconds
Started Aug 27 09:17:27 AM UTC 24
Finished Aug 27 09:17:29 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869804479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2869804479
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/130.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/131.edn_alert.2219618734
Short name T765
Test name
Test status
Simulation time 246934563 ps
CPU time 1.72 seconds
Started Aug 27 09:17:28 AM UTC 24
Finished Aug 27 09:17:30 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219618734 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 131.edn_alert.2219618734
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/131.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/132.edn_alert.3991946801
Short name T766
Test name
Test status
Simulation time 33521269 ps
CPU time 1.56 seconds
Started Aug 27 09:17:29 AM UTC 24
Finished Aug 27 09:17:31 AM UTC 24
Peak memory 228272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991946801 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 132.edn_alert.3991946801
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/132.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/132.edn_genbits.337413316
Short name T768
Test name
Test status
Simulation time 48051262 ps
CPU time 2.53 seconds
Started Aug 27 09:17:29 AM UTC 24
Finished Aug 27 09:17:32 AM UTC 24
Peak memory 229460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337413316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 132.edn_genbits.337413316
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/132.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/133.edn_alert.2437012146
Short name T767
Test name
Test status
Simulation time 67490355 ps
CPU time 1.62 seconds
Started Aug 27 09:17:29 AM UTC 24
Finished Aug 27 09:17:32 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437012146 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 133.edn_alert.2437012146
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/133.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/133.edn_genbits.3359551618
Short name T352
Test name
Test status
Simulation time 38051438 ps
CPU time 2.49 seconds
Started Aug 27 09:17:29 AM UTC 24
Finished Aug 27 09:17:32 AM UTC 24
Peak memory 229528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359551618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3359551618
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/133.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/134.edn_alert.1626465295
Short name T770
Test name
Test status
Simulation time 23258786 ps
CPU time 1.67 seconds
Started Aug 27 09:17:30 AM UTC 24
Finished Aug 27 09:17:33 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626465295 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 134.edn_alert.1626465295
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/134.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/134.edn_genbits.2971946706
Short name T774
Test name
Test status
Simulation time 153361553 ps
CPU time 3.32 seconds
Started Aug 27 09:17:29 AM UTC 24
Finished Aug 27 09:17:33 AM UTC 24
Peak memory 231504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971946706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2971946706
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/134.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/135.edn_alert.286637179
Short name T772
Test name
Test status
Simulation time 30091867 ps
CPU time 1.79 seconds
Started Aug 27 09:17:30 AM UTC 24
Finished Aug 27 09:17:33 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286637179 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 135.edn_alert.286637179
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/135.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/135.edn_genbits.166661117
Short name T769
Test name
Test status
Simulation time 25701861 ps
CPU time 1.64 seconds
Started Aug 27 09:17:30 AM UTC 24
Finished Aug 27 09:17:33 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166661117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 135.edn_genbits.166661117
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/135.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/136.edn_alert.2995961200
Short name T773
Test name
Test status
Simulation time 68477813 ps
CPU time 1.71 seconds
Started Aug 27 09:17:30 AM UTC 24
Finished Aug 27 09:17:33 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995961200 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 136.edn_alert.2995961200
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/136.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/137.edn_alert.959205568
Short name T775
Test name
Test status
Simulation time 275866050 ps
CPU time 1.95 seconds
Started Aug 27 09:17:31 AM UTC 24
Finished Aug 27 09:17:34 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959205568 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 137.edn_alert.959205568
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/137.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/137.edn_genbits.3956376886
Short name T339
Test name
Test status
Simulation time 31796536 ps
CPU time 1.88 seconds
Started Aug 27 09:17:31 AM UTC 24
Finished Aug 27 09:17:34 AM UTC 24
Peak memory 230604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956376886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 137.edn_genbits.3956376886
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/137.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/138.edn_alert.2416242468
Short name T777
Test name
Test status
Simulation time 23030777 ps
CPU time 1.66 seconds
Started Aug 27 09:17:33 AM UTC 24
Finished Aug 27 09:17:35 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416242468 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 138.edn_alert.2416242468
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/138.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/138.edn_genbits.1892030123
Short name T776
Test name
Test status
Simulation time 166808915 ps
CPU time 1.41 seconds
Started Aug 27 09:17:33 AM UTC 24
Finished Aug 27 09:17:35 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892030123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1892030123
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/138.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/139.edn_alert.1311426068
Short name T782
Test name
Test status
Simulation time 27384103 ps
CPU time 1.79 seconds
Started Aug 27 09:17:34 AM UTC 24
Finished Aug 27 09:17:37 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311426068 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 139.edn_alert.1311426068
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/139.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/139.edn_genbits.951058541
Short name T780
Test name
Test status
Simulation time 38718096 ps
CPU time 1.92 seconds
Started Aug 27 09:17:34 AM UTC 24
Finished Aug 27 09:17:37 AM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951058541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 139.edn_genbits.951058541
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/139.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/14.edn_alert.3510233054
Short name T196
Test name
Test status
Simulation time 74538211 ps
CPU time 1.5 seconds
Started Aug 27 09:12:11 AM UTC 24
Finished Aug 27 09:12:14 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510233054 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 14.edn_alert.3510233054
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/14.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/14.edn_alert_test.1524911509
Short name T398
Test name
Test status
Simulation time 20486480 ps
CPU time 1.14 seconds
Started Aug 27 09:12:17 AM UTC 24
Finished Aug 27 09:12:19 AM UTC 24
Peak memory 217048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524911509 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1524911509
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/14.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/14.edn_disable.2349909830
Short name T75
Test name
Test status
Simulation time 24900887 ps
CPU time 1.3 seconds
Started Aug 27 09:12:14 AM UTC 24
Finished Aug 27 09:12:17 AM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349909830 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.2349909830
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/14.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/14.edn_disable_auto_req_mode.2037336360
Short name T85
Test name
Test status
Simulation time 242763974 ps
CPU time 1.42 seconds
Started Aug 27 09:12:14 AM UTC 24
Finished Aug 27 09:12:17 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037336360 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable_auto_req_mode.2037336360
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/14.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/14.edn_err.3224686717
Short name T397
Test name
Test status
Simulation time 32018029 ps
CPU time 1.38 seconds
Started Aug 27 09:12:13 AM UTC 24
Finished Aug 27 09:12:16 AM UTC 24
Peak memory 228720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224686717 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 14.edn_err.3224686717
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/14.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/14.edn_genbits.2748736727
Short name T117
Test name
Test status
Simulation time 557251374 ps
CPU time 6.8 seconds
Started Aug 27 09:12:10 AM UTC 24
Finished Aug 27 09:12:18 AM UTC 24
Peak memory 229520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748736727 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2748736727
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/14.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/14.edn_intr.949150267
Short name T396
Test name
Test status
Simulation time 27966160 ps
CPU time 1.47 seconds
Started Aug 27 09:12:11 AM UTC 24
Finished Aug 27 09:12:14 AM UTC 24
Peak memory 237720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949150267 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 14.edn_intr.949150267
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/14.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/14.edn_smoke.755620011
Short name T395
Test name
Test status
Simulation time 19871080 ps
CPU time 1.22 seconds
Started Aug 27 09:12:10 AM UTC 24
Finished Aug 27 09:12:12 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755620011 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 14.edn_smoke.755620011
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/14.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/14.edn_stress_all.322356141
Short name T333
Test name
Test status
Simulation time 558100223 ps
CPU time 4.24 seconds
Started Aug 27 09:12:10 AM UTC 24
Finished Aug 27 09:12:15 AM UTC 24
Peak memory 227488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322356141 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.322356141
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/14.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/140.edn_alert.180879488
Short name T779
Test name
Test status
Simulation time 88216200 ps
CPU time 1.63 seconds
Started Aug 27 09:17:34 AM UTC 24
Finished Aug 27 09:17:36 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180879488 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 140.edn_alert.180879488
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/140.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/140.edn_genbits.363471910
Short name T781
Test name
Test status
Simulation time 84783067 ps
CPU time 1.73 seconds
Started Aug 27 09:17:34 AM UTC 24
Finished Aug 27 09:17:37 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363471910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 140.edn_genbits.363471910
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/140.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/141.edn_alert.856849554
Short name T778
Test name
Test status
Simulation time 65092757 ps
CPU time 1.48 seconds
Started Aug 27 09:17:34 AM UTC 24
Finished Aug 27 09:17:36 AM UTC 24
Peak memory 229952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856849554 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 141.edn_alert.856849554
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/141.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/141.edn_genbits.1008845731
Short name T784
Test name
Test status
Simulation time 104508535 ps
CPU time 1.85 seconds
Started Aug 27 09:17:34 AM UTC 24
Finished Aug 27 09:17:37 AM UTC 24
Peak memory 228152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008845731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1008845731
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/141.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/142.edn_alert.1516124888
Short name T787
Test name
Test status
Simulation time 36706884 ps
CPU time 1.6 seconds
Started Aug 27 09:17:35 AM UTC 24
Finished Aug 27 09:17:38 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516124888 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 142.edn_alert.1516124888
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/142.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/142.edn_genbits.4063399128
Short name T336
Test name
Test status
Simulation time 52551640 ps
CPU time 1.79 seconds
Started Aug 27 09:17:34 AM UTC 24
Finished Aug 27 09:17:37 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063399128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 142.edn_genbits.4063399128
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/142.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/143.edn_alert.945306124
Short name T270
Test name
Test status
Simulation time 35083261 ps
CPU time 1.54 seconds
Started Aug 27 09:17:35 AM UTC 24
Finished Aug 27 09:17:38 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945306124 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 143.edn_alert.945306124
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/143.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/143.edn_genbits.2891380956
Short name T786
Test name
Test status
Simulation time 100492189 ps
CPU time 1.45 seconds
Started Aug 27 09:17:35 AM UTC 24
Finished Aug 27 09:17:38 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891380956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2891380956
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/143.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/144.edn_alert.3680812040
Short name T788
Test name
Test status
Simulation time 37828645 ps
CPU time 1.27 seconds
Started Aug 27 09:17:36 AM UTC 24
Finished Aug 27 09:17:39 AM UTC 24
Peak memory 228416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680812040 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 144.edn_alert.3680812040
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/144.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/144.edn_genbits.2469308920
Short name T789
Test name
Test status
Simulation time 47081224 ps
CPU time 2.52 seconds
Started Aug 27 09:17:36 AM UTC 24
Finished Aug 27 09:17:40 AM UTC 24
Peak memory 229704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469308920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 144.edn_genbits.2469308920
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/144.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/145.edn_alert.3981815504
Short name T792
Test name
Test status
Simulation time 22635217 ps
CPU time 1.67 seconds
Started Aug 27 09:17:37 AM UTC 24
Finished Aug 27 09:17:40 AM UTC 24
Peak memory 228168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981815504 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 145.edn_alert.3981815504
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/145.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/145.edn_genbits.160041959
Short name T791
Test name
Test status
Simulation time 51723851 ps
CPU time 1.68 seconds
Started Aug 27 09:17:37 AM UTC 24
Finished Aug 27 09:17:40 AM UTC 24
Peak memory 228076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160041959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 145.edn_genbits.160041959
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/145.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/146.edn_alert.1470258894
Short name T306
Test name
Test status
Simulation time 172038588 ps
CPU time 1.85 seconds
Started Aug 27 09:17:38 AM UTC 24
Finished Aug 27 09:17:40 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470258894 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 146.edn_alert.1470258894
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/146.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/146.edn_genbits.1373377442
Short name T793
Test name
Test status
Simulation time 39722938 ps
CPU time 1.74 seconds
Started Aug 27 09:17:38 AM UTC 24
Finished Aug 27 09:17:40 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373377442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1373377442
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/146.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/147.edn_alert.2705437542
Short name T271
Test name
Test status
Simulation time 49637151 ps
CPU time 1.84 seconds
Started Aug 27 09:17:38 AM UTC 24
Finished Aug 27 09:17:41 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705437542 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 147.edn_alert.2705437542
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/147.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/148.edn_alert.4206603097
Short name T790
Test name
Test status
Simulation time 29565356 ps
CPU time 1.32 seconds
Started Aug 27 09:17:38 AM UTC 24
Finished Aug 27 09:17:40 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206603097 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 148.edn_alert.4206603097
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/148.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/148.edn_genbits.3520633287
Short name T794
Test name
Test status
Simulation time 89403897 ps
CPU time 1.59 seconds
Started Aug 27 09:17:38 AM UTC 24
Finished Aug 27 09:17:40 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520633287 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 148.edn_genbits.3520633287
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/148.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/149.edn_alert.442180628
Short name T796
Test name
Test status
Simulation time 53555954 ps
CPU time 1.73 seconds
Started Aug 27 09:17:39 AM UTC 24
Finished Aug 27 09:17:42 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442180628 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 149.edn_alert.442180628
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/149.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/149.edn_genbits.4267053070
Short name T798
Test name
Test status
Simulation time 42464787 ps
CPU time 1.94 seconds
Started Aug 27 09:17:39 AM UTC 24
Finished Aug 27 09:17:42 AM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267053070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 149.edn_genbits.4267053070
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/149.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/15.edn_alert.3227964380
Short name T113
Test name
Test status
Simulation time 29113779 ps
CPU time 1.67 seconds
Started Aug 27 09:12:20 AM UTC 24
Finished Aug 27 09:12:23 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227964380 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 15.edn_alert.3227964380
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/15.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/15.edn_alert_test.4032040259
Short name T404
Test name
Test status
Simulation time 31024326 ps
CPU time 1.29 seconds
Started Aug 27 09:12:23 AM UTC 24
Finished Aug 27 09:12:25 AM UTC 24
Peak memory 217048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032040259 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.4032040259
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/15.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/15.edn_disable_auto_req_mode.3812632862
Short name T129
Test name
Test status
Simulation time 239644074 ps
CPU time 1.53 seconds
Started Aug 27 09:12:22 AM UTC 24
Finished Aug 27 09:12:25 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812632862 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable_auto_req_mode.3812632862
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/15.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/15.edn_err.4059899966
Short name T403
Test name
Test status
Simulation time 21902533 ps
CPU time 1.42 seconds
Started Aug 27 09:12:21 AM UTC 24
Finished Aug 27 09:12:23 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059899966 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 15.edn_err.4059899966
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/15.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/15.edn_genbits.970789374
Short name T363
Test name
Test status
Simulation time 63356581 ps
CPU time 1.86 seconds
Started Aug 27 09:12:18 AM UTC 24
Finished Aug 27 09:12:21 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970789374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.edn_genbits.970789374
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/15.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/15.edn_intr.2758181873
Short name T402
Test name
Test status
Simulation time 23035932 ps
CPU time 1.94 seconds
Started Aug 27 09:12:20 AM UTC 24
Finished Aug 27 09:12:23 AM UTC 24
Peak memory 237340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758181873 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 15.edn_intr.2758181873
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/15.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/15.edn_smoke.3715370978
Short name T399
Test name
Test status
Simulation time 26505125 ps
CPU time 1.34 seconds
Started Aug 27 09:12:17 AM UTC 24
Finished Aug 27 09:12:19 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715370978 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 15.edn_smoke.3715370978
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/15.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/15.edn_stress_all.2080502573
Short name T406
Test name
Test status
Simulation time 822692838 ps
CPU time 6.75 seconds
Started Aug 27 09:12:18 AM UTC 24
Finished Aug 27 09:12:26 AM UTC 24
Peak memory 229536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080502573 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2080502573
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/15.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/150.edn_alert.1481468178
Short name T797
Test name
Test status
Simulation time 82805792 ps
CPU time 1.59 seconds
Started Aug 27 09:17:39 AM UTC 24
Finished Aug 27 09:17:42 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481468178 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 150.edn_alert.1481468178
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/150.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/151.edn_alert.3027128534
Short name T799
Test name
Test status
Simulation time 31138536 ps
CPU time 1.41 seconds
Started Aug 27 09:17:40 AM UTC 24
Finished Aug 27 09:17:43 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027128534 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 151.edn_alert.3027128534
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/151.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/151.edn_genbits.3688312666
Short name T800
Test name
Test status
Simulation time 46069745 ps
CPU time 2.37 seconds
Started Aug 27 09:17:40 AM UTC 24
Finished Aug 27 09:17:44 AM UTC 24
Peak memory 231764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688312666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 151.edn_genbits.3688312666
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/151.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/152.edn_alert.11092776
Short name T802
Test name
Test status
Simulation time 24196770 ps
CPU time 1.78 seconds
Started Aug 27 09:17:41 AM UTC 24
Finished Aug 27 09:17:44 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11092776 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 152.edn_alert.11092776
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/152.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/152.edn_genbits.1039228637
Short name T801
Test name
Test status
Simulation time 36343637 ps
CPU time 1.8 seconds
Started Aug 27 09:17:41 AM UTC 24
Finished Aug 27 09:17:44 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039228637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 152.edn_genbits.1039228637
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/152.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/153.edn_alert.418314656
Short name T803
Test name
Test status
Simulation time 90009413 ps
CPU time 1.75 seconds
Started Aug 27 09:17:42 AM UTC 24
Finished Aug 27 09:17:44 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418314656 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 153.edn_alert.418314656
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/153.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/153.edn_genbits.2470814585
Short name T806
Test name
Test status
Simulation time 73656780 ps
CPU time 1.88 seconds
Started Aug 27 09:17:42 AM UTC 24
Finished Aug 27 09:17:44 AM UTC 24
Peak memory 230604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470814585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2470814585
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/153.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/154.edn_alert.2558318338
Short name T807
Test name
Test status
Simulation time 32704814 ps
CPU time 1.75 seconds
Started Aug 27 09:17:42 AM UTC 24
Finished Aug 27 09:17:44 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558318338 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 154.edn_alert.2558318338
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/154.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/154.edn_genbits.2902612164
Short name T805
Test name
Test status
Simulation time 43070312 ps
CPU time 1.69 seconds
Started Aug 27 09:17:42 AM UTC 24
Finished Aug 27 09:17:44 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902612164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2902612164
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/154.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/155.edn_genbits.1878359249
Short name T804
Test name
Test status
Simulation time 85707766 ps
CPU time 1.73 seconds
Started Aug 27 09:17:42 AM UTC 24
Finished Aug 27 09:17:44 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878359249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1878359249
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/155.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/156.edn_genbits.1505521802
Short name T808
Test name
Test status
Simulation time 37044848 ps
CPU time 1.6 seconds
Started Aug 27 09:17:43 AM UTC 24
Finished Aug 27 09:17:46 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505521802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 156.edn_genbits.1505521802
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/156.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/157.edn_alert.3502264601
Short name T809
Test name
Test status
Simulation time 65072969 ps
CPU time 1.57 seconds
Started Aug 27 09:17:43 AM UTC 24
Finished Aug 27 09:17:46 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502264601 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 157.edn_alert.3502264601
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/157.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/157.edn_genbits.1533928480
Short name T810
Test name
Test status
Simulation time 41142784 ps
CPU time 2.01 seconds
Started Aug 27 09:17:43 AM UTC 24
Finished Aug 27 09:17:46 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533928480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 157.edn_genbits.1533928480
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/157.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/158.edn_alert.3738952361
Short name T811
Test name
Test status
Simulation time 98651135 ps
CPU time 2.07 seconds
Started Aug 27 09:17:43 AM UTC 24
Finished Aug 27 09:17:46 AM UTC 24
Peak memory 232132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738952361 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 158.edn_alert.3738952361
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/158.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/158.edn_genbits.771577023
Short name T345
Test name
Test status
Simulation time 70584830 ps
CPU time 1.64 seconds
Started Aug 27 09:17:43 AM UTC 24
Finished Aug 27 09:17:46 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771577023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 158.edn_genbits.771577023
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/158.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/159.edn_alert.80242605
Short name T814
Test name
Test status
Simulation time 73928883 ps
CPU time 1.75 seconds
Started Aug 27 09:17:46 AM UTC 24
Finished Aug 27 09:17:48 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80242605 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 159.edn_alert.80242605
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/159.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/16.edn_alert_test.3461861174
Short name T408
Test name
Test status
Simulation time 20191326 ps
CPU time 1.27 seconds
Started Aug 27 09:12:29 AM UTC 24
Finished Aug 27 09:12:32 AM UTC 24
Peak memory 217108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461861174 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3461861174
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/16.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/16.edn_disable_auto_req_mode.550078674
Short name T158
Test name
Test status
Simulation time 103208783 ps
CPU time 1.67 seconds
Started Aug 27 09:12:28 AM UTC 24
Finished Aug 27 09:12:30 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550078674 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable_auto_req_mode.550078674
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/16.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/16.edn_err.2003766279
Short name T149
Test name
Test status
Simulation time 31216429 ps
CPU time 1.41 seconds
Started Aug 27 09:12:27 AM UTC 24
Finished Aug 27 09:12:29 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003766279 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 16.edn_err.2003766279
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/16.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/16.edn_intr.1843159097
Short name T407
Test name
Test status
Simulation time 38730292 ps
CPU time 1.38 seconds
Started Aug 27 09:12:26 AM UTC 24
Finished Aug 27 09:12:29 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843159097 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 16.edn_intr.1843159097
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/16.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/16.edn_smoke.2174267387
Short name T405
Test name
Test status
Simulation time 44500536 ps
CPU time 1.3 seconds
Started Aug 27 09:12:23 AM UTC 24
Finished Aug 27 09:12:25 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174267387 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 16.edn_smoke.2174267387
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/16.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/16.edn_stress_all.2976595536
Short name T410
Test name
Test status
Simulation time 553347761 ps
CPU time 8.95 seconds
Started Aug 27 09:12:25 AM UTC 24
Finished Aug 27 09:12:35 AM UTC 24
Peak memory 231912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976595536 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2976595536
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/16.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/160.edn_alert.2749232919
Short name T813
Test name
Test status
Simulation time 66411762 ps
CPU time 1.66 seconds
Started Aug 27 09:17:46 AM UTC 24
Finished Aug 27 09:17:48 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749232919 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 160.edn_alert.2749232919
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/160.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/160.edn_genbits.564881619
Short name T816
Test name
Test status
Simulation time 40720420 ps
CPU time 1.99 seconds
Started Aug 27 09:17:46 AM UTC 24
Finished Aug 27 09:17:49 AM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564881619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 160.edn_genbits.564881619
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/160.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/161.edn_alert.1353142665
Short name T296
Test name
Test status
Simulation time 96513711 ps
CPU time 1.55 seconds
Started Aug 27 09:17:46 AM UTC 24
Finished Aug 27 09:17:48 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353142665 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 161.edn_alert.1353142665
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/161.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/161.edn_genbits.1825717507
Short name T817
Test name
Test status
Simulation time 91308223 ps
CPU time 2.37 seconds
Started Aug 27 09:17:46 AM UTC 24
Finished Aug 27 09:17:49 AM UTC 24
Peak memory 229528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825717507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1825717507
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/161.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/162.edn_alert.441362325
Short name T815
Test name
Test status
Simulation time 47546665 ps
CPU time 1.5 seconds
Started Aug 27 09:17:46 AM UTC 24
Finished Aug 27 09:17:48 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441362325 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 162.edn_alert.441362325
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/162.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/162.edn_genbits.4259211863
Short name T812
Test name
Test status
Simulation time 71124559 ps
CPU time 1.44 seconds
Started Aug 27 09:17:46 AM UTC 24
Finished Aug 27 09:17:48 AM UTC 24
Peak memory 228576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259211863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 162.edn_genbits.4259211863
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/162.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/163.edn_alert.2766507395
Short name T818
Test name
Test status
Simulation time 85792689 ps
CPU time 1.52 seconds
Started Aug 27 09:17:47 AM UTC 24
Finished Aug 27 09:17:49 AM UTC 24
Peak memory 228412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766507395 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 163.edn_alert.2766507395
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/163.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/163.edn_genbits.3443828230
Short name T820
Test name
Test status
Simulation time 66507766 ps
CPU time 2.1 seconds
Started Aug 27 09:17:47 AM UTC 24
Finished Aug 27 09:17:50 AM UTC 24
Peak memory 229704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443828230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 163.edn_genbits.3443828230
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/163.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/164.edn_alert.3106734292
Short name T819
Test name
Test status
Simulation time 72228889 ps
CPU time 1.58 seconds
Started Aug 27 09:17:47 AM UTC 24
Finished Aug 27 09:17:50 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106734292 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 164.edn_alert.3106734292
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/164.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/164.edn_genbits.1072442800
Short name T831
Test name
Test status
Simulation time 292094280 ps
CPU time 5.25 seconds
Started Aug 27 09:17:47 AM UTC 24
Finished Aug 27 09:17:53 AM UTC 24
Peak memory 231672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072442800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 164.edn_genbits.1072442800
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/164.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/165.edn_alert.4145324387
Short name T821
Test name
Test status
Simulation time 24879389 ps
CPU time 1.79 seconds
Started Aug 27 09:17:47 AM UTC 24
Finished Aug 27 09:17:50 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145324387 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 165.edn_alert.4145324387
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/165.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/165.edn_genbits.2115604708
Short name T354
Test name
Test status
Simulation time 71722992 ps
CPU time 3.02 seconds
Started Aug 27 09:17:47 AM UTC 24
Finished Aug 27 09:17:51 AM UTC 24
Peak memory 231464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115604708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 165.edn_genbits.2115604708
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/165.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/166.edn_alert.3096035888
Short name T822
Test name
Test status
Simulation time 22722056 ps
CPU time 1.75 seconds
Started Aug 27 09:17:48 AM UTC 24
Finished Aug 27 09:17:51 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096035888 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 166.edn_alert.3096035888
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/166.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/166.edn_genbits.3905533586
Short name T783
Test name
Test status
Simulation time 113847043 ps
CPU time 2.08 seconds
Started Aug 27 09:17:47 AM UTC 24
Finished Aug 27 09:17:50 AM UTC 24
Peak memory 229456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905533586 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 166.edn_genbits.3905533586
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/166.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/167.edn_alert.1676187725
Short name T824
Test name
Test status
Simulation time 86502670 ps
CPU time 1.59 seconds
Started Aug 27 09:17:49 AM UTC 24
Finished Aug 27 09:17:52 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676187725 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 167.edn_alert.1676187725
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/167.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/167.edn_genbits.4019101391
Short name T823
Test name
Test status
Simulation time 35937692 ps
CPU time 1.44 seconds
Started Aug 27 09:17:49 AM UTC 24
Finished Aug 27 09:17:52 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019101391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 167.edn_genbits.4019101391
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/167.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/168.edn_alert.3369234463
Short name T826
Test name
Test status
Simulation time 24889893 ps
CPU time 1.7 seconds
Started Aug 27 09:17:50 AM UTC 24
Finished Aug 27 09:17:52 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369234463 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 168.edn_alert.3369234463
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/168.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/168.edn_genbits.1915377695
Short name T825
Test name
Test status
Simulation time 93877322 ps
CPU time 1.66 seconds
Started Aug 27 09:17:50 AM UTC 24
Finished Aug 27 09:17:52 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915377695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1915377695
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/168.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/169.edn_alert.1677603013
Short name T827
Test name
Test status
Simulation time 27035743 ps
CPU time 1.74 seconds
Started Aug 27 09:17:50 AM UTC 24
Finished Aug 27 09:17:52 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677603013 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 169.edn_alert.1677603013
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/169.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/169.edn_genbits.2336154336
Short name T828
Test name
Test status
Simulation time 47464781 ps
CPU time 2.15 seconds
Started Aug 27 09:17:50 AM UTC 24
Finished Aug 27 09:17:53 AM UTC 24
Peak memory 229448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336154336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2336154336
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/169.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/17.edn_alert.321501321
Short name T155
Test name
Test status
Simulation time 27871368 ps
CPU time 1.54 seconds
Started Aug 27 09:12:32 AM UTC 24
Finished Aug 27 09:12:35 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321501321 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 17.edn_alert.321501321
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/17.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/17.edn_alert_test.3489470188
Short name T412
Test name
Test status
Simulation time 45731954 ps
CPU time 1.22 seconds
Started Aug 27 09:12:36 AM UTC 24
Finished Aug 27 09:12:38 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489470188 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3489470188
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/17.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/17.edn_disable.4211813802
Short name T79
Test name
Test status
Simulation time 11600030 ps
CPU time 1.34 seconds
Started Aug 27 09:12:34 AM UTC 24
Finished Aug 27 09:12:37 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211813802 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.4211813802
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/17.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/17.edn_disable_auto_req_mode.1959837096
Short name T164
Test name
Test status
Simulation time 37533563 ps
CPU time 1.73 seconds
Started Aug 27 09:12:35 AM UTC 24
Finished Aug 27 09:12:37 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959837096 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable_auto_req_mode.1959837096
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/17.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/17.edn_err.2800384563
Short name T168
Test name
Test status
Simulation time 23211682 ps
CPU time 1.51 seconds
Started Aug 27 09:12:33 AM UTC 24
Finished Aug 27 09:12:36 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800384563 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 17.edn_err.2800384563
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/17.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/17.edn_genbits.1210716064
Short name T42
Test name
Test status
Simulation time 113411180 ps
CPU time 1.85 seconds
Started Aug 27 09:12:30 AM UTC 24
Finished Aug 27 09:12:33 AM UTC 24
Peak memory 228352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210716064 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1210716064
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/17.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/17.edn_intr.578317018
Short name T409
Test name
Test status
Simulation time 42078308 ps
CPU time 1.16 seconds
Started Aug 27 09:12:31 AM UTC 24
Finished Aug 27 09:12:34 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578317018 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 17.edn_intr.578317018
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/17.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/17.edn_smoke.3606115479
Short name T325
Test name
Test status
Simulation time 35126946 ps
CPU time 1.47 seconds
Started Aug 27 09:12:30 AM UTC 24
Finished Aug 27 09:12:33 AM UTC 24
Peak memory 216016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606115479 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 17.edn_smoke.3606115479
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/17.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/17.edn_stress_all.979125521
Short name T411
Test name
Test status
Simulation time 496275674 ps
CPU time 4.12 seconds
Started Aug 27 09:12:30 AM UTC 24
Finished Aug 27 09:12:35 AM UTC 24
Peak memory 231636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979125521 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.979125521
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/17.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/170.edn_alert.148246957
Short name T829
Test name
Test status
Simulation time 21841928 ps
CPU time 1.4 seconds
Started Aug 27 09:17:51 AM UTC 24
Finished Aug 27 09:17:53 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148246957 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 170.edn_alert.148246957
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/170.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/171.edn_alert.2374370766
Short name T832
Test name
Test status
Simulation time 28714155 ps
CPU time 1.68 seconds
Started Aug 27 09:17:51 AM UTC 24
Finished Aug 27 09:17:54 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374370766 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 171.edn_alert.2374370766
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/171.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/171.edn_genbits.3028838151
Short name T830
Test name
Test status
Simulation time 100073501 ps
CPU time 1.54 seconds
Started Aug 27 09:17:51 AM UTC 24
Finished Aug 27 09:17:53 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028838151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 171.edn_genbits.3028838151
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/171.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/172.edn_alert.1614643851
Short name T834
Test name
Test status
Simulation time 82023285 ps
CPU time 1.74 seconds
Started Aug 27 09:17:51 AM UTC 24
Finished Aug 27 09:17:54 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614643851 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 172.edn_alert.1614643851
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/172.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/172.edn_genbits.415308030
Short name T342
Test name
Test status
Simulation time 34094437 ps
CPU time 1.81 seconds
Started Aug 27 09:17:51 AM UTC 24
Finished Aug 27 09:17:54 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415308030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 172.edn_genbits.415308030
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/172.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/173.edn_alert.3223491123
Short name T835
Test name
Test status
Simulation time 184764662 ps
CPU time 1.58 seconds
Started Aug 27 09:17:52 AM UTC 24
Finished Aug 27 09:17:55 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223491123 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 173.edn_alert.3223491123
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/173.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/173.edn_genbits.2986196173
Short name T836
Test name
Test status
Simulation time 65867496 ps
CPU time 1.6 seconds
Started Aug 27 09:17:52 AM UTC 24
Finished Aug 27 09:17:55 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986196173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2986196173
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/173.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/174.edn_alert.4103238452
Short name T838
Test name
Test status
Simulation time 28317541 ps
CPU time 1.64 seconds
Started Aug 27 09:17:53 AM UTC 24
Finished Aug 27 09:17:56 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103238452 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 174.edn_alert.4103238452
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/174.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/174.edn_genbits.90209893
Short name T842
Test name
Test status
Simulation time 39548899 ps
CPU time 2.42 seconds
Started Aug 27 09:17:53 AM UTC 24
Finished Aug 27 09:17:57 AM UTC 24
Peak memory 231584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90209893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 174.edn_genbits.90209893
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/174.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/175.edn_alert.169735206
Short name T837
Test name
Test status
Simulation time 63524264 ps
CPU time 1.44 seconds
Started Aug 27 09:17:53 AM UTC 24
Finished Aug 27 09:17:56 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169735206 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 175.edn_alert.169735206
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/175.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/175.edn_genbits.4029015312
Short name T841
Test name
Test status
Simulation time 77769348 ps
CPU time 1.78 seconds
Started Aug 27 09:17:53 AM UTC 24
Finished Aug 27 09:17:56 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029015312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 175.edn_genbits.4029015312
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/175.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/176.edn_alert.2640549998
Short name T297
Test name
Test status
Simulation time 198990057 ps
CPU time 1.79 seconds
Started Aug 27 09:17:53 AM UTC 24
Finished Aug 27 09:17:56 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640549998 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 176.edn_alert.2640549998
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/176.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/176.edn_genbits.734227686
Short name T839
Test name
Test status
Simulation time 162821865 ps
CPU time 1.69 seconds
Started Aug 27 09:17:53 AM UTC 24
Finished Aug 27 09:17:56 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734227686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 176.edn_genbits.734227686
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/176.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/177.edn_alert.774814579
Short name T845
Test name
Test status
Simulation time 89343828 ps
CPU time 1.67 seconds
Started Aug 27 09:17:55 AM UTC 24
Finished Aug 27 09:17:57 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774814579 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 177.edn_alert.774814579
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/177.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/177.edn_genbits.2797539747
Short name T840
Test name
Test status
Simulation time 22018962 ps
CPU time 1.49 seconds
Started Aug 27 09:17:54 AM UTC 24
Finished Aug 27 09:17:56 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797539747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2797539747
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/177.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/178.edn_alert.1186760675
Short name T843
Test name
Test status
Simulation time 116472716 ps
CPU time 1.54 seconds
Started Aug 27 09:17:55 AM UTC 24
Finished Aug 27 09:17:57 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186760675 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 178.edn_alert.1186760675
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/178.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/178.edn_genbits.3450680230
Short name T846
Test name
Test status
Simulation time 90512447 ps
CPU time 1.63 seconds
Started Aug 27 09:17:55 AM UTC 24
Finished Aug 27 09:17:57 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450680230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3450680230
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/178.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/179.edn_alert.623191791
Short name T844
Test name
Test status
Simulation time 38490163 ps
CPU time 1.48 seconds
Started Aug 27 09:17:55 AM UTC 24
Finished Aug 27 09:17:57 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623191791 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 179.edn_alert.623191791
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/179.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/179.edn_genbits.3003270268
Short name T848
Test name
Test status
Simulation time 44364517 ps
CPU time 1.63 seconds
Started Aug 27 09:17:55 AM UTC 24
Finished Aug 27 09:17:57 AM UTC 24
Peak memory 226488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003270268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3003270268
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/179.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/18.edn_alert.3395581625
Short name T319
Test name
Test status
Simulation time 125520563 ps
CPU time 1.78 seconds
Started Aug 27 09:12:39 AM UTC 24
Finished Aug 27 09:12:42 AM UTC 24
Peak memory 226360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395581625 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 18.edn_alert.3395581625
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/18.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/18.edn_alert_test.2007342474
Short name T401
Test name
Test status
Simulation time 59424096 ps
CPU time 1.3 seconds
Started Aug 27 09:12:42 AM UTC 24
Finished Aug 27 09:12:45 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007342474 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2007342474
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/18.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/18.edn_disable_auto_req_mode.1297023244
Short name T416
Test name
Test status
Simulation time 71512621 ps
CPU time 1.24 seconds
Started Aug 27 09:12:41 AM UTC 24
Finished Aug 27 09:12:43 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297023244 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable_auto_req_mode.1297023244
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/18.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/18.edn_err.3564559390
Short name T400
Test name
Test status
Simulation time 22702434 ps
CPU time 1.34 seconds
Started Aug 27 09:12:40 AM UTC 24
Finished Aug 27 09:12:42 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564559390 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 18.edn_err.3564559390
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/18.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/18.edn_genbits.2832435019
Short name T414
Test name
Test status
Simulation time 46395721 ps
CPU time 1.89 seconds
Started Aug 27 09:12:37 AM UTC 24
Finished Aug 27 09:12:40 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832435019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2832435019
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/18.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/18.edn_intr.2475214073
Short name T415
Test name
Test status
Simulation time 28636993 ps
CPU time 1.46 seconds
Started Aug 27 09:12:38 AM UTC 24
Finished Aug 27 09:12:40 AM UTC 24
Peak memory 236700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475214073 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 18.edn_intr.2475214073
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/18.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/18.edn_smoke.623435821
Short name T413
Test name
Test status
Simulation time 23145891 ps
CPU time 1.24 seconds
Started Aug 27 09:12:37 AM UTC 24
Finished Aug 27 09:12:39 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623435821 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 18.edn_smoke.623435821
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/18.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/18.edn_stress_all.2694509267
Short name T302
Test name
Test status
Simulation time 1020740310 ps
CPU time 6.23 seconds
Started Aug 27 09:12:37 AM UTC 24
Finished Aug 27 09:12:44 AM UTC 24
Peak memory 227472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694509267 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.2694509267
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/18.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/180.edn_alert.704987670
Short name T850
Test name
Test status
Simulation time 359452266 ps
CPU time 2.05 seconds
Started Aug 27 09:17:56 AM UTC 24
Finished Aug 27 09:17:59 AM UTC 24
Peak memory 232132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704987670 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 180.edn_alert.704987670
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/180.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/180.edn_genbits.814341886
Short name T847
Test name
Test status
Simulation time 92820457 ps
CPU time 1.53 seconds
Started Aug 27 09:17:55 AM UTC 24
Finished Aug 27 09:17:57 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814341886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 180.edn_genbits.814341886
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/180.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/181.edn_alert.1512527023
Short name T851
Test name
Test status
Simulation time 101408088 ps
CPU time 1.18 seconds
Started Aug 27 09:17:57 AM UTC 24
Finished Aug 27 09:17:59 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512527023 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 181.edn_alert.1512527023
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/181.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/181.edn_genbits.684970732
Short name T849
Test name
Test status
Simulation time 45391059 ps
CPU time 1.2 seconds
Started Aug 27 09:17:56 AM UTC 24
Finished Aug 27 09:17:58 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684970732 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 181.edn_genbits.684970732
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/181.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/182.edn_alert.1355177393
Short name T855
Test name
Test status
Simulation time 22887592 ps
CPU time 1.65 seconds
Started Aug 27 09:17:57 AM UTC 24
Finished Aug 27 09:18:00 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355177393 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 182.edn_alert.1355177393
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/182.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/182.edn_genbits.3440146714
Short name T853
Test name
Test status
Simulation time 51017531 ps
CPU time 1.68 seconds
Started Aug 27 09:17:57 AM UTC 24
Finished Aug 27 09:18:00 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440146714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 182.edn_genbits.3440146714
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/182.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/183.edn_alert.1368906795
Short name T856
Test name
Test status
Simulation time 96050348 ps
CPU time 1.61 seconds
Started Aug 27 09:17:57 AM UTC 24
Finished Aug 27 09:18:00 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368906795 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 183.edn_alert.1368906795
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/183.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/183.edn_genbits.3641530395
Short name T852
Test name
Test status
Simulation time 72789097 ps
CPU time 1.38 seconds
Started Aug 27 09:17:57 AM UTC 24
Finished Aug 27 09:18:00 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641530395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 183.edn_genbits.3641530395
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/183.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/184.edn_alert.1501456832
Short name T857
Test name
Test status
Simulation time 28639314 ps
CPU time 1.7 seconds
Started Aug 27 09:17:57 AM UTC 24
Finished Aug 27 09:18:00 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501456832 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 184.edn_alert.1501456832
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/184.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/184.edn_genbits.2593655792
Short name T854
Test name
Test status
Simulation time 139013749 ps
CPU time 1.46 seconds
Started Aug 27 09:17:57 AM UTC 24
Finished Aug 27 09:18:00 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593655792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2593655792
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/184.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/185.edn_alert.392991521
Short name T858
Test name
Test status
Simulation time 33880610 ps
CPU time 1.27 seconds
Started Aug 27 09:17:58 AM UTC 24
Finished Aug 27 09:18:01 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392991521 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 185.edn_alert.392991521
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/185.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/185.edn_genbits.3594909347
Short name T860
Test name
Test status
Simulation time 45071418 ps
CPU time 1.69 seconds
Started Aug 27 09:17:58 AM UTC 24
Finished Aug 27 09:18:01 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594909347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 185.edn_genbits.3594909347
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/185.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/186.edn_alert.1368874975
Short name T862
Test name
Test status
Simulation time 88842128 ps
CPU time 1.58 seconds
Started Aug 27 09:17:59 AM UTC 24
Finished Aug 27 09:18:01 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368874975 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 186.edn_alert.1368874975
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/186.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/186.edn_genbits.278601203
Short name T863
Test name
Test status
Simulation time 54367919 ps
CPU time 1.95 seconds
Started Aug 27 09:17:59 AM UTC 24
Finished Aug 27 09:18:01 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278601203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 186.edn_genbits.278601203
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/186.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/187.edn_alert.3957325382
Short name T861
Test name
Test status
Simulation time 45527502 ps
CPU time 1.58 seconds
Started Aug 27 09:17:59 AM UTC 24
Finished Aug 27 09:18:01 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957325382 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 187.edn_alert.3957325382
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/187.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/187.edn_genbits.2807734595
Short name T859
Test name
Test status
Simulation time 189197445 ps
CPU time 1.45 seconds
Started Aug 27 09:17:59 AM UTC 24
Finished Aug 27 09:18:01 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807734595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2807734595
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/187.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/188.edn_alert.389462097
Short name T866
Test name
Test status
Simulation time 68483618 ps
CPU time 1.7 seconds
Started Aug 27 09:18:00 AM UTC 24
Finished Aug 27 09:18:02 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389462097 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 188.edn_alert.389462097
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/188.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/188.edn_genbits.2456445575
Short name T865
Test name
Test status
Simulation time 45183111 ps
CPU time 1.65 seconds
Started Aug 27 09:18:00 AM UTC 24
Finished Aug 27 09:18:02 AM UTC 24
Peak memory 230680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456445575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 188.edn_genbits.2456445575
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/188.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/189.edn_alert.2757421821
Short name T867
Test name
Test status
Simulation time 52057531 ps
CPU time 1.56 seconds
Started Aug 27 09:18:01 AM UTC 24
Finished Aug 27 09:18:04 AM UTC 24
Peak memory 226220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757421821 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 189.edn_alert.2757421821
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/189.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/189.edn_genbits.862247274
Short name T864
Test name
Test status
Simulation time 160329735 ps
CPU time 1.41 seconds
Started Aug 27 09:18:00 AM UTC 24
Finished Aug 27 09:18:02 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862247274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 189.edn_genbits.862247274
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/189.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/19.edn_alert.3389434424
Short name T112
Test name
Test status
Simulation time 90843494 ps
CPU time 1.75 seconds
Started Aug 27 09:12:46 AM UTC 24
Finished Aug 27 09:12:48 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389434424 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 19.edn_alert.3389434424
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/19.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/19.edn_alert_test.547172890
Short name T248
Test name
Test status
Simulation time 20915891 ps
CPU time 1.3 seconds
Started Aug 27 09:12:47 AM UTC 24
Finished Aug 27 09:12:49 AM UTC 24
Peak memory 217104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547172890 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.547172890
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/19.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/19.edn_disable.1870385596
Short name T170
Test name
Test status
Simulation time 157989819 ps
CPU time 1.22 seconds
Started Aug 27 09:12:46 AM UTC 24
Finished Aug 27 09:12:48 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870385596 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1870385596
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/19.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/19.edn_disable_auto_req_mode.1902373194
Short name T246
Test name
Test status
Simulation time 160624596 ps
CPU time 1.41 seconds
Started Aug 27 09:12:46 AM UTC 24
Finished Aug 27 09:12:48 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902373194 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable_auto_req_mode.1902373194
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/19.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/19.edn_err.4267699582
Short name T185
Test name
Test status
Simulation time 21447654 ps
CPU time 1.51 seconds
Started Aug 27 09:12:46 AM UTC 24
Finished Aug 27 09:12:48 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267699582 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 19.edn_err.4267699582
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/19.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/19.edn_genbits.1125182579
Short name T366
Test name
Test status
Simulation time 28998996 ps
CPU time 1.87 seconds
Started Aug 27 09:12:42 AM UTC 24
Finished Aug 27 09:12:45 AM UTC 24
Peak memory 230612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125182579 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_genbits.1125182579
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/19.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/19.edn_intr.3426468318
Short name T35
Test name
Test status
Simulation time 20640545 ps
CPU time 1.36 seconds
Started Aug 27 09:12:45 AM UTC 24
Finished Aug 27 09:12:47 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426468318 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 19.edn_intr.3426468318
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/19.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/19.edn_smoke.1986379742
Short name T417
Test name
Test status
Simulation time 19168466 ps
CPU time 1.52 seconds
Started Aug 27 09:12:42 AM UTC 24
Finished Aug 27 09:12:45 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986379742 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 19.edn_smoke.1986379742
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/19.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/19.edn_stress_all.2595050694
Short name T247
Test name
Test status
Simulation time 691491741 ps
CPU time 4.28 seconds
Started Aug 27 09:12:44 AM UTC 24
Finished Aug 27 09:12:49 AM UTC 24
Peak memory 231508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595050694 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.2595050694
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/19.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/190.edn_alert.2726008381
Short name T868
Test name
Test status
Simulation time 69084394 ps
CPU time 1.57 seconds
Started Aug 27 09:18:01 AM UTC 24
Finished Aug 27 09:18:04 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726008381 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 190.edn_alert.2726008381
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/190.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/190.edn_genbits.1744576954
Short name T871
Test name
Test status
Simulation time 45730519 ps
CPU time 2.17 seconds
Started Aug 27 09:18:01 AM UTC 24
Finished Aug 27 09:18:04 AM UTC 24
Peak memory 229344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744576954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1744576954
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/190.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/191.edn_alert.1638048041
Short name T870
Test name
Test status
Simulation time 78556482 ps
CPU time 1.68 seconds
Started Aug 27 09:18:01 AM UTC 24
Finished Aug 27 09:18:04 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638048041 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 191.edn_alert.1638048041
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/191.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/191.edn_genbits.296698966
Short name T869
Test name
Test status
Simulation time 71947089 ps
CPU time 1.64 seconds
Started Aug 27 09:18:01 AM UTC 24
Finished Aug 27 09:18:04 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296698966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 191.edn_genbits.296698966
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/191.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/192.edn_alert.3024625772
Short name T873
Test name
Test status
Simulation time 235637483 ps
CPU time 1.72 seconds
Started Aug 27 09:18:02 AM UTC 24
Finished Aug 27 09:18:06 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024625772 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 192.edn_alert.3024625772
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/192.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/192.edn_genbits.3336467567
Short name T872
Test name
Test status
Simulation time 97378255 ps
CPU time 2.55 seconds
Started Aug 27 09:18:01 AM UTC 24
Finished Aug 27 09:18:05 AM UTC 24
Peak memory 231488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336467567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 192.edn_genbits.3336467567
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/192.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/193.edn_alert.1278789858
Short name T272
Test name
Test status
Simulation time 112967605 ps
CPU time 1.87 seconds
Started Aug 27 09:18:02 AM UTC 24
Finished Aug 27 09:18:06 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278789858 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 193.edn_alert.1278789858
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/193.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/193.edn_genbits.3393182218
Short name T875
Test name
Test status
Simulation time 33365929 ps
CPU time 1.88 seconds
Started Aug 27 09:18:02 AM UTC 24
Finished Aug 27 09:18:06 AM UTC 24
Peak memory 230604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393182218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3393182218
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/193.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/194.edn_alert.1800986826
Short name T874
Test name
Test status
Simulation time 64525032 ps
CPU time 1.6 seconds
Started Aug 27 09:18:03 AM UTC 24
Finished Aug 27 09:18:06 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800986826 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 194.edn_alert.1800986826
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/194.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/194.edn_genbits.380206370
Short name T876
Test name
Test status
Simulation time 37907383 ps
CPU time 1.79 seconds
Started Aug 27 09:18:02 AM UTC 24
Finished Aug 27 09:18:06 AM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380206370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 194.edn_genbits.380206370
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/194.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/195.edn_alert.1180432613
Short name T878
Test name
Test status
Simulation time 107348641 ps
CPU time 1.82 seconds
Started Aug 27 09:18:04 AM UTC 24
Finished Aug 27 09:18:07 AM UTC 24
Peak memory 226296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180432613 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 195.edn_alert.1180432613
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/195.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/195.edn_genbits.1117992921
Short name T877
Test name
Test status
Simulation time 33288269 ps
CPU time 1.72 seconds
Started Aug 27 09:18:03 AM UTC 24
Finished Aug 27 09:18:06 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117992921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 195.edn_genbits.1117992921
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/195.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/196.edn_alert.226414980
Short name T273
Test name
Test status
Simulation time 30774207 ps
CPU time 1.87 seconds
Started Aug 27 09:18:04 AM UTC 24
Finished Aug 27 09:18:07 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226414980 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 196.edn_alert.226414980
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/196.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/196.edn_genbits.770809281
Short name T879
Test name
Test status
Simulation time 96540518 ps
CPU time 2.16 seconds
Started Aug 27 09:18:04 AM UTC 24
Finished Aug 27 09:18:07 AM UTC 24
Peak memory 231448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770809281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 196.edn_genbits.770809281
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/196.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/197.edn_alert.1400171573
Short name T881
Test name
Test status
Simulation time 68544900 ps
CPU time 1.71 seconds
Started Aug 27 09:18:05 AM UTC 24
Finished Aug 27 09:18:08 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400171573 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 197.edn_alert.1400171573
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/197.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/197.edn_genbits.1705758572
Short name T883
Test name
Test status
Simulation time 43816931 ps
CPU time 2.51 seconds
Started Aug 27 09:18:05 AM UTC 24
Finished Aug 27 09:18:08 AM UTC 24
Peak memory 229448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705758572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1705758572
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/197.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/198.edn_alert.3524617090
Short name T880
Test name
Test status
Simulation time 78966190 ps
CPU time 1.41 seconds
Started Aug 27 09:18:05 AM UTC 24
Finished Aug 27 09:18:07 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524617090 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 198.edn_alert.3524617090
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/198.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/198.edn_genbits.2723728732
Short name T358
Test name
Test status
Simulation time 41828363 ps
CPU time 2.34 seconds
Started Aug 27 09:18:05 AM UTC 24
Finished Aug 27 09:18:08 AM UTC 24
Peak memory 231560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723728732 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2723728732
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/198.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/199.edn_alert.1917212641
Short name T884
Test name
Test status
Simulation time 45815375 ps
CPU time 1.46 seconds
Started Aug 27 09:18:06 AM UTC 24
Finished Aug 27 09:18:09 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917212641 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 199.edn_alert.1917212641
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/199.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/199.edn_genbits.43682843
Short name T882
Test name
Test status
Simulation time 79725964 ps
CPU time 1.55 seconds
Started Aug 27 09:18:05 AM UTC 24
Finished Aug 27 09:18:08 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43682843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 199.edn_genbits.43682843
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/199.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/2.edn_alert.1370072479
Short name T28
Test name
Test status
Simulation time 26271768 ps
CPU time 1.57 seconds
Started Aug 27 09:10:55 AM UTC 24
Finished Aug 27 09:10:57 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370072479 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 2.edn_alert.1370072479
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/2.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/2.edn_alert_test.190749644
Short name T67
Test name
Test status
Simulation time 84230327 ps
CPU time 1.27 seconds
Started Aug 27 09:10:58 AM UTC 24
Finished Aug 27 09:11:00 AM UTC 24
Peak memory 216972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190749644 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.190749644
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/2.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/2.edn_disable_auto_req_mode.744047827
Short name T17
Test name
Test status
Simulation time 22946409 ps
CPU time 1.34 seconds
Started Aug 27 09:10:56 AM UTC 24
Finished Aug 27 09:10:58 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744047827 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable_auto_req_mode.744047827
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/2.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/2.edn_err.1879082402
Short name T65
Test name
Test status
Simulation time 54932356 ps
CPU time 1.15 seconds
Started Aug 27 09:10:56 AM UTC 24
Finished Aug 27 09:10:58 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879082402 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 2.edn_err.1879082402
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/2.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/2.edn_genbits.78488249
Short name T40
Test name
Test status
Simulation time 70410309 ps
CPU time 1.91 seconds
Started Aug 27 09:10:52 AM UTC 24
Finished Aug 27 09:10:55 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78488249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 2.edn_genbits.78488249
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/2.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/2.edn_regwen.2383019684
Short name T27
Test name
Test status
Simulation time 16117595 ps
CPU time 1.63 seconds
Started Aug 27 09:10:52 AM UTC 24
Finished Aug 27 09:10:55 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383019684 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 2.edn_regwen.2383019684
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/2.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/2.edn_sec_cm.2298918877
Short name T16
Test name
Test status
Simulation time 439180208 ps
CPU time 7.27 seconds
Started Aug 27 09:10:57 AM UTC 24
Finished Aug 27 09:11:05 AM UTC 24
Peak memory 260388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298918877 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2298918877
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/2.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/2.edn_smoke.4214502252
Short name T64
Test name
Test status
Simulation time 48730586 ps
CPU time 1.16 seconds
Started Aug 27 09:10:52 AM UTC 24
Finished Aug 27 09:10:54 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214502252 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 2.edn_smoke.4214502252
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/2.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/2.edn_stress_all.838652640
Short name T66
Test name
Test status
Simulation time 173459105 ps
CPU time 4.39 seconds
Started Aug 27 09:10:52 AM UTC 24
Finished Aug 27 09:10:58 AM UTC 24
Peak memory 229520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838652640 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.838652640
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/2.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/2.edn_stress_all_with_rand_reset.2910713093
Short name T228
Test name
Test status
Simulation time 28393494803 ps
CPU time 91.91 seconds
Started Aug 27 09:10:53 AM UTC 24
Finished Aug 27 09:12:27 AM UTC 24
Peak memory 229720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2910713093 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_
with_rand_reset.2910713093
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/2.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/20.edn_alert_test.113886308
Short name T421
Test name
Test status
Simulation time 38616277 ps
CPU time 1.24 seconds
Started Aug 27 09:12:53 AM UTC 24
Finished Aug 27 09:12:55 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113886308 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.113886308
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/20.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/20.edn_disable.3202860584
Short name T221
Test name
Test status
Simulation time 16743065 ps
CPU time 1.25 seconds
Started Aug 27 09:12:52 AM UTC 24
Finished Aug 27 09:12:54 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202860584 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3202860584
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/20.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/20.edn_err.2322282217
Short name T189
Test name
Test status
Simulation time 88165349 ps
CPU time 1.18 seconds
Started Aug 27 09:12:51 AM UTC 24
Finished Aug 27 09:12:53 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322282217 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 20.edn_err.2322282217
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/20.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/20.edn_genbits.559481441
Short name T86
Test name
Test status
Simulation time 118471042 ps
CPU time 2.46 seconds
Started Aug 27 09:12:49 AM UTC 24
Finished Aug 27 09:12:53 AM UTC 24
Peak memory 229588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559481441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.edn_genbits.559481441
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/20.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/20.edn_intr.2884766569
Short name T418
Test name
Test status
Simulation time 22383956 ps
CPU time 1.78 seconds
Started Aug 27 09:12:49 AM UTC 24
Finished Aug 27 09:12:52 AM UTC 24
Peak memory 237820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884766569 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 20.edn_intr.2884766569
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/20.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/20.edn_smoke.3427604487
Short name T249
Test name
Test status
Simulation time 21151973 ps
CPU time 1.34 seconds
Started Aug 27 09:12:48 AM UTC 24
Finished Aug 27 09:12:50 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427604487 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 20.edn_smoke.3427604487
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/20.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/20.edn_stress_all.3599550303
Short name T419
Test name
Test status
Simulation time 298173727 ps
CPU time 4.33 seconds
Started Aug 27 09:12:49 AM UTC 24
Finished Aug 27 09:12:55 AM UTC 24
Peak memory 229464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599550303 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3599550303
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/20.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/200.edn_genbits.3405258081
Short name T885
Test name
Test status
Simulation time 41426258 ps
CPU time 1.53 seconds
Started Aug 27 09:18:06 AM UTC 24
Finished Aug 27 09:18:09 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405258081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3405258081
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/200.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/201.edn_genbits.4067803609
Short name T886
Test name
Test status
Simulation time 38674400 ps
CPU time 1.92 seconds
Started Aug 27 09:18:06 AM UTC 24
Finished Aug 27 09:18:10 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067803609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 201.edn_genbits.4067803609
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/201.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/202.edn_genbits.1781897672
Short name T887
Test name
Test status
Simulation time 37496043 ps
CPU time 1.52 seconds
Started Aug 27 09:18:07 AM UTC 24
Finished Aug 27 09:18:11 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781897672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 202.edn_genbits.1781897672
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/202.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/203.edn_genbits.976785723
Short name T889
Test name
Test status
Simulation time 42931587 ps
CPU time 2.07 seconds
Started Aug 27 09:18:07 AM UTC 24
Finished Aug 27 09:18:11 AM UTC 24
Peak memory 229444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976785723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 203.edn_genbits.976785723
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/203.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/204.edn_genbits.3096633909
Short name T888
Test name
Test status
Simulation time 68018925 ps
CPU time 1.88 seconds
Started Aug 27 09:18:07 AM UTC 24
Finished Aug 27 09:18:11 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096633909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3096633909
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/204.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/205.edn_genbits.3382890749
Short name T891
Test name
Test status
Simulation time 39287871 ps
CPU time 1.96 seconds
Started Aug 27 09:18:07 AM UTC 24
Finished Aug 27 09:18:11 AM UTC 24
Peak memory 230624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382890749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3382890749
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/205.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/206.edn_genbits.712177477
Short name T892
Test name
Test status
Simulation time 78013653 ps
CPU time 2.6 seconds
Started Aug 27 09:18:07 AM UTC 24
Finished Aug 27 09:18:12 AM UTC 24
Peak memory 229520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712177477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 206.edn_genbits.712177477
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/206.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/207.edn_genbits.1057521225
Short name T890
Test name
Test status
Simulation time 38588950 ps
CPU time 1.97 seconds
Started Aug 27 09:18:08 AM UTC 24
Finished Aug 27 09:18:11 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057521225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1057521225
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/207.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/208.edn_genbits.3350521513
Short name T897
Test name
Test status
Simulation time 84260320 ps
CPU time 2.38 seconds
Started Aug 27 09:18:09 AM UTC 24
Finished Aug 27 09:18:13 AM UTC 24
Peak memory 231768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350521513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 208.edn_genbits.3350521513
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/208.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/209.edn_genbits.3562845190
Short name T895
Test name
Test status
Simulation time 45954611 ps
CPU time 1.57 seconds
Started Aug 27 09:18:09 AM UTC 24
Finished Aug 27 09:18:12 AM UTC 24
Peak memory 227168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562845190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 209.edn_genbits.3562845190
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/209.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/21.edn_alert.2792646289
Short name T132
Test name
Test status
Simulation time 70707381 ps
CPU time 1.63 seconds
Started Aug 27 09:12:55 AM UTC 24
Finished Aug 27 09:12:58 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792646289 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 21.edn_alert.2792646289
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/21.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/21.edn_alert_test.2315886930
Short name T425
Test name
Test status
Simulation time 13841656 ps
CPU time 1.24 seconds
Started Aug 27 09:12:56 AM UTC 24
Finished Aug 27 09:12:59 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315886930 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2315886930
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/21.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/21.edn_disable.2008164989
Short name T80
Test name
Test status
Simulation time 29668137 ps
CPU time 1.11 seconds
Started Aug 27 09:12:56 AM UTC 24
Finished Aug 27 09:12:59 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008164989 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.2008164989
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/21.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/21.edn_disable_auto_req_mode.3566358232
Short name T424
Test name
Test status
Simulation time 58537552 ps
CPU time 1.14 seconds
Started Aug 27 09:12:56 AM UTC 24
Finished Aug 27 09:12:59 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566358232 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable_auto_req_mode.3566358232
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/21.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/21.edn_genbits.4248198031
Short name T12
Test name
Test status
Simulation time 75594139 ps
CPU time 2.1 seconds
Started Aug 27 09:12:54 AM UTC 24
Finished Aug 27 09:12:57 AM UTC 24
Peak memory 231588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248198031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_genbits.4248198031
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/21.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/21.edn_intr.1011123693
Short name T423
Test name
Test status
Simulation time 35410226 ps
CPU time 1.29 seconds
Started Aug 27 09:12:54 AM UTC 24
Finished Aug 27 09:12:57 AM UTC 24
Peak memory 226308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011123693 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 21.edn_intr.1011123693
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/21.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/21.edn_smoke.933248876
Short name T420
Test name
Test status
Simulation time 38497745 ps
CPU time 1.16 seconds
Started Aug 27 09:12:53 AM UTC 24
Finished Aug 27 09:12:55 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933248876 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 21.edn_smoke.933248876
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/21.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/21.edn_stress_all.644740119
Short name T427
Test name
Test status
Simulation time 183834691 ps
CPU time 4.88 seconds
Started Aug 27 09:12:54 AM UTC 24
Finished Aug 27 09:13:00 AM UTC 24
Peak memory 228996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644740119 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.644740119
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/21.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/210.edn_genbits.222505269
Short name T896
Test name
Test status
Simulation time 51463397 ps
CPU time 1.96 seconds
Started Aug 27 09:18:09 AM UTC 24
Finished Aug 27 09:18:13 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222505269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 210.edn_genbits.222505269
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/210.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/211.edn_genbits.3403697457
Short name T893
Test name
Test status
Simulation time 65365629 ps
CPU time 1.2 seconds
Started Aug 27 09:18:09 AM UTC 24
Finished Aug 27 09:18:12 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403697457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 211.edn_genbits.3403697457
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/211.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/212.edn_genbits.2570795700
Short name T900
Test name
Test status
Simulation time 76679492 ps
CPU time 1.9 seconds
Started Aug 27 09:18:10 AM UTC 24
Finished Aug 27 09:18:13 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570795700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2570795700
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/212.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/213.edn_genbits.2602655313
Short name T902
Test name
Test status
Simulation time 46134080 ps
CPU time 2.41 seconds
Started Aug 27 09:18:10 AM UTC 24
Finished Aug 27 09:18:14 AM UTC 24
Peak memory 231480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602655313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 213.edn_genbits.2602655313
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/213.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/214.edn_genbits.2987354912
Short name T901
Test name
Test status
Simulation time 140485527 ps
CPU time 2.07 seconds
Started Aug 27 09:18:10 AM UTC 24
Finished Aug 27 09:18:14 AM UTC 24
Peak memory 231636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987354912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 214.edn_genbits.2987354912
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/214.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/215.edn_genbits.1732357494
Short name T899
Test name
Test status
Simulation time 37144619 ps
CPU time 1.77 seconds
Started Aug 27 09:18:10 AM UTC 24
Finished Aug 27 09:18:13 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732357494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 215.edn_genbits.1732357494
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/215.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/216.edn_genbits.187246235
Short name T898
Test name
Test status
Simulation time 45537996 ps
CPU time 1.53 seconds
Started Aug 27 09:18:10 AM UTC 24
Finished Aug 27 09:18:13 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187246235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 216.edn_genbits.187246235
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/216.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/217.edn_genbits.2458301427
Short name T906
Test name
Test status
Simulation time 48083614 ps
CPU time 1.75 seconds
Started Aug 27 09:18:12 AM UTC 24
Finished Aug 27 09:18:15 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458301427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 217.edn_genbits.2458301427
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/217.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/218.edn_genbits.3556889108
Short name T905
Test name
Test status
Simulation time 28458701 ps
CPU time 1.71 seconds
Started Aug 27 09:18:12 AM UTC 24
Finished Aug 27 09:18:15 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556889108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 218.edn_genbits.3556889108
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/218.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/219.edn_genbits.3839231776
Short name T904
Test name
Test status
Simulation time 45463799 ps
CPU time 1.54 seconds
Started Aug 27 09:18:12 AM UTC 24
Finished Aug 27 09:18:15 AM UTC 24
Peak memory 230380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839231776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 219.edn_genbits.3839231776
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/219.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/22.edn_alert_test.400110425
Short name T431
Test name
Test status
Simulation time 83192031 ps
CPU time 1.35 seconds
Started Aug 27 09:13:01 AM UTC 24
Finished Aug 27 09:13:04 AM UTC 24
Peak memory 215864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400110425 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.400110425
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/22.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/22.edn_disable.2667924720
Short name T430
Test name
Test status
Simulation time 27756520 ps
CPU time 1.2 seconds
Started Aug 27 09:13:01 AM UTC 24
Finished Aug 27 09:13:04 AM UTC 24
Peak memory 216132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667924720 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2667924720
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/22.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/22.edn_disable_auto_req_mode.4018292099
Short name T432
Test name
Test status
Simulation time 396320308 ps
CPU time 1.84 seconds
Started Aug 27 09:13:01 AM UTC 24
Finished Aug 27 09:13:04 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018292099 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable_auto_req_mode.4018292099
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/22.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/22.edn_err.1402236751
Short name T150
Test name
Test status
Simulation time 55950741 ps
CPU time 1.34 seconds
Started Aug 27 09:13:00 AM UTC 24
Finished Aug 27 09:13:03 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402236751 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 22.edn_err.1402236751
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/22.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/22.edn_genbits.712757905
Short name T428
Test name
Test status
Simulation time 61151265 ps
CPU time 1.57 seconds
Started Aug 27 09:12:58 AM UTC 24
Finished Aug 27 09:13:01 AM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712757905 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.edn_genbits.712757905
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/22.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/22.edn_intr.2710104850
Short name T429
Test name
Test status
Simulation time 28239872 ps
CPU time 1.21 seconds
Started Aug 27 09:13:00 AM UTC 24
Finished Aug 27 09:13:02 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710104850 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 22.edn_intr.2710104850
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/22.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/22.edn_smoke.3583369533
Short name T426
Test name
Test status
Simulation time 18027031 ps
CPU time 1.27 seconds
Started Aug 27 09:12:57 AM UTC 24
Finished Aug 27 09:13:00 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583369533 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 22.edn_smoke.3583369533
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/22.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/22.edn_stress_all.977474706
Short name T434
Test name
Test status
Simulation time 267469001 ps
CPU time 4.72 seconds
Started Aug 27 09:13:00 AM UTC 24
Finished Aug 27 09:13:06 AM UTC 24
Peak memory 231584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977474706 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.977474706
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/22.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/220.edn_genbits.1429621753
Short name T903
Test name
Test status
Simulation time 30904816 ps
CPU time 1.28 seconds
Started Aug 27 09:18:12 AM UTC 24
Finished Aug 27 09:18:15 AM UTC 24
Peak memory 228332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429621753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 220.edn_genbits.1429621753
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/220.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/221.edn_genbits.1708490587
Short name T907
Test name
Test status
Simulation time 37130929 ps
CPU time 1.82 seconds
Started Aug 27 09:18:12 AM UTC 24
Finished Aug 27 09:18:16 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708490587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1708490587
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/221.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/222.edn_genbits.472464758
Short name T914
Test name
Test status
Simulation time 203813596 ps
CPU time 3.92 seconds
Started Aug 27 09:18:12 AM UTC 24
Finished Aug 27 09:18:18 AM UTC 24
Peak memory 231508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472464758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 222.edn_genbits.472464758
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/222.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/223.edn_genbits.2177143619
Short name T908
Test name
Test status
Simulation time 87037810 ps
CPU time 1.61 seconds
Started Aug 27 09:18:13 AM UTC 24
Finished Aug 27 09:18:16 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177143619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2177143619
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/223.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/224.edn_genbits.1959940638
Short name T910
Test name
Test status
Simulation time 45912772 ps
CPU time 1.84 seconds
Started Aug 27 09:18:14 AM UTC 24
Finished Aug 27 09:18:16 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959940638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 224.edn_genbits.1959940638
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/224.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/225.edn_genbits.1195025842
Short name T909
Test name
Test status
Simulation time 36534679 ps
CPU time 1.71 seconds
Started Aug 27 09:18:14 AM UTC 24
Finished Aug 27 09:18:16 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195025842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 225.edn_genbits.1195025842
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/225.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/226.edn_genbits.129233942
Short name T337
Test name
Test status
Simulation time 45259976 ps
CPU time 1.25 seconds
Started Aug 27 09:18:14 AM UTC 24
Finished Aug 27 09:18:16 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129233942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 226.edn_genbits.129233942
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/226.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/227.edn_genbits.2879786630
Short name T911
Test name
Test status
Simulation time 42362829 ps
CPU time 2.16 seconds
Started Aug 27 09:18:14 AM UTC 24
Finished Aug 27 09:18:17 AM UTC 24
Peak memory 229580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879786630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 227.edn_genbits.2879786630
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/227.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/228.edn_genbits.2730953047
Short name T894
Test name
Test status
Simulation time 80093355 ps
CPU time 2.62 seconds
Started Aug 27 09:18:15 AM UTC 24
Finished Aug 27 09:18:18 AM UTC 24
Peak memory 229512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730953047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2730953047
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/228.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/229.edn_genbits.3159491004
Short name T912
Test name
Test status
Simulation time 106125303 ps
CPU time 1.56 seconds
Started Aug 27 09:18:15 AM UTC 24
Finished Aug 27 09:18:17 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159491004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3159491004
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/229.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/23.edn_alert.2342159280
Short name T437
Test name
Test status
Simulation time 25815189 ps
CPU time 1.52 seconds
Started Aug 27 09:13:05 AM UTC 24
Finished Aug 27 09:13:07 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342159280 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 23.edn_alert.2342159280
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/23.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/23.edn_alert_test.4089792843
Short name T439
Test name
Test status
Simulation time 141200015 ps
CPU time 1.26 seconds
Started Aug 27 09:13:06 AM UTC 24
Finished Aug 27 09:13:08 AM UTC 24
Peak memory 216912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089792843 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.4089792843
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/23.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/23.edn_disable.3837142753
Short name T435
Test name
Test status
Simulation time 35624163 ps
CPU time 1.09 seconds
Started Aug 27 09:13:05 AM UTC 24
Finished Aug 27 09:13:07 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837142753 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3837142753
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/23.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/23.edn_disable_auto_req_mode.2257179630
Short name T81
Test name
Test status
Simulation time 20361106 ps
CPU time 1.34 seconds
Started Aug 27 09:13:06 AM UTC 24
Finished Aug 27 09:13:08 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257179630 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable_auto_req_mode.2257179630
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/23.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/23.edn_err.619993357
Short name T436
Test name
Test status
Simulation time 18309038 ps
CPU time 1.36 seconds
Started Aug 27 09:13:05 AM UTC 24
Finished Aug 27 09:13:07 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619993357 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 23.edn_err.619993357
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/23.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/23.edn_genbits.3148542361
Short name T55
Test name
Test status
Simulation time 95696135 ps
CPU time 1.67 seconds
Started Aug 27 09:13:03 AM UTC 24
Finished Aug 27 09:13:06 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148542361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3148542361
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/23.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/23.edn_intr.2921696603
Short name T47
Test name
Test status
Simulation time 41006263 ps
CPU time 1.33 seconds
Started Aug 27 09:13:04 AM UTC 24
Finished Aug 27 09:13:06 AM UTC 24
Peak memory 237820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921696603 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 23.edn_intr.2921696603
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/23.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/23.edn_smoke.2638255319
Short name T433
Test name
Test status
Simulation time 40212122 ps
CPU time 1.29 seconds
Started Aug 27 09:13:02 AM UTC 24
Finished Aug 27 09:13:05 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638255319 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 23.edn_smoke.2638255319
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/23.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/23.edn_stress_all.3535809955
Short name T438
Test name
Test status
Simulation time 104540751 ps
CPU time 3.7 seconds
Started Aug 27 09:13:04 AM UTC 24
Finished Aug 27 09:13:08 AM UTC 24
Peak memory 229516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535809955 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3535809955
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/23.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/23.edn_stress_all_with_rand_reset.641267196
Short name T524
Test name
Test status
Simulation time 7219232654 ps
CPU time 91.38 seconds
Started Aug 27 09:13:04 AM UTC 24
Finished Aug 27 09:14:37 AM UTC 24
Peak memory 233976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=641267196 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_
with_rand_reset.641267196
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/23.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/230.edn_genbits.2968758029
Short name T833
Test name
Test status
Simulation time 76937782 ps
CPU time 2.07 seconds
Started Aug 27 09:18:15 AM UTC 24
Finished Aug 27 09:18:18 AM UTC 24
Peak memory 231488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968758029 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2968758029
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/230.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/231.edn_genbits.2326076281
Short name T913
Test name
Test status
Simulation time 45091205 ps
CPU time 1.59 seconds
Started Aug 27 09:18:15 AM UTC 24
Finished Aug 27 09:18:18 AM UTC 24
Peak memory 228556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326076281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 231.edn_genbits.2326076281
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/231.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/232.edn_genbits.3225789276
Short name T916
Test name
Test status
Simulation time 92119452 ps
CPU time 1.49 seconds
Started Aug 27 09:18:16 AM UTC 24
Finished Aug 27 09:18:19 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225789276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 232.edn_genbits.3225789276
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/232.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/233.edn_genbits.3229270713
Short name T915
Test name
Test status
Simulation time 56345775 ps
CPU time 1.21 seconds
Started Aug 27 09:18:16 AM UTC 24
Finished Aug 27 09:18:18 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229270713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3229270713
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/233.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/234.edn_genbits.3215711458
Short name T917
Test name
Test status
Simulation time 73879867 ps
CPU time 1.52 seconds
Started Aug 27 09:18:16 AM UTC 24
Finished Aug 27 09:18:19 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215711458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 234.edn_genbits.3215711458
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/234.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/235.edn_genbits.112706878
Short name T919
Test name
Test status
Simulation time 76512261 ps
CPU time 1.7 seconds
Started Aug 27 09:18:16 AM UTC 24
Finished Aug 27 09:18:19 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112706878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 235.edn_genbits.112706878
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/235.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/236.edn_genbits.843869331
Short name T918
Test name
Test status
Simulation time 30658530 ps
CPU time 1.67 seconds
Started Aug 27 09:18:16 AM UTC 24
Finished Aug 27 09:18:19 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843869331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 236.edn_genbits.843869331
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/236.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/237.edn_genbits.1992211461
Short name T347
Test name
Test status
Simulation time 41051060 ps
CPU time 1.61 seconds
Started Aug 27 09:18:17 AM UTC 24
Finished Aug 27 09:18:20 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992211461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1992211461
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/237.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/238.edn_genbits.819674099
Short name T921
Test name
Test status
Simulation time 42722518 ps
CPU time 1.51 seconds
Started Aug 27 09:18:17 AM UTC 24
Finished Aug 27 09:18:20 AM UTC 24
Peak memory 228640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819674099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 238.edn_genbits.819674099
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/238.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/239.edn_genbits.4291875872
Short name T920
Test name
Test status
Simulation time 74161157 ps
CPU time 1.26 seconds
Started Aug 27 09:18:17 AM UTC 24
Finished Aug 27 09:18:20 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291875872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 239.edn_genbits.4291875872
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/239.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/24.edn_alert.3330048898
Short name T443
Test name
Test status
Simulation time 40076123 ps
CPU time 1.54 seconds
Started Aug 27 09:13:09 AM UTC 24
Finished Aug 27 09:13:11 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330048898 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 24.edn_alert.3330048898
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/24.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/24.edn_alert_test.1884774930
Short name T446
Test name
Test status
Simulation time 12757848 ps
CPU time 1.32 seconds
Started Aug 27 09:13:11 AM UTC 24
Finished Aug 27 09:13:13 AM UTC 24
Peak memory 217108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884774930 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.1884774930
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/24.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/24.edn_disable.605854626
Short name T82
Test name
Test status
Simulation time 12757315 ps
CPU time 1.4 seconds
Started Aug 27 09:13:10 AM UTC 24
Finished Aug 27 09:13:12 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605854626 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.605854626
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/24.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/24.edn_disable_auto_req_mode.1735131221
Short name T130
Test name
Test status
Simulation time 39615682 ps
CPU time 1.67 seconds
Started Aug 27 09:13:10 AM UTC 24
Finished Aug 27 09:13:13 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735131221 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable_auto_req_mode.1735131221
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/24.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/24.edn_err.739161481
Short name T444
Test name
Test status
Simulation time 29307710 ps
CPU time 1.56 seconds
Started Aug 27 09:13:10 AM UTC 24
Finished Aug 27 09:13:12 AM UTC 24
Peak memory 230772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739161481 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 24.edn_err.739161481
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/24.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/24.edn_genbits.1498019120
Short name T77
Test name
Test status
Simulation time 64565917 ps
CPU time 1.91 seconds
Started Aug 27 09:13:07 AM UTC 24
Finished Aug 27 09:13:10 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498019120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1498019120
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/24.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/24.edn_intr.901085588
Short name T442
Test name
Test status
Simulation time 56741375 ps
CPU time 1 seconds
Started Aug 27 09:13:08 AM UTC 24
Finished Aug 27 09:13:11 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901085588 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 24.edn_intr.901085588
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/24.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/24.edn_smoke.1206257137
Short name T440
Test name
Test status
Simulation time 24467063 ps
CPU time 1.45 seconds
Started Aug 27 09:13:07 AM UTC 24
Finished Aug 27 09:13:10 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206257137 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 24.edn_smoke.1206257137
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/24.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/24.edn_stress_all.2074510901
Short name T441
Test name
Test status
Simulation time 60893205 ps
CPU time 1.77 seconds
Started Aug 27 09:13:07 AM UTC 24
Finished Aug 27 09:13:10 AM UTC 24
Peak memory 226692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074510901 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2074510901
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/24.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/24.edn_stress_all_with_rand_reset.3462980371
Short name T238
Test name
Test status
Simulation time 2372676228 ps
CPU time 58.03 seconds
Started Aug 27 09:13:08 AM UTC 24
Finished Aug 27 09:14:08 AM UTC 24
Peak memory 231912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3462980371 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all
_with_rand_reset.3462980371
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/24.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/240.edn_genbits.670664719
Short name T923
Test name
Test status
Simulation time 45266129 ps
CPU time 2.13 seconds
Started Aug 27 09:18:17 AM UTC 24
Finished Aug 27 09:18:21 AM UTC 24
Peak memory 229660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670664719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 240.edn_genbits.670664719
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/240.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/241.edn_genbits.722414706
Short name T922
Test name
Test status
Simulation time 61717926 ps
CPU time 1.46 seconds
Started Aug 27 09:18:17 AM UTC 24
Finished Aug 27 09:18:20 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722414706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 241.edn_genbits.722414706
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/241.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/242.edn_genbits.3292590034
Short name T343
Test name
Test status
Simulation time 48013348 ps
CPU time 1.62 seconds
Started Aug 27 09:18:19 AM UTC 24
Finished Aug 27 09:18:21 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292590034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 242.edn_genbits.3292590034
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/242.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/243.edn_genbits.3221556740
Short name T925
Test name
Test status
Simulation time 103385543 ps
CPU time 1.79 seconds
Started Aug 27 09:18:19 AM UTC 24
Finished Aug 27 09:18:21 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221556740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3221556740
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/243.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/244.edn_genbits.2540249194
Short name T932
Test name
Test status
Simulation time 339009369 ps
CPU time 3.62 seconds
Started Aug 27 09:18:19 AM UTC 24
Finished Aug 27 09:18:23 AM UTC 24
Peak memory 229328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540249194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 244.edn_genbits.2540249194
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/244.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/245.edn_genbits.988795972
Short name T924
Test name
Test status
Simulation time 39351415 ps
CPU time 1.49 seconds
Started Aug 27 09:18:19 AM UTC 24
Finished Aug 27 09:18:21 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988795972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 245.edn_genbits.988795972
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/245.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/246.edn_genbits.2270637018
Short name T928
Test name
Test status
Simulation time 112001011 ps
CPU time 1.61 seconds
Started Aug 27 09:18:20 AM UTC 24
Finished Aug 27 09:18:22 AM UTC 24
Peak memory 228328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270637018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 246.edn_genbits.2270637018
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/246.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/247.edn_genbits.3477447478
Short name T926
Test name
Test status
Simulation time 47275336 ps
CPU time 1.08 seconds
Started Aug 27 09:18:20 AM UTC 24
Finished Aug 27 09:18:22 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477447478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 247.edn_genbits.3477447478
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/247.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/248.edn_genbits.29744810
Short name T927
Test name
Test status
Simulation time 96898143 ps
CPU time 1.38 seconds
Started Aug 27 09:18:20 AM UTC 24
Finished Aug 27 09:18:22 AM UTC 24
Peak memory 228352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29744810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 248.edn_genbits.29744810
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/248.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/249.edn_genbits.2818153080
Short name T929
Test name
Test status
Simulation time 34337580 ps
CPU time 1.34 seconds
Started Aug 27 09:18:20 AM UTC 24
Finished Aug 27 09:18:22 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818153080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 249.edn_genbits.2818153080
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/249.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/25.edn_alert.2142591451
Short name T448
Test name
Test status
Simulation time 47624941 ps
CPU time 1.68 seconds
Started Aug 27 09:13:13 AM UTC 24
Finished Aug 27 09:13:16 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142591451 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 25.edn_alert.2142591451
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/25.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/25.edn_alert_test.4168757018
Short name T449
Test name
Test status
Simulation time 33163416 ps
CPU time 1.17 seconds
Started Aug 27 09:13:16 AM UTC 24
Finished Aug 27 09:13:18 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168757018 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.4168757018
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/25.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/25.edn_genbits.3359210380
Short name T364
Test name
Test status
Simulation time 81958398 ps
CPU time 2.59 seconds
Started Aug 27 09:13:11 AM UTC 24
Finished Aug 27 09:13:15 AM UTC 24
Peak memory 231756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359210380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3359210380
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/25.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/25.edn_intr.309141419
Short name T447
Test name
Test status
Simulation time 27310901 ps
CPU time 1.4 seconds
Started Aug 27 09:13:13 AM UTC 24
Finished Aug 27 09:13:16 AM UTC 24
Peak memory 237820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309141419 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 25.edn_intr.309141419
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/25.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/25.edn_smoke.2644097660
Short name T445
Test name
Test status
Simulation time 26534536 ps
CPU time 1.33 seconds
Started Aug 27 09:13:11 AM UTC 24
Finished Aug 27 09:13:13 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644097660 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 25.edn_smoke.2644097660
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/25.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/25.edn_stress_all.3022184386
Short name T332
Test name
Test status
Simulation time 345729797 ps
CPU time 5.58 seconds
Started Aug 27 09:13:12 AM UTC 24
Finished Aug 27 09:13:19 AM UTC 24
Peak memory 229516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022184386 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.3022184386
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/25.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/25.edn_stress_all_with_rand_reset.1485104143
Short name T486
Test name
Test status
Simulation time 2681932480 ps
CPU time 41.6 seconds
Started Aug 27 09:13:12 AM UTC 24
Finished Aug 27 09:13:55 AM UTC 24
Peak memory 230140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1485104143 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all
_with_rand_reset.1485104143
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/25.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/250.edn_genbits.2203385638
Short name T930
Test name
Test status
Simulation time 75622667 ps
CPU time 1.58 seconds
Started Aug 27 09:18:20 AM UTC 24
Finished Aug 27 09:18:23 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203385638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 250.edn_genbits.2203385638
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/250.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/251.edn_genbits.300735612
Short name T931
Test name
Test status
Simulation time 130069772 ps
CPU time 1.82 seconds
Started Aug 27 09:18:20 AM UTC 24
Finished Aug 27 09:18:23 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300735612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 251.edn_genbits.300735612
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/251.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/252.edn_genbits.528970907
Short name T933
Test name
Test status
Simulation time 57857723 ps
CPU time 1.19 seconds
Started Aug 27 09:18:21 AM UTC 24
Finished Aug 27 09:18:24 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528970907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 252.edn_genbits.528970907
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/252.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/253.edn_genbits.772433032
Short name T941
Test name
Test status
Simulation time 219845117 ps
CPU time 4.02 seconds
Started Aug 27 09:18:21 AM UTC 24
Finished Aug 27 09:18:26 AM UTC 24
Peak memory 231500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772433032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 253.edn_genbits.772433032
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/253.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/254.edn_genbits.903913880
Short name T936
Test name
Test status
Simulation time 42539446 ps
CPU time 2.15 seconds
Started Aug 27 09:18:21 AM UTC 24
Finished Aug 27 09:18:25 AM UTC 24
Peak memory 229448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903913880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 254.edn_genbits.903913880
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/254.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/255.edn_genbits.2820772385
Short name T935
Test name
Test status
Simulation time 43264948 ps
CPU time 2.26 seconds
Started Aug 27 09:18:21 AM UTC 24
Finished Aug 27 09:18:25 AM UTC 24
Peak memory 229428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820772385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2820772385
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/255.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/256.edn_genbits.294810585
Short name T934
Test name
Test status
Simulation time 83954887 ps
CPU time 1.38 seconds
Started Aug 27 09:18:21 AM UTC 24
Finished Aug 27 09:18:24 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294810585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 256.edn_genbits.294810585
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/256.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/257.edn_genbits.1663272879
Short name T937
Test name
Test status
Simulation time 74470189 ps
CPU time 1.8 seconds
Started Aug 27 09:18:22 AM UTC 24
Finished Aug 27 09:18:26 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663272879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1663272879
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/257.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/258.edn_genbits.2238381239
Short name T938
Test name
Test status
Simulation time 220342305 ps
CPU time 1.99 seconds
Started Aug 27 09:18:22 AM UTC 24
Finished Aug 27 09:18:26 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238381239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 258.edn_genbits.2238381239
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/258.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/259.edn_genbits.1206627347
Short name T943
Test name
Test status
Simulation time 231610753 ps
CPU time 3.13 seconds
Started Aug 27 09:18:22 AM UTC 24
Finished Aug 27 09:18:27 AM UTC 24
Peak memory 231508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206627347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1206627347
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/259.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/26.edn_alert.775576121
Short name T326
Test name
Test status
Simulation time 70040038 ps
CPU time 1.37 seconds
Started Aug 27 09:13:18 AM UTC 24
Finished Aug 27 09:13:21 AM UTC 24
Peak memory 228232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775576121 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 26.edn_alert.775576121
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/26.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/26.edn_alert_test.3968262432
Short name T452
Test name
Test status
Simulation time 17530631 ps
CPU time 1.2 seconds
Started Aug 27 09:13:19 AM UTC 24
Finished Aug 27 09:13:22 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968262432 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.3968262432
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/26.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/26.edn_disable.2103386993
Short name T211
Test name
Test status
Simulation time 11756279 ps
CPU time 1.2 seconds
Started Aug 27 09:13:19 AM UTC 24
Finished Aug 27 09:13:22 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103386993 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2103386993
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/26.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/26.edn_disable_auto_req_mode.2044320838
Short name T453
Test name
Test status
Simulation time 30173459 ps
CPU time 1.41 seconds
Started Aug 27 09:13:19 AM UTC 24
Finished Aug 27 09:13:22 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044320838 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable_auto_req_mode.2044320838
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/26.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/26.edn_err.2527155232
Short name T177
Test name
Test status
Simulation time 70316172 ps
CPU time 1.48 seconds
Started Aug 27 09:13:19 AM UTC 24
Finished Aug 27 09:13:22 AM UTC 24
Peak memory 242188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527155232 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 26.edn_err.2527155232
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/26.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/26.edn_genbits.977683260
Short name T309
Test name
Test status
Simulation time 148765552 ps
CPU time 2.87 seconds
Started Aug 27 09:13:17 AM UTC 24
Finished Aug 27 09:13:21 AM UTC 24
Peak memory 229768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977683260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.edn_genbits.977683260
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/26.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/26.edn_smoke.1419737347
Short name T450
Test name
Test status
Simulation time 31272258 ps
CPU time 1.23 seconds
Started Aug 27 09:13:16 AM UTC 24
Finished Aug 27 09:13:18 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419737347 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 26.edn_smoke.1419737347
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/26.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/26.edn_stress_all.3698129262
Short name T252
Test name
Test status
Simulation time 90094309 ps
CPU time 2.38 seconds
Started Aug 27 09:13:17 AM UTC 24
Finished Aug 27 09:13:20 AM UTC 24
Peak memory 227484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698129262 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3698129262
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/26.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/260.edn_genbits.186965626
Short name T947
Test name
Test status
Simulation time 174994237 ps
CPU time 2.78 seconds
Started Aug 27 09:18:24 AM UTC 24
Finished Aug 27 09:18:27 AM UTC 24
Peak memory 231572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186965626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 260.edn_genbits.186965626
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/260.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/261.edn_genbits.1336850337
Short name T939
Test name
Test status
Simulation time 43033074 ps
CPU time 1.38 seconds
Started Aug 27 09:18:24 AM UTC 24
Finished Aug 27 09:18:26 AM UTC 24
Peak memory 230604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336850337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1336850337
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/261.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/262.edn_genbits.3683577941
Short name T940
Test name
Test status
Simulation time 165085893 ps
CPU time 1.48 seconds
Started Aug 27 09:18:24 AM UTC 24
Finished Aug 27 09:18:26 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683577941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3683577941
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/262.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/263.edn_genbits.145541917
Short name T944
Test name
Test status
Simulation time 41637001 ps
CPU time 2.12 seconds
Started Aug 27 09:18:24 AM UTC 24
Finished Aug 27 09:18:27 AM UTC 24
Peak memory 231580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145541917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 263.edn_genbits.145541917
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/263.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/264.edn_genbits.201734362
Short name T942
Test name
Test status
Simulation time 79450573 ps
CPU time 1.57 seconds
Started Aug 27 09:18:24 AM UTC 24
Finished Aug 27 09:18:26 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201734362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 264.edn_genbits.201734362
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/264.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/265.edn_genbits.4025245607
Short name T945
Test name
Test status
Simulation time 40543359 ps
CPU time 2.33 seconds
Started Aug 27 09:18:24 AM UTC 24
Finished Aug 27 09:18:27 AM UTC 24
Peak memory 229708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025245607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 265.edn_genbits.4025245607
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/265.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/266.edn_genbits.2652910074
Short name T946
Test name
Test status
Simulation time 51826715 ps
CPU time 1.25 seconds
Started Aug 27 09:18:25 AM UTC 24
Finished Aug 27 09:18:27 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652910074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2652910074
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/266.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/267.edn_genbits.4146089739
Short name T948
Test name
Test status
Simulation time 42622900 ps
CPU time 1.75 seconds
Started Aug 27 09:18:25 AM UTC 24
Finished Aug 27 09:18:28 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146089739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 267.edn_genbits.4146089739
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/267.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/268.edn_genbits.3154197343
Short name T950
Test name
Test status
Simulation time 40270993 ps
CPU time 2.19 seconds
Started Aug 27 09:18:25 AM UTC 24
Finished Aug 27 09:18:28 AM UTC 24
Peak memory 229660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154197343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 268.edn_genbits.3154197343
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/268.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/269.edn_genbits.3660782208
Short name T952
Test name
Test status
Simulation time 23206411 ps
CPU time 1.81 seconds
Started Aug 27 09:18:26 AM UTC 24
Finished Aug 27 09:18:29 AM UTC 24
Peak memory 228280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660782208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3660782208
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/269.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/27.edn_alert.2166142594
Short name T160
Test name
Test status
Simulation time 183130476 ps
CPU time 1.86 seconds
Started Aug 27 09:13:23 AM UTC 24
Finished Aug 27 09:13:26 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166142594 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 27.edn_alert.2166142594
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/27.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/27.edn_alert_test.1681880704
Short name T456
Test name
Test status
Simulation time 18256894 ps
CPU time 1.25 seconds
Started Aug 27 09:13:25 AM UTC 24
Finished Aug 27 09:13:27 AM UTC 24
Peak memory 216244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681880704 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1681880704
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/27.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/27.edn_disable.1756508676
Short name T194
Test name
Test status
Simulation time 13578406 ps
CPU time 1.39 seconds
Started Aug 27 09:13:23 AM UTC 24
Finished Aug 27 09:13:25 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756508676 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.1756508676
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/27.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/27.edn_disable_auto_req_mode.396543897
Short name T455
Test name
Test status
Simulation time 113790644 ps
CPU time 1.53 seconds
Started Aug 27 09:13:24 AM UTC 24
Finished Aug 27 09:13:27 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396543897 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable_auto_req_mode.396543897
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/27.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/27.edn_err.2808752963
Short name T178
Test name
Test status
Simulation time 58771766 ps
CPU time 1.42 seconds
Started Aug 27 09:13:23 AM UTC 24
Finished Aug 27 09:13:25 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808752963 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 27.edn_err.2808752963
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/27.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/27.edn_intr.1935486599
Short name T33
Test name
Test status
Simulation time 24662370 ps
CPU time 1.41 seconds
Started Aug 27 09:13:23 AM UTC 24
Finished Aug 27 09:13:25 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935486599 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 27.edn_intr.1935486599
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/27.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/27.edn_smoke.1145361417
Short name T454
Test name
Test status
Simulation time 18537456 ps
CPU time 1.27 seconds
Started Aug 27 09:13:22 AM UTC 24
Finished Aug 27 09:13:24 AM UTC 24
Peak memory 216016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145361417 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 27.edn_smoke.1145361417
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/27.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/27.edn_stress_all.2534704167
Short name T254
Test name
Test status
Simulation time 923267385 ps
CPU time 7.63 seconds
Started Aug 27 09:13:22 AM UTC 24
Finished Aug 27 09:13:30 AM UTC 24
Peak memory 227496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534704167 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2534704167
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/27.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/270.edn_genbits.2683625518
Short name T951
Test name
Test status
Simulation time 35935883 ps
CPU time 1.65 seconds
Started Aug 27 09:18:26 AM UTC 24
Finished Aug 27 09:18:29 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683625518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2683625518
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/270.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/271.edn_genbits.4106850697
Short name T355
Test name
Test status
Simulation time 47877374 ps
CPU time 2.26 seconds
Started Aug 27 09:18:26 AM UTC 24
Finished Aug 27 09:18:30 AM UTC 24
Peak memory 231556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106850697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 271.edn_genbits.4106850697
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/271.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/272.edn_genbits.3205613949
Short name T949
Test name
Test status
Simulation time 40209262 ps
CPU time 1.03 seconds
Started Aug 27 09:18:26 AM UTC 24
Finished Aug 27 09:18:28 AM UTC 24
Peak memory 228320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205613949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 272.edn_genbits.3205613949
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/272.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/273.edn_genbits.2150230759
Short name T958
Test name
Test status
Simulation time 44154727 ps
CPU time 2.53 seconds
Started Aug 27 09:18:27 AM UTC 24
Finished Aug 27 09:18:31 AM UTC 24
Peak memory 229724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150230759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2150230759
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/273.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/274.edn_genbits.1931662402
Short name T340
Test name
Test status
Simulation time 90461990 ps
CPU time 2.95 seconds
Started Aug 27 09:18:27 AM UTC 24
Finished Aug 27 09:18:31 AM UTC 24
Peak memory 231492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931662402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 274.edn_genbits.1931662402
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/274.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/275.edn_genbits.2085901432
Short name T955
Test name
Test status
Simulation time 45327295 ps
CPU time 1.84 seconds
Started Aug 27 09:18:27 AM UTC 24
Finished Aug 27 09:18:30 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085901432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2085901432
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/275.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/276.edn_genbits.2907574401
Short name T954
Test name
Test status
Simulation time 35684007 ps
CPU time 1.63 seconds
Started Aug 27 09:18:27 AM UTC 24
Finished Aug 27 09:18:30 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907574401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 276.edn_genbits.2907574401
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/276.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/277.edn_genbits.1770134429
Short name T953
Test name
Test status
Simulation time 98217422 ps
CPU time 1.58 seconds
Started Aug 27 09:18:27 AM UTC 24
Finished Aug 27 09:18:30 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770134429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 277.edn_genbits.1770134429
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/277.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/278.edn_genbits.906362397
Short name T956
Test name
Test status
Simulation time 29853150 ps
CPU time 1.88 seconds
Started Aug 27 09:18:28 AM UTC 24
Finished Aug 27 09:18:31 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906362397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 278.edn_genbits.906362397
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/278.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/279.edn_genbits.2342884313
Short name T967
Test name
Test status
Simulation time 97161242 ps
CPU time 4.29 seconds
Started Aug 27 09:18:29 AM UTC 24
Finished Aug 27 09:18:34 AM UTC 24
Peak memory 231644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342884313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2342884313
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/279.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/28.edn_alert.2892070585
Short name T173
Test name
Test status
Simulation time 29633525 ps
CPU time 1.79 seconds
Started Aug 27 09:13:27 AM UTC 24
Finished Aug 27 09:13:30 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892070585 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 28.edn_alert.2892070585
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/28.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/28.edn_alert_test.3509039101
Short name T461
Test name
Test status
Simulation time 16636619 ps
CPU time 1.25 seconds
Started Aug 27 09:13:30 AM UTC 24
Finished Aug 27 09:13:32 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509039101 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3509039101
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/28.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/28.edn_disable.4171396706
Short name T460
Test name
Test status
Simulation time 11836802 ps
CPU time 1.22 seconds
Started Aug 27 09:13:30 AM UTC 24
Finished Aug 27 09:13:32 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171396706 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.4171396706
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/28.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/28.edn_err.1733623321
Short name T459
Test name
Test status
Simulation time 34559178 ps
CPU time 1.42 seconds
Started Aug 27 09:13:28 AM UTC 24
Finished Aug 27 09:13:31 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733623321 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 28.edn_err.1733623321
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/28.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/28.edn_genbits.1958211972
Short name T13
Test name
Test status
Simulation time 36119344 ps
CPU time 1.83 seconds
Started Aug 27 09:13:26 AM UTC 24
Finished Aug 27 09:13:29 AM UTC 24
Peak memory 230596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958211972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_genbits.1958211972
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/28.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/28.edn_intr.4042257097
Short name T457
Test name
Test status
Simulation time 27359496 ps
CPU time 1.22 seconds
Started Aug 27 09:13:26 AM UTC 24
Finished Aug 27 09:13:29 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042257097 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 28.edn_intr.4042257097
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/28.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/28.edn_smoke.1614611572
Short name T253
Test name
Test status
Simulation time 16444344 ps
CPU time 1.45 seconds
Started Aug 27 09:13:26 AM UTC 24
Finished Aug 27 09:13:29 AM UTC 24
Peak memory 216016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614611572 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 28.edn_smoke.1614611572
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/28.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/28.edn_stress_all.3322647054
Short name T458
Test name
Test status
Simulation time 167901533 ps
CPU time 3.33 seconds
Started Aug 27 09:13:26 AM UTC 24
Finished Aug 27 09:13:31 AM UTC 24
Peak memory 229516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322647054 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3322647054
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/28.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/280.edn_genbits.2192572412
Short name T957
Test name
Test status
Simulation time 56824299 ps
CPU time 1.2 seconds
Started Aug 27 09:18:29 AM UTC 24
Finished Aug 27 09:18:31 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192572412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 280.edn_genbits.2192572412
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/280.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/281.edn_genbits.1009155729
Short name T959
Test name
Test status
Simulation time 45063508 ps
CPU time 1.65 seconds
Started Aug 27 09:18:29 AM UTC 24
Finished Aug 27 09:18:31 AM UTC 24
Peak memory 228288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009155729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1009155729
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/281.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/282.edn_genbits.2677476354
Short name T960
Test name
Test status
Simulation time 348833115 ps
CPU time 1.85 seconds
Started Aug 27 09:18:29 AM UTC 24
Finished Aug 27 09:18:32 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677476354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2677476354
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/282.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/283.edn_genbits.1514801454
Short name T964
Test name
Test status
Simulation time 132825583 ps
CPU time 2.68 seconds
Started Aug 27 09:18:30 AM UTC 24
Finished Aug 27 09:18:33 AM UTC 24
Peak memory 231576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514801454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1514801454
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/283.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/284.edn_genbits.2017518758
Short name T962
Test name
Test status
Simulation time 35025713 ps
CPU time 1.68 seconds
Started Aug 27 09:18:30 AM UTC 24
Finished Aug 27 09:18:33 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017518758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2017518758
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/284.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/285.edn_genbits.2198529719
Short name T963
Test name
Test status
Simulation time 70570116 ps
CPU time 2.54 seconds
Started Aug 27 09:18:30 AM UTC 24
Finished Aug 27 09:18:33 AM UTC 24
Peak memory 229448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198529719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2198529719
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/285.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/286.edn_genbits.3320951973
Short name T961
Test name
Test status
Simulation time 85061794 ps
CPU time 1.61 seconds
Started Aug 27 09:18:30 AM UTC 24
Finished Aug 27 09:18:33 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320951973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3320951973
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/286.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/287.edn_genbits.126934969
Short name T966
Test name
Test status
Simulation time 102733116 ps
CPU time 1.76 seconds
Started Aug 27 09:18:31 AM UTC 24
Finished Aug 27 09:18:34 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126934969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 287.edn_genbits.126934969
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/287.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/288.edn_genbits.3497500925
Short name T968
Test name
Test status
Simulation time 65677085 ps
CPU time 2.02 seconds
Started Aug 27 09:18:31 AM UTC 24
Finished Aug 27 09:18:34 AM UTC 24
Peak memory 229712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497500925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3497500925
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/288.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/289.edn_genbits.3762012752
Short name T965
Test name
Test status
Simulation time 59195488 ps
CPU time 1.44 seconds
Started Aug 27 09:18:31 AM UTC 24
Finished Aug 27 09:18:34 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762012752 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 289.edn_genbits.3762012752
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/289.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/29.edn_alert.1337354337
Short name T464
Test name
Test status
Simulation time 74536546 ps
CPU time 1.6 seconds
Started Aug 27 09:13:33 AM UTC 24
Finished Aug 27 09:13:36 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337354337 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 29.edn_alert.1337354337
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/29.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/29.edn_alert_test.1183798245
Short name T465
Test name
Test status
Simulation time 32173034 ps
CPU time 1.03 seconds
Started Aug 27 09:13:35 AM UTC 24
Finished Aug 27 09:13:37 AM UTC 24
Peak memory 216628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183798245 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1183798245
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/29.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/29.edn_disable_auto_req_mode.1189663319
Short name T466
Test name
Test status
Simulation time 27011521 ps
CPU time 1.43 seconds
Started Aug 27 09:13:35 AM UTC 24
Finished Aug 27 09:13:38 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189663319 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable_auto_req_mode.1189663319
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/29.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/29.edn_err.3688144824
Short name T126
Test name
Test status
Simulation time 49992228 ps
CPU time 1.42 seconds
Started Aug 27 09:13:33 AM UTC 24
Finished Aug 27 09:13:36 AM UTC 24
Peak memory 243736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688144824 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 29.edn_err.3688144824
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/29.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/29.edn_genbits.2719863971
Short name T311
Test name
Test status
Simulation time 76659615 ps
CPU time 1.42 seconds
Started Aug 27 09:13:32 AM UTC 24
Finished Aug 27 09:13:34 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719863971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2719863971
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/29.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/29.edn_intr.666366837
Short name T463
Test name
Test status
Simulation time 23698373 ps
CPU time 1.37 seconds
Started Aug 27 09:13:33 AM UTC 24
Finished Aug 27 09:13:35 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666366837 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 29.edn_intr.666366837
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/29.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/29.edn_smoke.2839317643
Short name T462
Test name
Test status
Simulation time 17784947 ps
CPU time 1.14 seconds
Started Aug 27 09:13:31 AM UTC 24
Finished Aug 27 09:13:33 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839317643 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 29.edn_smoke.2839317643
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/29.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/29.edn_stress_all.2667651292
Short name T469
Test name
Test status
Simulation time 465067771 ps
CPU time 6.48 seconds
Started Aug 27 09:13:32 AM UTC 24
Finished Aug 27 09:13:40 AM UTC 24
Peak memory 227676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667651292 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.2667651292
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/29.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/29.edn_stress_all_with_rand_reset.2693911773
Short name T667
Test name
Test status
Simulation time 7110177483 ps
CPU time 188.99 seconds
Started Aug 27 09:13:32 AM UTC 24
Finished Aug 27 09:16:44 AM UTC 24
Peak memory 230052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2693911773 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all
_with_rand_reset.2693911773
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/29.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/290.edn_genbits.1682031624
Short name T970
Test name
Test status
Simulation time 81496230 ps
CPU time 2.1 seconds
Started Aug 27 09:18:31 AM UTC 24
Finished Aug 27 09:18:34 AM UTC 24
Peak memory 231484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682031624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1682031624
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/290.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/291.edn_genbits.3600334676
Short name T969
Test name
Test status
Simulation time 54955362 ps
CPU time 1.94 seconds
Started Aug 27 09:18:31 AM UTC 24
Finished Aug 27 09:18:34 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600334676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 291.edn_genbits.3600334676
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/291.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/292.edn_genbits.1438299783
Short name T973
Test name
Test status
Simulation time 74920207 ps
CPU time 1.64 seconds
Started Aug 27 09:18:33 AM UTC 24
Finished Aug 27 09:18:35 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438299783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 292.edn_genbits.1438299783
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/292.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/293.edn_genbits.91291546
Short name T976
Test name
Test status
Simulation time 140215255 ps
CPU time 3.72 seconds
Started Aug 27 09:18:33 AM UTC 24
Finished Aug 27 09:18:37 AM UTC 24
Peak memory 231560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91291546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 293.edn_genbits.91291546
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/293.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/294.edn_genbits.4251501648
Short name T350
Test name
Test status
Simulation time 126945439 ps
CPU time 3.05 seconds
Started Aug 27 09:18:33 AM UTC 24
Finished Aug 27 09:18:37 AM UTC 24
Peak memory 231828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251501648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 294.edn_genbits.4251501648
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/294.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/295.edn_genbits.3144112607
Short name T972
Test name
Test status
Simulation time 37177714 ps
CPU time 1.37 seconds
Started Aug 27 09:18:33 AM UTC 24
Finished Aug 27 09:18:35 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144112607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 295.edn_genbits.3144112607
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/295.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/296.edn_genbits.1678914072
Short name T971
Test name
Test status
Simulation time 66954278 ps
CPU time 1.17 seconds
Started Aug 27 09:18:33 AM UTC 24
Finished Aug 27 09:18:35 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678914072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 296.edn_genbits.1678914072
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/296.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/297.edn_genbits.2423528065
Short name T974
Test name
Test status
Simulation time 29185861 ps
CPU time 1.39 seconds
Started Aug 27 09:18:33 AM UTC 24
Finished Aug 27 09:18:35 AM UTC 24
Peak memory 230604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423528065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 297.edn_genbits.2423528065
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/297.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/298.edn_genbits.3091911397
Short name T975
Test name
Test status
Simulation time 28565250 ps
CPU time 1.15 seconds
Started Aug 27 09:18:34 AM UTC 24
Finished Aug 27 09:18:36 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091911397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 298.edn_genbits.3091911397
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/298.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/299.edn_genbits.1240530595
Short name T977
Test name
Test status
Simulation time 49469265 ps
CPU time 2.45 seconds
Started Aug 27 09:18:34 AM UTC 24
Finished Aug 27 09:18:38 AM UTC 24
Peak memory 231576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240530595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1240530595
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/299.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/3.edn_alert.2857888075
Short name T115
Test name
Test status
Simulation time 84429218 ps
CPU time 1.7 seconds
Started Aug 27 09:11:01 AM UTC 24
Finished Aug 27 09:11:04 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857888075 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 3.edn_alert.2857888075
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/3.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/3.edn_alert_test.2887594362
Short name T255
Test name
Test status
Simulation time 38846927 ps
CPU time 1.27 seconds
Started Aug 27 09:11:05 AM UTC 24
Finished Aug 27 09:11:07 AM UTC 24
Peak memory 216244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887594362 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2887594362
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/3.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/3.edn_disable.3148471321
Short name T54
Test name
Test status
Simulation time 36931643 ps
CPU time 1.27 seconds
Started Aug 27 09:11:02 AM UTC 24
Finished Aug 27 09:11:04 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148471321 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.3148471321
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/3.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/3.edn_disable_auto_req_mode.2211713697
Short name T68
Test name
Test status
Simulation time 38751163 ps
CPU time 1.64 seconds
Started Aug 27 09:11:02 AM UTC 24
Finished Aug 27 09:11:04 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211713697 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable_auto_req_mode.2211713697
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/3.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/3.edn_err.4234515438
Short name T69
Test name
Test status
Simulation time 24155188 ps
CPU time 1.23 seconds
Started Aug 27 09:11:02 AM UTC 24
Finished Aug 27 09:11:04 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234515438 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 3.edn_err.4234515438
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/3.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/3.edn_genbits.1451283753
Short name T123
Test name
Test status
Simulation time 91538458 ps
CPU time 1.96 seconds
Started Aug 27 09:10:58 AM UTC 24
Finished Aug 27 09:11:01 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451283753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1451283753
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/3.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/3.edn_intr.1974740168
Short name T59
Test name
Test status
Simulation time 22990809 ps
CPU time 1.55 seconds
Started Aug 27 09:10:59 AM UTC 24
Finished Aug 27 09:11:02 AM UTC 24
Peak memory 237816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974740168 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 3.edn_intr.1974740168
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/3.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/3.edn_regwen.3867923265
Short name T250
Test name
Test status
Simulation time 58160063 ps
CPU time 1.27 seconds
Started Aug 27 09:10:58 AM UTC 24
Finished Aug 27 09:11:00 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867923265 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 3.edn_regwen.3867923265
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/3.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/3.edn_smoke.1792564972
Short name T370
Test name
Test status
Simulation time 40326188 ps
CPU time 1.17 seconds
Started Aug 27 09:10:58 AM UTC 24
Finished Aug 27 09:11:00 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792564972 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 3.edn_smoke.1792564972
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/3.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/3.edn_stress_all.2074931716
Short name T58
Test name
Test status
Simulation time 732386397 ps
CPU time 5.7 seconds
Started Aug 27 09:10:59 AM UTC 24
Finished Aug 27 09:11:06 AM UTC 24
Peak memory 227408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074931716 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2074931716
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/3.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/3.edn_stress_all_with_rand_reset.2769640168
Short name T226
Test name
Test status
Simulation time 5573277095 ps
CPU time 80.32 seconds
Started Aug 27 09:10:59 AM UTC 24
Finished Aug 27 09:12:21 AM UTC 24
Peak memory 234104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2769640168 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_
with_rand_reset.2769640168
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/3.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/30.edn_alert_test.771905021
Short name T475
Test name
Test status
Simulation time 12802643 ps
CPU time 1.19 seconds
Started Aug 27 09:13:41 AM UTC 24
Finished Aug 27 09:13:43 AM UTC 24
Peak memory 216684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771905021 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.771905021
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/30.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/30.edn_disable.1138794389
Short name T472
Test name
Test status
Simulation time 23835741 ps
CPU time 1.15 seconds
Started Aug 27 09:13:40 AM UTC 24
Finished Aug 27 09:13:42 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138794389 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1138794389
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/30.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/30.edn_disable_auto_req_mode.1341278133
Short name T474
Test name
Test status
Simulation time 45023914 ps
CPU time 1.42 seconds
Started Aug 27 09:13:40 AM UTC 24
Finished Aug 27 09:13:42 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341278133 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable_auto_req_mode.1341278133
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/30.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/30.edn_err.1343056448
Short name T473
Test name
Test status
Simulation time 19198000 ps
CPU time 1.55 seconds
Started Aug 27 09:13:40 AM UTC 24
Finished Aug 27 09:13:42 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343056448 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 30.edn_err.1343056448
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/30.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/30.edn_genbits.2182574903
Short name T468
Test name
Test status
Simulation time 59019570 ps
CPU time 1.85 seconds
Started Aug 27 09:13:37 AM UTC 24
Finished Aug 27 09:13:39 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182574903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2182574903
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/30.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/30.edn_intr.1871841559
Short name T471
Test name
Test status
Simulation time 28796212 ps
CPU time 1.24 seconds
Started Aug 27 09:13:39 AM UTC 24
Finished Aug 27 09:13:41 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871841559 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 30.edn_intr.1871841559
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/30.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/30.edn_smoke.1230146732
Short name T467
Test name
Test status
Simulation time 56750716 ps
CPU time 1.13 seconds
Started Aug 27 09:13:37 AM UTC 24
Finished Aug 27 09:13:39 AM UTC 24
Peak memory 216016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230146732 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 30.edn_smoke.1230146732
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/30.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/30.edn_stress_all.2502244559
Short name T470
Test name
Test status
Simulation time 635542253 ps
CPU time 2.81 seconds
Started Aug 27 09:13:37 AM UTC 24
Finished Aug 27 09:13:40 AM UTC 24
Peak memory 229536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502244559 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.2502244559
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/30.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/30.edn_stress_all_with_rand_reset.3314573423
Short name T551
Test name
Test status
Simulation time 3342105851 ps
CPU time 91.35 seconds
Started Aug 27 09:13:37 AM UTC 24
Finished Aug 27 09:15:10 AM UTC 24
Peak memory 230056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3314573423 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all
_with_rand_reset.3314573423
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/30.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/31.edn_alert.3042848679
Short name T186
Test name
Test status
Simulation time 66264721 ps
CPU time 1.41 seconds
Started Aug 27 09:13:44 AM UTC 24
Finished Aug 27 09:13:47 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042848679 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 31.edn_alert.3042848679
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/31.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/31.edn_alert_test.887700292
Short name T480
Test name
Test status
Simulation time 16572523 ps
CPU time 1.43 seconds
Started Aug 27 09:13:48 AM UTC 24
Finished Aug 27 09:13:50 AM UTC 24
Peak memory 217224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887700292 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.887700292
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/31.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/31.edn_disable.2057085766
Short name T478
Test name
Test status
Simulation time 14086420 ps
CPU time 1.32 seconds
Started Aug 27 09:13:46 AM UTC 24
Finished Aug 27 09:13:48 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057085766 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2057085766
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/31.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/31.edn_disable_auto_req_mode.169101219
Short name T479
Test name
Test status
Simulation time 47260606 ps
CPU time 1.53 seconds
Started Aug 27 09:13:47 AM UTC 24
Finished Aug 27 09:13:49 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169101219 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable_auto_req_mode.169101219
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/31.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/31.edn_err.4208120977
Short name T179
Test name
Test status
Simulation time 30164778 ps
CPU time 1.59 seconds
Started Aug 27 09:13:46 AM UTC 24
Finished Aug 27 09:13:48 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208120977 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 31.edn_err.4208120977
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/31.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/31.edn_genbits.2801450317
Short name T477
Test name
Test status
Simulation time 48442226 ps
CPU time 1.41 seconds
Started Aug 27 09:13:42 AM UTC 24
Finished Aug 27 09:13:45 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801450317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_genbits.2801450317
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/31.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/31.edn_intr.620134812
Short name T95
Test name
Test status
Simulation time 22108693 ps
CPU time 1.41 seconds
Started Aug 27 09:13:43 AM UTC 24
Finished Aug 27 09:13:46 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620134812 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 31.edn_intr.620134812
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/31.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/31.edn_smoke.3528797898
Short name T476
Test name
Test status
Simulation time 52295582 ps
CPU time 1.28 seconds
Started Aug 27 09:13:42 AM UTC 24
Finished Aug 27 09:13:44 AM UTC 24
Peak memory 215904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528797898 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 31.edn_smoke.3528797898
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/31.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/31.edn_stress_all.3348919625
Short name T482
Test name
Test status
Simulation time 266419334 ps
CPU time 7.43 seconds
Started Aug 27 09:13:43 AM UTC 24
Finished Aug 27 09:13:52 AM UTC 24
Peak memory 227480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348919625 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3348919625
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/31.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/31.edn_stress_all_with_rand_reset.4294880953
Short name T239
Test name
Test status
Simulation time 17691067268 ps
CPU time 101.24 seconds
Started Aug 27 09:13:43 AM UTC 24
Finished Aug 27 09:15:27 AM UTC 24
Peak memory 233820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=4294880953 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all
_with_rand_reset.4294880953
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/31.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/32.edn_alert.344170620
Short name T485
Test name
Test status
Simulation time 29174879 ps
CPU time 1.66 seconds
Started Aug 27 09:13:52 AM UTC 24
Finished Aug 27 09:13:55 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344170620 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 32.edn_alert.344170620
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/32.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/32.edn_alert_test.357850800
Short name T490
Test name
Test status
Simulation time 17551201 ps
CPU time 1.14 seconds
Started Aug 27 09:13:56 AM UTC 24
Finished Aug 27 09:13:58 AM UTC 24
Peak memory 216308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357850800 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.357850800
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/32.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/32.edn_disable.3123304850
Short name T214
Test name
Test status
Simulation time 21123585 ps
CPU time 1.14 seconds
Started Aug 27 09:13:55 AM UTC 24
Finished Aug 27 09:13:57 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123304850 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3123304850
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/32.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/32.edn_disable_auto_req_mode.1155435653
Short name T489
Test name
Test status
Simulation time 94757768 ps
CPU time 1.45 seconds
Started Aug 27 09:13:55 AM UTC 24
Finished Aug 27 09:13:58 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155435653 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable_auto_req_mode.1155435653
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/32.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/32.edn_err.2966278542
Short name T488
Test name
Test status
Simulation time 30954235 ps
CPU time 1.4 seconds
Started Aug 27 09:13:53 AM UTC 24
Finished Aug 27 09:13:56 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966278542 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 32.edn_err.2966278542
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/32.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/32.edn_genbits.443019894
Short name T483
Test name
Test status
Simulation time 38380969 ps
CPU time 2.4 seconds
Started Aug 27 09:13:49 AM UTC 24
Finished Aug 27 09:13:52 AM UTC 24
Peak memory 229464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443019894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.edn_genbits.443019894
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/32.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/32.edn_intr.2376721741
Short name T484
Test name
Test status
Simulation time 26115898 ps
CPU time 1.21 seconds
Started Aug 27 09:13:52 AM UTC 24
Finished Aug 27 09:13:54 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376721741 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 32.edn_intr.2376721741
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/32.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/32.edn_smoke.2196510061
Short name T481
Test name
Test status
Simulation time 71056925 ps
CPU time 1.36 seconds
Started Aug 27 09:13:49 AM UTC 24
Finished Aug 27 09:13:51 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196510061 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 32.edn_smoke.2196510061
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/32.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/32.edn_stress_all.122152758
Short name T487
Test name
Test status
Simulation time 136087567 ps
CPU time 4.43 seconds
Started Aug 27 09:13:50 AM UTC 24
Finished Aug 27 09:13:55 AM UTC 24
Peak memory 229480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122152758 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.122152758
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/32.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/33.edn_alert.3336899292
Short name T493
Test name
Test status
Simulation time 54198016 ps
CPU time 1.54 seconds
Started Aug 27 09:13:59 AM UTC 24
Finished Aug 27 09:14:01 AM UTC 24
Peak memory 228044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336899292 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 33.edn_alert.3336899292
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/33.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/33.edn_alert_test.3124548733
Short name T496
Test name
Test status
Simulation time 51996879 ps
CPU time 1.56 seconds
Started Aug 27 09:14:02 AM UTC 24
Finished Aug 27 09:14:05 AM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124548733 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.3124548733
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/33.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/33.edn_disable.2007870392
Short name T494
Test name
Test status
Simulation time 15930787 ps
CPU time 1.31 seconds
Started Aug 27 09:14:00 AM UTC 24
Finished Aug 27 09:14:02 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007870392 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.2007870392
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/33.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/33.edn_disable_auto_req_mode.3903826050
Short name T139
Test name
Test status
Simulation time 64791931 ps
CPU time 1.77 seconds
Started Aug 27 09:14:02 AM UTC 24
Finished Aug 27 09:14:05 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903826050 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable_auto_req_mode.3903826050
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/33.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/33.edn_err.2013498016
Short name T216
Test name
Test status
Simulation time 44947105 ps
CPU time 1.65 seconds
Started Aug 27 09:14:00 AM UTC 24
Finished Aug 27 09:14:03 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013498016 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 33.edn_err.2013498016
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/33.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/33.edn_genbits.4045812836
Short name T492
Test name
Test status
Simulation time 102641320 ps
CPU time 1.37 seconds
Started Aug 27 09:13:56 AM UTC 24
Finished Aug 27 09:13:59 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045812836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_genbits.4045812836
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/33.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/33.edn_smoke.4221107908
Short name T491
Test name
Test status
Simulation time 19920478 ps
CPU time 1.38 seconds
Started Aug 27 09:13:56 AM UTC 24
Finished Aug 27 09:13:59 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221107908 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 33.edn_smoke.4221107908
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/33.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/33.edn_stress_all.3002824460
Short name T495
Test name
Test status
Simulation time 583716492 ps
CPU time 4.83 seconds
Started Aug 27 09:13:58 AM UTC 24
Finished Aug 27 09:14:04 AM UTC 24
Peak memory 229516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002824460 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3002824460
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/33.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/33.edn_stress_all_with_rand_reset.961917529
Short name T544
Test name
Test status
Simulation time 2051885639 ps
CPU time 64.28 seconds
Started Aug 27 09:13:58 AM UTC 24
Finished Aug 27 09:15:04 AM UTC 24
Peak memory 229596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=961917529 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_
with_rand_reset.961917529
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/33.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/34.edn_alert.3313637067
Short name T190
Test name
Test status
Simulation time 78018880 ps
CPU time 1.31 seconds
Started Aug 27 09:14:07 AM UTC 24
Finished Aug 27 09:14:09 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313637067 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 34.edn_alert.3313637067
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/34.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/34.edn_alert_test.1902960908
Short name T503
Test name
Test status
Simulation time 203423797 ps
CPU time 1.53 seconds
Started Aug 27 09:14:09 AM UTC 24
Finished Aug 27 09:14:11 AM UTC 24
Peak memory 216628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902960908 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1902960908
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/34.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/34.edn_disable.1230675985
Short name T501
Test name
Test status
Simulation time 28378830 ps
CPU time 1.21 seconds
Started Aug 27 09:14:09 AM UTC 24
Finished Aug 27 09:14:11 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230675985 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1230675985
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/34.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/34.edn_disable_auto_req_mode.918565419
Short name T502
Test name
Test status
Simulation time 38671703 ps
CPU time 1.35 seconds
Started Aug 27 09:14:09 AM UTC 24
Finished Aug 27 09:14:11 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918565419 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable_auto_req_mode.918565419
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/34.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/34.edn_err.3924347881
Short name T124
Test name
Test status
Simulation time 111435503 ps
CPU time 1.12 seconds
Started Aug 27 09:14:07 AM UTC 24
Finished Aug 27 09:14:09 AM UTC 24
Peak memory 230348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924347881 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 34.edn_err.3924347881
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/34.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/34.edn_genbits.3926689208
Short name T498
Test name
Test status
Simulation time 29331290 ps
CPU time 1.88 seconds
Started Aug 27 09:14:03 AM UTC 24
Finished Aug 27 09:14:06 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926689208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3926689208
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/34.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/34.edn_intr.387255839
Short name T499
Test name
Test status
Simulation time 24196963 ps
CPU time 1.54 seconds
Started Aug 27 09:14:05 AM UTC 24
Finished Aug 27 09:14:08 AM UTC 24
Peak memory 237820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387255839 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 34.edn_intr.387255839
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/34.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/34.edn_smoke.1393867343
Short name T497
Test name
Test status
Simulation time 44900952 ps
CPU time 1.33 seconds
Started Aug 27 09:14:03 AM UTC 24
Finished Aug 27 09:14:06 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393867343 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 34.edn_smoke.1393867343
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/34.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/34.edn_stress_all.3528739792
Short name T500
Test name
Test status
Simulation time 537825117 ps
CPU time 2.9 seconds
Started Aug 27 09:14:04 AM UTC 24
Finished Aug 27 09:14:08 AM UTC 24
Peak memory 227484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528739792 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3528739792
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/34.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/34.edn_stress_all_with_rand_reset.2319419604
Short name T553
Test name
Test status
Simulation time 7665892644 ps
CPU time 65.68 seconds
Started Aug 27 09:14:05 AM UTC 24
Finished Aug 27 09:15:13 AM UTC 24
Peak memory 229788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2319419604 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all
_with_rand_reset.2319419604
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/34.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/35.edn_alert.2629038693
Short name T507
Test name
Test status
Simulation time 57792414 ps
CPU time 1.78 seconds
Started Aug 27 09:14:13 AM UTC 24
Finished Aug 27 09:14:16 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629038693 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 35.edn_alert.2629038693
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/35.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/35.edn_alert_test.4000066046
Short name T510
Test name
Test status
Simulation time 19926071 ps
CPU time 1.55 seconds
Started Aug 27 09:14:17 AM UTC 24
Finished Aug 27 09:14:20 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000066046 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.4000066046
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/35.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/35.edn_disable.928757682
Short name T224
Test name
Test status
Simulation time 22695212 ps
CPU time 1.07 seconds
Started Aug 27 09:14:15 AM UTC 24
Finished Aug 27 09:14:17 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928757682 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.928757682
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/35.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/35.edn_disable_auto_req_mode.2548851632
Short name T509
Test name
Test status
Simulation time 46941837 ps
CPU time 1.64 seconds
Started Aug 27 09:14:16 AM UTC 24
Finished Aug 27 09:14:19 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548851632 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable_auto_req_mode.2548851632
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/35.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/35.edn_err.3588354165
Short name T174
Test name
Test status
Simulation time 28601309 ps
CPU time 1.47 seconds
Started Aug 27 09:14:14 AM UTC 24
Finished Aug 27 09:14:17 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588354165 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 35.edn_err.3588354165
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/35.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/35.edn_genbits.477672282
Short name T505
Test name
Test status
Simulation time 49407653 ps
CPU time 2.19 seconds
Started Aug 27 09:14:10 AM UTC 24
Finished Aug 27 09:14:13 AM UTC 24
Peak memory 229468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477672282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.edn_genbits.477672282
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/35.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/35.edn_intr.1867604870
Short name T506
Test name
Test status
Simulation time 30854121 ps
CPU time 1.35 seconds
Started Aug 27 09:14:12 AM UTC 24
Finished Aug 27 09:14:14 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867604870 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 35.edn_intr.1867604870
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/35.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/35.edn_smoke.2969229568
Short name T504
Test name
Test status
Simulation time 34249473 ps
CPU time 1.13 seconds
Started Aug 27 09:14:10 AM UTC 24
Finished Aug 27 09:14:12 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969229568 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 35.edn_smoke.2969229568
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/35.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/35.edn_stress_all.2208279230
Short name T508
Test name
Test status
Simulation time 126670974 ps
CPU time 3.47 seconds
Started Aug 27 09:14:12 AM UTC 24
Finished Aug 27 09:14:16 AM UTC 24
Peak memory 227468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208279230 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2208279230
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/35.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/35.edn_stress_all_with_rand_reset.173507078
Short name T240
Test name
Test status
Simulation time 10626576970 ps
CPU time 75.87 seconds
Started Aug 27 09:14:12 AM UTC 24
Finished Aug 27 09:15:30 AM UTC 24
Peak memory 229796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=173507078 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_
with_rand_reset.173507078
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/35.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/36.edn_alert.1556134613
Short name T516
Test name
Test status
Simulation time 28694843 ps
CPU time 1.69 seconds
Started Aug 27 09:14:23 AM UTC 24
Finished Aug 27 09:14:26 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556134613 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 36.edn_alert.1556134613
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/36.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/36.edn_alert_test.84992829
Short name T518
Test name
Test status
Simulation time 23136579 ps
CPU time 1.23 seconds
Started Aug 27 09:14:26 AM UTC 24
Finished Aug 27 09:14:28 AM UTC 24
Peak memory 226528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84992829 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.84992829
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/36.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/36.edn_disable.1473571742
Short name T517
Test name
Test status
Simulation time 51437833 ps
CPU time 1.29 seconds
Started Aug 27 09:14:24 AM UTC 24
Finished Aug 27 09:14:26 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473571742 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1473571742
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/36.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/36.edn_disable_auto_req_mode.2246374662
Short name T519
Test name
Test status
Simulation time 38170667 ps
CPU time 1.36 seconds
Started Aug 27 09:14:26 AM UTC 24
Finished Aug 27 09:14:29 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246374662 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable_auto_req_mode.2246374662
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/36.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/36.edn_err.985253719
Short name T515
Test name
Test status
Simulation time 44163104 ps
CPU time 1.64 seconds
Started Aug 27 09:14:23 AM UTC 24
Finished Aug 27 09:14:25 AM UTC 24
Peak memory 236964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985253719 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 36.edn_err.985253719
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/36.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/36.edn_genbits.1221738612
Short name T512
Test name
Test status
Simulation time 46932784 ps
CPU time 2.35 seconds
Started Aug 27 09:14:19 AM UTC 24
Finished Aug 27 09:14:22 AM UTC 24
Peak memory 229520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221738612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1221738612
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/36.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/36.edn_intr.2404496701
Short name T514
Test name
Test status
Simulation time 27287093 ps
CPU time 1.41 seconds
Started Aug 27 09:14:21 AM UTC 24
Finished Aug 27 09:14:23 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404496701 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 36.edn_intr.2404496701
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/36.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/36.edn_smoke.96206758
Short name T511
Test name
Test status
Simulation time 18518161 ps
CPU time 1.51 seconds
Started Aug 27 09:14:17 AM UTC 24
Finished Aug 27 09:14:20 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96206758 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 36.edn_smoke.96206758
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/36.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/36.edn_stress_all.4223592573
Short name T513
Test name
Test status
Simulation time 27324540 ps
CPU time 1.56 seconds
Started Aug 27 09:14:20 AM UTC 24
Finished Aug 27 09:14:22 AM UTC 24
Peak memory 216016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223592573 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.4223592573
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/36.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/37.edn_alert.1115272501
Short name T523
Test name
Test status
Simulation time 211753583 ps
CPU time 1.6 seconds
Started Aug 27 09:14:32 AM UTC 24
Finished Aug 27 09:14:34 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115272501 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 37.edn_alert.1115272501
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/37.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/37.edn_alert_test.3331780420
Short name T527
Test name
Test status
Simulation time 19274396 ps
CPU time 1.34 seconds
Started Aug 27 09:14:36 AM UTC 24
Finished Aug 27 09:14:39 AM UTC 24
Peak memory 226788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331780420 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.3331780420
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/37.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/37.edn_disable.2039321755
Short name T208
Test name
Test status
Simulation time 29486124 ps
CPU time 1.19 seconds
Started Aug 27 09:14:33 AM UTC 24
Finished Aug 27 09:14:35 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039321755 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.2039321755
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/37.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/37.edn_disable_auto_req_mode.261568915
Short name T525
Test name
Test status
Simulation time 24738480 ps
CPU time 1.52 seconds
Started Aug 27 09:14:35 AM UTC 24
Finished Aug 27 09:14:38 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261568915 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable_auto_req_mode.261568915
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/37.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/37.edn_err.1728502297
Short name T209
Test name
Test status
Simulation time 71281007 ps
CPU time 1.44 seconds
Started Aug 27 09:14:33 AM UTC 24
Finished Aug 27 09:14:36 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728502297 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 37.edn_err.1728502297
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/37.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/37.edn_genbits.3529696925
Short name T521
Test name
Test status
Simulation time 86130432 ps
CPU time 1.7 seconds
Started Aug 27 09:14:27 AM UTC 24
Finished Aug 27 09:14:30 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529696925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3529696925
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/37.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/37.edn_intr.3654398869
Short name T522
Test name
Test status
Simulation time 38907717 ps
CPU time 1.26 seconds
Started Aug 27 09:14:30 AM UTC 24
Finished Aug 27 09:14:32 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654398869 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 37.edn_intr.3654398869
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/37.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/37.edn_smoke.1980834119
Short name T520
Test name
Test status
Simulation time 27713741 ps
CPU time 1.31 seconds
Started Aug 27 09:14:26 AM UTC 24
Finished Aug 27 09:14:29 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980834119 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 37.edn_smoke.1980834119
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/37.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/37.edn_stress_all.146084246
Short name T526
Test name
Test status
Simulation time 2604480491 ps
CPU time 6.87 seconds
Started Aug 27 09:14:29 AM UTC 24
Finished Aug 27 09:14:38 AM UTC 24
Peak memory 227672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146084246 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.146084246
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/37.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/37.edn_stress_all_with_rand_reset.3980242133
Short name T608
Test name
Test status
Simulation time 42565309894 ps
CPU time 91.3 seconds
Started Aug 27 09:14:30 AM UTC 24
Finished Aug 27 09:16:03 AM UTC 24
Peak memory 231776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3980242133 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all
_with_rand_reset.3980242133
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/37.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/38.edn_alert.3181953848
Short name T531
Test name
Test status
Simulation time 26360327 ps
CPU time 1.66 seconds
Started Aug 27 09:14:40 AM UTC 24
Finished Aug 27 09:14:42 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181953848 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 38.edn_alert.3181953848
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/38.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/38.edn_alert_test.3305380466
Short name T534
Test name
Test status
Simulation time 22282625 ps
CPU time 1.3 seconds
Started Aug 27 09:14:43 AM UTC 24
Finished Aug 27 09:14:45 AM UTC 24
Peak memory 226712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305380466 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3305380466
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/38.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/38.edn_disable.1930283898
Short name T532
Test name
Test status
Simulation time 31299974 ps
CPU time 1.21 seconds
Started Aug 27 09:14:43 AM UTC 24
Finished Aug 27 09:14:45 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930283898 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1930283898
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/38.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/38.edn_disable_auto_req_mode.1966685499
Short name T533
Test name
Test status
Simulation time 168446601 ps
CPU time 1.34 seconds
Started Aug 27 09:14:43 AM UTC 24
Finished Aug 27 09:14:45 AM UTC 24
Peak memory 230352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966685499 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable_auto_req_mode.1966685499
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/38.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/38.edn_err.766575969
Short name T535
Test name
Test status
Simulation time 45367563 ps
CPU time 1.65 seconds
Started Aug 27 09:14:43 AM UTC 24
Finished Aug 27 09:14:45 AM UTC 24
Peak memory 237160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766575969 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 38.edn_err.766575969
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/38.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/38.edn_genbits.952301077
Short name T529
Test name
Test status
Simulation time 98538204 ps
CPU time 1.89 seconds
Started Aug 27 09:14:38 AM UTC 24
Finished Aug 27 09:14:41 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952301077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_genbits.952301077
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/38.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/38.edn_intr.2820517813
Short name T120
Test name
Test status
Simulation time 22322551 ps
CPU time 1.36 seconds
Started Aug 27 09:14:40 AM UTC 24
Finished Aug 27 09:14:42 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820517813 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 38.edn_intr.2820517813
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/38.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/38.edn_smoke.2288338304
Short name T528
Test name
Test status
Simulation time 15682103 ps
CPU time 1.38 seconds
Started Aug 27 09:14:36 AM UTC 24
Finished Aug 27 09:14:39 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288338304 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 38.edn_smoke.2288338304
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/38.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/38.edn_stress_all.4245827871
Short name T530
Test name
Test status
Simulation time 48936883 ps
CPU time 1.94 seconds
Started Aug 27 09:14:38 AM UTC 24
Finished Aug 27 09:14:41 AM UTC 24
Peak memory 226672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245827871 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.4245827871
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/38.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/39.edn_alert.823448529
Short name T198
Test name
Test status
Simulation time 24890777 ps
CPU time 1.55 seconds
Started Aug 27 09:14:49 AM UTC 24
Finished Aug 27 09:14:52 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823448529 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 39.edn_alert.823448529
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/39.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/39.edn_alert_test.2755217538
Short name T540
Test name
Test status
Simulation time 27358365 ps
CPU time 1.6 seconds
Started Aug 27 09:14:54 AM UTC 24
Finished Aug 27 09:14:56 AM UTC 24
Peak memory 216644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755217538 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.2755217538
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/39.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/39.edn_disable.2784249095
Short name T217
Test name
Test status
Simulation time 18219433 ps
CPU time 1.25 seconds
Started Aug 27 09:14:52 AM UTC 24
Finished Aug 27 09:14:55 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784249095 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2784249095
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/39.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/39.edn_disable_auto_req_mode.1399405689
Short name T140
Test name
Test status
Simulation time 258441885 ps
CPU time 1.43 seconds
Started Aug 27 09:14:52 AM UTC 24
Finished Aug 27 09:14:55 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399405689 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable_auto_req_mode.1399405689
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/39.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/39.edn_err.950063639
Short name T162
Test name
Test status
Simulation time 38040566 ps
CPU time 1.43 seconds
Started Aug 27 09:14:50 AM UTC 24
Finished Aug 27 09:14:53 AM UTC 24
Peak memory 243740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950063639 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 39.edn_err.950063639
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/39.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/39.edn_genbits.3715372942
Short name T537
Test name
Test status
Simulation time 82640939 ps
CPU time 1.57 seconds
Started Aug 27 09:14:46 AM UTC 24
Finished Aug 27 09:14:49 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715372942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3715372942
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/39.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/39.edn_intr.1837650423
Short name T538
Test name
Test status
Simulation time 22779256 ps
CPU time 1.68 seconds
Started Aug 27 09:14:49 AM UTC 24
Finished Aug 27 09:14:52 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837650423 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 39.edn_intr.1837650423
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/39.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/39.edn_smoke.3029266101
Short name T536
Test name
Test status
Simulation time 26011879 ps
CPU time 1.4 seconds
Started Aug 27 09:14:46 AM UTC 24
Finished Aug 27 09:14:48 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029266101 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 39.edn_smoke.3029266101
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/39.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/39.edn_stress_all.2196896197
Short name T329
Test name
Test status
Simulation time 183287064 ps
CPU time 2.32 seconds
Started Aug 27 09:14:46 AM UTC 24
Finished Aug 27 09:14:49 AM UTC 24
Peak memory 229644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196896197 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2196896197
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/39.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/39.edn_stress_all_with_rand_reset.1512879710
Short name T621
Test name
Test status
Simulation time 2129895240 ps
CPU time 85.83 seconds
Started Aug 27 09:14:46 AM UTC 24
Finished Aug 27 09:16:14 AM UTC 24
Peak memory 231848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1512879710 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all
_with_rand_reset.1512879710
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/39.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/4.edn_alert.2525100946
Short name T56
Test name
Test status
Simulation time 83883938 ps
CPU time 1.6 seconds
Started Aug 27 09:11:07 AM UTC 24
Finished Aug 27 09:11:10 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525100946 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 4.edn_alert.2525100946
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/4.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/4.edn_alert_test.3980570690
Short name T372
Test name
Test status
Simulation time 30562784 ps
CPU time 1.31 seconds
Started Aug 27 09:11:11 AM UTC 24
Finished Aug 27 09:11:13 AM UTC 24
Peak memory 216928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980570690 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3980570690
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/4.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/4.edn_disable.233302087
Short name T87
Test name
Test status
Simulation time 31858185 ps
CPU time 1.27 seconds
Started Aug 27 09:11:09 AM UTC 24
Finished Aug 27 09:11:11 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233302087 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.233302087
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/4.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/4.edn_disable_auto_req_mode.287132860
Short name T43
Test name
Test status
Simulation time 78035482 ps
CPU time 1.4 seconds
Started Aug 27 09:11:09 AM UTC 24
Finished Aug 27 09:11:11 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287132860 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable_auto_req_mode.287132860
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/4.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/4.edn_err.2903159286
Short name T97
Test name
Test status
Simulation time 28064134 ps
CPU time 1.38 seconds
Started Aug 27 09:11:08 AM UTC 24
Finished Aug 27 09:11:11 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903159286 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 4.edn_err.2903159286
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/4.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/4.edn_genbits.1210068596
Short name T307
Test name
Test status
Simulation time 54002839 ps
CPU time 1.37 seconds
Started Aug 27 09:11:05 AM UTC 24
Finished Aug 27 09:11:07 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210068596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1210068596
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/4.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/4.edn_intr.3543539253
Short name T109
Test name
Test status
Simulation time 27975460 ps
CPU time 1.28 seconds
Started Aug 27 09:11:07 AM UTC 24
Finished Aug 27 09:11:10 AM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543539253 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 4.edn_intr.3543539253
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/4.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/4.edn_regwen.59951123
Short name T324
Test name
Test status
Simulation time 75263146 ps
CPU time 1.33 seconds
Started Aug 27 09:11:05 AM UTC 24
Finished Aug 27 09:11:07 AM UTC 24
Peak memory 216012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59951123 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 4.edn_regwen.59951123
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/4.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/4.edn_sec_cm.2401521379
Short name T60
Test name
Test status
Simulation time 1016631008 ps
CPU time 13.16 seconds
Started Aug 27 09:11:11 AM UTC 24
Finished Aug 27 09:11:25 AM UTC 24
Peak memory 258528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401521379 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.2401521379
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/4.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/4.edn_smoke.1212702363
Short name T371
Test name
Test status
Simulation time 22991527 ps
CPU time 1.51 seconds
Started Aug 27 09:11:05 AM UTC 24
Finished Aug 27 09:11:07 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212702363 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 4.edn_smoke.1212702363
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/4.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/4.edn_stress_all.1098652844
Short name T102
Test name
Test status
Simulation time 1195901178 ps
CPU time 5.48 seconds
Started Aug 27 09:11:06 AM UTC 24
Finished Aug 27 09:11:12 AM UTC 24
Peak memory 229536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098652844 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1098652844
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/4.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/4.edn_stress_all_with_rand_reset.880234347
Short name T227
Test name
Test status
Simulation time 12852350862 ps
CPU time 72.5 seconds
Started Aug 27 09:11:07 AM UTC 24
Finished Aug 27 09:12:22 AM UTC 24
Peak memory 229988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=880234347 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_w
ith_rand_reset.880234347
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/4.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/40.edn_alert_test.776949849
Short name T547
Test name
Test status
Simulation time 20061046 ps
CPU time 1.4 seconds
Started Aug 27 09:15:04 AM UTC 24
Finished Aug 27 09:15:07 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776949849 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.776949849
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/40.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/40.edn_disable.3314136821
Short name T545
Test name
Test status
Simulation time 30297870 ps
CPU time 1.2 seconds
Started Aug 27 09:15:03 AM UTC 24
Finished Aug 27 09:15:05 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314136821 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.3314136821
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/40.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/40.edn_disable_auto_req_mode.1384094347
Short name T546
Test name
Test status
Simulation time 69331735 ps
CPU time 1.4 seconds
Started Aug 27 09:15:03 AM UTC 24
Finished Aug 27 09:15:06 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384094347 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable_auto_req_mode.1384094347
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/40.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/40.edn_err.1435635264
Short name T542
Test name
Test status
Simulation time 23279923 ps
CPU time 1.32 seconds
Started Aug 27 09:15:00 AM UTC 24
Finished Aug 27 09:15:02 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435635264 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 40.edn_err.1435635264
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/40.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/40.edn_genbits.192454926
Short name T312
Test name
Test status
Simulation time 39945429 ps
CPU time 2.03 seconds
Started Aug 27 09:14:56 AM UTC 24
Finished Aug 27 09:14:59 AM UTC 24
Peak memory 231580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192454926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.edn_genbits.192454926
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/40.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/40.edn_intr.4130328567
Short name T541
Test name
Test status
Simulation time 20921115 ps
CPU time 1.43 seconds
Started Aug 27 09:14:57 AM UTC 24
Finished Aug 27 09:14:59 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130328567 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 40.edn_intr.4130328567
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/40.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/40.edn_smoke.3590007832
Short name T539
Test name
Test status
Simulation time 37816080 ps
CPU time 1.34 seconds
Started Aug 27 09:14:54 AM UTC 24
Finished Aug 27 09:14:56 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590007832 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 40.edn_smoke.3590007832
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/40.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/40.edn_stress_all.2149685859
Short name T543
Test name
Test status
Simulation time 511363688 ps
CPU time 6.68 seconds
Started Aug 27 09:14:56 AM UTC 24
Finished Aug 27 09:15:04 AM UTC 24
Peak memory 229708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149685859 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2149685859
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/40.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/40.edn_stress_all_with_rand_reset.3797447291
Short name T330
Test name
Test status
Simulation time 5612265056 ps
CPU time 37.59 seconds
Started Aug 27 09:14:57 AM UTC 24
Finished Aug 27 09:15:36 AM UTC 24
Peak memory 231924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3797447291 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all
_with_rand_reset.3797447291
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/40.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/41.edn_alert.2789596917
Short name T141
Test name
Test status
Simulation time 181753520 ps
CPU time 2.06 seconds
Started Aug 27 09:15:08 AM UTC 24
Finished Aug 27 09:15:11 AM UTC 24
Peak memory 230272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789596917 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 41.edn_alert.2789596917
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/41.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/41.edn_alert_test.1222999200
Short name T556
Test name
Test status
Simulation time 29663951 ps
CPU time 1.4 seconds
Started Aug 27 09:15:12 AM UTC 24
Finished Aug 27 09:15:14 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222999200 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1222999200
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/41.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/41.edn_disable.123136809
Short name T554
Test name
Test status
Simulation time 27625539 ps
CPU time 1.15 seconds
Started Aug 27 09:15:11 AM UTC 24
Finished Aug 27 09:15:13 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123136809 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.123136809
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/41.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/41.edn_disable_auto_req_mode.2555628631
Short name T159
Test name
Test status
Simulation time 24971747 ps
CPU time 1.5 seconds
Started Aug 27 09:15:11 AM UTC 24
Finished Aug 27 09:15:13 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555628631 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable_auto_req_mode.2555628631
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/41.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/41.edn_err.1419870971
Short name T175
Test name
Test status
Simulation time 20937825 ps
CPU time 1.15 seconds
Started Aug 27 09:15:10 AM UTC 24
Finished Aug 27 09:15:12 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419870971 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 41.edn_err.1419870971
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/41.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/41.edn_genbits.2922012845
Short name T549
Test name
Test status
Simulation time 32135147 ps
CPU time 1.75 seconds
Started Aug 27 09:15:06 AM UTC 24
Finished Aug 27 09:15:09 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922012845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2922012845
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/41.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/41.edn_intr.475351555
Short name T550
Test name
Test status
Simulation time 30381919 ps
CPU time 1.31 seconds
Started Aug 27 09:15:08 AM UTC 24
Finished Aug 27 09:15:10 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475351555 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 41.edn_intr.475351555
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/41.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/41.edn_smoke.2061273108
Short name T548
Test name
Test status
Simulation time 34808609 ps
CPU time 1.78 seconds
Started Aug 27 09:15:04 AM UTC 24
Finished Aug 27 09:15:07 AM UTC 24
Peak memory 226452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061273108 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 41.edn_smoke.2061273108
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/41.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/41.edn_stress_all.117768547
Short name T552
Test name
Test status
Simulation time 125339126 ps
CPU time 3.95 seconds
Started Aug 27 09:15:06 AM UTC 24
Finished Aug 27 09:15:11 AM UTC 24
Peak memory 231584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117768547 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.117768547
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/41.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/41.edn_stress_all_with_rand_reset.245731194
Short name T241
Test name
Test status
Simulation time 19112912788 ps
CPU time 62.44 seconds
Started Aug 27 09:15:08 AM UTC 24
Finished Aug 27 09:16:12 AM UTC 24
Peak memory 233820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=245731194 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_
with_rand_reset.245731194
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/41.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/42.edn_alert.2689744005
Short name T561
Test name
Test status
Simulation time 49116669 ps
CPU time 1.75 seconds
Started Aug 27 09:15:16 AM UTC 24
Finished Aug 27 09:15:18 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689744005 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 42.edn_alert.2689744005
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/42.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/42.edn_alert_test.988459103
Short name T564
Test name
Test status
Simulation time 22702737 ps
CPU time 1.51 seconds
Started Aug 27 09:15:17 AM UTC 24
Finished Aug 27 09:15:19 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988459103 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.988459103
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/42.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/42.edn_disable.3682040112
Short name T559
Test name
Test status
Simulation time 22890578 ps
CPU time 1.33 seconds
Started Aug 27 09:15:16 AM UTC 24
Finished Aug 27 09:15:18 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682040112 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3682040112
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/42.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/42.edn_disable_auto_req_mode.1788466115
Short name T563
Test name
Test status
Simulation time 67516091 ps
CPU time 1.41 seconds
Started Aug 27 09:15:17 AM UTC 24
Finished Aug 27 09:15:19 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788466115 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable_auto_req_mode.1788466115
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/42.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/42.edn_err.4214096322
Short name T560
Test name
Test status
Simulation time 19805498 ps
CPU time 1.41 seconds
Started Aug 27 09:15:16 AM UTC 24
Finished Aug 27 09:15:18 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214096322 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 42.edn_err.4214096322
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/42.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/42.edn_genbits.3018339577
Short name T557
Test name
Test status
Simulation time 213263830 ps
CPU time 1.42 seconds
Started Aug 27 09:15:13 AM UTC 24
Finished Aug 27 09:15:16 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018339577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_genbits.3018339577
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/42.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/42.edn_intr.3633673075
Short name T558
Test name
Test status
Simulation time 27538013 ps
CPU time 1.09 seconds
Started Aug 27 09:15:14 AM UTC 24
Finished Aug 27 09:15:16 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633673075 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 42.edn_intr.3633673075
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/42.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/42.edn_smoke.1004557478
Short name T555
Test name
Test status
Simulation time 40779569 ps
CPU time 1.3 seconds
Started Aug 27 09:15:12 AM UTC 24
Finished Aug 27 09:15:14 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004557478 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 42.edn_smoke.1004557478
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/42.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/42.edn_stress_all.1189687044
Short name T562
Test name
Test status
Simulation time 168242555 ps
CPU time 4.47 seconds
Started Aug 27 09:15:13 AM UTC 24
Finished Aug 27 09:15:19 AM UTC 24
Peak memory 229464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189687044 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1189687044
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/42.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/42.edn_stress_all_with_rand_reset.2302287617
Short name T261
Test name
Test status
Simulation time 17053878093 ps
CPU time 123.78 seconds
Started Aug 27 09:15:14 AM UTC 24
Finished Aug 27 09:17:21 AM UTC 24
Peak memory 229876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2302287617 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all
_with_rand_reset.2302287617
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/42.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/43.edn_alert_test.2509907453
Short name T570
Test name
Test status
Simulation time 16840071 ps
CPU time 1.45 seconds
Started Aug 27 09:15:23 AM UTC 24
Finished Aug 27 09:15:26 AM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509907453 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2509907453
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/43.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/43.edn_disable.140149196
Short name T569
Test name
Test status
Simulation time 19089089 ps
CPU time 1.25 seconds
Started Aug 27 09:15:22 AM UTC 24
Finished Aug 27 09:15:25 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140149196 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.140149196
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/43.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/43.edn_disable_auto_req_mode.1075894908
Short name T215
Test name
Test status
Simulation time 32466963 ps
CPU time 1.66 seconds
Started Aug 27 09:15:23 AM UTC 24
Finished Aug 27 09:15:26 AM UTC 24
Peak memory 230352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075894908 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable_auto_req_mode.1075894908
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/43.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/43.edn_err.2813758335
Short name T176
Test name
Test status
Simulation time 34224263 ps
CPU time 1.06 seconds
Started Aug 27 09:15:22 AM UTC 24
Finished Aug 27 09:15:24 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813758335 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 43.edn_err.2813758335
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/43.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/43.edn_genbits.4111251245
Short name T568
Test name
Test status
Simulation time 73498275 ps
CPU time 3.04 seconds
Started Aug 27 09:15:19 AM UTC 24
Finished Aug 27 09:15:23 AM UTC 24
Peak memory 231508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111251245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_genbits.4111251245
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/43.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/43.edn_intr.1011253936
Short name T567
Test name
Test status
Simulation time 78434989 ps
CPU time 1.17 seconds
Started Aug 27 09:15:20 AM UTC 24
Finished Aug 27 09:15:22 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011253936 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 43.edn_intr.1011253936
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/43.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/43.edn_smoke.442585585
Short name T565
Test name
Test status
Simulation time 48840774 ps
CPU time 1.08 seconds
Started Aug 27 09:15:19 AM UTC 24
Finished Aug 27 09:15:21 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442585585 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 43.edn_smoke.442585585
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/43.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/43.edn_stress_all.3540033966
Short name T566
Test name
Test status
Simulation time 43455966 ps
CPU time 1.88 seconds
Started Aug 27 09:15:19 AM UTC 24
Finished Aug 27 09:15:22 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540033966 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3540033966
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/43.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/43.edn_stress_all_with_rand_reset.3929156370
Short name T604
Test name
Test status
Simulation time 8353420056 ps
CPU time 40.17 seconds
Started Aug 27 09:15:20 AM UTC 24
Finished Aug 27 09:16:02 AM UTC 24
Peak memory 229872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3929156370 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all
_with_rand_reset.3929156370
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/43.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/44.edn_alert.27060177
Short name T134
Test name
Test status
Simulation time 72459487 ps
CPU time 1.5 seconds
Started Aug 27 09:15:27 AM UTC 24
Finished Aug 27 09:15:29 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27060177 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 44.edn_alert.27060177
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/44.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/44.edn_alert_test.2002285570
Short name T574
Test name
Test status
Simulation time 207679355 ps
CPU time 1.26 seconds
Started Aug 27 09:15:30 AM UTC 24
Finished Aug 27 09:15:33 AM UTC 24
Peak memory 216908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002285570 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2002285570
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/44.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/44.edn_disable.1003060250
Short name T223
Test name
Test status
Simulation time 13960308 ps
CPU time 1.39 seconds
Started Aug 27 09:15:27 AM UTC 24
Finished Aug 27 09:15:30 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003060250 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1003060250
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/44.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/44.edn_disable_auto_req_mode.16145371
Short name T218
Test name
Test status
Simulation time 68730150 ps
CPU time 1.61 seconds
Started Aug 27 09:15:28 AM UTC 24
Finished Aug 27 09:15:31 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16145371 -assert nopostproc +UVM_TESTNAME=edn_disab
le_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable_auto_req_mode.16145371
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/44.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/44.edn_err.592600905
Short name T572
Test name
Test status
Simulation time 36578231 ps
CPU time 1.58 seconds
Started Aug 27 09:15:27 AM UTC 24
Finished Aug 27 09:15:30 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592600905 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 44.edn_err.592600905
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/44.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/44.edn_genbits.3099502227
Short name T571
Test name
Test status
Simulation time 53809858 ps
CPU time 1.59 seconds
Started Aug 27 09:15:25 AM UTC 24
Finished Aug 27 09:15:27 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099502227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3099502227
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/44.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/44.edn_intr.3675009406
Short name T98
Test name
Test status
Simulation time 49497251 ps
CPU time 1.28 seconds
Started Aug 27 09:15:27 AM UTC 24
Finished Aug 27 09:15:29 AM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675009406 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 44.edn_intr.3675009406
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/44.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/44.edn_smoke.143303062
Short name T327
Test name
Test status
Simulation time 15310354 ps
CPU time 1.3 seconds
Started Aug 27 09:15:24 AM UTC 24
Finished Aug 27 09:15:26 AM UTC 24
Peak memory 216016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143303062 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 44.edn_smoke.143303062
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/44.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/44.edn_stress_all.387694031
Short name T573
Test name
Test status
Simulation time 242203957 ps
CPU time 3.57 seconds
Started Aug 27 09:15:26 AM UTC 24
Finished Aug 27 09:15:30 AM UTC 24
Peak memory 229708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387694031 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.387694031
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/44.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/44.edn_stress_all_with_rand_reset.2301980227
Short name T759
Test name
Test status
Simulation time 5030582334 ps
CPU time 118.52 seconds
Started Aug 27 09:15:27 AM UTC 24
Finished Aug 27 09:17:28 AM UTC 24
Peak memory 233828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2301980227 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all
_with_rand_reset.2301980227
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/44.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/45.edn_alert.1415871786
Short name T200
Test name
Test status
Simulation time 97248118 ps
CPU time 1.85 seconds
Started Aug 27 09:15:32 AM UTC 24
Finished Aug 27 09:15:35 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415871786 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 45.edn_alert.1415871786
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/45.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/45.edn_alert_test.3219118916
Short name T580
Test name
Test status
Simulation time 11468395 ps
CPU time 1.24 seconds
Started Aug 27 09:15:35 AM UTC 24
Finished Aug 27 09:15:37 AM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219118916 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3219118916
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/45.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/45.edn_disable.2645165465
Short name T578
Test name
Test status
Simulation time 13566885 ps
CPU time 1.3 seconds
Started Aug 27 09:15:34 AM UTC 24
Finished Aug 27 09:15:36 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645165465 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2645165465
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/45.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/45.edn_disable_auto_req_mode.4288440517
Short name T579
Test name
Test status
Simulation time 58910997 ps
CPU time 1.63 seconds
Started Aug 27 09:15:34 AM UTC 24
Finished Aug 27 09:15:36 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288440517 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable_auto_req_mode.4288440517
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/45.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/45.edn_err.3231606629
Short name T577
Test name
Test status
Simulation time 23214464 ps
CPU time 1.16 seconds
Started Aug 27 09:15:34 AM UTC 24
Finished Aug 27 09:15:36 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231606629 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 45.edn_err.3231606629
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/45.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/45.edn_genbits.3784055512
Short name T369
Test name
Test status
Simulation time 68627123 ps
CPU time 1.56 seconds
Started Aug 27 09:15:30 AM UTC 24
Finished Aug 27 09:15:33 AM UTC 24
Peak memory 230348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784055512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3784055512
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/45.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/45.edn_intr.2640845937
Short name T576
Test name
Test status
Simulation time 32002543 ps
CPU time 1.26 seconds
Started Aug 27 09:15:32 AM UTC 24
Finished Aug 27 09:15:34 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640845937 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 45.edn_intr.2640845937
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/45.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/45.edn_smoke.3656357408
Short name T575
Test name
Test status
Simulation time 22541974 ps
CPU time 1.37 seconds
Started Aug 27 09:15:30 AM UTC 24
Finished Aug 27 09:15:33 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656357408 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 45.edn_smoke.3656357408
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/45.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/45.edn_stress_all.1704408864
Short name T581
Test name
Test status
Simulation time 1936974699 ps
CPU time 6.28 seconds
Started Aug 27 09:15:30 AM UTC 24
Finished Aug 27 09:15:38 AM UTC 24
Peak memory 227408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704408864 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1704408864
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/45.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/46.edn_alert.1861745982
Short name T585
Test name
Test status
Simulation time 27428282 ps
CPU time 1.88 seconds
Started Aug 27 09:15:38 AM UTC 24
Finished Aug 27 09:15:41 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861745982 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 46.edn_alert.1861745982
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/46.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/46.edn_alert_test.4184692213
Short name T589
Test name
Test status
Simulation time 152419934 ps
CPU time 1.3 seconds
Started Aug 27 09:15:41 AM UTC 24
Finished Aug 27 09:15:44 AM UTC 24
Peak memory 216912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184692213 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.4184692213
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/46.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/46.edn_disable.2769143495
Short name T586
Test name
Test status
Simulation time 64549071 ps
CPU time 1.26 seconds
Started Aug 27 09:15:39 AM UTC 24
Finished Aug 27 09:15:42 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769143495 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.2769143495
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/46.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/46.edn_disable_auto_req_mode.2903946503
Short name T588
Test name
Test status
Simulation time 36165319 ps
CPU time 1.9 seconds
Started Aug 27 09:15:40 AM UTC 24
Finished Aug 27 09:15:43 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903946503 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable_auto_req_mode.2903946503
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/46.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/46.edn_err.2862098129
Short name T213
Test name
Test status
Simulation time 50465290 ps
CPU time 1.34 seconds
Started Aug 27 09:15:38 AM UTC 24
Finished Aug 27 09:15:41 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862098129 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 46.edn_err.2862098129
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/46.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/46.edn_genbits.3862971826
Short name T584
Test name
Test status
Simulation time 290062978 ps
CPU time 2.2 seconds
Started Aug 27 09:15:37 AM UTC 24
Finished Aug 27 09:15:40 AM UTC 24
Peak memory 231572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862971826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_genbits.3862971826
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/46.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/46.edn_intr.2874775012
Short name T583
Test name
Test status
Simulation time 24230618 ps
CPU time 1.63 seconds
Started Aug 27 09:15:37 AM UTC 24
Finished Aug 27 09:15:40 AM UTC 24
Peak memory 238076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874775012 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 46.edn_intr.2874775012
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/46.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/46.edn_smoke.2354642271
Short name T582
Test name
Test status
Simulation time 44408764 ps
CPU time 1.39 seconds
Started Aug 27 09:15:36 AM UTC 24
Finished Aug 27 09:15:38 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354642271 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 46.edn_smoke.2354642271
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/46.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/46.edn_stress_all.1220989341
Short name T331
Test name
Test status
Simulation time 253129767 ps
CPU time 3.49 seconds
Started Aug 27 09:15:37 AM UTC 24
Finished Aug 27 09:15:42 AM UTC 24
Peak memory 231508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220989341 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1220989341
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/46.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/47.edn_alert.3189231215
Short name T201
Test name
Test status
Simulation time 40217567 ps
CPU time 1.7 seconds
Started Aug 27 09:15:45 AM UTC 24
Finished Aug 27 09:15:48 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189231215 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 47.edn_alert.3189231215
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/47.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/47.edn_alert_test.366586367
Short name T594
Test name
Test status
Simulation time 15513667 ps
CPU time 1.33 seconds
Started Aug 27 09:15:48 AM UTC 24
Finished Aug 27 09:15:50 AM UTC 24
Peak memory 226904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366586367 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.366586367
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/47.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/47.edn_disable.3879358115
Short name T592
Test name
Test status
Simulation time 21631180 ps
CPU time 1.29 seconds
Started Aug 27 09:15:46 AM UTC 24
Finished Aug 27 09:15:48 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879358115 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3879358115
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/47.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/47.edn_disable_auto_req_mode.2935480893
Short name T593
Test name
Test status
Simulation time 88091251 ps
CPU time 1.66 seconds
Started Aug 27 09:15:47 AM UTC 24
Finished Aug 27 09:15:50 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935480893 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable_auto_req_mode.2935480893
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/47.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/47.edn_err.3005678940
Short name T119
Test name
Test status
Simulation time 37272156 ps
CPU time 1.37 seconds
Started Aug 27 09:15:45 AM UTC 24
Finished Aug 27 09:15:47 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005678940 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 47.edn_err.3005678940
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/47.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/47.edn_genbits.1657759998
Short name T591
Test name
Test status
Simulation time 81683088 ps
CPU time 1.95 seconds
Started Aug 27 09:15:42 AM UTC 24
Finished Aug 27 09:15:45 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657759998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1657759998
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/47.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/47.edn_intr.2181766557
Short name T328
Test name
Test status
Simulation time 28690268 ps
CPU time 1.23 seconds
Started Aug 27 09:15:44 AM UTC 24
Finished Aug 27 09:15:46 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181766557 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 47.edn_intr.2181766557
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/47.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/47.edn_smoke.3761915786
Short name T590
Test name
Test status
Simulation time 17766877 ps
CPU time 1.35 seconds
Started Aug 27 09:15:42 AM UTC 24
Finished Aug 27 09:15:44 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761915786 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 47.edn_smoke.3761915786
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/47.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/47.edn_stress_all.3419527313
Short name T596
Test name
Test status
Simulation time 836508901 ps
CPU time 6.93 seconds
Started Aug 27 09:15:43 AM UTC 24
Finished Aug 27 09:15:51 AM UTC 24
Peak memory 227480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419527313 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3419527313
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/47.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/47.edn_stress_all_with_rand_reset.2651104261
Short name T785
Test name
Test status
Simulation time 15323014348 ps
CPU time 112.04 seconds
Started Aug 27 09:15:43 AM UTC 24
Finished Aug 27 09:17:37 AM UTC 24
Peak memory 230052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2651104261 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all
_with_rand_reset.2651104261
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/47.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/48.edn_alert.1513836253
Short name T599
Test name
Test status
Simulation time 36501697 ps
CPU time 1.54 seconds
Started Aug 27 09:15:51 AM UTC 24
Finished Aug 27 09:15:54 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513836253 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 48.edn_alert.1513836253
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/48.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/48.edn_alert_test.2366835798
Short name T602
Test name
Test status
Simulation time 26977962 ps
CPU time 1.29 seconds
Started Aug 27 09:15:56 AM UTC 24
Finished Aug 27 09:15:58 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366835798 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.2366835798
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/48.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/48.edn_disable.153555980
Short name T601
Test name
Test status
Simulation time 56261679 ps
CPU time 1.15 seconds
Started Aug 27 09:15:55 AM UTC 24
Finished Aug 27 09:15:57 AM UTC 24
Peak memory 216132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153555980 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.153555980
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/48.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/48.edn_disable_auto_req_mode.1065370117
Short name T603
Test name
Test status
Simulation time 24719596 ps
CPU time 1.35 seconds
Started Aug 27 09:15:55 AM UTC 24
Finished Aug 27 09:15:57 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065370117 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable_auto_req_mode.1065370117
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/48.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/48.edn_err.1078100370
Short name T144
Test name
Test status
Simulation time 41404117 ps
CPU time 1.65 seconds
Started Aug 27 09:15:53 AM UTC 24
Finished Aug 27 09:15:55 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078100370 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 48.edn_err.1078100370
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/48.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/48.edn_genbits.4229410862
Short name T597
Test name
Test status
Simulation time 40223719 ps
CPU time 1.78 seconds
Started Aug 27 09:15:49 AM UTC 24
Finished Aug 27 09:15:52 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229410862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_genbits.4229410862
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/48.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/48.edn_intr.1157581376
Short name T598
Test name
Test status
Simulation time 21175912 ps
CPU time 1.51 seconds
Started Aug 27 09:15:51 AM UTC 24
Finished Aug 27 09:15:54 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157581376 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 48.edn_intr.1157581376
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/48.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/48.edn_smoke.1111975409
Short name T595
Test name
Test status
Simulation time 50973017 ps
CPU time 1.35 seconds
Started Aug 27 09:15:48 AM UTC 24
Finished Aug 27 09:15:50 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111975409 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 48.edn_smoke.1111975409
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/48.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/48.edn_stress_all.3699846217
Short name T600
Test name
Test status
Simulation time 543320336 ps
CPU time 4.86 seconds
Started Aug 27 09:15:50 AM UTC 24
Finished Aug 27 09:15:56 AM UTC 24
Peak memory 229504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699846217 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3699846217
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/48.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/48.edn_stress_all_with_rand_reset.631592728
Short name T726
Test name
Test status
Simulation time 4061803587 ps
CPU time 78.75 seconds
Started Aug 27 09:15:51 AM UTC 24
Finished Aug 27 09:17:12 AM UTC 24
Peak memory 230072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=631592728 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_
with_rand_reset.631592728
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/48.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/49.edn_alert.2814862019
Short name T609
Test name
Test status
Simulation time 83102751 ps
CPU time 1.86 seconds
Started Aug 27 09:16:02 AM UTC 24
Finished Aug 27 09:16:05 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814862019 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 49.edn_alert.2814862019
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/49.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/49.edn_alert_test.1437757829
Short name T612
Test name
Test status
Simulation time 20806466 ps
CPU time 1.15 seconds
Started Aug 27 09:16:04 AM UTC 24
Finished Aug 27 09:16:07 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437757829 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1437757829
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/49.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/49.edn_disable.153061683
Short name T610
Test name
Test status
Simulation time 17052519 ps
CPU time 1.29 seconds
Started Aug 27 09:16:03 AM UTC 24
Finished Aug 27 09:16:05 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153061683 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.153061683
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/49.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/49.edn_disable_auto_req_mode.383979141
Short name T611
Test name
Test status
Simulation time 213400019 ps
CPU time 1.59 seconds
Started Aug 27 09:16:03 AM UTC 24
Finished Aug 27 09:16:06 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383979141 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable_auto_req_mode.383979141
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/49.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/49.edn_err.2792727933
Short name T127
Test name
Test status
Simulation time 33607344 ps
CPU time 1.14 seconds
Started Aug 27 09:16:02 AM UTC 24
Finished Aug 27 09:16:04 AM UTC 24
Peak memory 243736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792727933 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 49.edn_err.2792727933
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/49.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/49.edn_genbits.246597871
Short name T605
Test name
Test status
Simulation time 278505418 ps
CPU time 2.87 seconds
Started Aug 27 09:15:58 AM UTC 24
Finished Aug 27 09:16:02 AM UTC 24
Peak memory 231664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246597871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.edn_genbits.246597871
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/49.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/49.edn_intr.123960271
Short name T607
Test name
Test status
Simulation time 22293967 ps
CPU time 1.58 seconds
Started Aug 27 09:16:00 AM UTC 24
Finished Aug 27 09:16:03 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123960271 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 49.edn_intr.123960271
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/49.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/49.edn_smoke.443920848
Short name T587
Test name
Test status
Simulation time 135563580 ps
CPU time 1.39 seconds
Started Aug 27 09:15:57 AM UTC 24
Finished Aug 27 09:15:59 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443920848 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 49.edn_smoke.443920848
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/49.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/49.edn_stress_all.2223120128
Short name T606
Test name
Test status
Simulation time 578262940 ps
CPU time 3.49 seconds
Started Aug 27 09:15:58 AM UTC 24
Finished Aug 27 09:16:02 AM UTC 24
Peak memory 227488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223120128 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2223120128
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/49.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/5.edn_alert.1500277267
Short name T44
Test name
Test status
Simulation time 36294468 ps
CPU time 1.23 seconds
Started Aug 27 09:11:15 AM UTC 24
Finished Aug 27 09:11:17 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500277267 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 5.edn_alert.1500277267
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/5.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/5.edn_alert_test.792838271
Short name T375
Test name
Test status
Simulation time 37755739 ps
CPU time 1.08 seconds
Started Aug 27 09:11:18 AM UTC 24
Finished Aug 27 09:11:20 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792838271 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.792838271
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/5.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/5.edn_disable.3978878490
Short name T48
Test name
Test status
Simulation time 19444090 ps
CPU time 1.1 seconds
Started Aug 27 09:11:17 AM UTC 24
Finished Aug 27 09:11:19 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978878490 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.3978878490
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/5.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/5.edn_disable_auto_req_mode.1528657298
Short name T45
Test name
Test status
Simulation time 32759774 ps
CPU time 1.47 seconds
Started Aug 27 09:11:17 AM UTC 24
Finished Aug 27 09:11:19 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528657298 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable_auto_req_mode.1528657298
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/5.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/5.edn_err.3965931786
Short name T374
Test name
Test status
Simulation time 22337746 ps
CPU time 1.3 seconds
Started Aug 27 09:11:15 AM UTC 24
Finished Aug 27 09:11:17 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965931786 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 5.edn_err.3965931786
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/5.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/5.edn_intr.3859650474
Short name T52
Test name
Test status
Simulation time 34044738 ps
CPU time 1.28 seconds
Started Aug 27 09:11:15 AM UTC 24
Finished Aug 27 09:11:17 AM UTC 24
Peak memory 237816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859650474 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 5.edn_intr.3859650474
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/5.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/5.edn_smoke.1013489070
Short name T373
Test name
Test status
Simulation time 66367032 ps
CPU time 1.14 seconds
Started Aug 27 09:11:12 AM UTC 24
Finished Aug 27 09:11:14 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013489070 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 5.edn_smoke.1013489070
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/5.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/5.edn_stress_all.1107344298
Short name T107
Test name
Test status
Simulation time 330031702 ps
CPU time 3.13 seconds
Started Aug 27 09:11:13 AM UTC 24
Finished Aug 27 09:11:17 AM UTC 24
Peak memory 229536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107344298 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1107344298
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/5.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/5.edn_stress_all_with_rand_reset.4194206624
Short name T231
Test name
Test status
Simulation time 3296335007 ps
CPU time 96.94 seconds
Started Aug 27 09:11:14 AM UTC 24
Finished Aug 27 09:12:53 AM UTC 24
Peak memory 229784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=4194206624 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_
with_rand_reset.4194206624
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/5.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/50.edn_alert.2530535967
Short name T142
Test name
Test status
Simulation time 35800958 ps
CPU time 1.43 seconds
Started Aug 27 09:16:05 AM UTC 24
Finished Aug 27 09:16:08 AM UTC 24
Peak memory 226360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530535967 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 50.edn_alert.2530535967
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/50.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/50.edn_err.3999410774
Short name T614
Test name
Test status
Simulation time 22381553 ps
CPU time 1.25 seconds
Started Aug 27 09:16:07 AM UTC 24
Finished Aug 27 09:16:09 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999410774 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 50.edn_err.3999410774
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/50.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/50.edn_genbits.2144992627
Short name T613
Test name
Test status
Simulation time 64450957 ps
CPU time 1.69 seconds
Started Aug 27 09:16:05 AM UTC 24
Finished Aug 27 09:16:08 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144992627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2144992627
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/50.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/51.edn_alert.4048905543
Short name T615
Test name
Test status
Simulation time 114345338 ps
CPU time 1.29 seconds
Started Aug 27 09:16:08 AM UTC 24
Finished Aug 27 09:16:10 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048905543 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 51.edn_alert.4048905543
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/51.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/51.edn_err.303058580
Short name T617
Test name
Test status
Simulation time 18067130 ps
CPU time 1.69 seconds
Started Aug 27 09:16:09 AM UTC 24
Finished Aug 27 09:16:11 AM UTC 24
Peak memory 237160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303058580 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 51.edn_err.303058580
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/51.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/51.edn_genbits.2289541009
Short name T616
Test name
Test status
Simulation time 111081402 ps
CPU time 2.37 seconds
Started Aug 27 09:16:07 AM UTC 24
Finished Aug 27 09:16:10 AM UTC 24
Peak memory 231496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289541009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2289541009
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/51.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/52.edn_alert.345214606
Short name T619
Test name
Test status
Simulation time 63001645 ps
CPU time 1.58 seconds
Started Aug 27 09:16:10 AM UTC 24
Finished Aug 27 09:16:13 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345214606 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 52.edn_alert.345214606
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/52.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/52.edn_err.3550133622
Short name T203
Test name
Test status
Simulation time 19393915 ps
CPU time 1.52 seconds
Started Aug 27 09:16:11 AM UTC 24
Finished Aug 27 09:16:13 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550133622 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 52.edn_err.3550133622
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/52.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/52.edn_genbits.4264139148
Short name T618
Test name
Test status
Simulation time 72921569 ps
CPU time 1.9 seconds
Started Aug 27 09:16:09 AM UTC 24
Finished Aug 27 09:16:12 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264139148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 52.edn_genbits.4264139148
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/52.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/53.edn_alert.4244811222
Short name T156
Test name
Test status
Simulation time 47114889 ps
CPU time 1.7 seconds
Started Aug 27 09:16:12 AM UTC 24
Finished Aug 27 09:16:15 AM UTC 24
Peak memory 228056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244811222 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 53.edn_alert.4244811222
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/53.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/53.edn_err.3598116843
Short name T622
Test name
Test status
Simulation time 33513257 ps
CPU time 1.29 seconds
Started Aug 27 09:16:12 AM UTC 24
Finished Aug 27 09:16:14 AM UTC 24
Peak memory 228072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598116843 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 53.edn_err.3598116843
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/53.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/53.edn_genbits.53494538
Short name T620
Test name
Test status
Simulation time 23264224 ps
CPU time 1.57 seconds
Started Aug 27 09:16:11 AM UTC 24
Finished Aug 27 09:16:13 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53494538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 53.edn_genbits.53494538
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/53.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/54.edn_alert.900487321
Short name T146
Test name
Test status
Simulation time 47191196 ps
CPU time 1.46 seconds
Started Aug 27 09:16:13 AM UTC 24
Finished Aug 27 09:16:16 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900487321 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 54.edn_alert.900487321
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/54.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/54.edn_err.3881420017
Short name T220
Test name
Test status
Simulation time 29508072 ps
CPU time 1.94 seconds
Started Aug 27 09:16:15 AM UTC 24
Finished Aug 27 09:16:18 AM UTC 24
Peak memory 244336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881420017 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 54.edn_err.3881420017
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/54.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/54.edn_genbits.718934749
Short name T313
Test name
Test status
Simulation time 40918708 ps
CPU time 1.75 seconds
Started Aug 27 09:16:13 AM UTC 24
Finished Aug 27 09:16:16 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718934749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 54.edn_genbits.718934749
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/54.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/55.edn_alert.1518152447
Short name T623
Test name
Test status
Simulation time 39595761 ps
CPU time 1.61 seconds
Started Aug 27 09:16:15 AM UTC 24
Finished Aug 27 09:16:17 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518152447 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 55.edn_alert.1518152447
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/55.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/55.edn_err.2721623211
Short name T128
Test name
Test status
Simulation time 24652032 ps
CPU time 1.59 seconds
Started Aug 27 09:16:15 AM UTC 24
Finished Aug 27 09:16:17 AM UTC 24
Peak memory 243796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721623211 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 55.edn_err.2721623211
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/55.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/56.edn_alert.3254799750
Short name T624
Test name
Test status
Simulation time 89566234 ps
CPU time 1.6 seconds
Started Aug 27 09:16:16 AM UTC 24
Finished Aug 27 09:16:18 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254799750 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 56.edn_alert.3254799750
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/56.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/56.edn_err.2183836960
Short name T627
Test name
Test status
Simulation time 29282690 ps
CPU time 1.98 seconds
Started Aug 27 09:16:17 AM UTC 24
Finished Aug 27 09:16:20 AM UTC 24
Peak memory 242128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183836960 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 56.edn_err.2183836960
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/56.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/56.edn_genbits.1511412567
Short name T625
Test name
Test status
Simulation time 97083121 ps
CPU time 2.03 seconds
Started Aug 27 09:16:16 AM UTC 24
Finished Aug 27 09:16:19 AM UTC 24
Peak memory 229772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511412567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 56.edn_genbits.1511412567
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/56.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/57.edn_alert.1749027803
Short name T121
Test name
Test status
Simulation time 40239151 ps
CPU time 1.62 seconds
Started Aug 27 09:16:18 AM UTC 24
Finished Aug 27 09:16:21 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749027803 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 57.edn_alert.1749027803
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/57.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/57.edn_err.2288056473
Short name T628
Test name
Test status
Simulation time 29796828 ps
CPU time 1.24 seconds
Started Aug 27 09:16:18 AM UTC 24
Finished Aug 27 09:16:20 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288056473 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 57.edn_err.2288056473
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/57.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/57.edn_genbits.1395226993
Short name T626
Test name
Test status
Simulation time 46254840 ps
CPU time 1.66 seconds
Started Aug 27 09:16:17 AM UTC 24
Finished Aug 27 09:16:20 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395226993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 57.edn_genbits.1395226993
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/57.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/58.edn_err.1876813983
Short name T631
Test name
Test status
Simulation time 30459488 ps
CPU time 1.63 seconds
Started Aug 27 09:16:19 AM UTC 24
Finished Aug 27 09:16:23 AM UTC 24
Peak memory 230316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876813983 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 58.edn_err.1876813983
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/58.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/58.edn_genbits.448851199
Short name T629
Test name
Test status
Simulation time 41705861 ps
CPU time 1.86 seconds
Started Aug 27 09:16:18 AM UTC 24
Finished Aug 27 09:16:21 AM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448851199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 58.edn_genbits.448851199
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/58.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/59.edn_alert.1825707689
Short name T632
Test name
Test status
Simulation time 55228815 ps
CPU time 1.81 seconds
Started Aug 27 09:16:21 AM UTC 24
Finished Aug 27 09:16:24 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825707689 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 59.edn_alert.1825707689
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/59.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/59.edn_err.407139739
Short name T633
Test name
Test status
Simulation time 19024561 ps
CPU time 1.58 seconds
Started Aug 27 09:16:21 AM UTC 24
Finished Aug 27 09:16:24 AM UTC 24
Peak memory 228724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407139739 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 59.edn_err.407139739
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/59.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/59.edn_genbits.1320522549
Short name T630
Test name
Test status
Simulation time 37924411 ps
CPU time 1.61 seconds
Started Aug 27 09:16:19 AM UTC 24
Finished Aug 27 09:16:23 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320522549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 59.edn_genbits.1320522549
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/59.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/6.edn_alert.3648395890
Short name T114
Test name
Test status
Simulation time 30749641 ps
CPU time 1.58 seconds
Started Aug 27 09:11:20 AM UTC 24
Finished Aug 27 09:11:23 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648395890 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 6.edn_alert.3648395890
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/6.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/6.edn_alert_test.869494658
Short name T377
Test name
Test status
Simulation time 35714576 ps
CPU time 1.18 seconds
Started Aug 27 09:11:23 AM UTC 24
Finished Aug 27 09:11:25 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869494658 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.869494658
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/6.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/6.edn_disable.2607759857
Short name T70
Test name
Test status
Simulation time 16885144 ps
CPU time 1.28 seconds
Started Aug 27 09:11:21 AM UTC 24
Finished Aug 27 09:11:24 AM UTC 24
Peak memory 216136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607759857 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2607759857
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/6.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/6.edn_disable_auto_req_mode.2836595479
Short name T163
Test name
Test status
Simulation time 48121027 ps
CPU time 1.44 seconds
Started Aug 27 09:11:21 AM UTC 24
Finished Aug 27 09:11:24 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836595479 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable_auto_req_mode.2836595479
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/6.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/6.edn_err.3954892122
Short name T205
Test name
Test status
Simulation time 18174905 ps
CPU time 1.41 seconds
Started Aug 27 09:11:21 AM UTC 24
Finished Aug 27 09:11:24 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954892122 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 6.edn_err.3954892122
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/6.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/6.edn_genbits.1839420806
Short name T301
Test name
Test status
Simulation time 51877917 ps
CPU time 1.13 seconds
Started Aug 27 09:11:18 AM UTC 24
Finished Aug 27 09:11:20 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839420806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_genbits.1839420806
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/6.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/6.edn_intr.3155004420
Short name T108
Test name
Test status
Simulation time 52814282 ps
CPU time 1.2 seconds
Started Aug 27 09:11:20 AM UTC 24
Finished Aug 27 09:11:23 AM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155004420 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 6.edn_intr.3155004420
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/6.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/6.edn_regwen.3085493736
Short name T322
Test name
Test status
Simulation time 19785851 ps
CPU time 1.34 seconds
Started Aug 27 09:11:18 AM UTC 24
Finished Aug 27 09:11:20 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085493736 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 6.edn_regwen.3085493736
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/6.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/6.edn_smoke.1074329186
Short name T376
Test name
Test status
Simulation time 17038786 ps
CPU time 1.28 seconds
Started Aug 27 09:11:18 AM UTC 24
Finished Aug 27 09:11:20 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074329186 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 6.edn_smoke.1074329186
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/6.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/6.edn_stress_all.1533802967
Short name T103
Test name
Test status
Simulation time 290999230 ps
CPU time 2.72 seconds
Started Aug 27 09:11:18 AM UTC 24
Finished Aug 27 09:11:22 AM UTC 24
Peak memory 229596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533802967 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.1533802967
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/6.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/60.edn_alert.2691367896
Short name T187
Test name
Test status
Simulation time 22655150 ps
CPU time 1.59 seconds
Started Aug 27 09:16:21 AM UTC 24
Finished Aug 27 09:16:24 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691367896 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 60.edn_alert.2691367896
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/60.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/60.edn_err.4286869193
Short name T635
Test name
Test status
Simulation time 26592921 ps
CPU time 1.27 seconds
Started Aug 27 09:16:23 AM UTC 24
Finished Aug 27 09:16:25 AM UTC 24
Peak memory 228184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286869193 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 60.edn_err.4286869193
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/60.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/60.edn_genbits.3179823409
Short name T634
Test name
Test status
Simulation time 104151841 ps
CPU time 2.16 seconds
Started Aug 27 09:16:21 AM UTC 24
Finished Aug 27 09:16:25 AM UTC 24
Peak memory 229280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179823409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3179823409
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/60.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/61.edn_alert.3535614673
Short name T165
Test name
Test status
Simulation time 156044253 ps
CPU time 1.98 seconds
Started Aug 27 09:16:24 AM UTC 24
Finished Aug 27 09:16:28 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535614673 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 61.edn_alert.3535614673
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/61.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/61.edn_err.4084870834
Short name T638
Test name
Test status
Simulation time 31626440 ps
CPU time 1.76 seconds
Started Aug 27 09:16:24 AM UTC 24
Finished Aug 27 09:16:28 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084870834 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 61.edn_err.4084870834
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/61.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/61.edn_genbits.2817013542
Short name T636
Test name
Test status
Simulation time 76513615 ps
CPU time 1.69 seconds
Started Aug 27 09:16:23 AM UTC 24
Finished Aug 27 09:16:26 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817013542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 61.edn_genbits.2817013542
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/61.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/62.edn_alert.3676880287
Short name T639
Test name
Test status
Simulation time 49101699 ps
CPU time 1.75 seconds
Started Aug 27 09:16:25 AM UTC 24
Finished Aug 27 09:16:29 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676880287 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 62.edn_alert.3676880287
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/62.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/62.edn_err.3748702468
Short name T204
Test name
Test status
Simulation time 18619211 ps
CPU time 1.5 seconds
Started Aug 27 09:16:25 AM UTC 24
Finished Aug 27 09:16:29 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748702468 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 62.edn_err.3748702468
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/62.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/62.edn_genbits.1659175731
Short name T637
Test name
Test status
Simulation time 72466870 ps
CPU time 1.66 seconds
Started Aug 27 09:16:24 AM UTC 24
Finished Aug 27 09:16:28 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659175731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1659175731
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/62.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/63.edn_alert.3212273337
Short name T641
Test name
Test status
Simulation time 33084600 ps
CPU time 1.59 seconds
Started Aug 27 09:16:26 AM UTC 24
Finished Aug 27 09:16:30 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212273337 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 63.edn_alert.3212273337
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/63.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/63.edn_err.2766674942
Short name T169
Test name
Test status
Simulation time 21329686 ps
CPU time 1.75 seconds
Started Aug 27 09:16:26 AM UTC 24
Finished Aug 27 09:16:30 AM UTC 24
Peak memory 237156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766674942 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 63.edn_err.2766674942
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/63.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/63.edn_genbits.4049834451
Short name T640
Test name
Test status
Simulation time 44658403 ps
CPU time 1.79 seconds
Started Aug 27 09:16:25 AM UTC 24
Finished Aug 27 09:16:29 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049834451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 63.edn_genbits.4049834451
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/63.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/64.edn_alert.1887202871
Short name T182
Test name
Test status
Simulation time 25094718 ps
CPU time 1.66 seconds
Started Aug 27 09:16:29 AM UTC 24
Finished Aug 27 09:16:33 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887202871 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 64.edn_alert.1887202871
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/64.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/64.edn_err.2243850995
Short name T644
Test name
Test status
Simulation time 23528592 ps
CPU time 1.53 seconds
Started Aug 27 09:16:29 AM UTC 24
Finished Aug 27 09:16:32 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243850995 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 64.edn_err.2243850995
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/64.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/64.edn_genbits.259018090
Short name T642
Test name
Test status
Simulation time 31878681 ps
CPU time 1.72 seconds
Started Aug 27 09:16:27 AM UTC 24
Finished Aug 27 09:16:31 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259018090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 64.edn_genbits.259018090
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/64.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/65.edn_alert.1684242699
Short name T225
Test name
Test status
Simulation time 37337389 ps
CPU time 1.93 seconds
Started Aug 27 09:16:30 AM UTC 24
Finished Aug 27 09:16:33 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684242699 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 65.edn_alert.1684242699
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/65.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/65.edn_err.4118014138
Short name T645
Test name
Test status
Simulation time 55992809 ps
CPU time 1.84 seconds
Started Aug 27 09:16:30 AM UTC 24
Finished Aug 27 09:16:33 AM UTC 24
Peak memory 230392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118014138 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 65.edn_err.4118014138
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/65.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/65.edn_genbits.4024019556
Short name T643
Test name
Test status
Simulation time 195940325 ps
CPU time 1.39 seconds
Started Aug 27 09:16:30 AM UTC 24
Finished Aug 27 09:16:32 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024019556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 65.edn_genbits.4024019556
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/65.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/66.edn_alert.1405976777
Short name T646
Test name
Test status
Simulation time 65102534 ps
CPU time 1.29 seconds
Started Aug 27 09:16:31 AM UTC 24
Finished Aug 27 09:16:33 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405976777 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 66.edn_alert.1405976777
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/66.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/66.edn_err.3988738548
Short name T193
Test name
Test status
Simulation time 18609319 ps
CPU time 1.44 seconds
Started Aug 27 09:16:31 AM UTC 24
Finished Aug 27 09:16:33 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988738548 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 66.edn_err.3988738548
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/66.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/66.edn_genbits.2220649145
Short name T647
Test name
Test status
Simulation time 214648558 ps
CPU time 2.33 seconds
Started Aug 27 09:16:30 AM UTC 24
Finished Aug 27 09:16:33 AM UTC 24
Peak memory 231712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220649145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 66.edn_genbits.2220649145
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/66.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/67.edn_alert.1995379032
Short name T650
Test name
Test status
Simulation time 43828114 ps
CPU time 1.65 seconds
Started Aug 27 09:16:33 AM UTC 24
Finished Aug 27 09:16:36 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995379032 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 67.edn_alert.1995379032
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/67.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/67.edn_err.2954417320
Short name T649
Test name
Test status
Simulation time 19399120 ps
CPU time 1.34 seconds
Started Aug 27 09:16:33 AM UTC 24
Finished Aug 27 09:16:35 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954417320 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 67.edn_err.2954417320
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/67.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/67.edn_genbits.1696869506
Short name T648
Test name
Test status
Simulation time 56380108 ps
CPU time 2.08 seconds
Started Aug 27 09:16:32 AM UTC 24
Finished Aug 27 09:16:35 AM UTC 24
Peak memory 229872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696869506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 67.edn_genbits.1696869506
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/67.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/68.edn_alert.1967916296
Short name T653
Test name
Test status
Simulation time 84146614 ps
CPU time 1.68 seconds
Started Aug 27 09:16:34 AM UTC 24
Finished Aug 27 09:16:37 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967916296 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 68.edn_alert.1967916296
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/68.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/68.edn_err.682251060
Short name T652
Test name
Test status
Simulation time 20509549 ps
CPU time 1.59 seconds
Started Aug 27 09:16:34 AM UTC 24
Finished Aug 27 09:16:37 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682251060 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 68.edn_err.682251060
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/68.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/68.edn_genbits.2939038123
Short name T655
Test name
Test status
Simulation time 70433580 ps
CPU time 2.8 seconds
Started Aug 27 09:16:34 AM UTC 24
Finished Aug 27 09:16:38 AM UTC 24
Peak memory 231716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939038123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2939038123
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/68.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/69.edn_alert.3162913007
Short name T654
Test name
Test status
Simulation time 88620435 ps
CPU time 1.84 seconds
Started Aug 27 09:16:34 AM UTC 24
Finished Aug 27 09:16:37 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162913007 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 69.edn_alert.3162913007
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/69.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/69.edn_err.2413006117
Short name T651
Test name
Test status
Simulation time 60750938 ps
CPU time 1.27 seconds
Started Aug 27 09:16:34 AM UTC 24
Finished Aug 27 09:16:37 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413006117 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 69.edn_err.2413006117
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/69.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/69.edn_genbits.2229366283
Short name T367
Test name
Test status
Simulation time 70013228 ps
CPU time 2.74 seconds
Started Aug 27 09:16:34 AM UTC 24
Finished Aug 27 09:16:38 AM UTC 24
Peak memory 231520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229366283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 69.edn_genbits.2229366283
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/69.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/7.edn_alert.1970464586
Short name T71
Test name
Test status
Simulation time 22796750 ps
CPU time 1.67 seconds
Started Aug 27 09:11:26 AM UTC 24
Finished Aug 27 09:11:29 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970464586 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 7.edn_alert.1970464586
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/7.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/7.edn_alert_test.3509406687
Short name T379
Test name
Test status
Simulation time 31875183 ps
CPU time 1.31 seconds
Started Aug 27 09:11:29 AM UTC 24
Finished Aug 27 09:11:32 AM UTC 24
Peak memory 216688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509406687 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3509406687
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/7.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/7.edn_disable.3246176736
Short name T50
Test name
Test status
Simulation time 22526250 ps
CPU time 1.15 seconds
Started Aug 27 09:11:27 AM UTC 24
Finished Aug 27 09:11:29 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246176736 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3246176736
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/7.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/7.edn_disable_auto_req_mode.732129088
Short name T78
Test name
Test status
Simulation time 60913300 ps
CPU time 1.77 seconds
Started Aug 27 09:11:28 AM UTC 24
Finished Aug 27 09:11:31 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732129088 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable_auto_req_mode.732129088
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/7.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/7.edn_err.55479865
Short name T100
Test name
Test status
Simulation time 18637383 ps
CPU time 1.53 seconds
Started Aug 27 09:11:27 AM UTC 24
Finished Aug 27 09:11:30 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55479865 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 7.edn_err.55479865
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/7.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/7.edn_intr.3796382189
Short name T34
Test name
Test status
Simulation time 22524468 ps
CPU time 1.34 seconds
Started Aug 27 09:11:26 AM UTC 24
Finished Aug 27 09:11:29 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796382189 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 7.edn_intr.3796382189
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/7.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/7.edn_regwen.3682706511
Short name T106
Test name
Test status
Simulation time 16344080 ps
CPU time 1.37 seconds
Started Aug 27 09:11:24 AM UTC 24
Finished Aug 27 09:11:26 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682706511 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 7.edn_regwen.3682706511
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/7.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/7.edn_smoke.3968251074
Short name T378
Test name
Test status
Simulation time 17345372 ps
CPU time 1.24 seconds
Started Aug 27 09:11:24 AM UTC 24
Finished Aug 27 09:11:26 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968251074 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 7.edn_smoke.3968251074
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/7.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/7.edn_stress_all_with_rand_reset.3896641239
Short name T36
Test name
Test status
Simulation time 273274921 ps
CPU time 10.44 seconds
Started Aug 27 09:11:25 AM UTC 24
Finished Aug 27 09:11:36 AM UTC 24
Peak memory 229592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3896641239 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_
with_rand_reset.3896641239
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/7.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/70.edn_alert.1301767562
Short name T152
Test name
Test status
Simulation time 23668584 ps
CPU time 1.63 seconds
Started Aug 27 09:16:36 AM UTC 24
Finished Aug 27 09:16:39 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301767562 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 70.edn_alert.1301767562
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/70.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/70.edn_err.1117304949
Short name T656
Test name
Test status
Simulation time 19204277 ps
CPU time 1.39 seconds
Started Aug 27 09:16:37 AM UTC 24
Finished Aug 27 09:16:39 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117304949 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 70.edn_err.1117304949
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/70.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/70.edn_genbits.2493315365
Short name T657
Test name
Test status
Simulation time 30740224 ps
CPU time 1.58 seconds
Started Aug 27 09:16:36 AM UTC 24
Finished Aug 27 09:16:39 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493315365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2493315365
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/70.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/71.edn_alert.812502561
Short name T658
Test name
Test status
Simulation time 39786091 ps
CPU time 1.62 seconds
Started Aug 27 09:16:38 AM UTC 24
Finished Aug 27 09:16:40 AM UTC 24
Peak memory 229744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812502561 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 71.edn_alert.812502561
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/71.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/71.edn_err.3190021490
Short name T180
Test name
Test status
Simulation time 19082768 ps
CPU time 1.28 seconds
Started Aug 27 09:16:38 AM UTC 24
Finished Aug 27 09:16:40 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190021490 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 71.edn_err.3190021490
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/71.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/71.edn_genbits.3827873561
Short name T659
Test name
Test status
Simulation time 41690610 ps
CPU time 2.06 seconds
Started Aug 27 09:16:38 AM UTC 24
Finished Aug 27 09:16:41 AM UTC 24
Peak memory 229524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827873561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 71.edn_genbits.3827873561
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/71.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/72.edn_alert.970248292
Short name T663
Test name
Test status
Simulation time 77827376 ps
CPU time 1.57 seconds
Started Aug 27 09:16:39 AM UTC 24
Finished Aug 27 09:16:42 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970248292 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 72.edn_alert.970248292
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/72.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/72.edn_err.1928637087
Short name T662
Test name
Test status
Simulation time 23208251 ps
CPU time 1.34 seconds
Started Aug 27 09:16:39 AM UTC 24
Finished Aug 27 09:16:42 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928637087 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 72.edn_err.1928637087
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/72.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/72.edn_genbits.166282263
Short name T661
Test name
Test status
Simulation time 43202349 ps
CPU time 1.94 seconds
Started Aug 27 09:16:38 AM UTC 24
Finished Aug 27 09:16:41 AM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166282263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 72.edn_genbits.166282263
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/72.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/73.edn_err.1332930418
Short name T135
Test name
Test status
Simulation time 36666996 ps
CPU time 1.21 seconds
Started Aug 27 09:16:40 AM UTC 24
Finished Aug 27 09:16:43 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332930418 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 73.edn_err.1332930418
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/73.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/73.edn_genbits.3856855268
Short name T664
Test name
Test status
Simulation time 40007825 ps
CPU time 1.97 seconds
Started Aug 27 09:16:39 AM UTC 24
Finished Aug 27 09:16:42 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856855268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 73.edn_genbits.3856855268
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/73.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/74.edn_alert.984609240
Short name T668
Test name
Test status
Simulation time 66653778 ps
CPU time 1.88 seconds
Started Aug 27 09:16:41 AM UTC 24
Finished Aug 27 09:16:44 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984609240 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 74.edn_alert.984609240
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/74.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/74.edn_err.1551232961
Short name T136
Test name
Test status
Simulation time 45988387 ps
CPU time 1.28 seconds
Started Aug 27 09:16:41 AM UTC 24
Finished Aug 27 09:16:44 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551232961 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 74.edn_err.1551232961
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/74.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/74.edn_genbits.3732144319
Short name T368
Test name
Test status
Simulation time 61971575 ps
CPU time 3.27 seconds
Started Aug 27 09:16:40 AM UTC 24
Finished Aug 27 09:16:45 AM UTC 24
Peak memory 231588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732144319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 74.edn_genbits.3732144319
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/74.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/75.edn_alert.3894035749
Short name T183
Test name
Test status
Simulation time 134886129 ps
CPU time 1.66 seconds
Started Aug 27 09:16:42 AM UTC 24
Finished Aug 27 09:16:44 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894035749 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 75.edn_alert.3894035749
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/75.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/75.edn_err.326897312
Short name T157
Test name
Test status
Simulation time 47181952 ps
CPU time 1.48 seconds
Started Aug 27 09:16:43 AM UTC 24
Finished Aug 27 09:16:46 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326897312 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 75.edn_err.326897312
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/75.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/75.edn_genbits.4028895929
Short name T666
Test name
Test status
Simulation time 26386742 ps
CPU time 1.3 seconds
Started Aug 27 09:16:41 AM UTC 24
Finished Aug 27 09:16:44 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028895929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 75.edn_genbits.4028895929
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/75.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/76.edn_alert.2644087731
Short name T669
Test name
Test status
Simulation time 60169247 ps
CPU time 1.46 seconds
Started Aug 27 09:16:44 AM UTC 24
Finished Aug 27 09:16:46 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644087731 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 76.edn_alert.2644087731
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/76.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/76.edn_err.2926562259
Short name T181
Test name
Test status
Simulation time 19748229 ps
CPU time 1.56 seconds
Started Aug 27 09:16:44 AM UTC 24
Finished Aug 27 09:16:46 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926562259 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 76.edn_err.2926562259
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/76.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/76.edn_genbits.4012818388
Short name T365
Test name
Test status
Simulation time 192745427 ps
CPU time 2.87 seconds
Started Aug 27 09:16:43 AM UTC 24
Finished Aug 27 09:16:47 AM UTC 24
Peak memory 229444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012818388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 76.edn_genbits.4012818388
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/76.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/77.edn_alert.4242043754
Short name T660
Test name
Test status
Simulation time 44560391 ps
CPU time 1.7 seconds
Started Aug 27 09:16:45 AM UTC 24
Finished Aug 27 09:16:48 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242043754 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 77.edn_alert.4242043754
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/77.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/77.edn_err.1483519154
Short name T665
Test name
Test status
Simulation time 36614255 ps
CPU time 1.56 seconds
Started Aug 27 09:16:45 AM UTC 24
Finished Aug 27 09:16:48 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483519154 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 77.edn_err.1483519154
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/77.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/77.edn_genbits.1189033697
Short name T335
Test name
Test status
Simulation time 35149418 ps
CPU time 2.1 seconds
Started Aug 27 09:16:44 AM UTC 24
Finished Aug 27 09:16:47 AM UTC 24
Peak memory 229520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189033697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 77.edn_genbits.1189033697
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/77.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/78.edn_alert.1590114292
Short name T147
Test name
Test status
Simulation time 57996067 ps
CPU time 1.78 seconds
Started Aug 27 09:16:45 AM UTC 24
Finished Aug 27 09:16:48 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590114292 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 78.edn_alert.1590114292
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/78.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/78.edn_err.872734454
Short name T670
Test name
Test status
Simulation time 19265750 ps
CPU time 1.45 seconds
Started Aug 27 09:16:45 AM UTC 24
Finished Aug 27 09:16:48 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872734454 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 78.edn_err.872734454
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/78.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/78.edn_genbits.383730382
Short name T671
Test name
Test status
Simulation time 31923828 ps
CPU time 1.54 seconds
Started Aug 27 09:16:45 AM UTC 24
Finished Aug 27 09:16:48 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383730382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 78.edn_genbits.383730382
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/78.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/79.edn_alert.2291743104
Short name T222
Test name
Test status
Simulation time 29556915 ps
CPU time 1.88 seconds
Started Aug 27 09:16:46 AM UTC 24
Finished Aug 27 09:16:49 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291743104 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 79.edn_alert.2291743104
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/79.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/79.edn_err.379819800
Short name T674
Test name
Test status
Simulation time 64013318 ps
CPU time 1.65 seconds
Started Aug 27 09:16:47 AM UTC 24
Finished Aug 27 09:16:50 AM UTC 24
Peak memory 244400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379819800 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 79.edn_err.379819800
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/79.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/79.edn_genbits.1651760647
Short name T672
Test name
Test status
Simulation time 66491437 ps
CPU time 1.92 seconds
Started Aug 27 09:16:46 AM UTC 24
Finished Aug 27 09:16:49 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651760647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 79.edn_genbits.1651760647
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/79.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/8.edn_alert_test.3589378338
Short name T234
Test name
Test status
Simulation time 33806214 ps
CPU time 1.3 seconds
Started Aug 27 09:11:36 AM UTC 24
Finished Aug 27 09:11:39 AM UTC 24
Peak memory 217288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589378338 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3589378338
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/8.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/8.edn_disable.2731394876
Short name T233
Test name
Test status
Simulation time 47245651 ps
CPU time 1.17 seconds
Started Aug 27 09:11:34 AM UTC 24
Finished Aug 27 09:11:36 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731394876 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2731394876
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/8.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/8.edn_genbits.1175434745
Short name T308
Test name
Test status
Simulation time 92704664 ps
CPU time 1.31 seconds
Started Aug 27 09:11:30 AM UTC 24
Finished Aug 27 09:11:33 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175434745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1175434745
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/8.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/8.edn_intr.3765403993
Short name T251
Test name
Test status
Simulation time 22769068 ps
CPU time 1.44 seconds
Started Aug 27 09:11:33 AM UTC 24
Finished Aug 27 09:11:36 AM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765403993 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 8.edn_intr.3765403993
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/8.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/8.edn_regwen.2653709465
Short name T323
Test name
Test status
Simulation time 124232384 ps
CPU time 1.4 seconds
Started Aug 27 09:11:30 AM UTC 24
Finished Aug 27 09:11:33 AM UTC 24
Peak memory 216016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653709465 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 8.edn_regwen.2653709465
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/8.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/8.edn_smoke.2739969341
Short name T380
Test name
Test status
Simulation time 26642376 ps
CPU time 1.27 seconds
Started Aug 27 09:11:30 AM UTC 24
Finished Aug 27 09:11:33 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739969341 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 8.edn_smoke.2739969341
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/8.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/80.edn_alert.1639606339
Short name T675
Test name
Test status
Simulation time 38964664 ps
CPU time 1.72 seconds
Started Aug 27 09:16:47 AM UTC 24
Finished Aug 27 09:16:50 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639606339 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 80.edn_alert.1639606339
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/80.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/80.edn_err.4186428037
Short name T137
Test name
Test status
Simulation time 34374733 ps
CPU time 1.37 seconds
Started Aug 27 09:16:49 AM UTC 24
Finished Aug 27 09:16:51 AM UTC 24
Peak memory 244216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186428037 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 80.edn_err.4186428037
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/80.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/80.edn_genbits.1696892832
Short name T673
Test name
Test status
Simulation time 47788163 ps
CPU time 1.49 seconds
Started Aug 27 09:16:47 AM UTC 24
Finished Aug 27 09:16:50 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696892832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 80.edn_genbits.1696892832
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/80.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/81.edn_alert.1523042969
Short name T677
Test name
Test status
Simulation time 27808485 ps
CPU time 1.39 seconds
Started Aug 27 09:16:49 AM UTC 24
Finished Aug 27 09:16:51 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523042969 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 81.edn_alert.1523042969
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/81.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/81.edn_err.4254747430
Short name T676
Test name
Test status
Simulation time 28327888 ps
CPU time 1.36 seconds
Started Aug 27 09:16:49 AM UTC 24
Finished Aug 27 09:16:51 AM UTC 24
Peak memory 245784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254747430 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 81.edn_err.4254747430
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/81.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/81.edn_genbits.3271850993
Short name T684
Test name
Test status
Simulation time 157750869 ps
CPU time 4.21 seconds
Started Aug 27 09:16:49 AM UTC 24
Finished Aug 27 09:16:54 AM UTC 24
Peak memory 231780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271850993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3271850993
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/81.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/82.edn_alert.1554873022
Short name T678
Test name
Test status
Simulation time 94061241 ps
CPU time 1.7 seconds
Started Aug 27 09:16:49 AM UTC 24
Finished Aug 27 09:16:52 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554873022 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 82.edn_alert.1554873022
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/82.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/82.edn_err.3720693169
Short name T680
Test name
Test status
Simulation time 57121668 ps
CPU time 1.9 seconds
Started Aug 27 09:16:50 AM UTC 24
Finished Aug 27 09:16:53 AM UTC 24
Peak memory 242084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720693169 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 82.edn_err.3720693169
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/82.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/82.edn_genbits.560371996
Short name T679
Test name
Test status
Simulation time 31615325 ps
CPU time 1.91 seconds
Started Aug 27 09:16:49 AM UTC 24
Finished Aug 27 09:16:52 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560371996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 82.edn_genbits.560371996
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/82.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/83.edn_alert.3421866105
Short name T683
Test name
Test status
Simulation time 25800306 ps
CPU time 1.44 seconds
Started Aug 27 09:16:51 AM UTC 24
Finished Aug 27 09:16:53 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421866105 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 83.edn_alert.3421866105
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/83.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/83.edn_err.1451929101
Short name T210
Test name
Test status
Simulation time 79280036 ps
CPU time 1.24 seconds
Started Aug 27 09:16:51 AM UTC 24
Finished Aug 27 09:16:53 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451929101 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 83.edn_err.1451929101
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/83.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/83.edn_genbits.787104370
Short name T681
Test name
Test status
Simulation time 70821015 ps
CPU time 2.2 seconds
Started Aug 27 09:16:50 AM UTC 24
Finished Aug 27 09:16:53 AM UTC 24
Peak memory 231608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787104370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 83.edn_genbits.787104370
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/83.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/84.edn_alert.332325503
Short name T686
Test name
Test status
Simulation time 45095099 ps
CPU time 1.59 seconds
Started Aug 27 09:16:52 AM UTC 24
Finished Aug 27 09:16:55 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332325503 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 84.edn_alert.332325503
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/84.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/84.edn_err.2918773754
Short name T685
Test name
Test status
Simulation time 28594667 ps
CPU time 1.43 seconds
Started Aug 27 09:16:52 AM UTC 24
Finished Aug 27 09:16:55 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918773754 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 84.edn_err.2918773754
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/84.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/84.edn_genbits.2260351255
Short name T682
Test name
Test status
Simulation time 65391079 ps
CPU time 1.1 seconds
Started Aug 27 09:16:51 AM UTC 24
Finished Aug 27 09:16:53 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260351255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2260351255
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/84.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/85.edn_alert.3276662652
Short name T167
Test name
Test status
Simulation time 48163623 ps
CPU time 1.82 seconds
Started Aug 27 09:16:52 AM UTC 24
Finished Aug 27 09:16:55 AM UTC 24
Peak memory 226356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276662652 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 85.edn_alert.3276662652
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/85.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/85.edn_err.2786561356
Short name T219
Test name
Test status
Simulation time 19496715 ps
CPU time 1.32 seconds
Started Aug 27 09:16:52 AM UTC 24
Finished Aug 27 09:16:55 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786561356 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 85.edn_err.2786561356
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/85.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/85.edn_genbits.4266990066
Short name T687
Test name
Test status
Simulation time 55790513 ps
CPU time 2.52 seconds
Started Aug 27 09:16:52 AM UTC 24
Finished Aug 27 09:16:56 AM UTC 24
Peak memory 229520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266990066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 85.edn_genbits.4266990066
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/85.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/86.edn_alert.4001894959
Short name T688
Test name
Test status
Simulation time 66867541 ps
CPU time 1.55 seconds
Started Aug 27 09:16:54 AM UTC 24
Finished Aug 27 09:16:56 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001894959 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 86.edn_alert.4001894959
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/86.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/86.edn_err.2217159792
Short name T689
Test name
Test status
Simulation time 29293626 ps
CPU time 1.68 seconds
Started Aug 27 09:16:54 AM UTC 24
Finished Aug 27 09:16:56 AM UTC 24
Peak memory 242188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217159792 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 86.edn_err.2217159792
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/86.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/86.edn_genbits.3703416821
Short name T356
Test name
Test status
Simulation time 48678427 ps
CPU time 2.49 seconds
Started Aug 27 09:16:54 AM UTC 24
Finished Aug 27 09:16:57 AM UTC 24
Peak memory 229716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703416821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3703416821
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/86.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/87.edn_alert.2537141578
Short name T294
Test name
Test status
Simulation time 29365963 ps
CPU time 1.85 seconds
Started Aug 27 09:16:55 AM UTC 24
Finished Aug 27 09:16:58 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537141578 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 87.edn_alert.2537141578
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/87.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/87.edn_err.3812131313
Short name T690
Test name
Test status
Simulation time 18657205 ps
CPU time 1.46 seconds
Started Aug 27 09:16:55 AM UTC 24
Finished Aug 27 09:16:57 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812131313 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 87.edn_err.3812131313
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/87.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/87.edn_genbits.3992150309
Short name T691
Test name
Test status
Simulation time 52790984 ps
CPU time 2.73 seconds
Started Aug 27 09:16:54 AM UTC 24
Finished Aug 27 09:16:57 AM UTC 24
Peak memory 229784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992150309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3992150309
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/87.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/88.edn_alert.4075595416
Short name T693
Test name
Test status
Simulation time 24725395 ps
CPU time 1.68 seconds
Started Aug 27 09:16:56 AM UTC 24
Finished Aug 27 09:16:59 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075595416 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 88.edn_alert.4075595416
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/88.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/88.edn_err.535988095
Short name T212
Test name
Test status
Simulation time 20426733 ps
CPU time 1.61 seconds
Started Aug 27 09:16:56 AM UTC 24
Finished Aug 27 09:16:59 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535988095 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 88.edn_err.535988095
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/88.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/88.edn_genbits.1944746911
Short name T692
Test name
Test status
Simulation time 49622894 ps
CPU time 1.33 seconds
Started Aug 27 09:16:56 AM UTC 24
Finished Aug 27 09:16:58 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944746911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1944746911
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/88.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/89.edn_alert.3051995938
Short name T697
Test name
Test status
Simulation time 39600637 ps
CPU time 1.62 seconds
Started Aug 27 09:16:57 AM UTC 24
Finished Aug 27 09:17:00 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051995938 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 89.edn_alert.3051995938
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/89.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/89.edn_err.1060664224
Short name T696
Test name
Test status
Simulation time 57246071 ps
CPU time 1.23 seconds
Started Aug 27 09:16:57 AM UTC 24
Finished Aug 27 09:16:59 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060664224 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 89.edn_err.1060664224
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/89.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/89.edn_genbits.1735338617
Short name T694
Test name
Test status
Simulation time 35939971 ps
CPU time 1.82 seconds
Started Aug 27 09:16:56 AM UTC 24
Finished Aug 27 09:16:59 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735338617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1735338617
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/89.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/9.edn_alert.382683779
Short name T88
Test name
Test status
Simulation time 50258369 ps
CPU time 1.67 seconds
Started Aug 27 09:11:40 AM UTC 24
Finished Aug 27 09:11:43 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382683779 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 9.edn_alert.382683779
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/9.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/9.edn_alert_test.1957148431
Short name T383
Test name
Test status
Simulation time 20866262 ps
CPU time 1.22 seconds
Started Aug 27 09:11:43 AM UTC 24
Finished Aug 27 09:11:45 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957148431 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1957148431
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/9.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/9.edn_disable.1084459182
Short name T91
Test name
Test status
Simulation time 35409744 ps
CPU time 1.19 seconds
Started Aug 27 09:11:41 AM UTC 24
Finished Aug 27 09:11:43 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084459182 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1084459182
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/9.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/9.edn_disable_auto_req_mode.597997810
Short name T92
Test name
Test status
Simulation time 111944886 ps
CPU time 1.93 seconds
Started Aug 27 09:11:42 AM UTC 24
Finished Aug 27 09:11:45 AM UTC 24
Peak memory 226448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597997810 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable_auto_req_mode.597997810
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/9.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/9.edn_err.1551422967
Short name T8
Test name
Test status
Simulation time 43678115 ps
CPU time 1.41 seconds
Started Aug 27 09:11:41 AM UTC 24
Finished Aug 27 09:11:43 AM UTC 24
Peak memory 236964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551422967 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 9.edn_err.1551422967
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/9.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/9.edn_genbits.3105516266
Short name T361
Test name
Test status
Simulation time 34842561 ps
CPU time 2.34 seconds
Started Aug 27 09:11:38 AM UTC 24
Finished Aug 27 09:11:41 AM UTC 24
Peak memory 229736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105516266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_genbits.3105516266
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/9.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/9.edn_intr.2308336334
Short name T381
Test name
Test status
Simulation time 26166616 ps
CPU time 1.44 seconds
Started Aug 27 09:11:40 AM UTC 24
Finished Aug 27 09:11:42 AM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308336334 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 9.edn_intr.2308336334
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/9.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/9.edn_regwen.3586293997
Short name T236
Test name
Test status
Simulation time 56778017 ps
CPU time 1.3 seconds
Started Aug 27 09:11:38 AM UTC 24
Finished Aug 27 09:11:40 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586293997 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 9.edn_regwen.3586293997
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/9.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/9.edn_smoke.2673528555
Short name T235
Test name
Test status
Simulation time 16423205 ps
CPU time 1.32 seconds
Started Aug 27 09:11:37 AM UTC 24
Finished Aug 27 09:11:40 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673528555 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 9.edn_smoke.2673528555
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/9.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/9.edn_stress_all.2231977528
Short name T104
Test name
Test status
Simulation time 504532099 ps
CPU time 7.94 seconds
Started Aug 27 09:11:38 AM UTC 24
Finished Aug 27 09:11:47 AM UTC 24
Peak memory 229516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231977528 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2231977528
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/9.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/9.edn_stress_all_with_rand_reset.3379600480
Short name T230
Test name
Test status
Simulation time 15438061230 ps
CPU time 70.37 seconds
Started Aug 27 09:11:40 AM UTC 24
Finished Aug 27 09:12:52 AM UTC 24
Peak memory 227672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3379600480 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_
with_rand_reset.3379600480
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/9.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/90.edn_alert.144762540
Short name T698
Test name
Test status
Simulation time 235667210 ps
CPU time 1.42 seconds
Started Aug 27 09:16:58 AM UTC 24
Finished Aug 27 09:17:01 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144762540 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 90.edn_alert.144762540
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/90.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/90.edn_err.2646695639
Short name T699
Test name
Test status
Simulation time 20287450 ps
CPU time 1.53 seconds
Started Aug 27 09:16:58 AM UTC 24
Finished Aug 27 09:17:01 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646695639 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 90.edn_err.2646695639
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/90.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/90.edn_genbits.1357468187
Short name T695
Test name
Test status
Simulation time 74540881 ps
CPU time 1.17 seconds
Started Aug 27 09:16:57 AM UTC 24
Finished Aug 27 09:16:59 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357468187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1357468187
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/90.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/91.edn_alert.1189753973
Short name T700
Test name
Test status
Simulation time 105480047 ps
CPU time 1.73 seconds
Started Aug 27 09:16:58 AM UTC 24
Finished Aug 27 09:17:01 AM UTC 24
Peak memory 232520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189753973 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 91.edn_alert.1189753973
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/91.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/91.edn_err.3700240040
Short name T702
Test name
Test status
Simulation time 32402591 ps
CPU time 1.54 seconds
Started Aug 27 09:17:00 AM UTC 24
Finished Aug 27 09:17:02 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700240040 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 91.edn_err.3700240040
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/91.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/91.edn_genbits.1659287107
Short name T348
Test name
Test status
Simulation time 66552827 ps
CPU time 3.12 seconds
Started Aug 27 09:16:58 AM UTC 24
Finished Aug 27 09:17:03 AM UTC 24
Peak memory 231860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659287107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 91.edn_genbits.1659287107
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/91.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/92.edn_alert.1430532065
Short name T704
Test name
Test status
Simulation time 281411712 ps
CPU time 1.91 seconds
Started Aug 27 09:17:00 AM UTC 24
Finished Aug 27 09:17:03 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430532065 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 92.edn_alert.1430532065
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/92.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/92.edn_err.576105547
Short name T701
Test name
Test status
Simulation time 32699706 ps
CPU time 1.06 seconds
Started Aug 27 09:17:00 AM UTC 24
Finished Aug 27 09:17:02 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576105547 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 92.edn_err.576105547
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/92.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/92.edn_genbits.3076592895
Short name T703
Test name
Test status
Simulation time 127225322 ps
CPU time 1.75 seconds
Started Aug 27 09:17:00 AM UTC 24
Finished Aug 27 09:17:02 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076592895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3076592895
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/92.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/93.edn_alert.4110515748
Short name T706
Test name
Test status
Simulation time 90944672 ps
CPU time 1.56 seconds
Started Aug 27 09:17:01 AM UTC 24
Finished Aug 27 09:17:03 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110515748 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 93.edn_alert.4110515748
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/93.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/93.edn_err.632908969
Short name T707
Test name
Test status
Simulation time 74816944 ps
CPU time 1.59 seconds
Started Aug 27 09:17:01 AM UTC 24
Finished Aug 27 09:17:03 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632908969 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 93.edn_err.632908969
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/93.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/93.edn_genbits.4078306320
Short name T705
Test name
Test status
Simulation time 94383153 ps
CPU time 1.38 seconds
Started Aug 27 09:17:01 AM UTC 24
Finished Aug 27 09:17:03 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078306320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 93.edn_genbits.4078306320
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/93.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/94.edn_alert.3188631717
Short name T709
Test name
Test status
Simulation time 43246145 ps
CPU time 1.6 seconds
Started Aug 27 09:17:02 AM UTC 24
Finished Aug 27 09:17:05 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188631717 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 94.edn_alert.3188631717
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/94.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/94.edn_err.3307931994
Short name T708
Test name
Test status
Simulation time 52525838 ps
CPU time 1.52 seconds
Started Aug 27 09:17:02 AM UTC 24
Finished Aug 27 09:17:05 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307931994 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 94.edn_err.3307931994
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/94.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/94.edn_genbits.1335492409
Short name T359
Test name
Test status
Simulation time 39947464 ps
CPU time 1.69 seconds
Started Aug 27 09:17:02 AM UTC 24
Finished Aug 27 09:17:05 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335492409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1335492409
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/94.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/95.edn_alert.1700658737
Short name T712
Test name
Test status
Simulation time 27662981 ps
CPU time 1.85 seconds
Started Aug 27 09:17:03 AM UTC 24
Finished Aug 27 09:17:06 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700658737 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 95.edn_alert.1700658737
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/95.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/95.edn_err.1072165391
Short name T710
Test name
Test status
Simulation time 30038576 ps
CPU time 1.4 seconds
Started Aug 27 09:17:03 AM UTC 24
Finished Aug 27 09:17:06 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072165391 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 95.edn_err.1072165391
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/95.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/95.edn_genbits.3346321857
Short name T711
Test name
Test status
Simulation time 144601050 ps
CPU time 1.61 seconds
Started Aug 27 09:17:03 AM UTC 24
Finished Aug 27 09:17:06 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346321857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 95.edn_genbits.3346321857
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/95.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/96.edn_alert.406951690
Short name T713
Test name
Test status
Simulation time 30143199 ps
CPU time 1.88 seconds
Started Aug 27 09:17:03 AM UTC 24
Finished Aug 27 09:17:06 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406951690 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 96.edn_alert.406951690
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/96.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/96.edn_err.218903573
Short name T714
Test name
Test status
Simulation time 49937719 ps
CPU time 1.24 seconds
Started Aug 27 09:17:04 AM UTC 24
Finished Aug 27 09:17:07 AM UTC 24
Peak memory 236940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218903573 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 96.edn_err.218903573
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/96.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/96.edn_genbits.3499084533
Short name T716
Test name
Test status
Simulation time 147697260 ps
CPU time 2.9 seconds
Started Aug 27 09:17:03 AM UTC 24
Finished Aug 27 09:17:07 AM UTC 24
Peak memory 231760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499084533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 96.edn_genbits.3499084533
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/96.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/97.edn_alert.385806636
Short name T717
Test name
Test status
Simulation time 29009717 ps
CPU time 1.83 seconds
Started Aug 27 09:17:05 AM UTC 24
Finished Aug 27 09:17:07 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385806636 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 97.edn_alert.385806636
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/97.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/97.edn_err.733995340
Short name T718
Test name
Test status
Simulation time 22112400 ps
CPU time 0.95 seconds
Started Aug 27 09:17:06 AM UTC 24
Finished Aug 27 09:17:08 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733995340 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 97.edn_err.733995340
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/97.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/97.edn_genbits.1080556538
Short name T715
Test name
Test status
Simulation time 34989272 ps
CPU time 1.42 seconds
Started Aug 27 09:17:04 AM UTC 24
Finished Aug 27 09:17:07 AM UTC 24
Peak memory 228344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080556538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 97.edn_genbits.1080556538
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/97.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/98.edn_alert.3526489769
Short name T161
Test name
Test status
Simulation time 28947222 ps
CPU time 1.49 seconds
Started Aug 27 09:17:06 AM UTC 24
Finished Aug 27 09:17:08 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526489769 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 98.edn_alert.3526489769
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/98.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/98.edn_err.1251077990
Short name T719
Test name
Test status
Simulation time 21672907 ps
CPU time 1.24 seconds
Started Aug 27 09:17:07 AM UTC 24
Finished Aug 27 09:17:09 AM UTC 24
Peak memory 245660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251077990 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 98.edn_err.1251077990
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/98.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/98.edn_genbits.4085469286
Short name T357
Test name
Test status
Simulation time 35418589 ps
CPU time 1.83 seconds
Started Aug 27 09:17:06 AM UTC 24
Finished Aug 27 09:17:08 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085469286 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 98.edn_genbits.4085469286
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/98.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/99.edn_alert.4278427644
Short name T295
Test name
Test status
Simulation time 62728872 ps
CPU time 1.91 seconds
Started Aug 27 09:17:07 AM UTC 24
Finished Aug 27 09:17:10 AM UTC 24
Peak memory 226356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278427644 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 99.edn_alert.4278427644
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/99.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default/99.edn_err.3278194645
Short name T720
Test name
Test status
Simulation time 28678340 ps
CPU time 1.81 seconds
Started Aug 27 09:17:07 AM UTC 24
Finished Aug 27 09:17:10 AM UTC 24
Peak memory 242068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278194645 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 99.edn_err.3278194645
Directory /workspaces/repo/scratch/os_regression_2024_08_26/edn-sim-vcs/99.edn_err/latest
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