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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.75 98.25 93.97 97.02 91.86 96.37 99.77 92.99


Total test records in report: 1110
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1005 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2160133520 Aug 28 10:49:45 PM UTC 24 Aug 28 10:49:48 PM UTC 24 49225388 ps
T1006 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_errors.132701572 Aug 28 10:49:44 PM UTC 24 Aug 28 10:49:49 PM UTC 24 470736792 ps
T1007 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_errors.1762040370 Aug 28 10:49:45 PM UTC 24 Aug 28 10:49:49 PM UTC 24 35845839 ps
T1008 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_rw.2717459089 Aug 28 10:49:47 PM UTC 24 Aug 28 10:49:49 PM UTC 24 57122469 ps
T1009 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/7.edn_intr_test.3624314894 Aug 28 10:49:47 PM UTC 24 Aug 28 10:49:49 PM UTC 24 12431595 ps
T1010 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/8.edn_intr_test.3593816763 Aug 28 10:49:47 PM UTC 24 Aug 28 10:49:49 PM UTC 24 20175229 ps
T1011 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/7.edn_same_csr_outstanding.491113456 Aug 28 10:49:47 PM UTC 24 Aug 28 10:49:50 PM UTC 24 110025447 ps
T1012 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1987378756 Aug 28 10:49:47 PM UTC 24 Aug 28 10:49:50 PM UTC 24 45188956 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_intg_err.4255886709 Aug 28 10:49:45 PM UTC 24 Aug 28 10:49:50 PM UTC 24 424432348 ps
T1013 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_rw.1142653985 Aug 28 10:49:48 PM UTC 24 Aug 28 10:49:50 PM UTC 24 53804418 ps
T1014 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/8.edn_same_csr_outstanding.2015827790 Aug 28 10:49:48 PM UTC 24 Aug 28 10:49:50 PM UTC 24 68045917 ps
T1015 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_intg_err.734573267 Aug 28 10:49:47 PM UTC 24 Aug 28 10:49:50 PM UTC 24 125239023 ps
T1016 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/9.edn_intr_test.406843058 Aug 28 10:49:48 PM UTC 24 Aug 28 10:49:51 PM UTC 24 11052542 ps
T1017 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_intg_err.3068961692 Aug 28 10:49:47 PM UTC 24 Aug 28 10:49:51 PM UTC 24 167392809 ps
T1018 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/10.edn_intr_test.2633189597 Aug 28 10:49:49 PM UTC 24 Aug 28 10:49:51 PM UTC 24 25821684 ps
T1019 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/9.edn_same_csr_outstanding.3361107877 Aug 28 10:49:48 PM UTC 24 Aug 28 10:49:51 PM UTC 24 61216516 ps
T1020 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_rw.3048664832 Aug 28 10:49:48 PM UTC 24 Aug 28 10:49:51 PM UTC 24 14634768 ps
T1021 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1203554832 Aug 28 10:49:48 PM UTC 24 Aug 28 10:49:51 PM UTC 24 35028565 ps
T1022 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.4063923044 Aug 28 10:49:48 PM UTC 24 Aug 28 10:49:51 PM UTC 24 20321608 ps
T1023 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_intg_err.620253382 Aug 28 10:49:48 PM UTC 24 Aug 28 10:49:52 PM UTC 24 355128751 ps
T1024 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_errors.3330436774 Aug 28 10:49:48 PM UTC 24 Aug 28 10:49:52 PM UTC 24 147773194 ps
T1025 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_errors.2838692093 Aug 28 10:49:47 PM UTC 24 Aug 28 10:49:52 PM UTC 24 98079102 ps
T1026 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_errors.641686214 Aug 28 10:49:49 PM UTC 24 Aug 28 10:49:53 PM UTC 24 368908026 ps
T1027 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2269526429 Aug 28 10:49:50 PM UTC 24 Aug 28 10:49:53 PM UTC 24 193405793 ps
T1028 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/10.edn_same_csr_outstanding.2518086938 Aug 28 10:49:50 PM UTC 24 Aug 28 10:49:53 PM UTC 24 31254750 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_intg_err.142695659 Aug 28 10:49:49 PM UTC 24 Aug 28 10:49:53 PM UTC 24 90753342 ps
T1029 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_rw.1047823440 Aug 28 10:49:51 PM UTC 24 Aug 28 10:49:54 PM UTC 24 23173315 ps
T1030 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_errors.3715376380 Aug 28 10:49:50 PM UTC 24 Aug 28 10:49:54 PM UTC 24 31152813 ps
T1031 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/11.edn_same_csr_outstanding.3336728244 Aug 28 10:49:51 PM UTC 24 Aug 28 10:49:54 PM UTC 24 28461606 ps
T1032 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/11.edn_intr_test.754028545 Aug 28 10:49:51 PM UTC 24 Aug 28 10:49:54 PM UTC 24 12574832 ps
T1033 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_intg_err.1366445024 Aug 28 10:49:50 PM UTC 24 Aug 28 10:49:54 PM UTC 24 608866409 ps
T1034 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/12.edn_intr_test.2501362477 Aug 28 10:49:51 PM UTC 24 Aug 28 10:49:54 PM UTC 24 41460298 ps
T1035 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_rw.3879921196 Aug 28 10:49:51 PM UTC 24 Aug 28 10:49:55 PM UTC 24 46181187 ps
T1036 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3857275973 Aug 28 10:49:51 PM UTC 24 Aug 28 10:49:55 PM UTC 24 73980976 ps
T1037 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/12.edn_same_csr_outstanding.78030730 Aug 28 10:49:51 PM UTC 24 Aug 28 10:49:55 PM UTC 24 186823134 ps
T1038 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1094556033 Aug 28 10:49:52 PM UTC 24 Aug 28 10:49:55 PM UTC 24 22008528 ps
T1039 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/13.edn_intr_test.2988498749 Aug 28 10:49:53 PM UTC 24 Aug 28 10:49:55 PM UTC 24 12243161 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_rw.952315162 Aug 28 10:49:53 PM UTC 24 Aug 28 10:49:55 PM UTC 24 57566369 ps
T1040 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_errors.3709593322 Aug 28 10:49:51 PM UTC 24 Aug 28 10:49:56 PM UTC 24 70799258 ps
T1041 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1567048882 Aug 28 10:49:53 PM UTC 24 Aug 28 10:49:56 PM UTC 24 50162365 ps
T1042 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_errors.2980255982 Aug 28 10:49:53 PM UTC 24 Aug 28 10:49:56 PM UTC 24 23265324 ps
T1043 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_intg_err.624931669 Aug 28 10:49:51 PM UTC 24 Aug 28 10:49:56 PM UTC 24 86272386 ps
T1044 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/13.edn_same_csr_outstanding.621513743 Aug 28 10:49:53 PM UTC 24 Aug 28 10:49:56 PM UTC 24 118464177 ps
T1045 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/14.edn_intr_test.671634816 Aug 28 10:49:54 PM UTC 24 Aug 28 10:49:56 PM UTC 24 15614169 ps
T1046 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_rw.1983721735 Aug 28 10:49:54 PM UTC 24 Aug 28 10:49:57 PM UTC 24 30961521 ps
T1047 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.4238470350 Aug 28 10:49:54 PM UTC 24 Aug 28 10:49:57 PM UTC 24 21219674 ps
T1048 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/14.edn_same_csr_outstanding.1696592041 Aug 28 10:49:54 PM UTC 24 Aug 28 10:49:57 PM UTC 24 62213848 ps
T1049 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_rw.1107037229 Aug 28 10:49:55 PM UTC 24 Aug 28 10:49:58 PM UTC 24 41043924 ps
T1050 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/15.edn_intr_test.1035569939 Aug 28 10:49:55 PM UTC 24 Aug 28 10:49:58 PM UTC 24 21851407 ps
T1051 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_errors.3811743057 Aug 28 10:49:54 PM UTC 24 Aug 28 10:49:58 PM UTC 24 95442226 ps
T1052 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/15.edn_same_csr_outstanding.3008894694 Aug 28 10:49:55 PM UTC 24 Aug 28 10:49:58 PM UTC 24 74179921 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_intg_err.641941317 Aug 28 10:49:53 PM UTC 24 Aug 28 10:49:58 PM UTC 24 104529966 ps
T1053 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/16.edn_intr_test.3779693985 Aug 28 10:49:56 PM UTC 24 Aug 28 10:49:58 PM UTC 24 53460108 ps
T1054 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_rw.3717592409 Aug 28 10:49:56 PM UTC 24 Aug 28 10:49:58 PM UTC 24 27693168 ps
T1055 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_intg_err.1528825366 Aug 28 10:49:54 PM UTC 24 Aug 28 10:49:58 PM UTC 24 123654352 ps
T1056 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_intg_err.592025746 Aug 28 10:49:54 PM UTC 24 Aug 28 10:49:58 PM UTC 24 154741733 ps
T1057 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/16.edn_same_csr_outstanding.710540163 Aug 28 10:49:56 PM UTC 24 Aug 28 10:49:58 PM UTC 24 14810989 ps
T1058 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.617180129 Aug 28 10:49:56 PM UTC 24 Aug 28 10:49:59 PM UTC 24 35615271 ps
T1059 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_intg_err.2473432155 Aug 28 10:49:56 PM UTC 24 Aug 28 10:49:59 PM UTC 24 203308707 ps
T1060 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_errors.229672403 Aug 28 10:49:56 PM UTC 24 Aug 28 10:49:59 PM UTC 24 56566517 ps
T1061 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_errors.2853398900 Aug 28 10:49:54 PM UTC 24 Aug 28 10:49:59 PM UTC 24 486893283 ps
T1062 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_rw.760481834 Aug 28 10:49:57 PM UTC 24 Aug 28 10:49:59 PM UTC 24 35071271 ps
T1063 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/17.edn_intr_test.3294471658 Aug 28 10:49:57 PM UTC 24 Aug 28 10:49:59 PM UTC 24 36400254 ps
T1064 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1140185667 Aug 28 10:49:57 PM UTC 24 Aug 28 10:49:59 PM UTC 24 144033282 ps
T1065 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3661323249 Aug 28 10:49:57 PM UTC 24 Aug 28 10:50:00 PM UTC 24 35515856 ps
T1066 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/17.edn_same_csr_outstanding.1884991136 Aug 28 10:49:57 PM UTC 24 Aug 28 10:50:00 PM UTC 24 23602152 ps
T1067 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_intg_err.1251569567 Aug 28 10:49:57 PM UTC 24 Aug 28 10:50:01 PM UTC 24 515015011 ps
T1068 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/18.edn_intr_test.3927949607 Aug 28 10:49:58 PM UTC 24 Aug 28 10:50:01 PM UTC 24 44340097 ps
T1069 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_rw.3297549984 Aug 28 10:49:58 PM UTC 24 Aug 28 10:50:01 PM UTC 24 14764958 ps
T1070 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/18.edn_same_csr_outstanding.1589540329 Aug 28 10:49:59 PM UTC 24 Aug 28 10:50:01 PM UTC 24 71855944 ps
T1071 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/19.edn_intr_test.2178155091 Aug 28 10:49:59 PM UTC 24 Aug 28 10:50:01 PM UTC 24 81724969 ps
T1072 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3971222824 Aug 28 10:49:59 PM UTC 24 Aug 28 10:50:01 PM UTC 24 79077664 ps
T1073 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_intg_err.2069428300 Aug 28 10:49:59 PM UTC 24 Aug 28 10:50:02 PM UTC 24 98730580 ps
T1074 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/20.edn_intr_test.220364729 Aug 28 10:50:00 PM UTC 24 Aug 28 10:50:02 PM UTC 24 85416233 ps
T1075 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_errors.3077467967 Aug 28 10:49:57 PM UTC 24 Aug 28 10:50:02 PM UTC 24 173643724 ps
T1076 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/21.edn_intr_test.4195464743 Aug 28 10:50:00 PM UTC 24 Aug 28 10:50:02 PM UTC 24 70731878 ps
T1077 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/23.edn_intr_test.3233479022 Aug 28 10:50:00 PM UTC 24 Aug 28 10:50:02 PM UTC 24 44898240 ps
T1078 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_rw.212998806 Aug 28 10:50:00 PM UTC 24 Aug 28 10:50:02 PM UTC 24 13915619 ps
T1079 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/24.edn_intr_test.142996880 Aug 28 10:50:00 PM UTC 24 Aug 28 10:50:02 PM UTC 24 16493203 ps
T1080 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/19.edn_same_csr_outstanding.540745236 Aug 28 10:50:00 PM UTC 24 Aug 28 10:50:02 PM UTC 24 22457730 ps
T1081 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/22.edn_intr_test.115087488 Aug 28 10:50:00 PM UTC 24 Aug 28 10:50:02 PM UTC 24 42810984 ps
T1082 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/26.edn_intr_test.1117942860 Aug 28 10:50:00 PM UTC 24 Aug 28 10:50:02 PM UTC 24 11619490 ps
T1083 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/25.edn_intr_test.2794054879 Aug 28 10:50:00 PM UTC 24 Aug 28 10:50:03 PM UTC 24 15562335 ps
T1084 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/27.edn_intr_test.1737065587 Aug 28 10:50:00 PM UTC 24 Aug 28 10:50:03 PM UTC 24 22071304 ps
T1085 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/28.edn_intr_test.3186708445 Aug 28 10:50:00 PM UTC 24 Aug 28 10:50:03 PM UTC 24 21852737 ps
T1086 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/29.edn_intr_test.872375757 Aug 28 10:50:00 PM UTC 24 Aug 28 10:50:03 PM UTC 24 134483133 ps
T1087 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_intg_err.1951238565 Aug 28 10:49:58 PM UTC 24 Aug 28 10:50:03 PM UTC 24 102355867 ps
T1088 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1727982178 Aug 28 10:50:00 PM UTC 24 Aug 28 10:50:03 PM UTC 24 101505402 ps
T1089 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_errors.38238967 Aug 28 10:49:59 PM UTC 24 Aug 28 10:50:03 PM UTC 24 166905581 ps
T1090 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_errors.1005597138 Aug 28 10:49:57 PM UTC 24 Aug 28 10:50:03 PM UTC 24 420087825 ps
T1091 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/30.edn_intr_test.2350825954 Aug 28 10:50:01 PM UTC 24 Aug 28 10:50:04 PM UTC 24 18060853 ps
T1092 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/31.edn_intr_test.3872242614 Aug 28 10:50:02 PM UTC 24 Aug 28 10:50:04 PM UTC 24 17036758 ps
T1093 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/33.edn_intr_test.2701697253 Aug 28 10:50:02 PM UTC 24 Aug 28 10:50:04 PM UTC 24 46124154 ps
T1094 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/32.edn_intr_test.3885640764 Aug 28 10:50:02 PM UTC 24 Aug 28 10:50:04 PM UTC 24 14413381 ps
T1095 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/36.edn_intr_test.3940182566 Aug 28 10:50:02 PM UTC 24 Aug 28 10:50:04 PM UTC 24 34637600 ps
T1096 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/34.edn_intr_test.3761847858 Aug 28 10:50:02 PM UTC 24 Aug 28 10:50:04 PM UTC 24 14013300 ps
T1097 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/35.edn_intr_test.3658789952 Aug 28 10:50:02 PM UTC 24 Aug 28 10:50:04 PM UTC 24 13591022 ps
T1098 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/38.edn_intr_test.3928454839 Aug 28 10:50:02 PM UTC 24 Aug 28 10:50:04 PM UTC 24 44029713 ps
T1099 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/37.edn_intr_test.2315539681 Aug 28 10:50:02 PM UTC 24 Aug 28 10:50:04 PM UTC 24 18651758 ps
T1100 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/41.edn_intr_test.464048851 Aug 28 10:50:03 PM UTC 24 Aug 28 10:50:05 PM UTC 24 45972994 ps
T1101 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/39.edn_intr_test.3492175157 Aug 28 10:50:03 PM UTC 24 Aug 28 10:50:05 PM UTC 24 12502474 ps
T1102 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/40.edn_intr_test.603243686 Aug 28 10:50:03 PM UTC 24 Aug 28 10:50:05 PM UTC 24 24621055 ps
T1103 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/43.edn_intr_test.1873983966 Aug 28 10:50:03 PM UTC 24 Aug 28 10:50:05 PM UTC 24 15734117 ps
T1104 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/42.edn_intr_test.1747924687 Aug 28 10:50:03 PM UTC 24 Aug 28 10:50:05 PM UTC 24 44143084 ps
T1105 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/45.edn_intr_test.85345681 Aug 28 10:50:03 PM UTC 24 Aug 28 10:50:05 PM UTC 24 30437051 ps
T1106 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/46.edn_intr_test.847978659 Aug 28 10:50:03 PM UTC 24 Aug 28 10:50:05 PM UTC 24 35363090 ps
T1107 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/49.edn_intr_test.2334659497 Aug 28 10:50:03 PM UTC 24 Aug 28 10:50:05 PM UTC 24 21535670 ps
T1108 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/47.edn_intr_test.3326909632 Aug 28 10:50:03 PM UTC 24 Aug 28 10:50:06 PM UTC 24 103525803 ps
T1109 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/44.edn_intr_test.1528355065 Aug 28 10:50:03 PM UTC 24 Aug 28 10:50:06 PM UTC 24 29535135 ps
T1110 /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/48.edn_intr_test.4191795299 Aug 28 10:50:03 PM UTC 24 Aug 28 10:50:06 PM UTC 24 20348644 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/0.edn_genbits.2690012641
Short name T10
Test name
Test status
Simulation time 34403312 ps
CPU time 1.72 seconds
Started Aug 29 12:22:46 AM UTC 24
Finished Aug 29 12:22:49 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690012641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2690012641
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/0.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/0.edn_err.2161085934
Short name T5
Test name
Test status
Simulation time 47594903 ps
CPU time 1.24 seconds
Started Aug 29 12:22:48 AM UTC 24
Finished Aug 29 12:22:50 AM UTC 24
Peak memory 230284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161085934 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 0.edn_err.2161085934
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/0.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/0.edn_sec_cm.1848626038
Short name T17
Test name
Test status
Simulation time 3860346986 ps
CPU time 8.75 seconds
Started Aug 29 12:22:48 AM UTC 24
Finished Aug 29 12:22:58 AM UTC 24
Peak memory 262724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848626038 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1848626038
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/0.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/7.edn_genbits.917369933
Short name T39
Test name
Test status
Simulation time 33789795 ps
CPU time 1.47 seconds
Started Aug 29 12:22:59 AM UTC 24
Finished Aug 29 12:23:01 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917369933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.edn_genbits.917369933
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/7.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/2.edn_stress_all.3841811541
Short name T59
Test name
Test status
Simulation time 1038365030 ps
CPU time 4.46 seconds
Started Aug 29 12:22:50 AM UTC 24
Finished Aug 29 12:22:56 AM UTC 24
Peak memory 227496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841811541 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.3841811541
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/2.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/4.edn_alert.2302710964
Short name T56
Test name
Test status
Simulation time 56786614 ps
CPU time 1.85 seconds
Started Aug 29 12:22:53 AM UTC 24
Finished Aug 29 12:22:56 AM UTC 24
Peak memory 228396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302710964 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 4.edn_alert.2302710964
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/4.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/0.edn_stress_all_with_rand_reset.3251824725
Short name T243
Test name
Test status
Simulation time 14579653610 ps
CPU time 79.53 seconds
Started Aug 29 12:22:48 AM UTC 24
Finished Aug 29 12:24:09 AM UTC 24
Peak memory 234620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3251824725 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_
with_rand_reset.3251824725
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/0.edn_regwen.3655528053
Short name T1
Test name
Test status
Simulation time 53794877 ps
CPU time 1.23 seconds
Started Aug 29 12:22:46 AM UTC 24
Finished Aug 29 12:22:48 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655528053 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 0.edn_regwen.3655528053
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/0.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/5.edn_alert.2869308233
Short name T75
Test name
Test status
Simulation time 49209100 ps
CPU time 1.56 seconds
Started Aug 29 12:22:55 AM UTC 24
Finished Aug 29 12:22:58 AM UTC 24
Peak memory 228212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869308233 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 5.edn_alert.2869308233
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/5.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/7.edn_disable_auto_req_mode.1006198405
Short name T101
Test name
Test status
Simulation time 29950728 ps
CPU time 1.38 seconds
Started Aug 29 12:22:59 AM UTC 24
Finished Aug 29 12:23:01 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006198405 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable_auto_req_mode.1006198405
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/7.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/5.edn_stress_all.1865812202
Short name T115
Test name
Test status
Simulation time 463015249 ps
CPU time 5.58 seconds
Started Aug 29 12:22:55 AM UTC 24
Finished Aug 29 12:23:02 AM UTC 24
Peak memory 229616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865812202 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1865812202
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/5.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/1.edn_alert.4051316996
Short name T29
Test name
Test status
Simulation time 30274883 ps
CPU time 1.27 seconds
Started Aug 29 12:22:50 AM UTC 24
Finished Aug 29 12:22:52 AM UTC 24
Peak memory 226360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051316996 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 1.edn_alert.4051316996
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/1.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_intg_err.4255886709
Short name T316
Test name
Test status
Simulation time 424432348 ps
CPU time 3.95 seconds
Started Aug 28 10:49:45 PM UTC 24
Finished Aug 28 10:49:50 PM UTC 24
Peak memory 217500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255886709 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.4255886709
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/6.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/7.edn_disable.2032440605
Short name T27
Test name
Test status
Simulation time 16827025 ps
CPU time 1.33 seconds
Started Aug 29 12:22:59 AM UTC 24
Finished Aug 29 12:23:01 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032440605 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.2032440605
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/7.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/10.edn_alert.3248153756
Short name T132
Test name
Test status
Simulation time 77426240 ps
CPU time 1.37 seconds
Started Aug 29 12:23:02 AM UTC 24
Finished Aug 29 12:23:05 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248153756 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 10.edn_alert.3248153756
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/10.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/6.edn_disable_auto_req_mode.3070165645
Short name T88
Test name
Test status
Simulation time 35150327 ps
CPU time 1.7 seconds
Started Aug 29 12:22:57 AM UTC 24
Finished Aug 29 12:23:00 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070165645 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable_auto_req_mode.3070165645
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/6.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/15.edn_disable.874270584
Short name T95
Test name
Test status
Simulation time 14788684 ps
CPU time 1.32 seconds
Started Aug 29 12:23:10 AM UTC 24
Finished Aug 29 12:23:13 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874270584 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.874270584
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/15.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/25.edn_alert.442611917
Short name T176
Test name
Test status
Simulation time 28094047 ps
CPU time 1.72 seconds
Started Aug 29 12:23:34 AM UTC 24
Finished Aug 29 12:23:55 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442611917 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 25.edn_alert.442611917
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/25.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/10.edn_disable.931449345
Short name T82
Test name
Test status
Simulation time 20707975 ps
CPU time 1.19 seconds
Started Aug 29 12:23:03 AM UTC 24
Finished Aug 29 12:23:05 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931449345 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.931449345
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/10.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/6.edn_disable.3006369899
Short name T52
Test name
Test status
Simulation time 30099063 ps
CPU time 0.87 seconds
Started Aug 29 12:22:57 AM UTC 24
Finished Aug 29 12:22:59 AM UTC 24
Peak memory 226364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006369899 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.3006369899
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/6.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/29.edn_disable_auto_req_mode.1487487680
Short name T151
Test name
Test status
Simulation time 53328002 ps
CPU time 1.74 seconds
Started Aug 29 12:24:04 AM UTC 24
Finished Aug 29 12:24:08 AM UTC 24
Peak memory 226220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487487680 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable_auto_req_mode.1487487680
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/29.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_aliasing.4091049342
Short name T283
Test name
Test status
Simulation time 26792669 ps
CPU time 1.53 seconds
Started Aug 28 10:49:40 PM UTC 24
Finished Aug 28 10:49:42 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091049342 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.4091049342
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/2.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/43.edn_alert.4135747767
Short name T181
Test name
Test status
Simulation time 30732676 ps
CPU time 1.81 seconds
Started Aug 29 12:24:39 AM UTC 24
Finished Aug 29 12:24:43 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135747767 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 43.edn_alert.4135747767
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/43.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/31.edn_intr.753824378
Short name T323
Test name
Test status
Simulation time 40593911 ps
CPU time 1.1 seconds
Started Aug 29 12:24:08 AM UTC 24
Finished Aug 29 12:24:12 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753824378 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 31.edn_intr.753824378
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/31.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/7.edn_alert.3798585296
Short name T49
Test name
Test status
Simulation time 22902812 ps
CPU time 1.67 seconds
Started Aug 29 12:22:59 AM UTC 24
Finished Aug 29 12:23:01 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798585296 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 7.edn_alert.3798585296
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/7.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/1.edn_genbits.4232877389
Short name T26
Test name
Test status
Simulation time 49039801 ps
CPU time 1.35 seconds
Started Aug 29 12:22:48 AM UTC 24
Finished Aug 29 12:22:50 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232877389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_genbits.4232877389
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/1.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/8.edn_alert.1795773114
Short name T89
Test name
Test status
Simulation time 31044083 ps
CPU time 1.56 seconds
Started Aug 29 12:22:59 AM UTC 24
Finished Aug 29 12:23:02 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795773114 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 8.edn_alert.1795773114
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/8.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/5.edn_intr.4282211830
Short name T31
Test name
Test status
Simulation time 25575538 ps
CPU time 1.15 seconds
Started Aug 29 12:22:55 AM UTC 24
Finished Aug 29 12:22:57 AM UTC 24
Peak memory 228484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282211830 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 5.edn_intr.4282211830
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/5.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/100.edn_alert.1204699541
Short name T696
Test name
Test status
Simulation time 75450381 ps
CPU time 1.49 seconds
Started Aug 29 12:25:21 AM UTC 24
Finished Aug 29 12:25:23 AM UTC 24
Peak memory 230292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204699541 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 100.edn_alert.1204699541
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/100.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/147.edn_alert.3083587299
Short name T772
Test name
Test status
Simulation time 283292610 ps
CPU time 1.4 seconds
Started Aug 29 12:25:37 AM UTC 24
Finished Aug 29 12:25:53 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083587299 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 147.edn_alert.3083587299
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/147.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/32.edn_alert.4092002273
Short name T162
Test name
Test status
Simulation time 44057889 ps
CPU time 1.16 seconds
Started Aug 29 12:24:13 AM UTC 24
Finished Aug 29 12:24:16 AM UTC 24
Peak memory 230100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092002273 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 32.edn_alert.4092002273
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/32.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/21.edn_intr.2632638460
Short name T33
Test name
Test status
Simulation time 25322790 ps
CPU time 1.42 seconds
Started Aug 29 12:23:20 AM UTC 24
Finished Aug 29 12:23:22 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632638460 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 21.edn_intr.2632638460
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/21.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/47.edn_genbits.2445746069
Short name T12
Test name
Test status
Simulation time 32700775 ps
CPU time 1.82 seconds
Started Aug 29 12:24:49 AM UTC 24
Finished Aug 29 12:24:52 AM UTC 24
Peak memory 230608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445746069 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_genbits.2445746069
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/47.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/2.edn_disable_auto_req_mode.2071032199
Short name T19
Test name
Test status
Simulation time 46780591 ps
CPU time 1.22 seconds
Started Aug 29 12:22:51 AM UTC 24
Finished Aug 29 12:22:54 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071032199 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable_auto_req_mode.2071032199
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/2.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/0.edn_alert_test.3102149642
Short name T21
Test name
Test status
Simulation time 47089954 ps
CPU time 0.97 seconds
Started Aug 29 12:22:48 AM UTC 24
Finished Aug 29 12:22:50 AM UTC 24
Peak memory 216748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102149642 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3102149642
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/0.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/48.edn_genbits.3053858506
Short name T313
Test name
Test status
Simulation time 228387448 ps
CPU time 1.61 seconds
Started Aug 29 12:24:52 AM UTC 24
Finished Aug 29 12:24:55 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053858506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3053858506
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/48.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/36.edn_alert.2190615017
Short name T158
Test name
Test status
Simulation time 30073918 ps
CPU time 1.93 seconds
Started Aug 29 12:24:24 AM UTC 24
Finished Aug 29 12:24:27 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190615017 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 36.edn_alert.2190615017
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/36.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/42.edn_disable.2285261422
Short name T527
Test name
Test status
Simulation time 14401384 ps
CPU time 1.12 seconds
Started Aug 29 12:24:37 AM UTC 24
Finished Aug 29 12:24:46 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285261422 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.2285261422
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/42.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/79.edn_alert.668888733
Short name T585
Test name
Test status
Simulation time 114599080 ps
CPU time 1.4 seconds
Started Aug 29 12:25:12 AM UTC 24
Finished Aug 29 12:25:14 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668888733 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 79.edn_alert.668888733
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/79.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/10.edn_disable_auto_req_mode.943645020
Short name T86
Test name
Test status
Simulation time 70891482 ps
CPU time 1.46 seconds
Started Aug 29 12:23:03 AM UTC 24
Finished Aug 29 12:23:05 AM UTC 24
Peak memory 226248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943645020 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable_auto_req_mode.943645020
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/10.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/107.edn_alert.2329466988
Short name T711
Test name
Test status
Simulation time 35829486 ps
CPU time 1.76 seconds
Started Aug 29 12:25:22 AM UTC 24
Finished Aug 29 12:25:25 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329466988 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 107.edn_alert.2329466988
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/107.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/11.edn_alert.4119360377
Short name T83
Test name
Test status
Simulation time 29135292 ps
CPU time 1.47 seconds
Started Aug 29 12:23:04 AM UTC 24
Finished Aug 29 12:23:07 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119360377 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 11.edn_alert.4119360377
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/11.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/12.edn_err.3229691889
Short name T217
Test name
Test status
Simulation time 28313477 ps
CPU time 1.26 seconds
Started Aug 29 12:23:06 AM UTC 24
Finished Aug 29 12:23:08 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229691889 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 12.edn_err.3229691889
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/12.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/120.edn_alert.1662165985
Short name T731
Test name
Test status
Simulation time 45971066 ps
CPU time 1.43 seconds
Started Aug 29 12:25:26 AM UTC 24
Finished Aug 29 12:25:28 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662165985 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 120.edn_alert.1662165985
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/120.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/30.edn_disable.3246725712
Short name T220
Test name
Test status
Simulation time 11134261 ps
CPU time 1.14 seconds
Started Aug 29 12:24:05 AM UTC 24
Finished Aug 29 12:24:18 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246725712 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3246725712
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/30.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/38.edn_disable.754091211
Short name T229
Test name
Test status
Simulation time 29387537 ps
CPU time 1.21 seconds
Started Aug 29 12:24:27 AM UTC 24
Finished Aug 29 12:24:29 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754091211 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.754091211
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/38.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/43.edn_err.3339752646
Short name T205
Test name
Test status
Simulation time 29493862 ps
CPU time 1.33 seconds
Started Aug 29 12:24:39 AM UTC 24
Finished Aug 29 12:24:41 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339752646 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 43.edn_err.3339752646
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/43.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/49.edn_disable.953677258
Short name T221
Test name
Test status
Simulation time 11907777 ps
CPU time 1.17 seconds
Started Aug 29 12:24:55 AM UTC 24
Finished Aug 29 12:24:57 AM UTC 24
Peak memory 226348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953677258 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.953677258
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/49.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/61.edn_err.267679907
Short name T214
Test name
Test status
Simulation time 31178774 ps
CPU time 1.27 seconds
Started Aug 29 12:25:03 AM UTC 24
Finished Aug 29 12:25:05 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267679907 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 61.edn_err.267679907
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/61.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/17.edn_genbits.3165062723
Short name T51
Test name
Test status
Simulation time 52035807 ps
CPU time 2.1 seconds
Started Aug 29 12:23:12 AM UTC 24
Finished Aug 29 12:23:15 AM UTC 24
Peak memory 227548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165062723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3165062723
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/17.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/10.edn_genbits.1677746445
Short name T265
Test name
Test status
Simulation time 49956174 ps
CPU time 1.68 seconds
Started Aug 29 12:23:02 AM UTC 24
Finished Aug 29 12:23:05 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677746445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_genbits.1677746445
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/10.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/11.edn_genbits.4033452220
Short name T309
Test name
Test status
Simulation time 58234149 ps
CPU time 1.07 seconds
Started Aug 29 12:23:04 AM UTC 24
Finished Aug 29 12:23:06 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033452220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_genbits.4033452220
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/11.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/14.edn_stress_all_with_rand_reset.597743611
Short name T460
Test name
Test status
Simulation time 40197819830 ps
CPU time 70.78 seconds
Started Aug 29 12:23:07 AM UTC 24
Finished Aug 29 12:24:20 AM UTC 24
Peak memory 233816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=597743611 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_
with_rand_reset.597743611
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/14.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/8.edn_stress_all.1083127621
Short name T119
Test name
Test status
Simulation time 233799425 ps
CPU time 4.86 seconds
Started Aug 29 12:22:59 AM UTC 24
Finished Aug 29 12:23:05 AM UTC 24
Peak memory 229684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083127621 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.1083127621
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/8.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/34.edn_intr.3885621856
Short name T111
Test name
Test status
Simulation time 38335737 ps
CPU time 1.23 seconds
Started Aug 29 12:24:19 AM UTC 24
Finished Aug 29 12:24:22 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885621856 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 34.edn_intr.3885621856
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/34.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/0.edn_same_csr_outstanding.1538732177
Short name T278
Test name
Test status
Simulation time 99492560 ps
CPU time 1.46 seconds
Started Aug 28 10:49:36 PM UTC 24
Finished Aug 28 10:49:39 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538732177 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_outstanding.1538732177
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/0.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/102.edn_genbits.19912431
Short name T697
Test name
Test status
Simulation time 47465668 ps
CPU time 1.51 seconds
Started Aug 29 12:25:21 AM UTC 24
Finished Aug 29 12:25:23 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19912431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 102.edn_genbits.19912431
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/102.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/110.edn_genbits.3101553115
Short name T351
Test name
Test status
Simulation time 175028275 ps
CPU time 1.67 seconds
Started Aug 29 12:25:23 AM UTC 24
Finished Aug 29 12:25:25 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101553115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 110.edn_genbits.3101553115
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/110.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/122.edn_genbits.1197809181
Short name T338
Test name
Test status
Simulation time 221913915 ps
CPU time 1.98 seconds
Started Aug 29 12:25:26 AM UTC 24
Finished Aug 29 12:25:29 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197809181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1197809181
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/122.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/144.edn_genbits.3537053374
Short name T332
Test name
Test status
Simulation time 38257676 ps
CPU time 1.27 seconds
Started Aug 29 12:25:32 AM UTC 24
Finished Aug 29 12:25:41 AM UTC 24
Peak memory 230696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537053374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 144.edn_genbits.3537053374
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/144.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/151.edn_genbits.1062362331
Short name T336
Test name
Test status
Simulation time 74594235 ps
CPU time 2.69 seconds
Started Aug 29 12:25:44 AM UTC 24
Finished Aug 29 12:25:55 AM UTC 24
Peak memory 231504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062362331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1062362331
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/151.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/157.edn_genbits.2049919772
Short name T798
Test name
Test status
Simulation time 59350854 ps
CPU time 1.22 seconds
Started Aug 29 12:25:55 AM UTC 24
Finished Aug 29 12:26:07 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049919772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 157.edn_genbits.2049919772
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/157.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/178.edn_genbits.1185618904
Short name T343
Test name
Test status
Simulation time 37614942 ps
CPU time 1.31 seconds
Started Aug 29 12:26:13 AM UTC 24
Finished Aug 29 12:26:17 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185618904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1185618904
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/178.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/243.edn_genbits.198149900
Short name T349
Test name
Test status
Simulation time 32762646 ps
CPU time 1.58 seconds
Started Aug 29 12:26:31 AM UTC 24
Finished Aug 29 12:26:44 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198149900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 243.edn_genbits.198149900
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/243.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/43.edn_intr.2649321830
Short name T112
Test name
Test status
Simulation time 24624014 ps
CPU time 1.37 seconds
Started Aug 29 12:24:39 AM UTC 24
Finished Aug 29 12:24:42 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649321830 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 43.edn_intr.2649321830
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/43.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/1.edn_err.2285949646
Short name T7
Test name
Test status
Simulation time 47840985 ps
CPU time 1.3 seconds
Started Aug 29 12:22:50 AM UTC 24
Finished Aug 29 12:22:52 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285949646 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 1.edn_err.2285949646
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/1.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/178.edn_alert.484588554
Short name T143
Test name
Test status
Simulation time 114273092 ps
CPU time 0.99 seconds
Started Aug 29 12:26:13 AM UTC 24
Finished Aug 29 12:26:16 AM UTC 24
Peak memory 232524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484588554 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 178.edn_alert.484588554
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/178.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_aliasing.603027517
Short name T279
Test name
Test status
Simulation time 99380536 ps
CPU time 1.72 seconds
Started Aug 28 10:49:36 PM UTC 24
Finished Aug 28 10:49:39 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603027517 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.603027517
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/0.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_bit_bash.1056746959
Short name T985
Test name
Test status
Simulation time 111230518 ps
CPU time 3.74 seconds
Started Aug 28 10:49:36 PM UTC 24
Finished Aug 28 10:49:41 PM UTC 24
Peak memory 217432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056746959 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1056746959
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/0.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_hw_reset.2911257684
Short name T276
Test name
Test status
Simulation time 17388465 ps
CPU time 1.16 seconds
Started Aug 28 10:49:35 PM UTC 24
Finished Aug 28 10:49:37 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911257684 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2911257684
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/0.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2398405375
Short name T984
Test name
Test status
Simulation time 41637514 ps
CPU time 2.96 seconds
Started Aug 28 10:49:36 PM UTC 24
Finished Aug 28 10:49:41 PM UTC 24
Peak memory 228000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2398405375 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2398405375
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_rw.1108039528
Short name T978
Test name
Test status
Simulation time 44178453 ps
CPU time 1.33 seconds
Started Aug 28 10:49:36 PM UTC 24
Finished Aug 28 10:49:39 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108039528 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1108039528
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/0.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/0.edn_intr_test.4164018695
Short name T976
Test name
Test status
Simulation time 74349699 ps
CPU time 1.15 seconds
Started Aug 28 10:49:35 PM UTC 24
Finished Aug 28 10:49:37 PM UTC 24
Peak memory 216580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164018695 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.4164018695
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/0.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/0.edn_tl_errors.3311553597
Short name T977
Test name
Test status
Simulation time 86389415 ps
CPU time 2.46 seconds
Started Aug 28 10:49:35 PM UTC 24
Finished Aug 28 10:49:38 PM UTC 24
Peak memory 227876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311553597 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3311553597
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/0.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/0.edn_tl_intg_err.748947475
Short name T302
Test name
Test status
Simulation time 141837502 ps
CPU time 1.68 seconds
Started Aug 28 10:49:35 PM UTC 24
Finished Aug 28 10:49:38 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748947475 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.748947475
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/0.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_aliasing.1353735454
Short name T280
Test name
Test status
Simulation time 27747496 ps
CPU time 1.48 seconds
Started Aug 28 10:49:38 PM UTC 24
Finished Aug 28 10:49:40 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353735454 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1353735454
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/1.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_bit_bash.1519277281
Short name T990
Test name
Test status
Simulation time 243964646 ps
CPU time 4.54 seconds
Started Aug 28 10:49:38 PM UTC 24
Finished Aug 28 10:49:43 PM UTC 24
Peak memory 217452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519277281 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.1519277281
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/1.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_hw_reset.3633931068
Short name T277
Test name
Test status
Simulation time 52163964 ps
CPU time 1.04 seconds
Started Aug 28 10:49:37 PM UTC 24
Finished Aug 28 10:49:39 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633931068 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3633931068
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/1.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.4146409620
Short name T986
Test name
Test status
Simulation time 71759372 ps
CPU time 2.1 seconds
Started Aug 28 10:49:38 PM UTC 24
Finished Aug 28 10:49:41 PM UTC 24
Peak memory 227860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4146409620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.4146409620
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_rw.1106061551
Short name T981
Test name
Test status
Simulation time 15851383 ps
CPU time 1.17 seconds
Started Aug 28 10:49:38 PM UTC 24
Finished Aug 28 10:49:40 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106061551 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.1106061551
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/1.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/1.edn_intr_test.2933052901
Short name T979
Test name
Test status
Simulation time 14613835 ps
CPU time 1.07 seconds
Started Aug 28 10:49:37 PM UTC 24
Finished Aug 28 10:49:39 PM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933052901 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.2933052901
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/1.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/1.edn_same_csr_outstanding.764490167
Short name T291
Test name
Test status
Simulation time 23382663 ps
CPU time 1.58 seconds
Started Aug 28 10:49:38 PM UTC 24
Finished Aug 28 10:49:41 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764490167 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_outstanding.764490167
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/1.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/1.edn_tl_errors.3560595013
Short name T980
Test name
Test status
Simulation time 141321755 ps
CPU time 1.97 seconds
Started Aug 28 10:49:37 PM UTC 24
Finished Aug 28 10:49:40 PM UTC 24
Peak memory 225632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560595013 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3560595013
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/1.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/1.edn_tl_intg_err.1575144044
Short name T303
Test name
Test status
Simulation time 141777856 ps
CPU time 3.29 seconds
Started Aug 28 10:49:37 PM UTC 24
Finished Aug 28 10:49:41 PM UTC 24
Peak memory 217500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575144044 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1575144044
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/1.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2269526429
Short name T1027
Test name
Test status
Simulation time 193405793 ps
CPU time 1.95 seconds
Started Aug 28 10:49:50 PM UTC 24
Finished Aug 28 10:49:53 PM UTC 24
Peak memory 225644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2269526429 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2269526429
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_rw.1646910155
Short name T982
Test name
Test status
Simulation time 12054137 ps
CPU time 1.23 seconds
Started Aug 28 10:49:50 PM UTC 24
Finished Aug 28 10:49:52 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646910155 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1646910155
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/10.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/10.edn_intr_test.2633189597
Short name T1018
Test name
Test status
Simulation time 25821684 ps
CPU time 1.06 seconds
Started Aug 28 10:49:49 PM UTC 24
Finished Aug 28 10:49:51 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633189597 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2633189597
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/10.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/10.edn_same_csr_outstanding.2518086938
Short name T1028
Test name
Test status
Simulation time 31254750 ps
CPU time 2.05 seconds
Started Aug 28 10:49:50 PM UTC 24
Finished Aug 28 10:49:53 PM UTC 24
Peak memory 217684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518086938 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_outstanding.2518086938
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/10.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_errors.641686214
Short name T1026
Test name
Test status
Simulation time 368908026 ps
CPU time 3.23 seconds
Started Aug 28 10:49:49 PM UTC 24
Finished Aug 28 10:49:53 PM UTC 24
Peak memory 227868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641686214 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.641686214
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/10.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_intg_err.142695659
Short name T317
Test name
Test status
Simulation time 90753342 ps
CPU time 3.26 seconds
Started Aug 28 10:49:49 PM UTC 24
Finished Aug 28 10:49:53 PM UTC 24
Peak memory 217372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142695659 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.142695659
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/10.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3857275973
Short name T1036
Test name
Test status
Simulation time 73980976 ps
CPU time 1.99 seconds
Started Aug 28 10:49:51 PM UTC 24
Finished Aug 28 10:49:55 PM UTC 24
Peak memory 225536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3857275973 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3857275973
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_rw.1047823440
Short name T1029
Test name
Test status
Simulation time 23173315 ps
CPU time 1.05 seconds
Started Aug 28 10:49:51 PM UTC 24
Finished Aug 28 10:49:54 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047823440 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1047823440
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/11.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/11.edn_intr_test.754028545
Short name T1032
Test name
Test status
Simulation time 12574832 ps
CPU time 1.29 seconds
Started Aug 28 10:49:51 PM UTC 24
Finished Aug 28 10:49:54 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754028545 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.754028545
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/11.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/11.edn_same_csr_outstanding.3336728244
Short name T1031
Test name
Test status
Simulation time 28461606 ps
CPU time 1.15 seconds
Started Aug 28 10:49:51 PM UTC 24
Finished Aug 28 10:49:54 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336728244 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_outstanding.3336728244
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/11.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_errors.3715376380
Short name T1030
Test name
Test status
Simulation time 31152813 ps
CPU time 2.87 seconds
Started Aug 28 10:49:50 PM UTC 24
Finished Aug 28 10:49:54 PM UTC 24
Peak memory 227884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715376380 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3715376380
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/11.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_intg_err.1366445024
Short name T1033
Test name
Test status
Simulation time 608866409 ps
CPU time 2.7 seconds
Started Aug 28 10:49:50 PM UTC 24
Finished Aug 28 10:49:54 PM UTC 24
Peak memory 217500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366445024 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1366445024
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/11.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1094556033
Short name T1038
Test name
Test status
Simulation time 22008528 ps
CPU time 1.85 seconds
Started Aug 28 10:49:52 PM UTC 24
Finished Aug 28 10:49:55 PM UTC 24
Peak memory 227692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1094556033 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1094556033
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_rw.3879921196
Short name T1035
Test name
Test status
Simulation time 46181187 ps
CPU time 1.35 seconds
Started Aug 28 10:49:51 PM UTC 24
Finished Aug 28 10:49:55 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879921196 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3879921196
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/12.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/12.edn_intr_test.2501362477
Short name T1034
Test name
Test status
Simulation time 41460298 ps
CPU time 0.96 seconds
Started Aug 28 10:49:51 PM UTC 24
Finished Aug 28 10:49:54 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501362477 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2501362477
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/12.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/12.edn_same_csr_outstanding.78030730
Short name T1037
Test name
Test status
Simulation time 186823134 ps
CPU time 1.53 seconds
Started Aug 28 10:49:51 PM UTC 24
Finished Aug 28 10:49:55 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78030730 -assert nopostproc +UVM_T
ESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_outstanding.78030730
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/12.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_errors.3709593322
Short name T1040
Test name
Test status
Simulation time 70799258 ps
CPU time 2.94 seconds
Started Aug 28 10:49:51 PM UTC 24
Finished Aug 28 10:49:56 PM UTC 24
Peak memory 227792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709593322 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3709593322
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/12.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_intg_err.624931669
Short name T1043
Test name
Test status
Simulation time 86272386 ps
CPU time 3.49 seconds
Started Aug 28 10:49:51 PM UTC 24
Finished Aug 28 10:49:56 PM UTC 24
Peak memory 217400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624931669 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.624931669
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/12.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1567048882
Short name T1041
Test name
Test status
Simulation time 50162365 ps
CPU time 1.32 seconds
Started Aug 28 10:49:53 PM UTC 24
Finished Aug 28 10:49:56 PM UTC 24
Peak memory 227692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1567048882 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.1567048882
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_rw.952315162
Short name T290
Test name
Test status
Simulation time 57566369 ps
CPU time 0.97 seconds
Started Aug 28 10:49:53 PM UTC 24
Finished Aug 28 10:49:55 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952315162 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.952315162
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/13.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/13.edn_intr_test.2988498749
Short name T1039
Test name
Test status
Simulation time 12243161 ps
CPU time 0.93 seconds
Started Aug 28 10:49:53 PM UTC 24
Finished Aug 28 10:49:55 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988498749 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2988498749
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/13.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/13.edn_same_csr_outstanding.621513743
Short name T1044
Test name
Test status
Simulation time 118464177 ps
CPU time 1.74 seconds
Started Aug 28 10:49:53 PM UTC 24
Finished Aug 28 10:49:56 PM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621513743 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_outstanding.621513743
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/13.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_errors.2980255982
Short name T1042
Test name
Test status
Simulation time 23265324 ps
CPU time 1.91 seconds
Started Aug 28 10:49:53 PM UTC 24
Finished Aug 28 10:49:56 PM UTC 24
Peak memory 225696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980255982 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2980255982
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/13.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_intg_err.641941317
Short name T318
Test name
Test status
Simulation time 104529966 ps
CPU time 3.55 seconds
Started Aug 28 10:49:53 PM UTC 24
Finished Aug 28 10:49:58 PM UTC 24
Peak memory 217496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641941317 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.641941317
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/13.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.4238470350
Short name T1047
Test name
Test status
Simulation time 21219674 ps
CPU time 1.13 seconds
Started Aug 28 10:49:54 PM UTC 24
Finished Aug 28 10:49:57 PM UTC 24
Peak memory 225644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4238470350 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.4238470350
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_rw.1983721735
Short name T1046
Test name
Test status
Simulation time 30961521 ps
CPU time 1.17 seconds
Started Aug 28 10:49:54 PM UTC 24
Finished Aug 28 10:49:57 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983721735 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1983721735
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/14.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/14.edn_intr_test.671634816
Short name T1045
Test name
Test status
Simulation time 15614169 ps
CPU time 1.08 seconds
Started Aug 28 10:49:54 PM UTC 24
Finished Aug 28 10:49:56 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671634816 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.671634816
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/14.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/14.edn_same_csr_outstanding.1696592041
Short name T1048
Test name
Test status
Simulation time 62213848 ps
CPU time 1.56 seconds
Started Aug 28 10:49:54 PM UTC 24
Finished Aug 28 10:49:57 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696592041 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_outstanding.1696592041
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/14.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_errors.2853398900
Short name T1061
Test name
Test status
Simulation time 486893283 ps
CPU time 4.06 seconds
Started Aug 28 10:49:54 PM UTC 24
Finished Aug 28 10:49:59 PM UTC 24
Peak memory 227988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853398900 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2853398900
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/14.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_intg_err.1528825366
Short name T1055
Test name
Test status
Simulation time 123654352 ps
CPU time 3.04 seconds
Started Aug 28 10:49:54 PM UTC 24
Finished Aug 28 10:49:58 PM UTC 24
Peak memory 217512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528825366 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1528825366
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/14.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.617180129
Short name T1058
Test name
Test status
Simulation time 35615271 ps
CPU time 1.88 seconds
Started Aug 28 10:49:56 PM UTC 24
Finished Aug 28 10:49:59 PM UTC 24
Peak memory 225700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=617180129 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.617180129
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_rw.1107037229
Short name T1049
Test name
Test status
Simulation time 41043924 ps
CPU time 1.25 seconds
Started Aug 28 10:49:55 PM UTC 24
Finished Aug 28 10:49:58 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107037229 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1107037229
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/15.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/15.edn_intr_test.1035569939
Short name T1050
Test name
Test status
Simulation time 21851407 ps
CPU time 1.29 seconds
Started Aug 28 10:49:55 PM UTC 24
Finished Aug 28 10:49:58 PM UTC 24
Peak memory 215428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035569939 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1035569939
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/15.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/15.edn_same_csr_outstanding.3008894694
Short name T1052
Test name
Test status
Simulation time 74179921 ps
CPU time 1.31 seconds
Started Aug 28 10:49:55 PM UTC 24
Finished Aug 28 10:49:58 PM UTC 24
Peak memory 215432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008894694 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_outstanding.3008894694
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/15.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_errors.3811743057
Short name T1051
Test name
Test status
Simulation time 95442226 ps
CPU time 2.27 seconds
Started Aug 28 10:49:54 PM UTC 24
Finished Aug 28 10:49:58 PM UTC 24
Peak memory 227988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811743057 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.3811743057
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/15.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_intg_err.592025746
Short name T1056
Test name
Test status
Simulation time 154741733 ps
CPU time 2.81 seconds
Started Aug 28 10:49:54 PM UTC 24
Finished Aug 28 10:49:58 PM UTC 24
Peak memory 227672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592025746 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.592025746
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/15.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1140185667
Short name T1064
Test name
Test status
Simulation time 144033282 ps
CPU time 1.44 seconds
Started Aug 28 10:49:57 PM UTC 24
Finished Aug 28 10:49:59 PM UTC 24
Peak memory 225644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1140185667 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1140185667
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_rw.3717592409
Short name T1054
Test name
Test status
Simulation time 27693168 ps
CPU time 1.3 seconds
Started Aug 28 10:49:56 PM UTC 24
Finished Aug 28 10:49:58 PM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717592409 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.3717592409
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/16.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/16.edn_intr_test.3779693985
Short name T1053
Test name
Test status
Simulation time 53460108 ps
CPU time 1.07 seconds
Started Aug 28 10:49:56 PM UTC 24
Finished Aug 28 10:49:58 PM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779693985 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3779693985
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/16.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/16.edn_same_csr_outstanding.710540163
Short name T1057
Test name
Test status
Simulation time 14810989 ps
CPU time 1.44 seconds
Started Aug 28 10:49:56 PM UTC 24
Finished Aug 28 10:49:58 PM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710540163 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_outstanding.710540163
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/16.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_errors.229672403
Short name T1060
Test name
Test status
Simulation time 56566517 ps
CPU time 2.3 seconds
Started Aug 28 10:49:56 PM UTC 24
Finished Aug 28 10:49:59 PM UTC 24
Peak memory 227792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229672403 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.229672403
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/16.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_intg_err.2473432155
Short name T1059
Test name
Test status
Simulation time 203308707 ps
CPU time 1.84 seconds
Started Aug 28 10:49:56 PM UTC 24
Finished Aug 28 10:49:59 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473432155 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2473432155
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/16.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3661323249
Short name T1065
Test name
Test status
Simulation time 35515856 ps
CPU time 1.34 seconds
Started Aug 28 10:49:57 PM UTC 24
Finished Aug 28 10:50:00 PM UTC 24
Peak memory 225644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3661323249 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3661323249
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_rw.760481834
Short name T1062
Test name
Test status
Simulation time 35071271 ps
CPU time 1.12 seconds
Started Aug 28 10:49:57 PM UTC 24
Finished Aug 28 10:49:59 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760481834 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.760481834
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/17.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/17.edn_intr_test.3294471658
Short name T1063
Test name
Test status
Simulation time 36400254 ps
CPU time 1.24 seconds
Started Aug 28 10:49:57 PM UTC 24
Finished Aug 28 10:49:59 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294471658 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.3294471658
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/17.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/17.edn_same_csr_outstanding.1884991136
Short name T1066
Test name
Test status
Simulation time 23602152 ps
CPU time 1.34 seconds
Started Aug 28 10:49:57 PM UTC 24
Finished Aug 28 10:50:00 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884991136 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_outstanding.1884991136
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/17.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_errors.3077467967
Short name T1075
Test name
Test status
Simulation time 173643724 ps
CPU time 4.1 seconds
Started Aug 28 10:49:57 PM UTC 24
Finished Aug 28 10:50:02 PM UTC 24
Peak memory 227852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077467967 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3077467967
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/17.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_intg_err.1251569567
Short name T1067
Test name
Test status
Simulation time 515015011 ps
CPU time 2.45 seconds
Started Aug 28 10:49:57 PM UTC 24
Finished Aug 28 10:50:01 PM UTC 24
Peak memory 217508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251569567 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.1251569567
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/17.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3971222824
Short name T1072
Test name
Test status
Simulation time 79077664 ps
CPU time 1.54 seconds
Started Aug 28 10:49:59 PM UTC 24
Finished Aug 28 10:50:01 PM UTC 24
Peak memory 225644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3971222824 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3971222824
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_rw.3297549984
Short name T1069
Test name
Test status
Simulation time 14764958 ps
CPU time 1.28 seconds
Started Aug 28 10:49:58 PM UTC 24
Finished Aug 28 10:50:01 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297549984 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.3297549984
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/18.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/18.edn_intr_test.3927949607
Short name T1068
Test name
Test status
Simulation time 44340097 ps
CPU time 1.23 seconds
Started Aug 28 10:49:58 PM UTC 24
Finished Aug 28 10:50:01 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927949607 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.3927949607
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/18.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/18.edn_same_csr_outstanding.1589540329
Short name T1070
Test name
Test status
Simulation time 71855944 ps
CPU time 1.35 seconds
Started Aug 28 10:49:59 PM UTC 24
Finished Aug 28 10:50:01 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589540329 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_outstanding.1589540329
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/18.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_errors.1005597138
Short name T1090
Test name
Test status
Simulation time 420087825 ps
CPU time 4.61 seconds
Started Aug 28 10:49:57 PM UTC 24
Finished Aug 28 10:50:03 PM UTC 24
Peak memory 227988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005597138 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.1005597138
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/18.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_intg_err.1951238565
Short name T1087
Test name
Test status
Simulation time 102355867 ps
CPU time 3.18 seconds
Started Aug 28 10:49:58 PM UTC 24
Finished Aug 28 10:50:03 PM UTC 24
Peak memory 227668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951238565 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1951238565
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/18.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1727982178
Short name T1088
Test name
Test status
Simulation time 101505402 ps
CPU time 1.79 seconds
Started Aug 28 10:50:00 PM UTC 24
Finished Aug 28 10:50:03 PM UTC 24
Peak memory 225644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1727982178 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1727982178
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_rw.212998806
Short name T1078
Test name
Test status
Simulation time 13915619 ps
CPU time 1.31 seconds
Started Aug 28 10:50:00 PM UTC 24
Finished Aug 28 10:50:02 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212998806 -assert nopostproc +UVM_TESTNAME=edn_base_
test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.212998806
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/19.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/19.edn_intr_test.2178155091
Short name T1071
Test name
Test status
Simulation time 81724969 ps
CPU time 1.16 seconds
Started Aug 28 10:49:59 PM UTC 24
Finished Aug 28 10:50:01 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178155091 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2178155091
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/19.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/19.edn_same_csr_outstanding.540745236
Short name T1080
Test name
Test status
Simulation time 22457730 ps
CPU time 1.45 seconds
Started Aug 28 10:50:00 PM UTC 24
Finished Aug 28 10:50:02 PM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540745236 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_outstanding.540745236
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/19.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_errors.38238967
Short name T1089
Test name
Test status
Simulation time 166905581 ps
CPU time 3.29 seconds
Started Aug 28 10:49:59 PM UTC 24
Finished Aug 28 10:50:03 PM UTC 24
Peak memory 227872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38238967 -assert nopostproc +UVM_TESTNAME=edn_base_test
+UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.38238967
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/19.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_intg_err.2069428300
Short name T1073
Test name
Test status
Simulation time 98730580 ps
CPU time 1.87 seconds
Started Aug 28 10:49:59 PM UTC 24
Finished Aug 28 10:50:02 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069428300 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.2069428300
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/19.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_bit_bash.3301828405
Short name T1002
Test name
Test status
Simulation time 251323955 ps
CPU time 6.56 seconds
Started Aug 28 10:49:39 PM UTC 24
Finished Aug 28 10:49:47 PM UTC 24
Peak memory 217360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301828405 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3301828405
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/2.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_hw_reset.2321110105
Short name T281
Test name
Test status
Simulation time 12896033 ps
CPU time 1.27 seconds
Started Aug 28 10:49:38 PM UTC 24
Finished Aug 28 10:49:41 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321110105 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2321110105
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/2.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1220132335
Short name T988
Test name
Test status
Simulation time 28520189 ps
CPU time 1.54 seconds
Started Aug 28 10:49:40 PM UTC 24
Finished Aug 28 10:49:42 PM UTC 24
Peak memory 215464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1220132335 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1220132335
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_rw.4279814720
Short name T292
Test name
Test status
Simulation time 17695825 ps
CPU time 1.22 seconds
Started Aug 28 10:49:38 PM UTC 24
Finished Aug 28 10:49:41 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279814720 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.4279814720
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/2.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/2.edn_intr_test.1375808133
Short name T983
Test name
Test status
Simulation time 80258153 ps
CPU time 1.01 seconds
Started Aug 28 10:49:38 PM UTC 24
Finished Aug 28 10:49:40 PM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375808133 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1375808133
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/2.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/2.edn_same_csr_outstanding.609747032
Short name T293
Test name
Test status
Simulation time 70559884 ps
CPU time 1.86 seconds
Started Aug 28 10:49:40 PM UTC 24
Finished Aug 28 10:49:42 PM UTC 24
Peak memory 215176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609747032 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_outstanding.609747032
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/2.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/2.edn_tl_errors.2388208930
Short name T989
Test name
Test status
Simulation time 345771868 ps
CPU time 3.24 seconds
Started Aug 28 10:49:38 PM UTC 24
Finished Aug 28 10:49:42 PM UTC 24
Peak memory 227796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388208930 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.2388208930
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/2.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/2.edn_tl_intg_err.640275731
Short name T304
Test name
Test status
Simulation time 198245871 ps
CPU time 2.48 seconds
Started Aug 28 10:49:38 PM UTC 24
Finished Aug 28 10:49:42 PM UTC 24
Peak memory 217492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640275731 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.640275731
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/2.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/20.edn_intr_test.220364729
Short name T1074
Test name
Test status
Simulation time 85416233 ps
CPU time 1.08 seconds
Started Aug 28 10:50:00 PM UTC 24
Finished Aug 28 10:50:02 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220364729 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.220364729
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/20.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/21.edn_intr_test.4195464743
Short name T1076
Test name
Test status
Simulation time 70731878 ps
CPU time 1.07 seconds
Started Aug 28 10:50:00 PM UTC 24
Finished Aug 28 10:50:02 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195464743 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.4195464743
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/21.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/22.edn_intr_test.115087488
Short name T1081
Test name
Test status
Simulation time 42810984 ps
CPU time 1.17 seconds
Started Aug 28 10:50:00 PM UTC 24
Finished Aug 28 10:50:02 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115087488 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.115087488
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/22.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/23.edn_intr_test.3233479022
Short name T1077
Test name
Test status
Simulation time 44898240 ps
CPU time 1.04 seconds
Started Aug 28 10:50:00 PM UTC 24
Finished Aug 28 10:50:02 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233479022 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3233479022
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/23.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/24.edn_intr_test.142996880
Short name T1079
Test name
Test status
Simulation time 16493203 ps
CPU time 1.25 seconds
Started Aug 28 10:50:00 PM UTC 24
Finished Aug 28 10:50:02 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142996880 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.142996880
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/24.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/25.edn_intr_test.2794054879
Short name T1083
Test name
Test status
Simulation time 15562335 ps
CPU time 1.21 seconds
Started Aug 28 10:50:00 PM UTC 24
Finished Aug 28 10:50:03 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794054879 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2794054879
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/25.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/26.edn_intr_test.1117942860
Short name T1082
Test name
Test status
Simulation time 11619490 ps
CPU time 1.07 seconds
Started Aug 28 10:50:00 PM UTC 24
Finished Aug 28 10:50:02 PM UTC 24
Peak memory 215440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117942860 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.1117942860
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/26.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/27.edn_intr_test.1737065587
Short name T1084
Test name
Test status
Simulation time 22071304 ps
CPU time 1.07 seconds
Started Aug 28 10:50:00 PM UTC 24
Finished Aug 28 10:50:03 PM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737065587 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1737065587
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/27.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/28.edn_intr_test.3186708445
Short name T1085
Test name
Test status
Simulation time 21852737 ps
CPU time 1.06 seconds
Started Aug 28 10:50:00 PM UTC 24
Finished Aug 28 10:50:03 PM UTC 24
Peak memory 215448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186708445 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.3186708445
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/28.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/29.edn_intr_test.872375757
Short name T1086
Test name
Test status
Simulation time 134483133 ps
CPU time 1.02 seconds
Started Aug 28 10:50:00 PM UTC 24
Finished Aug 28 10:50:03 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872375757 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.872375757
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/29.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_aliasing.34959155
Short name T285
Test name
Test status
Simulation time 18951861 ps
CPU time 1.57 seconds
Started Aug 28 10:49:41 PM UTC 24
Finished Aug 28 10:49:44 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34959155 -assert nopostproc +UVM_TESTNAME=edn_
base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ed
n-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.34959155
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/3.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_bit_bash.3809247951
Short name T999
Test name
Test status
Simulation time 1096470870 ps
CPU time 4.66 seconds
Started Aug 28 10:49:41 PM UTC 24
Finished Aug 28 10:49:47 PM UTC 24
Peak memory 217428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809247951 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3809247951
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/3.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_hw_reset.2392162779
Short name T282
Test name
Test status
Simulation time 78848954 ps
CPU time 1.12 seconds
Started Aug 28 10:49:40 PM UTC 24
Finished Aug 28 10:49:42 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392162779 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2392162779
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/3.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2025425629
Short name T991
Test name
Test status
Simulation time 19322060 ps
CPU time 1.47 seconds
Started Aug 28 10:49:41 PM UTC 24
Finished Aug 28 10:49:44 PM UTC 24
Peak memory 225668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2025425629 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2025425629
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_rw.4020494452
Short name T284
Test name
Test status
Simulation time 31692936 ps
CPU time 1.32 seconds
Started Aug 28 10:49:41 PM UTC 24
Finished Aug 28 10:49:43 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020494452 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.4020494452
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/3.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/3.edn_intr_test.2032921606
Short name T987
Test name
Test status
Simulation time 140205541 ps
CPU time 1.18 seconds
Started Aug 28 10:49:40 PM UTC 24
Finished Aug 28 10:49:42 PM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032921606 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.2032921606
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/3.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/3.edn_same_csr_outstanding.3166207950
Short name T294
Test name
Test status
Simulation time 26318739 ps
CPU time 1.53 seconds
Started Aug 28 10:49:41 PM UTC 24
Finished Aug 28 10:49:44 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166207950 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_outstanding.3166207950
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/3.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_errors.3636152410
Short name T1000
Test name
Test status
Simulation time 814904739 ps
CPU time 6.02 seconds
Started Aug 28 10:49:40 PM UTC 24
Finished Aug 28 10:49:47 PM UTC 24
Peak memory 228072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636152410 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3636152410
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/3.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_intg_err.2391851853
Short name T319
Test name
Test status
Simulation time 1128787347 ps
CPU time 4.34 seconds
Started Aug 28 10:49:40 PM UTC 24
Finished Aug 28 10:49:45 PM UTC 24
Peak memory 228020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391851853 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2391851853
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/3.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/30.edn_intr_test.2350825954
Short name T1091
Test name
Test status
Simulation time 18060853 ps
CPU time 1.02 seconds
Started Aug 28 10:50:01 PM UTC 24
Finished Aug 28 10:50:04 PM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350825954 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2350825954
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/30.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/31.edn_intr_test.3872242614
Short name T1092
Test name
Test status
Simulation time 17036758 ps
CPU time 1.11 seconds
Started Aug 28 10:50:02 PM UTC 24
Finished Aug 28 10:50:04 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872242614 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3872242614
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/31.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/32.edn_intr_test.3885640764
Short name T1094
Test name
Test status
Simulation time 14413381 ps
CPU time 1.14 seconds
Started Aug 28 10:50:02 PM UTC 24
Finished Aug 28 10:50:04 PM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885640764 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3885640764
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/32.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/33.edn_intr_test.2701697253
Short name T1093
Test name
Test status
Simulation time 46124154 ps
CPU time 1.05 seconds
Started Aug 28 10:50:02 PM UTC 24
Finished Aug 28 10:50:04 PM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701697253 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2701697253
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/33.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/34.edn_intr_test.3761847858
Short name T1096
Test name
Test status
Simulation time 14013300 ps
CPU time 1.04 seconds
Started Aug 28 10:50:02 PM UTC 24
Finished Aug 28 10:50:04 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761847858 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3761847858
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/34.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/35.edn_intr_test.3658789952
Short name T1097
Test name
Test status
Simulation time 13591022 ps
CPU time 1.11 seconds
Started Aug 28 10:50:02 PM UTC 24
Finished Aug 28 10:50:04 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658789952 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3658789952
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/35.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/36.edn_intr_test.3940182566
Short name T1095
Test name
Test status
Simulation time 34637600 ps
CPU time 0.98 seconds
Started Aug 28 10:50:02 PM UTC 24
Finished Aug 28 10:50:04 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940182566 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3940182566
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/36.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/37.edn_intr_test.2315539681
Short name T1099
Test name
Test status
Simulation time 18651758 ps
CPU time 1.26 seconds
Started Aug 28 10:50:02 PM UTC 24
Finished Aug 28 10:50:04 PM UTC 24
Peak memory 215452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315539681 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2315539681
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/37.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/38.edn_intr_test.3928454839
Short name T1098
Test name
Test status
Simulation time 44029713 ps
CPU time 1.05 seconds
Started Aug 28 10:50:02 PM UTC 24
Finished Aug 28 10:50:04 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928454839 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3928454839
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/38.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/39.edn_intr_test.3492175157
Short name T1101
Test name
Test status
Simulation time 12502474 ps
CPU time 0.98 seconds
Started Aug 28 10:50:03 PM UTC 24
Finished Aug 28 10:50:05 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492175157 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3492175157
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/39.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_aliasing.1852198868
Short name T996
Test name
Test status
Simulation time 68143601 ps
CPU time 2.22 seconds
Started Aug 28 10:49:43 PM UTC 24
Finished Aug 28 10:49:46 PM UTC 24
Peak memory 217508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852198868 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.1852198868
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/4.edn_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_bit_bash.2293242207
Short name T288
Test name
Test status
Simulation time 59408892 ps
CPU time 3.66 seconds
Started Aug 28 10:49:43 PM UTC 24
Finished Aug 28 10:49:47 PM UTC 24
Peak memory 217432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293242207 -assert nopostproc +UVM_TESTNAME=ed
n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2293242207
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/4.edn_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_hw_reset.415637769
Short name T286
Test name
Test status
Simulation time 28171512 ps
CPU time 1.3 seconds
Started Aug 28 10:49:42 PM UTC 24
Finished Aug 28 10:49:45 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415637769 -assert nopostproc +UVM_TESTNAME=edn
_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.415637769
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/4.edn_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3052250001
Short name T995
Test name
Test status
Simulation time 84814188 ps
CPU time 1.59 seconds
Started Aug 28 10:49:43 PM UTC 24
Finished Aug 28 10:49:45 PM UTC 24
Peak memory 227752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3052250001 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3052250001
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_rw.3437647995
Short name T993
Test name
Test status
Simulation time 11785950 ps
CPU time 1.22 seconds
Started Aug 28 10:49:42 PM UTC 24
Finished Aug 28 10:49:45 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437647995 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.3437647995
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/4.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/4.edn_intr_test.553286536
Short name T992
Test name
Test status
Simulation time 11968578 ps
CPU time 1.24 seconds
Started Aug 28 10:49:42 PM UTC 24
Finished Aug 28 10:49:45 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553286536 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.553286536
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/4.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/4.edn_same_csr_outstanding.2442055276
Short name T295
Test name
Test status
Simulation time 100886118 ps
CPU time 1.87 seconds
Started Aug 28 10:49:43 PM UTC 24
Finished Aug 28 10:49:45 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442055276 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_outstanding.2442055276
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/4.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_errors.794171715
Short name T994
Test name
Test status
Simulation time 101553365 ps
CPU time 2.72 seconds
Started Aug 28 10:49:41 PM UTC 24
Finished Aug 28 10:49:45 PM UTC 24
Peak memory 227780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794171715 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.794171715
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/4.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_intg_err.274303131
Short name T315
Test name
Test status
Simulation time 190551372 ps
CPU time 3.07 seconds
Started Aug 28 10:49:41 PM UTC 24
Finished Aug 28 10:49:45 PM UTC 24
Peak memory 227736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274303131 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.274303131
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/4.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/40.edn_intr_test.603243686
Short name T1102
Test name
Test status
Simulation time 24621055 ps
CPU time 1.08 seconds
Started Aug 28 10:50:03 PM UTC 24
Finished Aug 28 10:50:05 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603243686 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.603243686
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/40.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/41.edn_intr_test.464048851
Short name T1100
Test name
Test status
Simulation time 45972994 ps
CPU time 0.84 seconds
Started Aug 28 10:50:03 PM UTC 24
Finished Aug 28 10:50:05 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464048851 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.464048851
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/41.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/42.edn_intr_test.1747924687
Short name T1104
Test name
Test status
Simulation time 44143084 ps
CPU time 1.15 seconds
Started Aug 28 10:50:03 PM UTC 24
Finished Aug 28 10:50:05 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747924687 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.1747924687
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/42.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/43.edn_intr_test.1873983966
Short name T1103
Test name
Test status
Simulation time 15734117 ps
CPU time 1.01 seconds
Started Aug 28 10:50:03 PM UTC 24
Finished Aug 28 10:50:05 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873983966 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.1873983966
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/43.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/44.edn_intr_test.1528355065
Short name T1109
Test name
Test status
Simulation time 29535135 ps
CPU time 1.18 seconds
Started Aug 28 10:50:03 PM UTC 24
Finished Aug 28 10:50:06 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528355065 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.1528355065
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/44.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/45.edn_intr_test.85345681
Short name T1105
Test name
Test status
Simulation time 30437051 ps
CPU time 1.06 seconds
Started Aug 28 10:50:03 PM UTC 24
Finished Aug 28 10:50:05 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85345681 -assert nopostproc +UVM_TESTNAME=edn_base_test
+UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.85345681
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/45.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/46.edn_intr_test.847978659
Short name T1106
Test name
Test status
Simulation time 35363090 ps
CPU time 1.07 seconds
Started Aug 28 10:50:03 PM UTC 24
Finished Aug 28 10:50:05 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847978659 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.847978659
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/46.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/47.edn_intr_test.3326909632
Short name T1108
Test name
Test status
Simulation time 103525803 ps
CPU time 1.06 seconds
Started Aug 28 10:50:03 PM UTC 24
Finished Aug 28 10:50:06 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326909632 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.3326909632
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/47.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/48.edn_intr_test.4191795299
Short name T1110
Test name
Test status
Simulation time 20348644 ps
CPU time 1.26 seconds
Started Aug 28 10:50:03 PM UTC 24
Finished Aug 28 10:50:06 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191795299 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.4191795299
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/48.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/49.edn_intr_test.2334659497
Short name T1107
Test name
Test status
Simulation time 21535670 ps
CPU time 0.99 seconds
Started Aug 28 10:50:03 PM UTC 24
Finished Aug 28 10:50:05 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334659497 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2334659497
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/49.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.665783173
Short name T998
Test name
Test status
Simulation time 125949569 ps
CPU time 1.43 seconds
Started Aug 28 10:49:44 PM UTC 24
Finished Aug 28 10:49:46 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=665783173 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.665783173
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_rw.2103169833
Short name T287
Test name
Test status
Simulation time 12285901 ps
CPU time 1.26 seconds
Started Aug 28 10:49:44 PM UTC 24
Finished Aug 28 10:49:46 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103169833 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2103169833
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/5.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/5.edn_intr_test.94489358
Short name T997
Test name
Test status
Simulation time 13481120 ps
CPU time 1.22 seconds
Started Aug 28 10:49:44 PM UTC 24
Finished Aug 28 10:49:46 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94489358 -assert nopostproc +UVM_TESTNAME=edn_base_test
+UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.94489358
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/5.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/5.edn_same_csr_outstanding.1778610953
Short name T296
Test name
Test status
Simulation time 40090034 ps
CPU time 1.51 seconds
Started Aug 28 10:49:44 PM UTC 24
Finished Aug 28 10:49:46 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778610953 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_outstanding.1778610953
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/5.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_errors.981947513
Short name T1001
Test name
Test status
Simulation time 33850398 ps
CPU time 3.26 seconds
Started Aug 28 10:49:43 PM UTC 24
Finished Aug 28 10:49:47 PM UTC 24
Peak memory 231956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981947513 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.981947513
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/5.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_intg_err.2528338338
Short name T1004
Test name
Test status
Simulation time 359447601 ps
CPU time 2.63 seconds
Started Aug 28 10:49:44 PM UTC 24
Finished Aug 28 10:49:47 PM UTC 24
Peak memory 217488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528338338 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2528338338
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/5.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2160133520
Short name T1005
Test name
Test status
Simulation time 49225388 ps
CPU time 1.73 seconds
Started Aug 28 10:49:45 PM UTC 24
Finished Aug 28 10:49:48 PM UTC 24
Peak memory 225704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2160133520 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.2160133520
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_rw.1705227059
Short name T289
Test name
Test status
Simulation time 59846255 ps
CPU time 1.31 seconds
Started Aug 28 10:49:45 PM UTC 24
Finished Aug 28 10:49:48 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705227059 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1705227059
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/6.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/6.edn_intr_test.3059924423
Short name T1003
Test name
Test status
Simulation time 16474164 ps
CPU time 1.12 seconds
Started Aug 28 10:49:45 PM UTC 24
Finished Aug 28 10:49:47 PM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059924423 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3059924423
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/6.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/6.edn_same_csr_outstanding.5089173
Short name T297
Test name
Test status
Simulation time 62657904 ps
CPU time 1.26 seconds
Started Aug 28 10:49:45 PM UTC 24
Finished Aug 28 10:49:48 PM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5089173 -assert nopostproc +UVM_TE
STNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_outstanding.5089173
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/6.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_errors.132701572
Short name T1006
Test name
Test status
Simulation time 470736792 ps
CPU time 4.05 seconds
Started Aug 28 10:49:44 PM UTC 24
Finished Aug 28 10:49:49 PM UTC 24
Peak memory 227812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132701572 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.132701572
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/6.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1987378756
Short name T1012
Test name
Test status
Simulation time 45188956 ps
CPU time 1.89 seconds
Started Aug 28 10:49:47 PM UTC 24
Finished Aug 28 10:49:50 PM UTC 24
Peak memory 225704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1987378756 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1987378756
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_rw.2717459089
Short name T1008
Test name
Test status
Simulation time 57122469 ps
CPU time 1.06 seconds
Started Aug 28 10:49:47 PM UTC 24
Finished Aug 28 10:49:49 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717459089 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.2717459089
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/7.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/7.edn_intr_test.3624314894
Short name T1009
Test name
Test status
Simulation time 12431595 ps
CPU time 1.23 seconds
Started Aug 28 10:49:47 PM UTC 24
Finished Aug 28 10:49:49 PM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624314894 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.3624314894
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/7.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/7.edn_same_csr_outstanding.491113456
Short name T1011
Test name
Test status
Simulation time 110025447 ps
CPU time 1.9 seconds
Started Aug 28 10:49:47 PM UTC 24
Finished Aug 28 10:49:50 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491113456 -assert nopostproc +UVM_
TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_outstanding.491113456
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/7.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_errors.1762040370
Short name T1007
Test name
Test status
Simulation time 35845839 ps
CPU time 2.65 seconds
Started Aug 28 10:49:45 PM UTC 24
Finished Aug 28 10:49:49 PM UTC 24
Peak memory 227876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762040370 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.1762040370
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/7.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_intg_err.3068961692
Short name T1017
Test name
Test status
Simulation time 167392809 ps
CPU time 2.43 seconds
Started Aug 28 10:49:47 PM UTC 24
Finished Aug 28 10:49:51 PM UTC 24
Peak memory 227804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068961692 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.3068961692
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/7.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1203554832
Short name T1021
Test name
Test status
Simulation time 35028565 ps
CPU time 1.77 seconds
Started Aug 28 10:49:48 PM UTC 24
Finished Aug 28 10:49:51 PM UTC 24
Peak memory 225704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1203554832 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1203554832
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_rw.1142653985
Short name T1013
Test name
Test status
Simulation time 53804418 ps
CPU time 1.14 seconds
Started Aug 28 10:49:48 PM UTC 24
Finished Aug 28 10:49:50 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142653985 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1142653985
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/8.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/8.edn_intr_test.3593816763
Short name T1010
Test name
Test status
Simulation time 20175229 ps
CPU time 1.05 seconds
Started Aug 28 10:49:47 PM UTC 24
Finished Aug 28 10:49:49 PM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593816763 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3593816763
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/8.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/8.edn_same_csr_outstanding.2015827790
Short name T1014
Test name
Test status
Simulation time 68045917 ps
CPU time 1.31 seconds
Started Aug 28 10:49:48 PM UTC 24
Finished Aug 28 10:49:50 PM UTC 24
Peak memory 214844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015827790 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_outstanding.2015827790
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/8.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_errors.2838692093
Short name T1025
Test name
Test status
Simulation time 98079102 ps
CPU time 3.96 seconds
Started Aug 28 10:49:47 PM UTC 24
Finished Aug 28 10:49:52 PM UTC 24
Peak memory 227880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838692093 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.2838692093
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/8.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_intg_err.734573267
Short name T1015
Test name
Test status
Simulation time 125239023 ps
CPU time 2.1 seconds
Started Aug 28 10:49:47 PM UTC 24
Finished Aug 28 10:49:50 PM UTC 24
Peak memory 217496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734573267 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.734573267
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/8.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.4063923044
Short name T1022
Test name
Test status
Simulation time 20321608 ps
CPU time 1.58 seconds
Started Aug 28 10:49:48 PM UTC 24
Finished Aug 28 10:49:51 PM UTC 24
Peak memory 225704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4063923044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.4063923044
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_rw.3048664832
Short name T1020
Test name
Test status
Simulation time 14634768 ps
CPU time 1.39 seconds
Started Aug 28 10:49:48 PM UTC 24
Finished Aug 28 10:49:51 PM UTC 24
Peak memory 215460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048664832 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3048664832
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/9.edn_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/9.edn_intr_test.406843058
Short name T1016
Test name
Test status
Simulation time 11052542 ps
CPU time 1.13 seconds
Started Aug 28 10:49:48 PM UTC 24
Finished Aug 28 10:49:51 PM UTC 24
Peak memory 215456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406843058 -assert nopostproc +UVM_TESTNAME=edn_base_tes
t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.406843058
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/9.edn_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/9.edn_same_csr_outstanding.3361107877
Short name T1019
Test name
Test status
Simulation time 61216516 ps
CPU time 1.33 seconds
Started Aug 28 10:49:48 PM UTC 24
Finished Aug 28 10:49:51 PM UTC 24
Peak memory 215396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361107877 -assert nopostproc +UVM
_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_outstanding.3361107877
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/9.edn_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_errors.3330436774
Short name T1024
Test name
Test status
Simulation time 147773194 ps
CPU time 3.04 seconds
Started Aug 28 10:49:48 PM UTC 24
Finished Aug 28 10:49:52 PM UTC 24
Peak memory 227876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330436774 -assert nopostproc +UVM_TESTNAME=edn_base_te
st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3330436774
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/9.edn_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_intg_err.620253382
Short name T1023
Test name
Test status
Simulation time 355128751 ps
CPU time 2.97 seconds
Started Aug 28 10:49:48 PM UTC 24
Finished Aug 28 10:49:52 PM UTC 24
Peak memory 217500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620253382 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.620253382
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/9.edn_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/0.edn_alert.2278799601
Short name T28
Test name
Test status
Simulation time 97998980 ps
CPU time 1.47 seconds
Started Aug 29 12:22:48 AM UTC 24
Finished Aug 29 12:22:50 AM UTC 24
Peak memory 230392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278799601 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 0.edn_alert.2278799601
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/0.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/0.edn_disable.3529694313
Short name T22
Test name
Test status
Simulation time 12899881 ps
CPU time 1.22 seconds
Started Aug 29 12:22:48 AM UTC 24
Finished Aug 29 12:22:50 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529694313 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3529694313
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/0.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/0.edn_disable_auto_req_mode.1019994678
Short name T9
Test name
Test status
Simulation time 25101902 ps
CPU time 1.26 seconds
Started Aug 29 12:22:48 AM UTC 24
Finished Aug 29 12:22:50 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019994678 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable_auto_req_mode.1019994678
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/0.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/0.edn_intr.2804276485
Short name T4
Test name
Test status
Simulation time 27812833 ps
CPU time 1.08 seconds
Started Aug 29 12:22:48 AM UTC 24
Finished Aug 29 12:22:50 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804276485 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 0.edn_intr.2804276485
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/0.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/0.edn_smoke.838945528
Short name T2
Test name
Test status
Simulation time 42873272 ps
CPU time 1.3 seconds
Started Aug 29 12:22:46 AM UTC 24
Finished Aug 29 12:22:48 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838945528 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 0.edn_smoke.838945528
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/0.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/0.edn_stress_all.2461550172
Short name T3
Test name
Test status
Simulation time 296174899 ps
CPU time 1.63 seconds
Started Aug 29 12:22:46 AM UTC 24
Finished Aug 29 12:22:49 AM UTC 24
Peak memory 228308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461550172 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2461550172
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/0.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/1.edn_alert_test.2085268528
Short name T79
Test name
Test status
Simulation time 15793161 ps
CPU time 1.32 seconds
Started Aug 29 12:22:50 AM UTC 24
Finished Aug 29 12:22:52 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085268528 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.2085268528
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/1.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/1.edn_disable.1601416006
Short name T40
Test name
Test status
Simulation time 23285154 ps
CPU time 1.18 seconds
Started Aug 29 12:22:50 AM UTC 24
Finished Aug 29 12:22:52 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601416006 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1601416006
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/1.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/1.edn_disable_auto_req_mode.3246141060
Short name T13
Test name
Test status
Simulation time 112477795 ps
CPU time 1.37 seconds
Started Aug 29 12:22:50 AM UTC 24
Finished Aug 29 12:22:52 AM UTC 24
Peak memory 228420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246141060 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable_auto_req_mode.3246141060
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/1.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/1.edn_intr.618930306
Short name T6
Test name
Test status
Simulation time 28623475 ps
CPU time 0.99 seconds
Started Aug 29 12:22:49 AM UTC 24
Finished Aug 29 12:22:52 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618930306 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 1.edn_intr.618930306
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/1.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/1.edn_regwen.3756170940
Short name T24
Test name
Test status
Simulation time 22868130 ps
CPU time 1.13 seconds
Started Aug 29 12:22:48 AM UTC 24
Finished Aug 29 12:22:50 AM UTC 24
Peak memory 216032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756170940 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 1.edn_regwen.3756170940
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/1.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/1.edn_sec_cm.913315125
Short name T18
Test name
Test status
Simulation time 622648721 ps
CPU time 9.27 seconds
Started Aug 29 12:22:50 AM UTC 24
Finished Aug 29 12:23:00 AM UTC 24
Peak memory 260364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913315125 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.913315125
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/1.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/1.edn_smoke.3942516688
Short name T23
Test name
Test status
Simulation time 35865099 ps
CPU time 1.07 seconds
Started Aug 29 12:22:48 AM UTC 24
Finished Aug 29 12:22:50 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942516688 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 1.edn_smoke.3942516688
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/1.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/1.edn_stress_all.2046721394
Short name T58
Test name
Test status
Simulation time 375298290 ps
CPU time 4.47 seconds
Started Aug 29 12:22:48 AM UTC 24
Finished Aug 29 12:22:53 AM UTC 24
Peak memory 229528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046721394 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2046721394
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/1.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/1.edn_stress_all_with_rand_reset.1193209888
Short name T239
Test name
Test status
Simulation time 4084756956 ps
CPU time 47.85 seconds
Started Aug 29 12:22:48 AM UTC 24
Finished Aug 29 12:23:38 AM UTC 24
Peak memory 229776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1193209888 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_
with_rand_reset.1193209888
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/1.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/10.edn_alert_test.1523451355
Short name T363
Test name
Test status
Simulation time 17980626 ps
CPU time 1.2 seconds
Started Aug 29 12:23:03 AM UTC 24
Finished Aug 29 12:23:05 AM UTC 24
Peak memory 217052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523451355 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.1523451355
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/10.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/10.edn_err.1992604114
Short name T362
Test name
Test status
Simulation time 18153987 ps
CPU time 1.34 seconds
Started Aug 29 12:23:03 AM UTC 24
Finished Aug 29 12:23:05 AM UTC 24
Peak memory 228240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992604114 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 10.edn_err.1992604114
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/10.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/10.edn_intr.3905740093
Short name T93
Test name
Test status
Simulation time 27119621 ps
CPU time 1.37 seconds
Started Aug 29 12:23:02 AM UTC 24
Finished Aug 29 12:23:05 AM UTC 24
Peak memory 237296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905740093 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 10.edn_intr.3905740093
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/10.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/10.edn_smoke.2359652812
Short name T128
Test name
Test status
Simulation time 65743277 ps
CPU time 1.4 seconds
Started Aug 29 12:23:02 AM UTC 24
Finished Aug 29 12:23:05 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359652812 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 10.edn_smoke.2359652812
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/10.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/10.edn_stress_all.1049108103
Short name T123
Test name
Test status
Simulation time 813994241 ps
CPU time 4.49 seconds
Started Aug 29 12:23:02 AM UTC 24
Finished Aug 29 12:23:08 AM UTC 24
Peak memory 229672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049108103 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1049108103
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/10.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/10.edn_stress_all_with_rand_reset.1257776842
Short name T251
Test name
Test status
Simulation time 38054866066 ps
CPU time 84.46 seconds
Started Aug 29 12:23:02 AM UTC 24
Finished Aug 29 12:24:29 AM UTC 24
Peak memory 229816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1257776842 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all
_with_rand_reset.1257776842
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/10.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/100.edn_genbits.3478734322
Short name T699
Test name
Test status
Simulation time 37658750 ps
CPU time 1.83 seconds
Started Aug 29 12:25:21 AM UTC 24
Finished Aug 29 12:25:23 AM UTC 24
Peak memory 228344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478734322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 100.edn_genbits.3478734322
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/100.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/101.edn_alert.70535318
Short name T693
Test name
Test status
Simulation time 22189712 ps
CPU time 1.27 seconds
Started Aug 29 12:25:21 AM UTC 24
Finished Aug 29 12:25:23 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70535318 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 101.edn_alert.70535318
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/101.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/101.edn_genbits.755559624
Short name T694
Test name
Test status
Simulation time 76695213 ps
CPU time 1.41 seconds
Started Aug 29 12:25:21 AM UTC 24
Finished Aug 29 12:25:23 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755559624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 101.edn_genbits.755559624
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/101.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/102.edn_alert.2347543359
Short name T695
Test name
Test status
Simulation time 69591609 ps
CPU time 1.37 seconds
Started Aug 29 12:25:21 AM UTC 24
Finished Aug 29 12:25:23 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347543359 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 102.edn_alert.2347543359
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/102.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/103.edn_alert.3263411400
Short name T701
Test name
Test status
Simulation time 28258665 ps
CPU time 1.7 seconds
Started Aug 29 12:25:22 AM UTC 24
Finished Aug 29 12:25:25 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263411400 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 103.edn_alert.3263411400
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/103.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/103.edn_genbits.4094157379
Short name T700
Test name
Test status
Simulation time 27747672 ps
CPU time 1.55 seconds
Started Aug 29 12:25:21 AM UTC 24
Finished Aug 29 12:25:23 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094157379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 103.edn_genbits.4094157379
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/103.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/104.edn_alert.2940247028
Short name T704
Test name
Test status
Simulation time 92249842 ps
CPU time 1.79 seconds
Started Aug 29 12:25:22 AM UTC 24
Finished Aug 29 12:25:25 AM UTC 24
Peak memory 226356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940247028 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 104.edn_alert.2940247028
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/104.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/104.edn_genbits.2406131584
Short name T710
Test name
Test status
Simulation time 216710495 ps
CPU time 2.02 seconds
Started Aug 29 12:25:22 AM UTC 24
Finished Aug 29 12:25:25 AM UTC 24
Peak memory 231560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406131584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2406131584
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/104.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/105.edn_alert.984195280
Short name T706
Test name
Test status
Simulation time 46886138 ps
CPU time 1.67 seconds
Started Aug 29 12:25:22 AM UTC 24
Finished Aug 29 12:25:25 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984195280 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 105.edn_alert.984195280
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/105.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/105.edn_genbits.2999940349
Short name T712
Test name
Test status
Simulation time 53940336 ps
CPU time 2.01 seconds
Started Aug 29 12:25:22 AM UTC 24
Finished Aug 29 12:25:25 AM UTC 24
Peak memory 229704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999940349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 105.edn_genbits.2999940349
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/105.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/106.edn_alert.3844893441
Short name T702
Test name
Test status
Simulation time 106297630 ps
CPU time 1.45 seconds
Started Aug 29 12:25:22 AM UTC 24
Finished Aug 29 12:25:25 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844893441 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 106.edn_alert.3844893441
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/106.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/106.edn_genbits.2192507113
Short name T705
Test name
Test status
Simulation time 117728771 ps
CPU time 1.76 seconds
Started Aug 29 12:25:22 AM UTC 24
Finished Aug 29 12:25:25 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192507113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 106.edn_genbits.2192507113
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/106.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/107.edn_genbits.341596386
Short name T709
Test name
Test status
Simulation time 61493950 ps
CPU time 1.8 seconds
Started Aug 29 12:25:22 AM UTC 24
Finished Aug 29 12:25:25 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341596386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 107.edn_genbits.341596386
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/107.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/108.edn_alert.52987610
Short name T164
Test name
Test status
Simulation time 36660131 ps
CPU time 1.38 seconds
Started Aug 29 12:25:22 AM UTC 24
Finished Aug 29 12:25:25 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52987610 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 108.edn_alert.52987610
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/108.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/108.edn_genbits.3011734861
Short name T708
Test name
Test status
Simulation time 62341328 ps
CPU time 1.58 seconds
Started Aug 29 12:25:22 AM UTC 24
Finished Aug 29 12:25:25 AM UTC 24
Peak memory 230616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011734861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3011734861
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/108.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/109.edn_alert.2893176070
Short name T707
Test name
Test status
Simulation time 27800324 ps
CPU time 1.4 seconds
Started Aug 29 12:25:23 AM UTC 24
Finished Aug 29 12:25:25 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893176070 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 109.edn_alert.2893176070
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/109.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/109.edn_genbits.4224151139
Short name T703
Test name
Test status
Simulation time 37823553 ps
CPU time 1.22 seconds
Started Aug 29 12:25:23 AM UTC 24
Finished Aug 29 12:25:25 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224151139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 109.edn_genbits.4224151139
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/109.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/11.edn_alert_test.4237903898
Short name T365
Test name
Test status
Simulation time 14235488 ps
CPU time 1.33 seconds
Started Aug 29 12:23:04 AM UTC 24
Finished Aug 29 12:23:07 AM UTC 24
Peak memory 216932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237903898 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.4237903898
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/11.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/11.edn_disable.2748611385
Short name T94
Test name
Test status
Simulation time 11086266 ps
CPU time 1.12 seconds
Started Aug 29 12:23:04 AM UTC 24
Finished Aug 29 12:23:06 AM UTC 24
Peak memory 226368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748611385 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2748611385
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/11.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/11.edn_disable_auto_req_mode.3445570336
Short name T156
Test name
Test status
Simulation time 30506258 ps
CPU time 1.51 seconds
Started Aug 29 12:23:04 AM UTC 24
Finished Aug 29 12:23:07 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445570336 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable_auto_req_mode.3445570336
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/11.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/11.edn_err.1734267443
Short name T228
Test name
Test status
Simulation time 22994251 ps
CPU time 1.35 seconds
Started Aug 29 12:23:04 AM UTC 24
Finished Aug 29 12:23:06 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734267443 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 11.edn_err.1734267443
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/11.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/11.edn_intr.1075501963
Short name T366
Test name
Test status
Simulation time 21736101 ps
CPU time 1.65 seconds
Started Aug 29 12:23:04 AM UTC 24
Finished Aug 29 12:23:07 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075501963 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 11.edn_intr.1075501963
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/11.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/11.edn_smoke.2434322422
Short name T129
Test name
Test status
Simulation time 25571685 ps
CPU time 1.41 seconds
Started Aug 29 12:23:04 AM UTC 24
Finished Aug 29 12:23:06 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434322422 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 11.edn_smoke.2434322422
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/11.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/11.edn_stress_all.3254550276
Short name T308
Test name
Test status
Simulation time 259358354 ps
CPU time 5.3 seconds
Started Aug 29 12:23:04 AM UTC 24
Finished Aug 29 12:23:10 AM UTC 24
Peak memory 227680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254550276 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.3254550276
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/11.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/11.edn_stress_all_with_rand_reset.3322571560
Short name T464
Test name
Test status
Simulation time 3607900450 ps
CPU time 75.94 seconds
Started Aug 29 12:23:04 AM UTC 24
Finished Aug 29 12:24:22 AM UTC 24
Peak memory 229844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3322571560 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all
_with_rand_reset.3322571560
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/11.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/110.edn_alert.2806080600
Short name T715
Test name
Test status
Simulation time 85618357 ps
CPU time 1.57 seconds
Started Aug 29 12:25:24 AM UTC 24
Finished Aug 29 12:25:26 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806080600 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 110.edn_alert.2806080600
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/110.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/111.edn_alert.3830097924
Short name T719
Test name
Test status
Simulation time 47678675 ps
CPU time 1.79 seconds
Started Aug 29 12:25:24 AM UTC 24
Finished Aug 29 12:25:27 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830097924 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 111.edn_alert.3830097924
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/111.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/111.edn_genbits.2552099381
Short name T716
Test name
Test status
Simulation time 51188521 ps
CPU time 1.57 seconds
Started Aug 29 12:25:24 AM UTC 24
Finished Aug 29 12:25:26 AM UTC 24
Peak memory 228544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552099381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 111.edn_genbits.2552099381
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/111.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/112.edn_alert.4265765505
Short name T714
Test name
Test status
Simulation time 52395647 ps
CPU time 1.28 seconds
Started Aug 29 12:25:24 AM UTC 24
Finished Aug 29 12:25:26 AM UTC 24
Peak memory 226356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265765505 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 112.edn_alert.4265765505
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/112.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/112.edn_genbits.156288778
Short name T713
Test name
Test status
Simulation time 29875581 ps
CPU time 1.29 seconds
Started Aug 29 12:25:24 AM UTC 24
Finished Aug 29 12:25:26 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156288778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 112.edn_genbits.156288778
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/112.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/113.edn_alert.554634197
Short name T723
Test name
Test status
Simulation time 30852746 ps
CPU time 1.87 seconds
Started Aug 29 12:25:24 AM UTC 24
Finished Aug 29 12:25:27 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554634197 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 113.edn_alert.554634197
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/113.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/113.edn_genbits.296486686
Short name T718
Test name
Test status
Simulation time 124030269 ps
CPU time 1.6 seconds
Started Aug 29 12:25:24 AM UTC 24
Finished Aug 29 12:25:27 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296486686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 113.edn_genbits.296486686
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/113.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/114.edn_alert.2758886578
Short name T717
Test name
Test status
Simulation time 30999256 ps
CPU time 1.5 seconds
Started Aug 29 12:25:24 AM UTC 24
Finished Aug 29 12:25:27 AM UTC 24
Peak memory 230436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758886578 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 114.edn_alert.2758886578
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/114.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/114.edn_genbits.3478077206
Short name T720
Test name
Test status
Simulation time 50255363 ps
CPU time 1.55 seconds
Started Aug 29 12:25:24 AM UTC 24
Finished Aug 29 12:25:27 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478077206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3478077206
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/114.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/115.edn_alert.2135031743
Short name T724
Test name
Test status
Simulation time 104395207 ps
CPU time 1.8 seconds
Started Aug 29 12:25:24 AM UTC 24
Finished Aug 29 12:25:27 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135031743 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 115.edn_alert.2135031743
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/115.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/115.edn_genbits.257207822
Short name T727
Test name
Test status
Simulation time 89174017 ps
CPU time 2.11 seconds
Started Aug 29 12:25:24 AM UTC 24
Finished Aug 29 12:25:27 AM UTC 24
Peak memory 231780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257207822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 115.edn_genbits.257207822
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/115.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/116.edn_alert.1965083685
Short name T722
Test name
Test status
Simulation time 25223738 ps
CPU time 1.67 seconds
Started Aug 29 12:25:24 AM UTC 24
Finished Aug 29 12:25:27 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965083685 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 116.edn_alert.1965083685
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/116.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/116.edn_genbits.2957632538
Short name T726
Test name
Test status
Simulation time 37547033 ps
CPU time 1.9 seconds
Started Aug 29 12:25:24 AM UTC 24
Finished Aug 29 12:25:27 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957632538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 116.edn_genbits.2957632538
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/116.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/117.edn_alert.1862110659
Short name T321
Test name
Test status
Simulation time 27319805 ps
CPU time 1.85 seconds
Started Aug 29 12:25:25 AM UTC 24
Finished Aug 29 12:25:28 AM UTC 24
Peak memory 232520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862110659 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 117.edn_alert.1862110659
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/117.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/117.edn_genbits.608437485
Short name T721
Test name
Test status
Simulation time 85662893 ps
CPU time 1.34 seconds
Started Aug 29 12:25:24 AM UTC 24
Finished Aug 29 12:25:27 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608437485 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 117.edn_genbits.608437485
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/117.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/118.edn_alert.2555107255
Short name T734
Test name
Test status
Simulation time 146233634 ps
CPU time 2.21 seconds
Started Aug 29 12:25:26 AM UTC 24
Finished Aug 29 12:25:29 AM UTC 24
Peak memory 232124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555107255 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 118.edn_alert.2555107255
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/118.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/118.edn_genbits.3862795380
Short name T728
Test name
Test status
Simulation time 98717132 ps
CPU time 1.4 seconds
Started Aug 29 12:25:25 AM UTC 24
Finished Aug 29 12:25:28 AM UTC 24
Peak memory 230420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862795380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3862795380
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/118.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/119.edn_alert.3129527448
Short name T732
Test name
Test status
Simulation time 132749192 ps
CPU time 1.57 seconds
Started Aug 29 12:25:26 AM UTC 24
Finished Aug 29 12:25:28 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129527448 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 119.edn_alert.3129527448
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/119.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/119.edn_genbits.2799196206
Short name T729
Test name
Test status
Simulation time 88433557 ps
CPU time 1.47 seconds
Started Aug 29 12:25:26 AM UTC 24
Finished Aug 29 12:25:28 AM UTC 24
Peak memory 230420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799196206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 119.edn_genbits.2799196206
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/119.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/12.edn_alert.715479017
Short name T54
Test name
Test status
Simulation time 120762312 ps
CPU time 1.63 seconds
Started Aug 29 12:23:06 AM UTC 24
Finished Aug 29 12:23:08 AM UTC 24
Peak memory 230468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715479017 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 12.edn_alert.715479017
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/12.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/12.edn_alert_test.1647489808
Short name T367
Test name
Test status
Simulation time 32686659 ps
CPU time 0.96 seconds
Started Aug 29 12:23:06 AM UTC 24
Finished Aug 29 12:23:08 AM UTC 24
Peak memory 216916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647489808 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.1647489808
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/12.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/12.edn_disable.4056191681
Short name T227
Test name
Test status
Simulation time 18213972 ps
CPU time 1.13 seconds
Started Aug 29 12:23:06 AM UTC 24
Finished Aug 29 12:23:08 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056191681 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.4056191681
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/12.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/12.edn_disable_auto_req_mode.2940101074
Short name T370
Test name
Test status
Simulation time 76234908 ps
CPU time 1.47 seconds
Started Aug 29 12:23:06 AM UTC 24
Finished Aug 29 12:23:08 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940101074 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable_auto_req_mode.2940101074
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/12.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/12.edn_genbits.3315584135
Short name T47
Test name
Test status
Simulation time 40551081 ps
CPU time 1.35 seconds
Started Aug 29 12:23:04 AM UTC 24
Finished Aug 29 12:23:07 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315584135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_genbits.3315584135
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/12.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/12.edn_intr.4003016104
Short name T369
Test name
Test status
Simulation time 25894546 ps
CPU time 1.58 seconds
Started Aug 29 12:23:05 AM UTC 24
Finished Aug 29 12:23:08 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003016104 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 12.edn_intr.4003016104
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/12.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/12.edn_smoke.1521517858
Short name T364
Test name
Test status
Simulation time 43750664 ps
CPU time 1.09 seconds
Started Aug 29 12:23:04 AM UTC 24
Finished Aug 29 12:23:06 AM UTC 24
Peak memory 226120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521517858 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 12.edn_smoke.1521517858
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/12.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/12.edn_stress_all.165468479
Short name T381
Test name
Test status
Simulation time 275873983 ps
CPU time 6.4 seconds
Started Aug 29 12:23:04 AM UTC 24
Finished Aug 29 12:23:12 AM UTC 24
Peak memory 227612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165468479 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.165468479
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/12.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/12.edn_stress_all_with_rand_reset.2102935817
Short name T519
Test name
Test status
Simulation time 4230481910 ps
CPU time 93.38 seconds
Started Aug 29 12:23:05 AM UTC 24
Finished Aug 29 12:24:41 AM UTC 24
Peak memory 229720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2102935817 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all
_with_rand_reset.2102935817
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/12.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/120.edn_genbits.1037358416
Short name T733
Test name
Test status
Simulation time 120070777 ps
CPU time 1.85 seconds
Started Aug 29 12:25:26 AM UTC 24
Finished Aug 29 12:25:29 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037358416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 120.edn_genbits.1037358416
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/120.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/121.edn_alert.2549837688
Short name T725
Test name
Test status
Simulation time 22993693 ps
CPU time 1.24 seconds
Started Aug 29 12:25:26 AM UTC 24
Finished Aug 29 12:25:28 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549837688 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 121.edn_alert.2549837688
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/121.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/121.edn_genbits.3920701807
Short name T730
Test name
Test status
Simulation time 45579552 ps
CPU time 1.22 seconds
Started Aug 29 12:25:26 AM UTC 24
Finished Aug 29 12:25:28 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920701807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 121.edn_genbits.3920701807
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/121.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/122.edn_alert.4244023173
Short name T207
Test name
Test status
Simulation time 60135396 ps
CPU time 1.27 seconds
Started Aug 29 12:25:27 AM UTC 24
Finished Aug 29 12:25:29 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244023173 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 122.edn_alert.4244023173
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/122.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/123.edn_alert.543405811
Short name T735
Test name
Test status
Simulation time 109105553 ps
CPU time 1.22 seconds
Started Aug 29 12:25:27 AM UTC 24
Finished Aug 29 12:25:29 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543405811 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 123.edn_alert.543405811
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/123.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/123.edn_genbits.2304809195
Short name T738
Test name
Test status
Simulation time 31989728 ps
CPU time 1.68 seconds
Started Aug 29 12:25:27 AM UTC 24
Finished Aug 29 12:25:30 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304809195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2304809195
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/123.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/124.edn_alert.817820388
Short name T208
Test name
Test status
Simulation time 88605817 ps
CPU time 1.29 seconds
Started Aug 29 12:25:27 AM UTC 24
Finished Aug 29 12:25:29 AM UTC 24
Peak memory 230128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817820388 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 124.edn_alert.817820388
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/124.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/124.edn_genbits.1864795925
Short name T737
Test name
Test status
Simulation time 49682370 ps
CPU time 1.56 seconds
Started Aug 29 12:25:27 AM UTC 24
Finished Aug 29 12:25:30 AM UTC 24
Peak memory 228568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864795925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1864795925
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/124.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/125.edn_alert.1055976940
Short name T739
Test name
Test status
Simulation time 31403546 ps
CPU time 1.54 seconds
Started Aug 29 12:25:27 AM UTC 24
Finished Aug 29 12:25:30 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055976940 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 125.edn_alert.1055976940
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/125.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/125.edn_genbits.3089348006
Short name T741
Test name
Test status
Simulation time 79131539 ps
CPU time 1.76 seconds
Started Aug 29 12:25:27 AM UTC 24
Finished Aug 29 12:25:30 AM UTC 24
Peak memory 228016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089348006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 125.edn_genbits.3089348006
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/125.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/126.edn_alert.3924293454
Short name T736
Test name
Test status
Simulation time 29259530 ps
CPU time 1.25 seconds
Started Aug 29 12:25:27 AM UTC 24
Finished Aug 29 12:25:30 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924293454 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 126.edn_alert.3924293454
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/126.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/126.edn_genbits.3221201506
Short name T742
Test name
Test status
Simulation time 78190327 ps
CPU time 1.72 seconds
Started Aug 29 12:25:27 AM UTC 24
Finished Aug 29 12:25:30 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221201506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3221201506
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/126.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/127.edn_alert.3715603166
Short name T740
Test name
Test status
Simulation time 67154962 ps
CPU time 1.42 seconds
Started Aug 29 12:25:27 AM UTC 24
Finished Aug 29 12:25:30 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715603166 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 127.edn_alert.3715603166
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/127.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/127.edn_genbits.173949201
Short name T743
Test name
Test status
Simulation time 40835759 ps
CPU time 2.11 seconds
Started Aug 29 12:25:27 AM UTC 24
Finished Aug 29 12:25:31 AM UTC 24
Peak memory 229716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173949201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 127.edn_genbits.173949201
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/127.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/128.edn_alert.2394610942
Short name T745
Test name
Test status
Simulation time 132835202 ps
CPU time 1.25 seconds
Started Aug 29 12:25:28 AM UTC 24
Finished Aug 29 12:25:31 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394610942 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 128.edn_alert.2394610942
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/128.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/128.edn_genbits.240240172
Short name T744
Test name
Test status
Simulation time 147098690 ps
CPU time 1.36 seconds
Started Aug 29 12:25:28 AM UTC 24
Finished Aug 29 12:25:31 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240240172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 128.edn_genbits.240240172
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/128.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/129.edn_alert.1066369875
Short name T746
Test name
Test status
Simulation time 166534488 ps
CPU time 1.36 seconds
Started Aug 29 12:25:29 AM UTC 24
Finished Aug 29 12:25:31 AM UTC 24
Peak memory 232520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066369875 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 129.edn_alert.1066369875
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/129.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/129.edn_genbits.2688381158
Short name T750
Test name
Test status
Simulation time 67646102 ps
CPU time 1.94 seconds
Started Aug 29 12:25:28 AM UTC 24
Finished Aug 29 12:25:32 AM UTC 24
Peak memory 230420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688381158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2688381158
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/129.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/13.edn_alert.1186564296
Short name T139
Test name
Test status
Simulation time 24560098 ps
CPU time 1.29 seconds
Started Aug 29 12:23:07 AM UTC 24
Finished Aug 29 12:23:09 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186564296 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 13.edn_alert.1186564296
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/13.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/13.edn_alert_test.431516004
Short name T373
Test name
Test status
Simulation time 26804937 ps
CPU time 1.31 seconds
Started Aug 29 12:23:07 AM UTC 24
Finished Aug 29 12:23:10 AM UTC 24
Peak memory 216244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431516004 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.431516004
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/13.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/13.edn_disable.991778545
Short name T186
Test name
Test status
Simulation time 44574083 ps
CPU time 1.15 seconds
Started Aug 29 12:23:07 AM UTC 24
Finished Aug 29 12:23:09 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991778545 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.991778545
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/13.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/13.edn_disable_auto_req_mode.3659058435
Short name T374
Test name
Test status
Simulation time 165499765 ps
CPU time 1.63 seconds
Started Aug 29 12:23:07 AM UTC 24
Finished Aug 29 12:23:10 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659058435 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable_auto_req_mode.3659058435
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/13.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/13.edn_err.4133435384
Short name T218
Test name
Test status
Simulation time 25307274 ps
CPU time 1.33 seconds
Started Aug 29 12:23:07 AM UTC 24
Finished Aug 29 12:23:09 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133435384 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 13.edn_err.4133435384
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/13.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/13.edn_genbits.3575277511
Short name T45
Test name
Test status
Simulation time 61112512 ps
CPU time 1.59 seconds
Started Aug 29 12:23:06 AM UTC 24
Finished Aug 29 12:23:08 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575277511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3575277511
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/13.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/13.edn_intr.233121544
Short name T104
Test name
Test status
Simulation time 25275486 ps
CPU time 1.36 seconds
Started Aug 29 12:23:06 AM UTC 24
Finished Aug 29 12:23:08 AM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233121544 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 13.edn_intr.233121544
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/13.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/13.edn_smoke.1664142598
Short name T368
Test name
Test status
Simulation time 22313342 ps
CPU time 1.11 seconds
Started Aug 29 12:23:06 AM UTC 24
Finished Aug 29 12:23:08 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664142598 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 13.edn_smoke.1664142598
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/13.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/13.edn_stress_all.680363238
Short name T306
Test name
Test status
Simulation time 148174272 ps
CPU time 3.48 seconds
Started Aug 29 12:23:06 AM UTC 24
Finished Aug 29 12:23:10 AM UTC 24
Peak memory 229516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680363238 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.680363238
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/13.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/130.edn_alert.2214385008
Short name T749
Test name
Test status
Simulation time 48851983 ps
CPU time 1.6 seconds
Started Aug 29 12:25:29 AM UTC 24
Finished Aug 29 12:25:31 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214385008 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 130.edn_alert.2214385008
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/130.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/130.edn_genbits.2591677978
Short name T751
Test name
Test status
Simulation time 121183479 ps
CPU time 2.26 seconds
Started Aug 29 12:25:29 AM UTC 24
Finished Aug 29 12:25:32 AM UTC 24
Peak memory 231532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591677978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2591677978
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/130.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/131.edn_alert.3756910135
Short name T747
Test name
Test status
Simulation time 95723612 ps
CPU time 1.34 seconds
Started Aug 29 12:25:29 AM UTC 24
Finished Aug 29 12:25:31 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756910135 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 131.edn_alert.3756910135
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/131.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/131.edn_genbits.2994318098
Short name T748
Test name
Test status
Simulation time 44962572 ps
CPU time 1.47 seconds
Started Aug 29 12:25:29 AM UTC 24
Finished Aug 29 12:25:31 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994318098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2994318098
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/131.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/132.edn_alert.1185404861
Short name T758
Test name
Test status
Simulation time 28677490 ps
CPU time 1.13 seconds
Started Aug 29 12:25:30 AM UTC 24
Finished Aug 29 12:25:42 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185404861 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 132.edn_alert.1185404861
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/132.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/132.edn_genbits.3033753092
Short name T347
Test name
Test status
Simulation time 72714557 ps
CPU time 2.87 seconds
Started Aug 29 12:25:29 AM UTC 24
Finished Aug 29 12:25:33 AM UTC 24
Peak memory 231580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033753092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3033753092
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/132.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/133.edn_alert.2477665014
Short name T759
Test name
Test status
Simulation time 52938546 ps
CPU time 1.11 seconds
Started Aug 29 12:25:30 AM UTC 24
Finished Aug 29 12:25:42 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477665014 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 133.edn_alert.2477665014
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/133.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/133.edn_genbits.1157260940
Short name T761
Test name
Test status
Simulation time 35669555 ps
CPU time 1.47 seconds
Started Aug 29 12:25:30 AM UTC 24
Finished Aug 29 12:25:43 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157260940 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1157260940
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/133.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/134.edn_alert.3642143090
Short name T769
Test name
Test status
Simulation time 52176078 ps
CPU time 1.37 seconds
Started Aug 29 12:25:30 AM UTC 24
Finished Aug 29 12:25:53 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642143090 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 134.edn_alert.3642143090
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/134.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/134.edn_genbits.3998705392
Short name T760
Test name
Test status
Simulation time 38301744 ps
CPU time 1.4 seconds
Started Aug 29 12:25:30 AM UTC 24
Finished Aug 29 12:25:42 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998705392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3998705392
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/134.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/135.edn_alert.2395009062
Short name T768
Test name
Test status
Simulation time 27790265 ps
CPU time 1.23 seconds
Started Aug 29 12:25:30 AM UTC 24
Finished Aug 29 12:25:53 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395009062 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 135.edn_alert.2395009062
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/135.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/135.edn_genbits.2959378449
Short name T767
Test name
Test status
Simulation time 122755689 ps
CPU time 1.44 seconds
Started Aug 29 12:25:30 AM UTC 24
Finished Aug 29 12:25:53 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959378449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 135.edn_genbits.2959378449
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/135.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/136.edn_alert.401100721
Short name T771
Test name
Test status
Simulation time 318916617 ps
CPU time 1.38 seconds
Started Aug 29 12:25:30 AM UTC 24
Finished Aug 29 12:25:53 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401100721 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 136.edn_alert.401100721
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/136.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/136.edn_genbits.457467076
Short name T773
Test name
Test status
Simulation time 146909576 ps
CPU time 1.55 seconds
Started Aug 29 12:25:30 AM UTC 24
Finished Aug 29 12:25:53 AM UTC 24
Peak memory 228320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457467076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 136.edn_genbits.457467076
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/136.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/137.edn_alert.3234482501
Short name T776
Test name
Test status
Simulation time 45732303 ps
CPU time 1.66 seconds
Started Aug 29 12:25:30 AM UTC 24
Finished Aug 29 12:25:53 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234482501 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 137.edn_alert.3234482501
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/137.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/137.edn_genbits.1298104749
Short name T777
Test name
Test status
Simulation time 41199412 ps
CPU time 2.1 seconds
Started Aug 29 12:25:30 AM UTC 24
Finished Aug 29 12:25:54 AM UTC 24
Peak memory 229716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298104749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1298104749
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/137.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/138.edn_alert.3580699492
Short name T785
Test name
Test status
Simulation time 27638550 ps
CPU time 1.78 seconds
Started Aug 29 12:25:32 AM UTC 24
Finished Aug 29 12:25:55 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580699492 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 138.edn_alert.3580699492
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/138.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/138.edn_genbits.147113902
Short name T762
Test name
Test status
Simulation time 43617769 ps
CPU time 1.45 seconds
Started Aug 29 12:25:30 AM UTC 24
Finished Aug 29 12:25:46 AM UTC 24
Peak memory 230612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147113902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 138.edn_genbits.147113902
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/138.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/139.edn_alert.3164510556
Short name T782
Test name
Test status
Simulation time 229875176 ps
CPU time 1.55 seconds
Started Aug 29 12:25:32 AM UTC 24
Finished Aug 29 12:25:55 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164510556 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 139.edn_alert.3164510556
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/139.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/139.edn_genbits.2149232501
Short name T787
Test name
Test status
Simulation time 150079144 ps
CPU time 3.3 seconds
Started Aug 29 12:25:32 AM UTC 24
Finished Aug 29 12:25:56 AM UTC 24
Peak memory 231764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149232501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 139.edn_genbits.2149232501
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/139.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/14.edn_alert.1734953953
Short name T170
Test name
Test status
Simulation time 37197625 ps
CPU time 1.2 seconds
Started Aug 29 12:23:08 AM UTC 24
Finished Aug 29 12:23:10 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734953953 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 14.edn_alert.1734953953
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/14.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/14.edn_alert_test.229783462
Short name T378
Test name
Test status
Simulation time 13822488 ps
CPU time 1.33 seconds
Started Aug 29 12:23:09 AM UTC 24
Finished Aug 29 12:23:11 AM UTC 24
Peak memory 217048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229783462 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.229783462
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/14.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/14.edn_disable.2513735346
Short name T187
Test name
Test status
Simulation time 17869013 ps
CPU time 1.31 seconds
Started Aug 29 12:23:09 AM UTC 24
Finished Aug 29 12:23:11 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513735346 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.2513735346
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/14.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/14.edn_disable_auto_req_mode.4166798733
Short name T379
Test name
Test status
Simulation time 28070597 ps
CPU time 1.58 seconds
Started Aug 29 12:23:09 AM UTC 24
Finished Aug 29 12:23:11 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166798733 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable_auto_req_mode.4166798733
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/14.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/14.edn_err.2764848983
Short name T179
Test name
Test status
Simulation time 32110675 ps
CPU time 1.21 seconds
Started Aug 29 12:23:08 AM UTC 24
Finished Aug 29 12:23:10 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764848983 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 14.edn_err.2764848983
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/14.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/14.edn_genbits.2566200411
Short name T50
Test name
Test status
Simulation time 54055748 ps
CPU time 1.84 seconds
Started Aug 29 12:23:07 AM UTC 24
Finished Aug 29 12:23:10 AM UTC 24
Peak memory 228560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566200411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2566200411
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/14.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/14.edn_intr.1233464348
Short name T375
Test name
Test status
Simulation time 21507715 ps
CPU time 1.6 seconds
Started Aug 29 12:23:07 AM UTC 24
Finished Aug 29 12:23:10 AM UTC 24
Peak memory 236700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233464348 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 14.edn_intr.1233464348
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/14.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/14.edn_smoke.1680033267
Short name T372
Test name
Test status
Simulation time 73349262 ps
CPU time 1.22 seconds
Started Aug 29 12:23:07 AM UTC 24
Finished Aug 29 12:23:10 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680033267 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 14.edn_smoke.1680033267
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/14.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/14.edn_stress_all.3080342055
Short name T376
Test name
Test status
Simulation time 81238812 ps
CPU time 1.79 seconds
Started Aug 29 12:23:07 AM UTC 24
Finished Aug 29 12:23:10 AM UTC 24
Peak memory 226332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080342055 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3080342055
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/14.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/140.edn_alert.2069870430
Short name T784
Test name
Test status
Simulation time 41345204 ps
CPU time 1.51 seconds
Started Aug 29 12:25:32 AM UTC 24
Finished Aug 29 12:25:55 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069870430 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 140.edn_alert.2069870430
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/140.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/140.edn_genbits.3660432201
Short name T780
Test name
Test status
Simulation time 132592987 ps
CPU time 1.35 seconds
Started Aug 29 12:25:32 AM UTC 24
Finished Aug 29 12:25:54 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660432201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 140.edn_genbits.3660432201
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/140.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/141.edn_alert.4065631201
Short name T274
Test name
Test status
Simulation time 47320075 ps
CPU time 1.55 seconds
Started Aug 29 12:25:32 AM UTC 24
Finished Aug 29 12:25:55 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065631201 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 141.edn_alert.4065631201
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/141.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/141.edn_genbits.57732322
Short name T786
Test name
Test status
Simulation time 57830152 ps
CPU time 1.64 seconds
Started Aug 29 12:25:32 AM UTC 24
Finished Aug 29 12:25:55 AM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57732322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 141.edn_genbits.57732322
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/141.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/142.edn_alert.1083386664
Short name T781
Test name
Test status
Simulation time 36932151 ps
CPU time 1.46 seconds
Started Aug 29 12:25:32 AM UTC 24
Finished Aug 29 12:25:55 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083386664 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 142.edn_alert.1083386664
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/142.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/142.edn_genbits.895640630
Short name T790
Test name
Test status
Simulation time 290052082 ps
CPU time 3.28 seconds
Started Aug 29 12:25:32 AM UTC 24
Finished Aug 29 12:25:56 AM UTC 24
Peak memory 231516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895640630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 142.edn_genbits.895640630
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/142.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/143.edn_alert.3467913236
Short name T755
Test name
Test status
Simulation time 22680928 ps
CPU time 1.17 seconds
Started Aug 29 12:25:32 AM UTC 24
Finished Aug 29 12:25:41 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467913236 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 143.edn_alert.3467913236
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/143.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/143.edn_genbits.2428018079
Short name T757
Test name
Test status
Simulation time 41223180 ps
CPU time 1.64 seconds
Started Aug 29 12:25:32 AM UTC 24
Finished Aug 29 12:25:42 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428018079 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2428018079
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/143.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/144.edn_alert.3710483553
Short name T160
Test name
Test status
Simulation time 249965423 ps
CPU time 1.25 seconds
Started Aug 29 12:25:33 AM UTC 24
Finished Aug 29 12:25:37 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710483553 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 144.edn_alert.3710483553
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/144.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/145.edn_alert.3611639645
Short name T753
Test name
Test status
Simulation time 133897778 ps
CPU time 1.28 seconds
Started Aug 29 12:25:33 AM UTC 24
Finished Aug 29 12:25:37 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611639645 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 145.edn_alert.3611639645
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/145.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/145.edn_genbits.442697176
Short name T752
Test name
Test status
Simulation time 31647345 ps
CPU time 1.13 seconds
Started Aug 29 12:25:33 AM UTC 24
Finished Aug 29 12:25:36 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442697176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 145.edn_genbits.442697176
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/145.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/146.edn_alert.4241006646
Short name T774
Test name
Test status
Simulation time 50549897 ps
CPU time 1.56 seconds
Started Aug 29 12:25:37 AM UTC 24
Finished Aug 29 12:25:53 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241006646 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 146.edn_alert.4241006646
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/146.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/146.edn_genbits.2561144313
Short name T754
Test name
Test status
Simulation time 39835075 ps
CPU time 1.4 seconds
Started Aug 29 12:25:33 AM UTC 24
Finished Aug 29 12:25:37 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561144313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2561144313
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/146.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/147.edn_genbits.3461969032
Short name T770
Test name
Test status
Simulation time 64552636 ps
CPU time 1.4 seconds
Started Aug 29 12:25:37 AM UTC 24
Finished Aug 29 12:25:53 AM UTC 24
Peak memory 230572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461969032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3461969032
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/147.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/148.edn_alert.3820525940
Short name T763
Test name
Test status
Simulation time 26028779 ps
CPU time 1.1 seconds
Started Aug 29 12:25:42 AM UTC 24
Finished Aug 29 12:25:52 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820525940 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 148.edn_alert.3820525940
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/148.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/148.edn_genbits.3061680916
Short name T775
Test name
Test status
Simulation time 44179224 ps
CPU time 1.55 seconds
Started Aug 29 12:25:37 AM UTC 24
Finished Aug 29 12:25:53 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061680916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 148.edn_genbits.3061680916
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/148.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/149.edn_alert.899646529
Short name T764
Test name
Test status
Simulation time 29315170 ps
CPU time 1.24 seconds
Started Aug 29 12:25:42 AM UTC 24
Finished Aug 29 12:25:52 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899646529 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 149.edn_alert.899646529
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/149.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/149.edn_genbits.1152170974
Short name T766
Test name
Test status
Simulation time 41491400 ps
CPU time 1.57 seconds
Started Aug 29 12:25:42 AM UTC 24
Finished Aug 29 12:25:52 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152170974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1152170974
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/149.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/15.edn_alert.757713082
Short name T147
Test name
Test status
Simulation time 78133935 ps
CPU time 1.38 seconds
Started Aug 29 12:23:09 AM UTC 24
Finished Aug 29 12:23:12 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757713082 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 15.edn_alert.757713082
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/15.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/15.edn_alert_test.3570089056
Short name T382
Test name
Test status
Simulation time 21111221 ps
CPU time 1.42 seconds
Started Aug 29 12:23:10 AM UTC 24
Finished Aug 29 12:23:13 AM UTC 24
Peak memory 226764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570089056 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3570089056
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/15.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/15.edn_disable_auto_req_mode.2000367622
Short name T385
Test name
Test status
Simulation time 55401116 ps
CPU time 1.81 seconds
Started Aug 29 12:23:10 AM UTC 24
Finished Aug 29 12:23:13 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000367622 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable_auto_req_mode.2000367622
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/15.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/15.edn_err.2369801382
Short name T191
Test name
Test status
Simulation time 19596645 ps
CPU time 1.27 seconds
Started Aug 29 12:23:10 AM UTC 24
Finished Aug 29 12:23:13 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369801382 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 15.edn_err.2369801382
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/15.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/15.edn_genbits.899707518
Short name T91
Test name
Test status
Simulation time 40498273 ps
CPU time 1.66 seconds
Started Aug 29 12:23:09 AM UTC 24
Finished Aug 29 12:23:12 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899707518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.edn_genbits.899707518
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/15.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/15.edn_intr.31186488
Short name T380
Test name
Test status
Simulation time 22043198 ps
CPU time 1.17 seconds
Started Aug 29 12:23:09 AM UTC 24
Finished Aug 29 12:23:11 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31186488 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_in
tr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 15.edn_intr.31186488
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/15.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/15.edn_smoke.3288027569
Short name T377
Test name
Test status
Simulation time 28950179 ps
CPU time 1.27 seconds
Started Aug 29 12:23:09 AM UTC 24
Finished Aug 29 12:23:11 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288027569 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 15.edn_smoke.3288027569
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/15.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/15.edn_stress_all.2864094861
Short name T393
Test name
Test status
Simulation time 334162929 ps
CPU time 7.61 seconds
Started Aug 29 12:23:09 AM UTC 24
Finished Aug 29 12:23:18 AM UTC 24
Peak memory 227420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864094861 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2864094861
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/15.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/15.edn_stress_all_with_rand_reset.1396824038
Short name T526
Test name
Test status
Simulation time 4414428843 ps
CPU time 93 seconds
Started Aug 29 12:23:09 AM UTC 24
Finished Aug 29 12:24:44 AM UTC 24
Peak memory 229852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1396824038 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all
_with_rand_reset.1396824038
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/15.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/150.edn_alert.1671370637
Short name T778
Test name
Test status
Simulation time 88574183 ps
CPU time 1.16 seconds
Started Aug 29 12:25:44 AM UTC 24
Finished Aug 29 12:25:54 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671370637 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 150.edn_alert.1671370637
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/150.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/150.edn_genbits.3030264842
Short name T765
Test name
Test status
Simulation time 269114720 ps
CPU time 1.26 seconds
Started Aug 29 12:25:43 AM UTC 24
Finished Aug 29 12:25:52 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030264842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3030264842
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/150.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/151.edn_alert.1263905434
Short name T779
Test name
Test status
Simulation time 25075107 ps
CPU time 1.17 seconds
Started Aug 29 12:25:44 AM UTC 24
Finished Aug 29 12:25:54 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263905434 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 151.edn_alert.1263905434
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/151.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/152.edn_alert.2370630992
Short name T789
Test name
Test status
Simulation time 61662545 ps
CPU time 1.39 seconds
Started Aug 29 12:25:53 AM UTC 24
Finished Aug 29 12:25:56 AM UTC 24
Peak memory 226292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370630992 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 152.edn_alert.2370630992
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/152.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/152.edn_genbits.1737384678
Short name T783
Test name
Test status
Simulation time 182436185 ps
CPU time 3.71 seconds
Started Aug 29 12:25:47 AM UTC 24
Finished Aug 29 12:25:55 AM UTC 24
Peak memory 231572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737384678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 152.edn_genbits.1737384678
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/152.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/153.edn_alert.2543692014
Short name T788
Test name
Test status
Simulation time 77282069 ps
CPU time 1.3 seconds
Started Aug 29 12:25:53 AM UTC 24
Finished Aug 29 12:25:56 AM UTC 24
Peak memory 230352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543692014 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 153.edn_alert.2543692014
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/153.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/153.edn_genbits.3299306010
Short name T334
Test name
Test status
Simulation time 41670251 ps
CPU time 1.3 seconds
Started Aug 29 12:25:53 AM UTC 24
Finished Aug 29 12:25:56 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299306010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3299306010
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/153.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/154.edn_alert.389760021
Short name T794
Test name
Test status
Simulation time 28470613 ps
CPU time 1.3 seconds
Started Aug 29 12:25:55 AM UTC 24
Finished Aug 29 12:26:07 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389760021 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 154.edn_alert.389760021
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/154.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/154.edn_genbits.1460819965
Short name T791
Test name
Test status
Simulation time 40507032 ps
CPU time 1.61 seconds
Started Aug 29 12:25:53 AM UTC 24
Finished Aug 29 12:25:57 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460819965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1460819965
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/154.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/155.edn_alert.3045797963
Short name T801
Test name
Test status
Simulation time 24567608 ps
CPU time 1.58 seconds
Started Aug 29 12:25:55 AM UTC 24
Finished Aug 29 12:26:07 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045797963 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 155.edn_alert.3045797963
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/155.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/155.edn_genbits.3704336953
Short name T795
Test name
Test status
Simulation time 60352356 ps
CPU time 1.24 seconds
Started Aug 29 12:25:55 AM UTC 24
Finished Aug 29 12:26:07 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704336953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3704336953
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/155.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/156.edn_alert.389426339
Short name T802
Test name
Test status
Simulation time 58188212 ps
CPU time 1.51 seconds
Started Aug 29 12:25:55 AM UTC 24
Finished Aug 29 12:26:07 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389426339 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 156.edn_alert.389426339
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/156.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/156.edn_genbits.916690923
Short name T804
Test name
Test status
Simulation time 231683345 ps
CPU time 3.1 seconds
Started Aug 29 12:25:55 AM UTC 24
Finished Aug 29 12:26:09 AM UTC 24
Peak memory 231776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916690923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 156.edn_genbits.916690923
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/156.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/157.edn_alert.4179808979
Short name T756
Test name
Test status
Simulation time 26215907 ps
CPU time 1.29 seconds
Started Aug 29 12:25:55 AM UTC 24
Finished Aug 29 12:26:17 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179808979 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 157.edn_alert.4179808979
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/157.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/158.edn_alert.4230650356
Short name T800
Test name
Test status
Simulation time 42658548 ps
CPU time 1.32 seconds
Started Aug 29 12:25:55 AM UTC 24
Finished Aug 29 12:26:07 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230650356 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 158.edn_alert.4230650356
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/158.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/158.edn_genbits.598435115
Short name T793
Test name
Test status
Simulation time 78301257 ps
CPU time 1 seconds
Started Aug 29 12:25:55 AM UTC 24
Finished Aug 29 12:26:07 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598435115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 158.edn_genbits.598435115
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/158.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/159.edn_alert.929045473
Short name T816
Test name
Test status
Simulation time 58892076 ps
CPU time 1.14 seconds
Started Aug 29 12:25:55 AM UTC 24
Finished Aug 29 12:26:17 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929045473 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 159.edn_alert.929045473
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/159.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/159.edn_genbits.3186306220
Short name T811
Test name
Test status
Simulation time 76457836 ps
CPU time 1.02 seconds
Started Aug 29 12:25:55 AM UTC 24
Finished Aug 29 12:26:17 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186306220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3186306220
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/159.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/16.edn_alert.3552085113
Short name T96
Test name
Test status
Simulation time 68747627 ps
CPU time 1.7 seconds
Started Aug 29 12:23:12 AM UTC 24
Finished Aug 29 12:23:14 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552085113 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 16.edn_alert.3552085113
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/16.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/16.edn_alert_test.3271430564
Short name T248
Test name
Test status
Simulation time 17908647 ps
CPU time 1.48 seconds
Started Aug 29 12:23:12 AM UTC 24
Finished Aug 29 12:23:14 AM UTC 24
Peak memory 226912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271430564 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3271430564
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/16.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/16.edn_disable.1351679839
Short name T105
Test name
Test status
Simulation time 40509648 ps
CPU time 1.23 seconds
Started Aug 29 12:23:12 AM UTC 24
Finished Aug 29 12:23:14 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351679839 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.1351679839
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/16.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/16.edn_disable_auto_req_mode.907874229
Short name T157
Test name
Test status
Simulation time 245864451 ps
CPU time 1.34 seconds
Started Aug 29 12:23:12 AM UTC 24
Finished Aug 29 12:23:14 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907874229 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable_auto_req_mode.907874229
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/16.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/16.edn_err.4009320716
Short name T245
Test name
Test status
Simulation time 49882475 ps
CPU time 0.93 seconds
Started Aug 29 12:23:12 AM UTC 24
Finished Aug 29 12:23:14 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009320716 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 16.edn_err.4009320716
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/16.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/16.edn_genbits.3704236028
Short name T386
Test name
Test status
Simulation time 67168299 ps
CPU time 1.87 seconds
Started Aug 29 12:23:10 AM UTC 24
Finished Aug 29 12:23:13 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704236028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_genbits.3704236028
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/16.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/16.edn_intr.756489624
Short name T384
Test name
Test status
Simulation time 22592905 ps
CPU time 1.36 seconds
Started Aug 29 12:23:11 AM UTC 24
Finished Aug 29 12:23:13 AM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756489624 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 16.edn_intr.756489624
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/16.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/16.edn_smoke.2105667245
Short name T383
Test name
Test status
Simulation time 36135671 ps
CPU time 1.4 seconds
Started Aug 29 12:23:10 AM UTC 24
Finished Aug 29 12:23:13 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105667245 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 16.edn_smoke.2105667245
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/16.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/16.edn_stress_all.2106408073
Short name T247
Test name
Test status
Simulation time 371097303 ps
CPU time 2.56 seconds
Started Aug 29 12:23:10 AM UTC 24
Finished Aug 29 12:23:14 AM UTC 24
Peak memory 227688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106408073 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2106408073
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/16.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/160.edn_alert.541933921
Short name T815
Test name
Test status
Simulation time 24655401 ps
CPU time 1.16 seconds
Started Aug 29 12:25:55 AM UTC 24
Finished Aug 29 12:26:17 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541933921 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 160.edn_alert.541933921
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/160.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/160.edn_genbits.1292473202
Short name T813
Test name
Test status
Simulation time 120076974 ps
CPU time 1.15 seconds
Started Aug 29 12:25:55 AM UTC 24
Finished Aug 29 12:26:17 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292473202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1292473202
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/160.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/161.edn_alert.3021055189
Short name T822
Test name
Test status
Simulation time 52257338 ps
CPU time 1.28 seconds
Started Aug 29 12:25:56 AM UTC 24
Finished Aug 29 12:26:19 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021055189 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 161.edn_alert.3021055189
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/161.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/161.edn_genbits.122127417
Short name T818
Test name
Test status
Simulation time 34299392 ps
CPU time 1.38 seconds
Started Aug 29 12:25:55 AM UTC 24
Finished Aug 29 12:26:18 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122127417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 161.edn_genbits.122127417
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/161.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/162.edn_alert.3964426592
Short name T821
Test name
Test status
Simulation time 95339834 ps
CPU time 1.23 seconds
Started Aug 29 12:25:56 AM UTC 24
Finished Aug 29 12:26:19 AM UTC 24
Peak memory 226360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964426592 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 162.edn_alert.3964426592
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/162.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/162.edn_genbits.3602403291
Short name T805
Test name
Test status
Simulation time 30612821 ps
CPU time 1.27 seconds
Started Aug 29 12:25:56 AM UTC 24
Finished Aug 29 12:26:12 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602403291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 162.edn_genbits.3602403291
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/162.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/163.edn_alert.2228624417
Short name T824
Test name
Test status
Simulation time 57877734 ps
CPU time 1.12 seconds
Started Aug 29 12:25:56 AM UTC 24
Finished Aug 29 12:26:19 AM UTC 24
Peak memory 225448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228624417 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 163.edn_alert.2228624417
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/163.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/163.edn_genbits.1094945896
Short name T806
Test name
Test status
Simulation time 172056093 ps
CPU time 1.17 seconds
Started Aug 29 12:25:56 AM UTC 24
Finished Aug 29 12:26:12 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094945896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1094945896
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/163.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/164.edn_alert.3033957780
Short name T833
Test name
Test status
Simulation time 87021637 ps
CPU time 1.24 seconds
Started Aug 29 12:25:56 AM UTC 24
Finished Aug 29 12:26:22 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033957780 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 164.edn_alert.3033957780
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/164.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/164.edn_genbits.2597588812
Short name T339
Test name
Test status
Simulation time 45815636 ps
CPU time 1.6 seconds
Started Aug 29 12:25:56 AM UTC 24
Finished Aug 29 12:26:19 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597588812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2597588812
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/164.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/165.edn_alert.1506999086
Short name T844
Test name
Test status
Simulation time 48466329 ps
CPU time 1.53 seconds
Started Aug 29 12:25:56 AM UTC 24
Finished Aug 29 12:26:22 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506999086 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 165.edn_alert.1506999086
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/165.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/165.edn_genbits.813698519
Short name T835
Test name
Test status
Simulation time 27744964 ps
CPU time 1.17 seconds
Started Aug 29 12:25:56 AM UTC 24
Finished Aug 29 12:26:22 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813698519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 165.edn_genbits.813698519
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/165.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/166.edn_alert.512054729
Short name T797
Test name
Test status
Simulation time 27990415 ps
CPU time 1.15 seconds
Started Aug 29 12:25:58 AM UTC 24
Finished Aug 29 12:26:07 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512054729 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 166.edn_alert.512054729
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/166.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/166.edn_genbits.1773496791
Short name T852
Test name
Test status
Simulation time 41741944 ps
CPU time 2.04 seconds
Started Aug 29 12:25:57 AM UTC 24
Finished Aug 29 12:26:23 AM UTC 24
Peak memory 229428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773496791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 166.edn_genbits.1773496791
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/166.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/167.edn_alert.3079024148
Short name T817
Test name
Test status
Simulation time 30581163 ps
CPU time 1.33 seconds
Started Aug 29 12:25:58 AM UTC 24
Finished Aug 29 12:26:17 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079024148 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 167.edn_alert.3079024148
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/167.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/167.edn_genbits.57802071
Short name T803
Test name
Test status
Simulation time 49105400 ps
CPU time 1.84 seconds
Started Aug 29 12:25:58 AM UTC 24
Finished Aug 29 12:26:08 AM UTC 24
Peak memory 230612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57802071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 167.edn_genbits.57802071
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/167.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/168.edn_alert.2681001208
Short name T812
Test name
Test status
Simulation time 77304369 ps
CPU time 1.08 seconds
Started Aug 29 12:25:58 AM UTC 24
Finished Aug 29 12:26:17 AM UTC 24
Peak memory 232520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681001208 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 168.edn_alert.2681001208
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/168.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/168.edn_genbits.2079486470
Short name T796
Test name
Test status
Simulation time 23176435 ps
CPU time 1.12 seconds
Started Aug 29 12:25:58 AM UTC 24
Finished Aug 29 12:26:07 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079486470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 168.edn_genbits.2079486470
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/168.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/169.edn_alert.1160726742
Short name T814
Test name
Test status
Simulation time 27278986 ps
CPU time 1.03 seconds
Started Aug 29 12:26:05 AM UTC 24
Finished Aug 29 12:26:17 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160726742 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 169.edn_alert.1160726742
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/169.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/169.edn_genbits.47063135
Short name T799
Test name
Test status
Simulation time 64604116 ps
CPU time 1.11 seconds
Started Aug 29 12:25:58 AM UTC 24
Finished Aug 29 12:26:07 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47063135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 169.edn_genbits.47063135
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/169.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/17.edn_alert.2360906756
Short name T171
Test name
Test status
Simulation time 44152339 ps
CPU time 1.22 seconds
Started Aug 29 12:23:13 AM UTC 24
Finished Aug 29 12:23:16 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360906756 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 17.edn_alert.2360906756
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/17.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/17.edn_alert_test.2988778219
Short name T388
Test name
Test status
Simulation time 48385224 ps
CPU time 1.29 seconds
Started Aug 29 12:23:14 AM UTC 24
Finished Aug 29 12:23:16 AM UTC 24
Peak memory 226912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988778219 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2988778219
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/17.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/17.edn_disable.826348959
Short name T211
Test name
Test status
Simulation time 15836610 ps
CPU time 1.03 seconds
Started Aug 29 12:23:13 AM UTC 24
Finished Aug 29 12:23:16 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826348959 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.826348959
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/17.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/17.edn_disable_auto_req_mode.402241029
Short name T266
Test name
Test status
Simulation time 24028309 ps
CPU time 1.62 seconds
Started Aug 29 12:23:14 AM UTC 24
Finished Aug 29 12:23:16 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402241029 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable_auto_req_mode.402241029
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/17.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/17.edn_err.1040684284
Short name T219
Test name
Test status
Simulation time 19987889 ps
CPU time 1.52 seconds
Started Aug 29 12:23:13 AM UTC 24
Finished Aug 29 12:23:16 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040684284 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 17.edn_err.1040684284
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/17.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/17.edn_intr.128981954
Short name T249
Test name
Test status
Simulation time 26145687 ps
CPU time 1.42 seconds
Started Aug 29 12:23:12 AM UTC 24
Finished Aug 29 12:23:15 AM UTC 24
Peak memory 228480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128981954 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 17.edn_intr.128981954
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/17.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/17.edn_smoke.2362682822
Short name T246
Test name
Test status
Simulation time 158163006 ps
CPU time 1.18 seconds
Started Aug 29 12:23:12 AM UTC 24
Finished Aug 29 12:23:14 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362682822 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 17.edn_smoke.2362682822
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/17.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/17.edn_stress_all.1841997209
Short name T330
Test name
Test status
Simulation time 163813780 ps
CPU time 1.81 seconds
Started Aug 29 12:23:12 AM UTC 24
Finished Aug 29 12:23:15 AM UTC 24
Peak memory 226264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841997209 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1841997209
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/17.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/170.edn_alert.1424088875
Short name T820
Test name
Test status
Simulation time 120472139 ps
CPU time 1.06 seconds
Started Aug 29 12:26:08 AM UTC 24
Finished Aug 29 12:26:19 AM UTC 24
Peak memory 226368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424088875 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 170.edn_alert.1424088875
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/170.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/170.edn_genbits.3654556636
Short name T827
Test name
Test status
Simulation time 193360435 ps
CPU time 1.83 seconds
Started Aug 29 12:26:08 AM UTC 24
Finished Aug 29 12:26:19 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654556636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 170.edn_genbits.3654556636
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/170.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/171.edn_alert.3459726900
Short name T825
Test name
Test status
Simulation time 29047991 ps
CPU time 1.24 seconds
Started Aug 29 12:26:08 AM UTC 24
Finished Aug 29 12:26:19 AM UTC 24
Peak memory 229364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459726900 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 171.edn_alert.3459726900
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/171.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/171.edn_genbits.1166336908
Short name T826
Test name
Test status
Simulation time 68891093 ps
CPU time 1.37 seconds
Started Aug 29 12:26:08 AM UTC 24
Finished Aug 29 12:26:19 AM UTC 24
Peak memory 230584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166336908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1166336908
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/171.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/172.edn_alert.4205383460
Short name T823
Test name
Test status
Simulation time 34688636 ps
CPU time 1.15 seconds
Started Aug 29 12:26:08 AM UTC 24
Finished Aug 29 12:26:19 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205383460 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 172.edn_alert.4205383460
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/172.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/172.edn_genbits.1918604363
Short name T837
Test name
Test status
Simulation time 85929743 ps
CPU time 1.46 seconds
Started Aug 29 12:26:08 AM UTC 24
Finished Aug 29 12:26:22 AM UTC 24
Peak memory 228280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918604363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 172.edn_genbits.1918604363
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/172.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/173.edn_alert.3766531489
Short name T830
Test name
Test status
Simulation time 67963205 ps
CPU time 1.09 seconds
Started Aug 29 12:26:09 AM UTC 24
Finished Aug 29 12:26:22 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766531489 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 173.edn_alert.3766531489
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/173.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/173.edn_genbits.1281918174
Short name T849
Test name
Test status
Simulation time 149801460 ps
CPU time 1.89 seconds
Started Aug 29 12:26:08 AM UTC 24
Finished Aug 29 12:26:22 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281918174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1281918174
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/173.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/174.edn_alert.3430443625
Short name T831
Test name
Test status
Simulation time 53466097 ps
CPU time 1.12 seconds
Started Aug 29 12:26:09 AM UTC 24
Finished Aug 29 12:26:22 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430443625 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 174.edn_alert.3430443625
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/174.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/174.edn_genbits.3211146702
Short name T838
Test name
Test status
Simulation time 60611539 ps
CPU time 1.42 seconds
Started Aug 29 12:26:09 AM UTC 24
Finished Aug 29 12:26:22 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211146702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3211146702
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/174.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/175.edn_alert.330683993
Short name T850
Test name
Test status
Simulation time 253081322 ps
CPU time 1.61 seconds
Started Aug 29 12:26:09 AM UTC 24
Finished Aug 29 12:26:23 AM UTC 24
Peak memory 230432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330683993 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 175.edn_alert.330683993
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/175.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/175.edn_genbits.2468501173
Short name T834
Test name
Test status
Simulation time 22596375 ps
CPU time 1.14 seconds
Started Aug 29 12:26:09 AM UTC 24
Finished Aug 29 12:26:22 AM UTC 24
Peak memory 227836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468501173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 175.edn_genbits.2468501173
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/175.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/176.edn_alert.2727176773
Short name T840
Test name
Test status
Simulation time 97742246 ps
CPU time 1.25 seconds
Started Aug 29 12:26:10 AM UTC 24
Finished Aug 29 12:26:22 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727176773 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 176.edn_alert.2727176773
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/176.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/176.edn_genbits.1741749097
Short name T842
Test name
Test status
Simulation time 33086278 ps
CPU time 1.46 seconds
Started Aug 29 12:26:10 AM UTC 24
Finished Aug 29 12:26:22 AM UTC 24
Peak memory 228348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741749097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1741749097
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/176.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/177.edn_alert.1629579789
Short name T810
Test name
Test status
Simulation time 89414587 ps
CPU time 1.12 seconds
Started Aug 29 12:26:13 AM UTC 24
Finished Aug 29 12:26:16 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629579789 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 177.edn_alert.1629579789
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/177.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/177.edn_genbits.3063052410
Short name T809
Test name
Test status
Simulation time 62383129 ps
CPU time 0.93 seconds
Started Aug 29 12:26:13 AM UTC 24
Finished Aug 29 12:26:16 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063052410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 177.edn_genbits.3063052410
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/177.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/179.edn_alert.900584255
Short name T861
Test name
Test status
Simulation time 65353318 ps
CPU time 1.03 seconds
Started Aug 29 12:26:17 AM UTC 24
Finished Aug 29 12:26:27 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900584255 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 179.edn_alert.900584255
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/179.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/179.edn_genbits.385416205
Short name T819
Test name
Test status
Simulation time 45808296 ps
CPU time 1.42 seconds
Started Aug 29 12:26:15 AM UTC 24
Finished Aug 29 12:26:18 AM UTC 24
Peak memory 228564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385416205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 179.edn_genbits.385416205
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/179.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/18.edn_alert.2678737616
Short name T92
Test name
Test status
Simulation time 79211054 ps
CPU time 1.34 seconds
Started Aug 29 12:23:15 AM UTC 24
Finished Aug 29 12:23:17 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678737616 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 18.edn_alert.2678737616
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/18.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/18.edn_alert_test.2411373622
Short name T391
Test name
Test status
Simulation time 41125087 ps
CPU time 1.28 seconds
Started Aug 29 12:23:15 AM UTC 24
Finished Aug 29 12:23:17 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411373622 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2411373622
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/18.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/18.edn_disable.2815984350
Short name T222
Test name
Test status
Simulation time 37517695 ps
CPU time 1.22 seconds
Started Aug 29 12:23:15 AM UTC 24
Finished Aug 29 12:23:17 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815984350 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2815984350
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/18.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/18.edn_disable_auto_req_mode.1323566325
Short name T390
Test name
Test status
Simulation time 16685813 ps
CPU time 1.22 seconds
Started Aug 29 12:23:15 AM UTC 24
Finished Aug 29 12:23:17 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323566325 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable_auto_req_mode.1323566325
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/18.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/18.edn_err.1201340978
Short name T124
Test name
Test status
Simulation time 19552098 ps
CPU time 1.56 seconds
Started Aug 29 12:23:15 AM UTC 24
Finished Aug 29 12:23:18 AM UTC 24
Peak memory 236968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201340978 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 18.edn_err.1201340978
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/18.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/18.edn_genbits.669708907
Short name T389
Test name
Test status
Simulation time 156738435 ps
CPU time 2.41 seconds
Started Aug 29 12:23:14 AM UTC 24
Finished Aug 29 12:23:17 AM UTC 24
Peak memory 231492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669708907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.edn_genbits.669708907
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/18.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/18.edn_intr.235402287
Short name T140
Test name
Test status
Simulation time 21985452 ps
CPU time 1.31 seconds
Started Aug 29 12:23:15 AM UTC 24
Finished Aug 29 12:23:17 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235402287 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 18.edn_intr.235402287
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/18.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/18.edn_smoke.1932586698
Short name T387
Test name
Test status
Simulation time 78349562 ps
CPU time 1.25 seconds
Started Aug 29 12:23:14 AM UTC 24
Finished Aug 29 12:23:16 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932586698 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 18.edn_smoke.1932586698
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/18.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/18.edn_stress_all.2239519354
Short name T396
Test name
Test status
Simulation time 606280371 ps
CPU time 4.59 seconds
Started Aug 29 12:23:14 AM UTC 24
Finished Aug 29 12:23:19 AM UTC 24
Peak memory 229544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239519354 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.2239519354
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/18.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/18.edn_stress_all_with_rand_reset.3079765667
Short name T595
Test name
Test status
Simulation time 9381415974 ps
CPU time 106.5 seconds
Started Aug 29 12:23:14 AM UTC 24
Finished Aug 29 12:25:02 AM UTC 24
Peak memory 229876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3079765667 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all
_with_rand_reset.3079765667
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/18.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/180.edn_alert.500837247
Short name T275
Test name
Test status
Simulation time 46417696 ps
CPU time 1.44 seconds
Started Aug 29 12:26:17 AM UTC 24
Finished Aug 29 12:26:27 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500837247 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 180.edn_alert.500837247
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/180.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/180.edn_genbits.1123225996
Short name T887
Test name
Test status
Simulation time 190837578 ps
CPU time 3.21 seconds
Started Aug 29 12:26:17 AM UTC 24
Finished Aug 29 12:26:29 AM UTC 24
Peak memory 231560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123225996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 180.edn_genbits.1123225996
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/180.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/181.edn_alert.3624938520
Short name T843
Test name
Test status
Simulation time 27357668 ps
CPU time 1.48 seconds
Started Aug 29 12:26:19 AM UTC 24
Finished Aug 29 12:26:22 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624938520 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 181.edn_alert.3624938520
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/181.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/181.edn_genbits.1802291978
Short name T875
Test name
Test status
Simulation time 57027747 ps
CPU time 1.72 seconds
Started Aug 29 12:26:17 AM UTC 24
Finished Aug 29 12:26:27 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802291978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 181.edn_genbits.1802291978
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/181.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/182.edn_alert.1185596967
Short name T836
Test name
Test status
Simulation time 32264550 ps
CPU time 1.27 seconds
Started Aug 29 12:26:19 AM UTC 24
Finished Aug 29 12:26:22 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185596967 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 182.edn_alert.1185596967
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/182.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/182.edn_genbits.2880574908
Short name T839
Test name
Test status
Simulation time 79426786 ps
CPU time 1.56 seconds
Started Aug 29 12:26:19 AM UTC 24
Finished Aug 29 12:26:22 AM UTC 24
Peak memory 230420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880574908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 182.edn_genbits.2880574908
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/182.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/183.edn_alert.182238510
Short name T832
Test name
Test status
Simulation time 81198724 ps
CPU time 1.04 seconds
Started Aug 29 12:26:19 AM UTC 24
Finished Aug 29 12:26:22 AM UTC 24
Peak memory 229588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182238510 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 183.edn_alert.182238510
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/183.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/183.edn_genbits.1757252711
Short name T846
Test name
Test status
Simulation time 52973721 ps
CPU time 1.56 seconds
Started Aug 29 12:26:19 AM UTC 24
Finished Aug 29 12:26:22 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757252711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 183.edn_genbits.1757252711
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/183.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/184.edn_alert.2302902440
Short name T828
Test name
Test status
Simulation time 27431094 ps
CPU time 1.18 seconds
Started Aug 29 12:26:19 AM UTC 24
Finished Aug 29 12:26:21 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302902440 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 184.edn_alert.2302902440
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/184.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/184.edn_genbits.2513800966
Short name T854
Test name
Test status
Simulation time 43220893 ps
CPU time 1.98 seconds
Started Aug 29 12:26:19 AM UTC 24
Finished Aug 29 12:26:23 AM UTC 24
Peak memory 230420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513800966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2513800966
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/184.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/185.edn_alert.3477501771
Short name T848
Test name
Test status
Simulation time 54543252 ps
CPU time 1.44 seconds
Started Aug 29 12:26:19 AM UTC 24
Finished Aug 29 12:26:22 AM UTC 24
Peak memory 226304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477501771 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 185.edn_alert.3477501771
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/185.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/185.edn_genbits.2570004027
Short name T851
Test name
Test status
Simulation time 46600561 ps
CPU time 1.79 seconds
Started Aug 29 12:26:19 AM UTC 24
Finished Aug 29 12:26:23 AM UTC 24
Peak memory 228200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570004027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2570004027
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/185.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/186.edn_alert.3181178415
Short name T888
Test name
Test status
Simulation time 22997862 ps
CPU time 1.08 seconds
Started Aug 29 12:26:20 AM UTC 24
Finished Aug 29 12:26:29 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181178415 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 186.edn_alert.3181178415
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/186.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/186.edn_genbits.473566996
Short name T841
Test name
Test status
Simulation time 90219811 ps
CPU time 1.15 seconds
Started Aug 29 12:26:19 AM UTC 24
Finished Aug 29 12:26:22 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473566996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 186.edn_genbits.473566996
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/186.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/187.edn_alert.3832329568
Short name T845
Test name
Test status
Simulation time 44124657 ps
CPU time 1.2 seconds
Started Aug 29 12:26:20 AM UTC 24
Finished Aug 29 12:26:22 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832329568 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 187.edn_alert.3832329568
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/187.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/187.edn_genbits.3510014041
Short name T908
Test name
Test status
Simulation time 167994166 ps
CPU time 2.45 seconds
Started Aug 29 12:26:20 AM UTC 24
Finished Aug 29 12:26:31 AM UTC 24
Peak memory 231576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510014041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3510014041
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/187.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/188.edn_alert.4294054721
Short name T889
Test name
Test status
Simulation time 40091093 ps
CPU time 1.1 seconds
Started Aug 29 12:26:20 AM UTC 24
Finished Aug 29 12:26:29 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294054721 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 188.edn_alert.4294054721
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/188.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/188.edn_genbits.3584960915
Short name T890
Test name
Test status
Simulation time 245060072 ps
CPU time 1.16 seconds
Started Aug 29 12:26:20 AM UTC 24
Finished Aug 29 12:26:29 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584960915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3584960915
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/188.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/189.edn_alert.2399393900
Short name T847
Test name
Test status
Simulation time 62546195 ps
CPU time 1.15 seconds
Started Aug 29 12:26:20 AM UTC 24
Finished Aug 29 12:26:22 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399393900 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 189.edn_alert.2399393900
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/189.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/189.edn_genbits.3359032216
Short name T891
Test name
Test status
Simulation time 187094338 ps
CPU time 1.18 seconds
Started Aug 29 12:26:20 AM UTC 24
Finished Aug 29 12:26:29 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359032216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 189.edn_genbits.3359032216
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/189.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/19.edn_alert.825952534
Short name T138
Test name
Test status
Simulation time 31380598 ps
CPU time 1.38 seconds
Started Aug 29 12:23:16 AM UTC 24
Finished Aug 29 12:23:19 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825952534 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 19.edn_alert.825952534
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/19.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/19.edn_alert_test.2141731335
Short name T371
Test name
Test status
Simulation time 34161884 ps
CPU time 1.22 seconds
Started Aug 29 12:23:17 AM UTC 24
Finished Aug 29 12:23:19 AM UTC 24
Peak memory 217052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141731335 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2141731335
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/19.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/19.edn_disable.2780356951
Short name T107
Test name
Test status
Simulation time 12003696 ps
CPU time 1.41 seconds
Started Aug 29 12:23:17 AM UTC 24
Finished Aug 29 12:23:19 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780356951 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2780356951
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/19.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/19.edn_disable_auto_req_mode.3840906191
Short name T395
Test name
Test status
Simulation time 75952504 ps
CPU time 1.72 seconds
Started Aug 29 12:23:17 AM UTC 24
Finished Aug 29 12:23:19 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840906191 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable_auto_req_mode.3840906191
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/19.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/19.edn_err.3616163421
Short name T125
Test name
Test status
Simulation time 21233044 ps
CPU time 1.35 seconds
Started Aug 29 12:23:16 AM UTC 24
Finished Aug 29 12:23:19 AM UTC 24
Peak memory 236968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616163421 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 19.edn_err.3616163421
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/19.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/19.edn_genbits.3992946793
Short name T106
Test name
Test status
Simulation time 53903680 ps
CPU time 1.94 seconds
Started Aug 29 12:23:15 AM UTC 24
Finished Aug 29 12:23:18 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992946793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3992946793
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/19.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/19.edn_intr.500657063
Short name T90
Test name
Test status
Simulation time 36709106 ps
CPU time 1.29 seconds
Started Aug 29 12:23:16 AM UTC 24
Finished Aug 29 12:23:19 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500657063 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 19.edn_intr.500657063
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/19.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/19.edn_smoke.796411843
Short name T392
Test name
Test status
Simulation time 37659484 ps
CPU time 1.3 seconds
Started Aug 29 12:23:15 AM UTC 24
Finished Aug 29 12:23:17 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796411843 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 19.edn_smoke.796411843
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/19.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/19.edn_stress_all.3796897824
Short name T307
Test name
Test status
Simulation time 404245891 ps
CPU time 4.91 seconds
Started Aug 29 12:23:15 AM UTC 24
Finished Aug 29 12:23:21 AM UTC 24
Peak memory 227688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796897824 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3796897824
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/19.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/19.edn_stress_all_with_rand_reset.3089827645
Short name T242
Test name
Test status
Simulation time 12809825519 ps
CPU time 47.71 seconds
Started Aug 29 12:23:15 AM UTC 24
Finished Aug 29 12:24:04 AM UTC 24
Peak memory 230132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3089827645 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all
_with_rand_reset.3089827645
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/19.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/190.edn_alert.3295115437
Short name T853
Test name
Test status
Simulation time 29217047 ps
CPU time 1.38 seconds
Started Aug 29 12:26:20 AM UTC 24
Finished Aug 29 12:26:23 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295115437 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 190.edn_alert.3295115437
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/190.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/190.edn_genbits.696558601
Short name T893
Test name
Test status
Simulation time 180423335 ps
CPU time 1.08 seconds
Started Aug 29 12:26:20 AM UTC 24
Finished Aug 29 12:26:30 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696558601 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 190.edn_genbits.696558601
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/190.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/191.edn_alert.2352740474
Short name T877
Test name
Test status
Simulation time 84483739 ps
CPU time 1.24 seconds
Started Aug 29 12:26:22 AM UTC 24
Finished Aug 29 12:26:28 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352740474 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 191.edn_alert.2352740474
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/191.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/191.edn_genbits.2736793405
Short name T864
Test name
Test status
Simulation time 207236439 ps
CPU time 1.36 seconds
Started Aug 29 12:26:21 AM UTC 24
Finished Aug 29 12:26:27 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736793405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2736793405
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/191.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/192.edn_alert.2449961752
Short name T880
Test name
Test status
Simulation time 24397176 ps
CPU time 1.31 seconds
Started Aug 29 12:26:22 AM UTC 24
Finished Aug 29 12:26:28 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449961752 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 192.edn_alert.2449961752
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/192.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/192.edn_genbits.2960770479
Short name T883
Test name
Test status
Simulation time 37607008 ps
CPU time 1.57 seconds
Started Aug 29 12:26:22 AM UTC 24
Finished Aug 29 12:26:28 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960770479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2960770479
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/192.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/193.edn_alert.3889732671
Short name T878
Test name
Test status
Simulation time 38843324 ps
CPU time 1.17 seconds
Started Aug 29 12:26:23 AM UTC 24
Finished Aug 29 12:26:28 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889732671 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 193.edn_alert.3889732671
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/193.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/193.edn_genbits.2288847231
Short name T882
Test name
Test status
Simulation time 37868517 ps
CPU time 1.44 seconds
Started Aug 29 12:26:23 AM UTC 24
Finished Aug 29 12:26:28 AM UTC 24
Peak memory 230616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288847231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2288847231
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/193.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/194.edn_alert.4216007817
Short name T881
Test name
Test status
Simulation time 24078383 ps
CPU time 1.07 seconds
Started Aug 29 12:26:23 AM UTC 24
Finished Aug 29 12:26:28 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216007817 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 194.edn_alert.4216007817
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/194.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/194.edn_genbits.3415769365
Short name T879
Test name
Test status
Simulation time 93787049 ps
CPU time 1.14 seconds
Started Aug 29 12:26:23 AM UTC 24
Finished Aug 29 12:26:28 AM UTC 24
Peak memory 230208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415769365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3415769365
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/194.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/195.edn_alert.529094102
Short name T868
Test name
Test status
Simulation time 27963370 ps
CPU time 1.32 seconds
Started Aug 29 12:26:24 AM UTC 24
Finished Aug 29 12:26:27 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529094102 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 195.edn_alert.529094102
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/195.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/195.edn_genbits.1588918015
Short name T886
Test name
Test status
Simulation time 152299712 ps
CPU time 1.77 seconds
Started Aug 29 12:26:23 AM UTC 24
Finished Aug 29 12:26:29 AM UTC 24
Peak memory 230420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588918015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 195.edn_genbits.1588918015
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/195.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/196.edn_alert.938705489
Short name T866
Test name
Test status
Simulation time 97829874 ps
CPU time 1.13 seconds
Started Aug 29 12:26:24 AM UTC 24
Finished Aug 29 12:26:27 AM UTC 24
Peak memory 228428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938705489 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 196.edn_alert.938705489
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/196.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/196.edn_genbits.3566091413
Short name T869
Test name
Test status
Simulation time 33663937 ps
CPU time 1.18 seconds
Started Aug 29 12:26:24 AM UTC 24
Finished Aug 29 12:26:27 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566091413 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3566091413
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/196.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/197.edn_alert.2557029733
Short name T870
Test name
Test status
Simulation time 21725018 ps
CPU time 1.15 seconds
Started Aug 29 12:26:24 AM UTC 24
Finished Aug 29 12:26:27 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557029733 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 197.edn_alert.2557029733
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/197.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/197.edn_genbits.1627202571
Short name T867
Test name
Test status
Simulation time 207121327 ps
CPU time 1.08 seconds
Started Aug 29 12:26:24 AM UTC 24
Finished Aug 29 12:26:27 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627202571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1627202571
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/197.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/198.edn_alert.1379479228
Short name T874
Test name
Test status
Simulation time 28356218 ps
CPU time 1.23 seconds
Started Aug 29 12:26:24 AM UTC 24
Finished Aug 29 12:26:27 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379479228 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 198.edn_alert.1379479228
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/198.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/198.edn_genbits.2156446320
Short name T876
Test name
Test status
Simulation time 143452962 ps
CPU time 1.6 seconds
Started Aug 29 12:26:24 AM UTC 24
Finished Aug 29 12:26:28 AM UTC 24
Peak memory 230420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156446320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2156446320
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/198.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/199.edn_alert.2392505327
Short name T856
Test name
Test status
Simulation time 65946625 ps
CPU time 1.21 seconds
Started Aug 29 12:26:24 AM UTC 24
Finished Aug 29 12:26:26 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392505327 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 199.edn_alert.2392505327
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/199.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/199.edn_genbits.597853585
Short name T857
Test name
Test status
Simulation time 52005212 ps
CPU time 1.33 seconds
Started Aug 29 12:26:24 AM UTC 24
Finished Aug 29 12:26:26 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597853585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 199.edn_genbits.597853585
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/199.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/2.edn_alert.4038589304
Short name T30
Test name
Test status
Simulation time 63996481 ps
CPU time 1.16 seconds
Started Aug 29 12:22:50 AM UTC 24
Finished Aug 29 12:22:53 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038589304 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 2.edn_alert.4038589304
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/2.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/2.edn_alert_test.1636666162
Short name T80
Test name
Test status
Simulation time 66011869 ps
CPU time 1.22 seconds
Started Aug 29 12:22:51 AM UTC 24
Finished Aug 29 12:22:54 AM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636666162 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.1636666162
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/2.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/2.edn_disable.1886440518
Short name T84
Test name
Test status
Simulation time 13182516 ps
CPU time 0.99 seconds
Started Aug 29 12:22:50 AM UTC 24
Finished Aug 29 12:22:53 AM UTC 24
Peak memory 216132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886440518 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1886440518
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/2.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/2.edn_err.2118024829
Short name T8
Test name
Test status
Simulation time 22979330 ps
CPU time 1.16 seconds
Started Aug 29 12:22:50 AM UTC 24
Finished Aug 29 12:22:53 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118024829 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 2.edn_err.2118024829
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/2.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/2.edn_genbits.267221620
Short name T135
Test name
Test status
Simulation time 86227337 ps
CPU time 1.46 seconds
Started Aug 29 12:22:50 AM UTC 24
Finished Aug 29 12:22:53 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267221620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_genbits.267221620
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/2.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/2.edn_intr.646588898
Short name T61
Test name
Test status
Simulation time 21397409 ps
CPU time 1.43 seconds
Started Aug 29 12:22:50 AM UTC 24
Finished Aug 29 12:22:53 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646588898 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 2.edn_intr.646588898
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/2.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/2.edn_regwen.3868952556
Short name T25
Test name
Test status
Simulation time 49185142 ps
CPU time 1.28 seconds
Started Aug 29 12:22:50 AM UTC 24
Finished Aug 29 12:22:52 AM UTC 24
Peak memory 216032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868952556 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 2.edn_regwen.3868952556
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/2.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/2.edn_sec_cm.1829428485
Short name T16
Test name
Test status
Simulation time 236418315 ps
CPU time 4.86 seconds
Started Aug 29 12:22:51 AM UTC 24
Finished Aug 29 12:22:57 AM UTC 24
Peak memory 260388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829428485 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1829428485
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/2.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/2.edn_smoke.2661243423
Short name T81
Test name
Test status
Simulation time 37637207 ps
CPU time 0.95 seconds
Started Aug 29 12:22:50 AM UTC 24
Finished Aug 29 12:22:52 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661243423 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 2.edn_smoke.2661243423
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/2.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/2.edn_stress_all_with_rand_reset.1839530170
Short name T37
Test name
Test status
Simulation time 1233922860 ps
CPU time 22.93 seconds
Started Aug 29 12:22:50 AM UTC 24
Finished Aug 29 12:23:15 AM UTC 24
Peak memory 229588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1839530170 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_
with_rand_reset.1839530170
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/2.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/20.edn_alert.493459157
Short name T203
Test name
Test status
Simulation time 72873332 ps
CPU time 1.52 seconds
Started Aug 29 12:23:18 AM UTC 24
Finished Aug 29 12:23:21 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493459157 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 20.edn_alert.493459157
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/20.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/20.edn_alert_test.3259425447
Short name T399
Test name
Test status
Simulation time 29827013 ps
CPU time 1.32 seconds
Started Aug 29 12:23:18 AM UTC 24
Finished Aug 29 12:23:20 AM UTC 24
Peak memory 217052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259425447 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3259425447
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/20.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/20.edn_disable.1007903387
Short name T232
Test name
Test status
Simulation time 12896184 ps
CPU time 1.31 seconds
Started Aug 29 12:23:18 AM UTC 24
Finished Aug 29 12:23:20 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007903387 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1007903387
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/20.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/20.edn_disable_auto_req_mode.2402135529
Short name T397
Test name
Test status
Simulation time 17670486 ps
CPU time 1.06 seconds
Started Aug 29 12:23:18 AM UTC 24
Finished Aug 29 12:23:20 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402135529 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable_auto_req_mode.2402135529
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/20.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/20.edn_err.3112563464
Short name T184
Test name
Test status
Simulation time 22268203 ps
CPU time 1.09 seconds
Started Aug 29 12:23:18 AM UTC 24
Finished Aug 29 12:23:20 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112563464 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 20.edn_err.3112563464
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/20.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/20.edn_genbits.3729454505
Short name T97
Test name
Test status
Simulation time 77229178 ps
CPU time 1.63 seconds
Started Aug 29 12:23:17 AM UTC 24
Finished Aug 29 12:23:19 AM UTC 24
Peak memory 230344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729454505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3729454505
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/20.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/20.edn_intr.3190209548
Short name T398
Test name
Test status
Simulation time 43663335 ps
CPU time 1.34 seconds
Started Aug 29 12:23:18 AM UTC 24
Finished Aug 29 12:23:20 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190209548 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 20.edn_intr.3190209548
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/20.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/20.edn_smoke.1296418232
Short name T394
Test name
Test status
Simulation time 57226391 ps
CPU time 1.21 seconds
Started Aug 29 12:23:17 AM UTC 24
Finished Aug 29 12:23:19 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296418232 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 20.edn_smoke.1296418232
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/20.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/20.edn_stress_all.842735445
Short name T402
Test name
Test status
Simulation time 624384051 ps
CPU time 4.19 seconds
Started Aug 29 12:23:17 AM UTC 24
Finished Aug 29 12:23:22 AM UTC 24
Peak memory 227412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842735445 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.842735445
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/20.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/20.edn_stress_all_with_rand_reset.3052741600
Short name T241
Test name
Test status
Simulation time 1634630307 ps
CPU time 38.4 seconds
Started Aug 29 12:23:18 AM UTC 24
Finished Aug 29 12:23:58 AM UTC 24
Peak memory 229984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3052741600 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all
_with_rand_reset.3052741600
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/20.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/200.edn_genbits.1271179444
Short name T855
Test name
Test status
Simulation time 105905423 ps
CPU time 1.08 seconds
Started Aug 29 12:26:24 AM UTC 24
Finished Aug 29 12:26:26 AM UTC 24
Peak memory 228320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271179444 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 200.edn_genbits.1271179444
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/200.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/201.edn_genbits.1384850999
Short name T859
Test name
Test status
Simulation time 38716245 ps
CPU time 1.28 seconds
Started Aug 29 12:26:24 AM UTC 24
Finished Aug 29 12:26:26 AM UTC 24
Peak memory 228328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384850999 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 201.edn_genbits.1384850999
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/201.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/202.edn_genbits.2049389749
Short name T865
Test name
Test status
Simulation time 86903893 ps
CPU time 1.57 seconds
Started Aug 29 12:26:24 AM UTC 24
Finished Aug 29 12:26:27 AM UTC 24
Peak memory 230420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049389749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 202.edn_genbits.2049389749
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/202.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/203.edn_genbits.295620079
Short name T863
Test name
Test status
Simulation time 34974392 ps
CPU time 1.48 seconds
Started Aug 29 12:26:24 AM UTC 24
Finished Aug 29 12:26:27 AM UTC 24
Peak memory 230632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295620079 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 203.edn_genbits.295620079
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/203.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/204.edn_genbits.775376063
Short name T884
Test name
Test status
Simulation time 146214950 ps
CPU time 2.9 seconds
Started Aug 29 12:26:24 AM UTC 24
Finished Aug 29 12:26:28 AM UTC 24
Peak memory 231508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775376063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 204.edn_genbits.775376063
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/204.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/205.edn_genbits.736179778
Short name T872
Test name
Test status
Simulation time 39336024 ps
CPU time 1.89 seconds
Started Aug 29 12:26:24 AM UTC 24
Finished Aug 29 12:26:27 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736179778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 205.edn_genbits.736179778
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/205.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/206.edn_genbits.478449057
Short name T860
Test name
Test status
Simulation time 35653617 ps
CPU time 1.02 seconds
Started Aug 29 12:26:24 AM UTC 24
Finished Aug 29 12:26:26 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478449057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 206.edn_genbits.478449057
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/206.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/207.edn_genbits.631599429
Short name T873
Test name
Test status
Simulation time 47022912 ps
CPU time 1.93 seconds
Started Aug 29 12:26:24 AM UTC 24
Finished Aug 29 12:26:27 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631599429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 207.edn_genbits.631599429
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/207.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/208.edn_genbits.761015532
Short name T894
Test name
Test status
Simulation time 33439313 ps
CPU time 1.46 seconds
Started Aug 29 12:26:28 AM UTC 24
Finished Aug 29 12:26:30 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761015532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 208.edn_genbits.761015532
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/208.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/209.edn_genbits.1612544704
Short name T904
Test name
Test status
Simulation time 61789093 ps
CPU time 1.84 seconds
Started Aug 29 12:26:28 AM UTC 24
Finished Aug 29 12:26:30 AM UTC 24
Peak memory 230616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612544704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 209.edn_genbits.1612544704
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/209.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/21.edn_alert.4146184094
Short name T405
Test name
Test status
Simulation time 76803953 ps
CPU time 1.73 seconds
Started Aug 29 12:23:20 AM UTC 24
Finished Aug 29 12:23:22 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146184094 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 21.edn_alert.4146184094
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/21.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/21.edn_alert_test.4247808491
Short name T404
Test name
Test status
Simulation time 80790104 ps
CPU time 1.26 seconds
Started Aug 29 12:23:20 AM UTC 24
Finished Aug 29 12:23:22 AM UTC 24
Peak memory 216248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247808491 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.4247808491
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/21.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/21.edn_disable.371290921
Short name T108
Test name
Test status
Simulation time 10347768 ps
CPU time 1.13 seconds
Started Aug 29 12:23:20 AM UTC 24
Finished Aug 29 12:23:22 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371290921 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.371290921
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/21.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/21.edn_disable_auto_req_mode.735176474
Short name T403
Test name
Test status
Simulation time 81995663 ps
CPU time 1.29 seconds
Started Aug 29 12:23:20 AM UTC 24
Finished Aug 29 12:23:22 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735176474 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable_auto_req_mode.735176474
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/21.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/21.edn_err.896657507
Short name T225
Test name
Test status
Simulation time 24426733 ps
CPU time 1.43 seconds
Started Aug 29 12:23:20 AM UTC 24
Finished Aug 29 12:23:22 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896657507 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 21.edn_err.896657507
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/21.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/21.edn_genbits.2115427965
Short name T11
Test name
Test status
Simulation time 37708533 ps
CPU time 1.71 seconds
Started Aug 29 12:23:18 AM UTC 24
Finished Aug 29 12:23:21 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115427965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2115427965
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/21.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/21.edn_smoke.3248575947
Short name T400
Test name
Test status
Simulation time 25052362 ps
CPU time 1.43 seconds
Started Aug 29 12:23:18 AM UTC 24
Finished Aug 29 12:23:21 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248575947 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 21.edn_smoke.3248575947
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/21.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/21.edn_stress_all.4264361683
Short name T401
Test name
Test status
Simulation time 166961570 ps
CPU time 2.46 seconds
Started Aug 29 12:23:18 AM UTC 24
Finished Aug 29 12:23:22 AM UTC 24
Peak memory 229460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264361683 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.4264361683
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/21.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/210.edn_genbits.522570572
Short name T895
Test name
Test status
Simulation time 41688481 ps
CPU time 1.54 seconds
Started Aug 29 12:26:28 AM UTC 24
Finished Aug 29 12:26:30 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522570572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 210.edn_genbits.522570572
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/210.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/211.edn_genbits.4221180187
Short name T903
Test name
Test status
Simulation time 27066553 ps
CPU time 1.63 seconds
Started Aug 29 12:26:28 AM UTC 24
Finished Aug 29 12:26:30 AM UTC 24
Peak memory 230616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221180187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 211.edn_genbits.4221180187
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/211.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/212.edn_genbits.2958792921
Short name T899
Test name
Test status
Simulation time 65488914 ps
CPU time 1.57 seconds
Started Aug 29 12:26:28 AM UTC 24
Finished Aug 29 12:26:30 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958792921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2958792921
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/212.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/213.edn_genbits.1660147582
Short name T905
Test name
Test status
Simulation time 38076140 ps
CPU time 1.66 seconds
Started Aug 29 12:26:28 AM UTC 24
Finished Aug 29 12:26:30 AM UTC 24
Peak memory 230616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660147582 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 213.edn_genbits.1660147582
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/213.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/214.edn_genbits.3802630002
Short name T898
Test name
Test status
Simulation time 109105265 ps
CPU time 1.44 seconds
Started Aug 29 12:26:28 AM UTC 24
Finished Aug 29 12:26:30 AM UTC 24
Peak memory 230420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802630002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 214.edn_genbits.3802630002
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/214.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/215.edn_genbits.2795682217
Short name T896
Test name
Test status
Simulation time 86808801 ps
CPU time 1.47 seconds
Started Aug 29 12:26:28 AM UTC 24
Finished Aug 29 12:26:30 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795682217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 215.edn_genbits.2795682217
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/215.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/216.edn_genbits.2549488753
Short name T902
Test name
Test status
Simulation time 30294510 ps
CPU time 1.49 seconds
Started Aug 29 12:26:28 AM UTC 24
Finished Aug 29 12:26:30 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549488753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2549488753
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/216.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/217.edn_genbits.3989765124
Short name T906
Test name
Test status
Simulation time 33411047 ps
CPU time 1.64 seconds
Started Aug 29 12:26:28 AM UTC 24
Finished Aug 29 12:26:31 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989765124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 217.edn_genbits.3989765124
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/217.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/218.edn_genbits.3898743348
Short name T897
Test name
Test status
Simulation time 140723087 ps
CPU time 1.24 seconds
Started Aug 29 12:26:28 AM UTC 24
Finished Aug 29 12:26:30 AM UTC 24
Peak memory 228252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898743348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 218.edn_genbits.3898743348
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/218.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/219.edn_genbits.1262226253
Short name T907
Test name
Test status
Simulation time 40851476 ps
CPU time 1.58 seconds
Started Aug 29 12:26:28 AM UTC 24
Finished Aug 29 12:26:31 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262226253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1262226253
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/219.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/22.edn_alert.3490901164
Short name T298
Test name
Test status
Simulation time 52970300 ps
CPU time 1.64 seconds
Started Aug 29 12:23:22 AM UTC 24
Finished Aug 29 12:23:24 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490901164 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 22.edn_alert.3490901164
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/22.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/22.edn_alert_test.1109198835
Short name T411
Test name
Test status
Simulation time 22422911 ps
CPU time 1.09 seconds
Started Aug 29 12:23:22 AM UTC 24
Finished Aug 29 12:23:31 AM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109198835 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1109198835
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/22.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/22.edn_disable.3120561551
Short name T235
Test name
Test status
Simulation time 148700169 ps
CPU time 1.14 seconds
Started Aug 29 12:23:22 AM UTC 24
Finished Aug 29 12:23:31 AM UTC 24
Peak memory 225812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120561551 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3120561551
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/22.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/22.edn_disable_auto_req_mode.4054865199
Short name T174
Test name
Test status
Simulation time 132556551 ps
CPU time 1.2 seconds
Started Aug 29 12:23:22 AM UTC 24
Finished Aug 29 12:23:31 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054865199 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable_auto_req_mode.4054865199
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/22.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/22.edn_err.888540475
Short name T410
Test name
Test status
Simulation time 34947175 ps
CPU time 1.03 seconds
Started Aug 29 12:23:22 AM UTC 24
Finished Aug 29 12:23:31 AM UTC 24
Peak memory 227236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888540475 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 22.edn_err.888540475
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/22.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/22.edn_genbits.2613015073
Short name T408
Test name
Test status
Simulation time 45842876 ps
CPU time 1.57 seconds
Started Aug 29 12:23:20 AM UTC 24
Finished Aug 29 12:23:23 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613015073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2613015073
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/22.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/22.edn_intr.2345766575
Short name T409
Test name
Test status
Simulation time 22590711 ps
CPU time 1.47 seconds
Started Aug 29 12:23:22 AM UTC 24
Finished Aug 29 12:23:24 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345766575 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 22.edn_intr.2345766575
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/22.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/22.edn_smoke.186239760
Short name T407
Test name
Test status
Simulation time 18253918 ps
CPU time 1.53 seconds
Started Aug 29 12:23:20 AM UTC 24
Finished Aug 29 12:23:23 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186239760 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 22.edn_smoke.186239760
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/22.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/22.edn_stress_all.4203356066
Short name T406
Test name
Test status
Simulation time 26262314 ps
CPU time 1.41 seconds
Started Aug 29 12:23:20 AM UTC 24
Finished Aug 29 12:23:23 AM UTC 24
Peak memory 226264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203356066 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.4203356066
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/22.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/220.edn_genbits.454991075
Short name T340
Test name
Test status
Simulation time 66507314 ps
CPU time 1.18 seconds
Started Aug 29 12:26:28 AM UTC 24
Finished Aug 29 12:26:30 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454991075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 220.edn_genbits.454991075
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/220.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/221.edn_genbits.3275240750
Short name T909
Test name
Test status
Simulation time 51110567 ps
CPU time 1.53 seconds
Started Aug 29 12:26:28 AM UTC 24
Finished Aug 29 12:26:31 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275240750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3275240750
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/221.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/222.edn_genbits.3705899674
Short name T910
Test name
Test status
Simulation time 76459277 ps
CPU time 1.63 seconds
Started Aug 29 12:26:28 AM UTC 24
Finished Aug 29 12:26:31 AM UTC 24
Peak memory 230616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705899674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3705899674
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/222.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/223.edn_genbits.2415695228
Short name T900
Test name
Test status
Simulation time 85399484 ps
CPU time 1.17 seconds
Started Aug 29 12:26:28 AM UTC 24
Finished Aug 29 12:26:30 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415695228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2415695228
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/223.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/224.edn_genbits.1899522918
Short name T901
Test name
Test status
Simulation time 90498660 ps
CPU time 1.3 seconds
Started Aug 29 12:26:28 AM UTC 24
Finished Aug 29 12:26:30 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899522918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 224.edn_genbits.1899522918
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/224.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/225.edn_genbits.3371026639
Short name T858
Test name
Test status
Simulation time 56583763 ps
CPU time 1.32 seconds
Started Aug 29 12:26:29 AM UTC 24
Finished Aug 29 12:26:32 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371026639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3371026639
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/225.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/226.edn_genbits.1698211370
Short name T912
Test name
Test status
Simulation time 43176928 ps
CPU time 1.51 seconds
Started Aug 29 12:26:29 AM UTC 24
Finished Aug 29 12:26:32 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698211370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 226.edn_genbits.1698211370
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/226.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/227.edn_genbits.3972136390
Short name T892
Test name
Test status
Simulation time 59625954 ps
CPU time 1.52 seconds
Started Aug 29 12:26:29 AM UTC 24
Finished Aug 29 12:26:32 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972136390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3972136390
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/227.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/228.edn_genbits.3828242240
Short name T911
Test name
Test status
Simulation time 43441897 ps
CPU time 1.49 seconds
Started Aug 29 12:26:29 AM UTC 24
Finished Aug 29 12:26:32 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828242240 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 228.edn_genbits.3828242240
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/228.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/229.edn_genbits.84139206
Short name T862
Test name
Test status
Simulation time 54752214 ps
CPU time 1.29 seconds
Started Aug 29 12:26:29 AM UTC 24
Finished Aug 29 12:26:32 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84139206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 229.edn_genbits.84139206
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/229.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/23.edn_alert.3680954778
Short name T325
Test name
Test status
Simulation time 24855487 ps
CPU time 1.11 seconds
Started Aug 29 12:23:23 AM UTC 24
Finished Aug 29 12:23:36 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680954778 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 23.edn_alert.3680954778
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/23.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/23.edn_alert_test.999058942
Short name T415
Test name
Test status
Simulation time 15798477 ps
CPU time 1.2 seconds
Started Aug 29 12:23:23 AM UTC 24
Finished Aug 29 12:23:37 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999058942 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.999058942
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/23.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/23.edn_disable.3409128773
Short name T413
Test name
Test status
Simulation time 14019475 ps
CPU time 1.42 seconds
Started Aug 29 12:23:23 AM UTC 24
Finished Aug 29 12:23:37 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409128773 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3409128773
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/23.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/23.edn_disable_auto_req_mode.3067338869
Short name T414
Test name
Test status
Simulation time 34776078 ps
CPU time 1.35 seconds
Started Aug 29 12:23:23 AM UTC 24
Finished Aug 29 12:23:37 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067338869 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable_auto_req_mode.3067338869
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/23.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/23.edn_err.76072364
Short name T196
Test name
Test status
Simulation time 32277465 ps
CPU time 1.12 seconds
Started Aug 29 12:23:23 AM UTC 24
Finished Aug 29 12:23:36 AM UTC 24
Peak memory 236968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76072364 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 23.edn_err.76072364
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/23.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/23.edn_genbits.216969049
Short name T259
Test name
Test status
Simulation time 36557181 ps
CPU time 1.24 seconds
Started Aug 29 12:23:22 AM UTC 24
Finished Aug 29 12:23:41 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216969049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.edn_genbits.216969049
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/23.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/23.edn_intr.2503539781
Short name T267
Test name
Test status
Simulation time 39022798 ps
CPU time 1.32 seconds
Started Aug 29 12:23:23 AM UTC 24
Finished Aug 29 12:23:36 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503539781 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 23.edn_intr.2503539781
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/23.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/23.edn_smoke.2033850356
Short name T258
Test name
Test status
Simulation time 105224140 ps
CPU time 1.02 seconds
Started Aug 29 12:23:22 AM UTC 24
Finished Aug 29 12:23:41 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033850356 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 23.edn_smoke.2033850356
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/23.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/23.edn_stress_all.4035713158
Short name T261
Test name
Test status
Simulation time 844564264 ps
CPU time 4.1 seconds
Started Aug 29 12:23:22 AM UTC 24
Finished Aug 29 12:23:44 AM UTC 24
Peak memory 229464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035713158 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.4035713158
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/23.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/230.edn_genbits.2930403247
Short name T913
Test name
Test status
Simulation time 72754921 ps
CPU time 1.53 seconds
Started Aug 29 12:26:30 AM UTC 24
Finished Aug 29 12:26:32 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930403247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2930403247
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/230.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/231.edn_genbits.842665114
Short name T829
Test name
Test status
Simulation time 46544982 ps
CPU time 1.11 seconds
Started Aug 29 12:26:30 AM UTC 24
Finished Aug 29 12:26:32 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842665114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 231.edn_genbits.842665114
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/231.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/232.edn_genbits.2867676025
Short name T871
Test name
Test status
Simulation time 32908421 ps
CPU time 1.19 seconds
Started Aug 29 12:26:30 AM UTC 24
Finished Aug 29 12:26:32 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867676025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2867676025
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/232.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/233.edn_genbits.2540301244
Short name T914
Test name
Test status
Simulation time 42481171 ps
CPU time 1.43 seconds
Started Aug 29 12:26:30 AM UTC 24
Finished Aug 29 12:26:32 AM UTC 24
Peak memory 230616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540301244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 233.edn_genbits.2540301244
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/233.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/234.edn_genbits.966280085
Short name T915
Test name
Test status
Simulation time 53205997 ps
CPU time 1.34 seconds
Started Aug 29 12:26:30 AM UTC 24
Finished Aug 29 12:26:32 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966280085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 234.edn_genbits.966280085
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/234.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/235.edn_genbits.473936273
Short name T917
Test name
Test status
Simulation time 78267710 ps
CPU time 2.85 seconds
Started Aug 29 12:26:30 AM UTC 24
Finished Aug 29 12:26:34 AM UTC 24
Peak memory 231580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473936273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 235.edn_genbits.473936273
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/235.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/236.edn_genbits.1826778688
Short name T916
Test name
Test status
Simulation time 56540215 ps
CPU time 1.42 seconds
Started Aug 29 12:26:30 AM UTC 24
Finished Aug 29 12:26:32 AM UTC 24
Peak memory 228568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826778688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 236.edn_genbits.1826778688
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/236.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/237.edn_genbits.2596223898
Short name T885
Test name
Test status
Simulation time 43509939 ps
CPU time 1.05 seconds
Started Aug 29 12:26:30 AM UTC 24
Finished Aug 29 12:26:32 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596223898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 237.edn_genbits.2596223898
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/237.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/238.edn_genbits.4117716354
Short name T921
Test name
Test status
Simulation time 58090080 ps
CPU time 1.31 seconds
Started Aug 29 12:26:31 AM UTC 24
Finished Aug 29 12:26:43 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117716354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 238.edn_genbits.4117716354
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/238.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/239.edn_genbits.3299189412
Short name T922
Test name
Test status
Simulation time 46785312 ps
CPU time 1.6 seconds
Started Aug 29 12:26:31 AM UTC 24
Finished Aug 29 12:26:44 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299189412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 239.edn_genbits.3299189412
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/239.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/24.edn_alert.19449574
Short name T233
Test name
Test status
Simulation time 31242235 ps
CPU time 1.41 seconds
Started Aug 29 12:23:25 AM UTC 24
Finished Aug 29 12:23:47 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19449574 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 24.edn_alert.19449574
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/24.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/24.edn_alert_test.42185697
Short name T434
Test name
Test status
Simulation time 20035989 ps
CPU time 0.94 seconds
Started Aug 29 12:23:32 AM UTC 24
Finished Aug 29 12:24:07 AM UTC 24
Peak memory 216264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42185697 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.42185697
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/24.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/24.edn_disable.4249469991
Short name T110
Test name
Test status
Simulation time 27824598 ps
CPU time 1.29 seconds
Started Aug 29 12:23:25 AM UTC 24
Finished Aug 29 12:24:08 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249469991 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.4249469991
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/24.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/24.edn_disable_auto_req_mode.1336459418
Short name T437
Test name
Test status
Simulation time 52547066 ps
CPU time 1.29 seconds
Started Aug 29 12:23:32 AM UTC 24
Finished Aug 29 12:24:08 AM UTC 24
Peak memory 230268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336459418 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable_auto_req_mode.1336459418
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/24.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/24.edn_err.3145235133
Short name T192
Test name
Test status
Simulation time 24178696 ps
CPU time 1.23 seconds
Started Aug 29 12:23:25 AM UTC 24
Finished Aug 29 12:24:07 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145235133 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 24.edn_err.3145235133
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/24.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/24.edn_genbits.1942279470
Short name T412
Test name
Test status
Simulation time 69263461 ps
CPU time 1.11 seconds
Started Aug 29 12:23:23 AM UTC 24
Finished Aug 29 12:23:37 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942279470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1942279470
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/24.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/24.edn_intr.2206873360
Short name T34
Test name
Test status
Simulation time 33835076 ps
CPU time 0.93 seconds
Started Aug 29 12:23:24 AM UTC 24
Finished Aug 29 12:23:37 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206873360 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 24.edn_intr.2206873360
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/24.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/24.edn_smoke.1583766260
Short name T416
Test name
Test status
Simulation time 46876914 ps
CPU time 1.39 seconds
Started Aug 29 12:23:23 AM UTC 24
Finished Aug 29 12:23:37 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583766260 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 24.edn_smoke.1583766260
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/24.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/24.edn_stress_all.280737190
Short name T417
Test name
Test status
Simulation time 240581614 ps
CPU time 2.06 seconds
Started Aug 29 12:23:24 AM UTC 24
Finished Aug 29 12:23:38 AM UTC 24
Peak memory 229592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280737190 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.280737190
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/24.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/24.edn_stress_all_with_rand_reset.3176171902
Short name T504
Test name
Test status
Simulation time 7358885691 ps
CPU time 57.48 seconds
Started Aug 29 12:23:24 AM UTC 24
Finished Aug 29 12:24:34 AM UTC 24
Peak memory 230036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3176171902 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all
_with_rand_reset.3176171902
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/24.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/240.edn_genbits.2850079285
Short name T923
Test name
Test status
Simulation time 43868184 ps
CPU time 1.64 seconds
Started Aug 29 12:26:31 AM UTC 24
Finished Aug 29 12:26:44 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850079285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 240.edn_genbits.2850079285
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/240.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/241.edn_genbits.2287212378
Short name T920
Test name
Test status
Simulation time 96759384 ps
CPU time 1.18 seconds
Started Aug 29 12:26:31 AM UTC 24
Finished Aug 29 12:26:43 AM UTC 24
Peak memory 228288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287212378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 241.edn_genbits.2287212378
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/241.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/242.edn_genbits.2562421950
Short name T919
Test name
Test status
Simulation time 168529450 ps
CPU time 1.18 seconds
Started Aug 29 12:26:31 AM UTC 24
Finished Aug 29 12:26:43 AM UTC 24
Peak memory 228256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562421950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 242.edn_genbits.2562421950
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/242.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/244.edn_genbits.2135051163
Short name T934
Test name
Test status
Simulation time 58979817 ps
CPU time 1.41 seconds
Started Aug 29 12:26:31 AM UTC 24
Finished Aug 29 12:26:47 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135051163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 244.edn_genbits.2135051163
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/244.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/245.edn_genbits.251411249
Short name T941
Test name
Test status
Simulation time 55670803 ps
CPU time 1.83 seconds
Started Aug 29 12:26:31 AM UTC 24
Finished Aug 29 12:26:47 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251411249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 245.edn_genbits.251411249
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/245.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/246.edn_genbits.1301045490
Short name T939
Test name
Test status
Simulation time 54004337 ps
CPU time 1.66 seconds
Started Aug 29 12:26:31 AM UTC 24
Finished Aug 29 12:26:47 AM UTC 24
Peak memory 228568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301045490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1301045490
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/246.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/247.edn_genbits.1774781110
Short name T940
Test name
Test status
Simulation time 102755419 ps
CPU time 1.51 seconds
Started Aug 29 12:26:31 AM UTC 24
Finished Aug 29 12:26:47 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774781110 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1774781110
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/247.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/248.edn_genbits.851590439
Short name T938
Test name
Test status
Simulation time 122456024 ps
CPU time 1.52 seconds
Started Aug 29 12:26:31 AM UTC 24
Finished Aug 29 12:26:47 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851590439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 248.edn_genbits.851590439
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/248.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/249.edn_genbits.3116858732
Short name T937
Test name
Test status
Simulation time 52651149 ps
CPU time 1.48 seconds
Started Aug 29 12:26:31 AM UTC 24
Finished Aug 29 12:26:47 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116858732 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 249.edn_genbits.3116858732
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/249.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/25.edn_alert_test.2974962708
Short name T423
Test name
Test status
Simulation time 17471901 ps
CPU time 1.25 seconds
Started Aug 29 12:23:37 AM UTC 24
Finished Aug 29 12:23:54 AM UTC 24
Peak memory 216800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974962708 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2974962708
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/25.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/25.edn_disable.2861446095
Short name T262
Test name
Test status
Simulation time 21306266 ps
CPU time 1.09 seconds
Started Aug 29 12:23:37 AM UTC 24
Finished Aug 29 12:23:46 AM UTC 24
Peak memory 225344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861446095 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2861446095
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/25.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/25.edn_disable_auto_req_mode.74330354
Short name T425
Test name
Test status
Simulation time 89781199 ps
CPU time 1.64 seconds
Started Aug 29 12:23:37 AM UTC 24
Finished Aug 29 12:23:54 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74330354 -assert nopostproc +UVM_TESTNAME=edn_disab
le_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable_auto_req_mode.74330354
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/25.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/25.edn_err.2772109417
Short name T263
Test name
Test status
Simulation time 20324410 ps
CPU time 1.21 seconds
Started Aug 29 12:23:37 AM UTC 24
Finished Aug 29 12:23:46 AM UTC 24
Peak memory 227172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772109417 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 25.edn_err.2772109417
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/25.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/25.edn_genbits.413344253
Short name T260
Test name
Test status
Simulation time 44292620 ps
CPU time 2.04 seconds
Started Aug 29 12:23:32 AM UTC 24
Finished Aug 29 12:23:42 AM UTC 24
Peak memory 229436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413344253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.edn_genbits.413344253
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/25.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/25.edn_intr.1745579664
Short name T427
Test name
Test status
Simulation time 34279368 ps
CPU time 1.17 seconds
Started Aug 29 12:23:34 AM UTC 24
Finished Aug 29 12:23:54 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745579664 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 25.edn_intr.1745579664
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/25.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/25.edn_stress_all_with_rand_reset.1918838299
Short name T244
Test name
Test status
Simulation time 2131119824 ps
CPU time 23.55 seconds
Started Aug 29 12:23:34 AM UTC 24
Finished Aug 29 12:24:17 AM UTC 24
Peak memory 227604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1918838299 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all
_with_rand_reset.1918838299
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/25.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/250.edn_genbits.3490012246
Short name T946
Test name
Test status
Simulation time 70966724 ps
CPU time 1.54 seconds
Started Aug 29 12:26:31 AM UTC 24
Finished Aug 29 12:26:51 AM UTC 24
Peak memory 230420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490012246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3490012246
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/250.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/251.edn_genbits.1433749733
Short name T944
Test name
Test status
Simulation time 32292475 ps
CPU time 1.22 seconds
Started Aug 29 12:26:32 AM UTC 24
Finished Aug 29 12:26:51 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433749733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 251.edn_genbits.1433749733
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/251.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/252.edn_genbits.2805456491
Short name T947
Test name
Test status
Simulation time 60390925 ps
CPU time 1.35 seconds
Started Aug 29 12:26:32 AM UTC 24
Finished Aug 29 12:26:51 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805456491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2805456491
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/252.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/253.edn_genbits.1972476363
Short name T943
Test name
Test status
Simulation time 88362097 ps
CPU time 1.17 seconds
Started Aug 29 12:26:32 AM UTC 24
Finished Aug 29 12:26:51 AM UTC 24
Peak memory 226324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972476363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 253.edn_genbits.1972476363
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/253.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/254.edn_genbits.908937735
Short name T945
Test name
Test status
Simulation time 91142115 ps
CPU time 1.1 seconds
Started Aug 29 12:26:32 AM UTC 24
Finished Aug 29 12:26:51 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908937735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 254.edn_genbits.908937735
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/254.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/255.edn_genbits.2993004687
Short name T948
Test name
Test status
Simulation time 28394335 ps
CPU time 1.3 seconds
Started Aug 29 12:26:32 AM UTC 24
Finished Aug 29 12:26:51 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993004687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2993004687
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/255.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/256.edn_genbits.1174924603
Short name T966
Test name
Test status
Simulation time 98124527 ps
CPU time 1.49 seconds
Started Aug 29 12:26:32 AM UTC 24
Finished Aug 29 12:26:58 AM UTC 24
Peak memory 225892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174924603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1174924603
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/256.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/257.edn_genbits.2215490436
Short name T970
Test name
Test status
Simulation time 39934165 ps
CPU time 1.84 seconds
Started Aug 29 12:26:32 AM UTC 24
Finished Aug 29 12:26:58 AM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215490436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 257.edn_genbits.2215490436
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/257.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/258.edn_genbits.2813708993
Short name T973
Test name
Test status
Simulation time 51785298 ps
CPU time 1.97 seconds
Started Aug 29 12:26:32 AM UTC 24
Finished Aug 29 12:26:58 AM UTC 24
Peak memory 230612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813708993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 258.edn_genbits.2813708993
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/258.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/259.edn_genbits.494624050
Short name T918
Test name
Test status
Simulation time 61320556 ps
CPU time 1.48 seconds
Started Aug 29 12:26:33 AM UTC 24
Finished Aug 29 12:26:43 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494624050 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 259.edn_genbits.494624050
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/259.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/26.edn_alert.866307324
Short name T236
Test name
Test status
Simulation time 45138993 ps
CPU time 1.27 seconds
Started Aug 29 12:23:38 AM UTC 24
Finished Aug 29 12:23:42 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866307324 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 26.edn_alert.866307324
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/26.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/26.edn_alert_test.4055097756
Short name T421
Test name
Test status
Simulation time 19214629 ps
CPU time 1.15 seconds
Started Aug 29 12:23:42 AM UTC 24
Finished Aug 29 12:23:52 AM UTC 24
Peak memory 216512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055097756 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.4055097756
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/26.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/26.edn_disable.1857124755
Short name T264
Test name
Test status
Simulation time 47066171 ps
CPU time 0.79 seconds
Started Aug 29 12:23:38 AM UTC 24
Finished Aug 29 12:23:51 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857124755 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1857124755
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/26.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/26.edn_disable_auto_req_mode.713624376
Short name T175
Test name
Test status
Simulation time 66191494 ps
CPU time 1.28 seconds
Started Aug 29 12:23:41 AM UTC 24
Finished Aug 29 12:23:54 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713624376 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable_auto_req_mode.713624376
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/26.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/26.edn_err.3858850867
Short name T419
Test name
Test status
Simulation time 31394697 ps
CPU time 0.98 seconds
Started Aug 29 12:23:38 AM UTC 24
Finished Aug 29 12:23:51 AM UTC 24
Peak memory 236968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858850867 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 26.edn_err.3858850867
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/26.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/26.edn_genbits.418214620
Short name T98
Test name
Test status
Simulation time 40809244 ps
CPU time 1.61 seconds
Started Aug 29 12:23:37 AM UTC 24
Finished Aug 29 12:23:54 AM UTC 24
Peak memory 228476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418214620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.edn_genbits.418214620
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/26.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/26.edn_intr.2955909389
Short name T418
Test name
Test status
Simulation time 21958751 ps
CPU time 1.03 seconds
Started Aug 29 12:23:38 AM UTC 24
Finished Aug 29 12:23:51 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955909389 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 26.edn_intr.2955909389
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/26.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/26.edn_smoke.573631998
Short name T424
Test name
Test status
Simulation time 22784740 ps
CPU time 1.35 seconds
Started Aug 29 12:23:37 AM UTC 24
Finished Aug 29 12:23:54 AM UTC 24
Peak memory 226008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573631998 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 26.edn_smoke.573631998
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/26.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/26.edn_stress_all.1461746983
Short name T428
Test name
Test status
Simulation time 74705785 ps
CPU time 2.63 seconds
Started Aug 29 12:23:37 AM UTC 24
Finished Aug 29 12:23:55 AM UTC 24
Peak memory 229524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461746983 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1461746983
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/26.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/26.edn_stress_all_with_rand_reset.913746451
Short name T254
Test name
Test status
Simulation time 14969974380 ps
CPU time 90.63 seconds
Started Aug 29 12:23:38 AM UTC 24
Finished Aug 29 12:25:22 AM UTC 24
Peak memory 229792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=913746451 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_
with_rand_reset.913746451
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/26.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/260.edn_genbits.149622944
Short name T344
Test name
Test status
Simulation time 67992781 ps
CPU time 1.32 seconds
Started Aug 29 12:26:33 AM UTC 24
Finished Aug 29 12:26:42 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149622944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 260.edn_genbits.149622944
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/260.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/261.edn_genbits.2646091194
Short name T924
Test name
Test status
Simulation time 171169510 ps
CPU time 1.93 seconds
Started Aug 29 12:26:33 AM UTC 24
Finished Aug 29 12:26:44 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646091194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 261.edn_genbits.2646091194
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/261.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/262.edn_genbits.1144755701
Short name T926
Test name
Test status
Simulation time 125996227 ps
CPU time 2.28 seconds
Started Aug 29 12:26:33 AM UTC 24
Finished Aug 29 12:26:45 AM UTC 24
Peak memory 227628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144755701 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1144755701
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/262.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/263.edn_genbits.3341357687
Short name T929
Test name
Test status
Simulation time 65531790 ps
CPU time 1.2 seconds
Started Aug 29 12:26:33 AM UTC 24
Finished Aug 29 12:26:46 AM UTC 24
Peak memory 228240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341357687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3341357687
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/263.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/264.edn_genbits.869375159
Short name T931
Test name
Test status
Simulation time 98230364 ps
CPU time 1.44 seconds
Started Aug 29 12:26:33 AM UTC 24
Finished Aug 29 12:26:47 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869375159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 264.edn_genbits.869375159
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/264.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/265.edn_genbits.2296364378
Short name T927
Test name
Test status
Simulation time 27660844 ps
CPU time 1.08 seconds
Started Aug 29 12:26:33 AM UTC 24
Finished Aug 29 12:26:46 AM UTC 24
Peak memory 230612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296364378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2296364378
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/265.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/266.edn_genbits.2739987557
Short name T928
Test name
Test status
Simulation time 116934906 ps
CPU time 1.04 seconds
Started Aug 29 12:26:33 AM UTC 24
Finished Aug 29 12:26:46 AM UTC 24
Peak memory 228296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739987557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2739987557
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/266.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/267.edn_genbits.1191791946
Short name T345
Test name
Test status
Simulation time 45275286 ps
CPU time 1.14 seconds
Started Aug 29 12:26:33 AM UTC 24
Finished Aug 29 12:26:44 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191791946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1191791946
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/267.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/268.edn_genbits.892304661
Short name T932
Test name
Test status
Simulation time 82393863 ps
CPU time 1.26 seconds
Started Aug 29 12:26:33 AM UTC 24
Finished Aug 29 12:26:47 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892304661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 268.edn_genbits.892304661
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/268.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/269.edn_genbits.585997220
Short name T930
Test name
Test status
Simulation time 65959577 ps
CPU time 1.1 seconds
Started Aug 29 12:26:33 AM UTC 24
Finished Aug 29 12:26:46 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585997220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 269.edn_genbits.585997220
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/269.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/27.edn_alert.1429955285
Short name T198
Test name
Test status
Simulation time 48796876 ps
CPU time 0.97 seconds
Started Aug 29 12:23:48 AM UTC 24
Finished Aug 29 12:23:53 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429955285 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 27.edn_alert.1429955285
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/27.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/27.edn_alert_test.2091768722
Short name T430
Test name
Test status
Simulation time 26211975 ps
CPU time 1.29 seconds
Started Aug 29 12:23:53 AM UTC 24
Finished Aug 29 12:24:03 AM UTC 24
Peak memory 226760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091768722 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2091768722
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/27.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/27.edn_disable.2411302670
Short name T99
Test name
Test status
Simulation time 31176023 ps
CPU time 1.11 seconds
Started Aug 29 12:23:52 AM UTC 24
Finished Aug 29 12:23:54 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411302670 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.2411302670
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/27.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/27.edn_disable_auto_req_mode.1777420875
Short name T327
Test name
Test status
Simulation time 23798124 ps
CPU time 1.41 seconds
Started Aug 29 12:23:52 AM UTC 24
Finished Aug 29 12:23:54 AM UTC 24
Peak memory 226384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777420875 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable_auto_req_mode.1777420875
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/27.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/27.edn_err.573528579
Short name T136
Test name
Test status
Simulation time 104438389 ps
CPU time 1.01 seconds
Started Aug 29 12:23:52 AM UTC 24
Finished Aug 29 12:23:54 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573528579 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 27.edn_err.573528579
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/27.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/27.edn_genbits.1227603884
Short name T426
Test name
Test status
Simulation time 60367251 ps
CPU time 1.25 seconds
Started Aug 29 12:23:44 AM UTC 24
Finished Aug 29 12:23:54 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227603884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_genbits.1227603884
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/27.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/27.edn_intr.3231318781
Short name T422
Test name
Test status
Simulation time 21038686 ps
CPU time 1.25 seconds
Started Aug 29 12:23:47 AM UTC 24
Finished Aug 29 12:23:52 AM UTC 24
Peak memory 237340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231318781 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 27.edn_intr.3231318781
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/27.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/27.edn_smoke.1282908298
Short name T420
Test name
Test status
Simulation time 23626589 ps
CPU time 0.95 seconds
Started Aug 29 12:23:43 AM UTC 24
Finished Aug 29 12:23:52 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282908298 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 27.edn_smoke.1282908298
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/27.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/27.edn_stress_all.3077407199
Short name T429
Test name
Test status
Simulation time 393819341 ps
CPU time 3.56 seconds
Started Aug 29 12:23:45 AM UTC 24
Finished Aug 29 12:23:56 AM UTC 24
Peak memory 229540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077407199 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3077407199
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/27.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/270.edn_genbits.799282077
Short name T936
Test name
Test status
Simulation time 37098818 ps
CPU time 1.52 seconds
Started Aug 29 12:26:33 AM UTC 24
Finished Aug 29 12:26:47 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799282077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 270.edn_genbits.799282077
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/270.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/271.edn_genbits.3048209318
Short name T942
Test name
Test status
Simulation time 90995154 ps
CPU time 1.96 seconds
Started Aug 29 12:26:33 AM UTC 24
Finished Aug 29 12:26:48 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048209318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 271.edn_genbits.3048209318
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/271.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/272.edn_genbits.1659578955
Short name T925
Test name
Test status
Simulation time 153191809 ps
CPU time 3.03 seconds
Started Aug 29 12:26:33 AM UTC 24
Finished Aug 29 12:26:45 AM UTC 24
Peak memory 231572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659578955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1659578955
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/272.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/273.edn_genbits.1248207798
Short name T933
Test name
Test status
Simulation time 30842732 ps
CPU time 1.3 seconds
Started Aug 29 12:26:33 AM UTC 24
Finished Aug 29 12:26:47 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248207798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 273.edn_genbits.1248207798
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/273.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/274.edn_genbits.4048050065
Short name T961
Test name
Test status
Simulation time 42315909 ps
CPU time 1.46 seconds
Started Aug 29 12:26:35 AM UTC 24
Finished Aug 29 12:26:57 AM UTC 24
Peak memory 228044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048050065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 274.edn_genbits.4048050065
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/274.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/275.edn_genbits.653224847
Short name T935
Test name
Test status
Simulation time 25828342 ps
CPU time 1.18 seconds
Started Aug 29 12:26:35 AM UTC 24
Finished Aug 29 12:26:47 AM UTC 24
Peak memory 230116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653224847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 275.edn_genbits.653224847
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/275.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/276.edn_genbits.3902778770
Short name T964
Test name
Test status
Simulation time 37827726 ps
CPU time 1.66 seconds
Started Aug 29 12:26:44 AM UTC 24
Finished Aug 29 12:26:57 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902778770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3902778770
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/276.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/277.edn_genbits.4253285550
Short name T337
Test name
Test status
Simulation time 31657487 ps
CPU time 1.53 seconds
Started Aug 29 12:26:44 AM UTC 24
Finished Aug 29 12:26:57 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253285550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 277.edn_genbits.4253285550
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/277.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/278.edn_genbits.947394157
Short name T971
Test name
Test status
Simulation time 47752773 ps
CPU time 1.86 seconds
Started Aug 29 12:26:44 AM UTC 24
Finished Aug 29 12:26:58 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947394157 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 278.edn_genbits.947394157
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/278.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/279.edn_genbits.3575247487
Short name T962
Test name
Test status
Simulation time 49433300 ps
CPU time 1.32 seconds
Started Aug 29 12:26:44 AM UTC 24
Finished Aug 29 12:26:57 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575247487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 279.edn_genbits.3575247487
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/279.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/28.edn_alert.858407516
Short name T194
Test name
Test status
Simulation time 93995557 ps
CPU time 1.75 seconds
Started Aug 29 12:23:54 AM UTC 24
Finished Aug 29 12:24:08 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858407516 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 28.edn_alert.858407516
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/28.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/28.edn_alert_test.2684295266
Short name T438
Test name
Test status
Simulation time 54287205 ps
CPU time 1.12 seconds
Started Aug 29 12:23:55 AM UTC 24
Finished Aug 29 12:24:11 AM UTC 24
Peak memory 217024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684295266 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2684295266
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/28.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/28.edn_disable.2243888612
Short name T234
Test name
Test status
Simulation time 31326595 ps
CPU time 1.1 seconds
Started Aug 29 12:23:54 AM UTC 24
Finished Aug 29 12:24:04 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243888612 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2243888612
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/28.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/28.edn_disable_auto_req_mode.2579995350
Short name T432
Test name
Test status
Simulation time 36233084 ps
CPU time 1.07 seconds
Started Aug 29 12:23:54 AM UTC 24
Finished Aug 29 12:24:04 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579995350 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable_auto_req_mode.2579995350
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/28.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/28.edn_err.1353464758
Short name T223
Test name
Test status
Simulation time 38244093 ps
CPU time 1.23 seconds
Started Aug 29 12:23:54 AM UTC 24
Finished Aug 29 12:24:07 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353464758 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 28.edn_err.1353464758
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/28.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/28.edn_genbits.2660328751
Short name T431
Test name
Test status
Simulation time 57088943 ps
CPU time 1.25 seconds
Started Aug 29 12:23:53 AM UTC 24
Finished Aug 29 12:24:03 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660328751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2660328751
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/28.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/28.edn_intr.2577187504
Short name T322
Test name
Test status
Simulation time 22554056 ps
CPU time 1.3 seconds
Started Aug 29 12:23:54 AM UTC 24
Finished Aug 29 12:24:04 AM UTC 24
Peak memory 236700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577187504 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 28.edn_intr.2577187504
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/28.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/28.edn_smoke.3561774013
Short name T433
Test name
Test status
Simulation time 18339001 ps
CPU time 1.45 seconds
Started Aug 29 12:23:53 AM UTC 24
Finished Aug 29 12:24:04 AM UTC 24
Peak memory 226092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561774013 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 28.edn_smoke.3561774013
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/28.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/28.edn_stress_all.247729758
Short name T268
Test name
Test status
Simulation time 184525806 ps
CPU time 3.93 seconds
Started Aug 29 12:23:54 AM UTC 24
Finished Aug 29 12:24:06 AM UTC 24
Peak memory 227412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247729758 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.247729758
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/28.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/28.edn_stress_all_with_rand_reset.355820981
Short name T535
Test name
Test status
Simulation time 9022105833 ps
CPU time 44.36 seconds
Started Aug 29 12:23:54 AM UTC 24
Finished Aug 29 12:24:47 AM UTC 24
Peak memory 229792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=355820981 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_
with_rand_reset.355820981
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/28.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/280.edn_genbits.3046260635
Short name T967
Test name
Test status
Simulation time 24932210 ps
CPU time 1.5 seconds
Started Aug 29 12:26:44 AM UTC 24
Finished Aug 29 12:26:58 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046260635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3046260635
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/280.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/281.edn_genbits.799579743
Short name T974
Test name
Test status
Simulation time 85037843 ps
CPU time 1.98 seconds
Started Aug 29 12:26:45 AM UTC 24
Finished Aug 29 12:26:58 AM UTC 24
Peak memory 230624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799579743 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 281.edn_genbits.799579743
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/281.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/282.edn_genbits.486991018
Short name T965
Test name
Test status
Simulation time 20628913 ps
CPU time 1.28 seconds
Started Aug 29 12:26:45 AM UTC 24
Finished Aug 29 12:26:57 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486991018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 282.edn_genbits.486991018
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/282.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/283.edn_genbits.44454555
Short name T963
Test name
Test status
Simulation time 94029035 ps
CPU time 1.31 seconds
Started Aug 29 12:26:45 AM UTC 24
Finished Aug 29 12:26:57 AM UTC 24
Peak memory 227956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44454555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 283.edn_genbits.44454555
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/283.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/284.edn_genbits.1056330577
Short name T968
Test name
Test status
Simulation time 29121118 ps
CPU time 1.37 seconds
Started Aug 29 12:26:45 AM UTC 24
Finished Aug 29 12:26:58 AM UTC 24
Peak memory 230616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056330577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1056330577
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/284.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/285.edn_genbits.2057158537
Short name T969
Test name
Test status
Simulation time 33069560 ps
CPU time 1.52 seconds
Started Aug 29 12:26:45 AM UTC 24
Finished Aug 29 12:26:58 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057158537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2057158537
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/285.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/286.edn_genbits.625320058
Short name T975
Test name
Test status
Simulation time 67097142 ps
CPU time 1.92 seconds
Started Aug 29 12:26:45 AM UTC 24
Finished Aug 29 12:26:58 AM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625320058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 286.edn_genbits.625320058
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/286.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/287.edn_genbits.3923054968
Short name T972
Test name
Test status
Simulation time 264999083 ps
CPU time 1.5 seconds
Started Aug 29 12:26:45 AM UTC 24
Finished Aug 29 12:26:58 AM UTC 24
Peak memory 230420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923054968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 287.edn_genbits.3923054968
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/287.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/288.edn_genbits.3620591222
Short name T953
Test name
Test status
Simulation time 37023862 ps
CPU time 1.46 seconds
Started Aug 29 12:26:47 AM UTC 24
Finished Aug 29 12:26:53 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620591222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3620591222
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/288.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/289.edn_genbits.3970753086
Short name T952
Test name
Test status
Simulation time 44177721 ps
CPU time 1.05 seconds
Started Aug 29 12:26:47 AM UTC 24
Finished Aug 29 12:26:52 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970753086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 289.edn_genbits.3970753086
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/289.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/29.edn_alert.2454921403
Short name T177
Test name
Test status
Simulation time 68019517 ps
CPU time 1.1 seconds
Started Aug 29 12:23:57 AM UTC 24
Finished Aug 29 12:24:02 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454921403 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 29.edn_alert.2454921403
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/29.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/29.edn_alert_test.2177010600
Short name T436
Test name
Test status
Simulation time 27411857 ps
CPU time 1.1 seconds
Started Aug 29 12:24:04 AM UTC 24
Finished Aug 29 12:24:07 AM UTC 24
Peak memory 217112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177010600 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.2177010600
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/29.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/29.edn_disable.1770312091
Short name T109
Test name
Test status
Simulation time 12120967 ps
CPU time 1.16 seconds
Started Aug 29 12:24:00 AM UTC 24
Finished Aug 29 12:24:02 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770312091 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1770312091
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/29.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/29.edn_err.374233483
Short name T209
Test name
Test status
Simulation time 19677766 ps
CPU time 1.17 seconds
Started Aug 29 12:23:59 AM UTC 24
Finished Aug 29 12:24:02 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374233483 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 29.edn_err.374233483
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/29.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/29.edn_genbits.212481496
Short name T100
Test name
Test status
Simulation time 325447385 ps
CPU time 3.94 seconds
Started Aug 29 12:23:56 AM UTC 24
Finished Aug 29 12:24:14 AM UTC 24
Peak memory 231504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212481496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.edn_genbits.212481496
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/29.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/29.edn_intr.316254195
Short name T440
Test name
Test status
Simulation time 25878502 ps
CPU time 1.08 seconds
Started Aug 29 12:23:56 AM UTC 24
Finished Aug 29 12:24:11 AM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316254195 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 29.edn_intr.316254195
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/29.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/29.edn_smoke.4034390276
Short name T439
Test name
Test status
Simulation time 27015156 ps
CPU time 1.07 seconds
Started Aug 29 12:23:56 AM UTC 24
Finished Aug 29 12:24:11 AM UTC 24
Peak memory 226232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034390276 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 29.edn_smoke.4034390276
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/29.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/29.edn_stress_all.3015576915
Short name T459
Test name
Test status
Simulation time 211316892 ps
CPU time 2.52 seconds
Started Aug 29 12:23:56 AM UTC 24
Finished Aug 29 12:24:19 AM UTC 24
Peak memory 227424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015576915 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3015576915
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/29.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/29.edn_stress_all_with_rand_reset.1756514387
Short name T613
Test name
Test status
Simulation time 2341711477 ps
CPU time 49.4 seconds
Started Aug 29 12:23:56 AM UTC 24
Finished Aug 29 12:25:07 AM UTC 24
Peak memory 229744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1756514387 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all
_with_rand_reset.1756514387
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/29.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/290.edn_genbits.1554219955
Short name T951
Test name
Test status
Simulation time 39332597 ps
CPU time 1.06 seconds
Started Aug 29 12:26:47 AM UTC 24
Finished Aug 29 12:26:52 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554219955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1554219955
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/290.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/291.edn_genbits.1369046547
Short name T958
Test name
Test status
Simulation time 99645519 ps
CPU time 1.47 seconds
Started Aug 29 12:26:47 AM UTC 24
Finished Aug 29 12:26:53 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369046547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 291.edn_genbits.1369046547
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/291.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/292.edn_genbits.1400988292
Short name T959
Test name
Test status
Simulation time 39226414 ps
CPU time 1.64 seconds
Started Aug 29 12:26:47 AM UTC 24
Finished Aug 29 12:26:53 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400988292 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 292.edn_genbits.1400988292
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/292.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/293.edn_genbits.1178905696
Short name T960
Test name
Test status
Simulation time 148341412 ps
CPU time 2.44 seconds
Started Aug 29 12:26:47 AM UTC 24
Finished Aug 29 12:26:54 AM UTC 24
Peak memory 229448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178905696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1178905696
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/293.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/294.edn_genbits.888915908
Short name T955
Test name
Test status
Simulation time 36484366 ps
CPU time 1.33 seconds
Started Aug 29 12:26:47 AM UTC 24
Finished Aug 29 12:26:53 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888915908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 294.edn_genbits.888915908
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/294.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/295.edn_genbits.2410962652
Short name T957
Test name
Test status
Simulation time 33938181 ps
CPU time 1.24 seconds
Started Aug 29 12:26:47 AM UTC 24
Finished Aug 29 12:26:53 AM UTC 24
Peak memory 228568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410962652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 295.edn_genbits.2410962652
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/295.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/296.edn_genbits.688843071
Short name T956
Test name
Test status
Simulation time 83204320 ps
CPU time 1.26 seconds
Started Aug 29 12:26:47 AM UTC 24
Finished Aug 29 12:26:53 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688843071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 296.edn_genbits.688843071
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/296.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/297.edn_genbits.3921481990
Short name T954
Test name
Test status
Simulation time 43469920 ps
CPU time 1.32 seconds
Started Aug 29 12:26:48 AM UTC 24
Finished Aug 29 12:26:53 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921481990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 297.edn_genbits.3921481990
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/297.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/298.edn_genbits.3404081535
Short name T949
Test name
Test status
Simulation time 39491356 ps
CPU time 1.27 seconds
Started Aug 29 12:26:49 AM UTC 24
Finished Aug 29 12:26:52 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404081535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 298.edn_genbits.3404081535
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/298.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/299.edn_genbits.3876891068
Short name T950
Test name
Test status
Simulation time 63598457 ps
CPU time 1.44 seconds
Started Aug 29 12:26:49 AM UTC 24
Finished Aug 29 12:26:52 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876891068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3876891068
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/299.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/3.edn_alert.2818111083
Short name T55
Test name
Test status
Simulation time 40988139 ps
CPU time 1.09 seconds
Started Aug 29 12:22:52 AM UTC 24
Finished Aug 29 12:22:54 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818111083 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 3.edn_alert.2818111083
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/3.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/3.edn_alert_test.812485903
Short name T66
Test name
Test status
Simulation time 20857012 ps
CPU time 0.95 seconds
Started Aug 29 12:22:53 AM UTC 24
Finished Aug 29 12:22:55 AM UTC 24
Peak memory 226536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812485903 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.812485903
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/3.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/3.edn_disable.2387936232
Short name T48
Test name
Test status
Simulation time 35178356 ps
CPU time 0.96 seconds
Started Aug 29 12:22:52 AM UTC 24
Finished Aug 29 12:22:54 AM UTC 24
Peak memory 216132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387936232 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.2387936232
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/3.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/3.edn_disable_auto_req_mode.1514086408
Short name T67
Test name
Test status
Simulation time 47986469 ps
CPU time 1.27 seconds
Started Aug 29 12:22:53 AM UTC 24
Finished Aug 29 12:22:55 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514086408 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable_auto_req_mode.1514086408
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/3.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/3.edn_err.3521124496
Short name T14
Test name
Test status
Simulation time 20105017 ps
CPU time 1.37 seconds
Started Aug 29 12:22:52 AM UTC 24
Finished Aug 29 12:22:54 AM UTC 24
Peak memory 236968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521124496 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 3.edn_err.3521124496
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/3.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/3.edn_genbits.3925413740
Short name T43
Test name
Test status
Simulation time 69914723 ps
CPU time 1.6 seconds
Started Aug 29 12:22:51 AM UTC 24
Finished Aug 29 12:22:54 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925413740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3925413740
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/3.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/3.edn_intr.1115518805
Short name T41
Test name
Test status
Simulation time 24418566 ps
CPU time 1.14 seconds
Started Aug 29 12:22:52 AM UTC 24
Finished Aug 29 12:22:54 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115518805 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 3.edn_intr.1115518805
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/3.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/3.edn_regwen.1298640263
Short name T117
Test name
Test status
Simulation time 26294850 ps
CPU time 1.29 seconds
Started Aug 29 12:22:51 AM UTC 24
Finished Aug 29 12:22:54 AM UTC 24
Peak memory 216032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298640263 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 3.edn_regwen.1298640263
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/3.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/3.edn_sec_cm.191799121
Short name T64
Test name
Test status
Simulation time 1203703969 ps
CPU time 8.1 seconds
Started Aug 29 12:22:53 AM UTC 24
Finished Aug 29 12:23:02 AM UTC 24
Peak memory 262424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191799121 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.191799121
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/3.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/3.edn_smoke.2377996174
Short name T305
Test name
Test status
Simulation time 17124479 ps
CPU time 1.36 seconds
Started Aug 29 12:22:51 AM UTC 24
Finished Aug 29 12:22:54 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377996174 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 3.edn_smoke.2377996174
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/3.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/3.edn_stress_all.1548565158
Short name T60
Test name
Test status
Simulation time 242446006 ps
CPU time 3.16 seconds
Started Aug 29 12:22:51 AM UTC 24
Finished Aug 29 12:22:56 AM UTC 24
Peak memory 231644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548565158 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1548565158
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/3.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/3.edn_stress_all_with_rand_reset.3105697264
Short name T38
Test name
Test status
Simulation time 1368670872 ps
CPU time 37.96 seconds
Started Aug 29 12:22:52 AM UTC 24
Finished Aug 29 12:23:31 AM UTC 24
Peak memory 231640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3105697264 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_
with_rand_reset.3105697264
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/3.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/30.edn_alert.2723897684
Short name T299
Test name
Test status
Simulation time 29207703 ps
CPU time 1.32 seconds
Started Aug 29 12:24:05 AM UTC 24
Finished Aug 29 12:24:11 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723897684 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 30.edn_alert.2723897684
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/30.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/30.edn_alert_test.3770015877
Short name T452
Test name
Test status
Simulation time 16075141 ps
CPU time 1.19 seconds
Started Aug 29 12:24:07 AM UTC 24
Finished Aug 29 12:24:17 AM UTC 24
Peak memory 216932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770015877 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3770015877
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/30.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/30.edn_disable_auto_req_mode.1291045289
Short name T152
Test name
Test status
Simulation time 77468020 ps
CPU time 1.44 seconds
Started Aug 29 12:24:05 AM UTC 24
Finished Aug 29 12:24:12 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291045289 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable_auto_req_mode.1291045289
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/30.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/30.edn_err.3758379661
Short name T173
Test name
Test status
Simulation time 24558410 ps
CPU time 1.87 seconds
Started Aug 29 12:24:05 AM UTC 24
Finished Aug 29 12:24:18 AM UTC 24
Peak memory 245148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758379661 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 30.edn_err.3758379661
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/30.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/30.edn_genbits.169881472
Short name T353
Test name
Test status
Simulation time 86053608 ps
CPU time 2.01 seconds
Started Aug 29 12:24:04 AM UTC 24
Finished Aug 29 12:24:08 AM UTC 24
Peak memory 231648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169881472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.edn_genbits.169881472
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/30.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/30.edn_intr.3749902593
Short name T456
Test name
Test status
Simulation time 26393154 ps
CPU time 1.28 seconds
Started Aug 29 12:24:05 AM UTC 24
Finished Aug 29 12:24:18 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749902593 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 30.edn_intr.3749902593
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/30.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/30.edn_smoke.167649069
Short name T435
Test name
Test status
Simulation time 22729158 ps
CPU time 0.91 seconds
Started Aug 29 12:24:04 AM UTC 24
Finished Aug 29 12:24:07 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167649069 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 30.edn_smoke.167649069
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/30.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/30.edn_stress_all.214722563
Short name T461
Test name
Test status
Simulation time 418132755 ps
CPU time 4.58 seconds
Started Aug 29 12:24:05 AM UTC 24
Finished Aug 29 12:24:21 AM UTC 24
Peak memory 229644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214722563 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.214722563
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/30.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/31.edn_alert.319076406
Short name T204
Test name
Test status
Simulation time 40447690 ps
CPU time 1.35 seconds
Started Aug 29 12:24:08 AM UTC 24
Finished Aug 29 12:24:22 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319076406 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 31.edn_alert.319076406
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/31.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/31.edn_alert_test.738982290
Short name T442
Test name
Test status
Simulation time 14056383 ps
CPU time 1.14 seconds
Started Aug 29 12:24:10 AM UTC 24
Finished Aug 29 12:24:12 AM UTC 24
Peak memory 217228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738982290 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.738982290
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/31.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/31.edn_disable.896246523
Short name T224
Test name
Test status
Simulation time 12854899 ps
CPU time 1.18 seconds
Started Aug 29 12:24:09 AM UTC 24
Finished Aug 29 12:24:12 AM UTC 24
Peak memory 226348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896246523 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.896246523
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/31.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/31.edn_disable_auto_req_mode.1993846800
Short name T472
Test name
Test status
Simulation time 81189329 ps
CPU time 1.49 seconds
Started Aug 29 12:24:09 AM UTC 24
Finished Aug 29 12:24:22 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993846800 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable_auto_req_mode.1993846800
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/31.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/31.edn_err.4281021415
Short name T137
Test name
Test status
Simulation time 24644013 ps
CPU time 1.54 seconds
Started Aug 29 12:24:08 AM UTC 24
Finished Aug 29 12:24:12 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281021415 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 31.edn_err.4281021415
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/31.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/31.edn_genbits.4205265055
Short name T443
Test name
Test status
Simulation time 37792985 ps
CPU time 1.44 seconds
Started Aug 29 12:24:08 AM UTC 24
Finished Aug 29 12:24:12 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205265055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_genbits.4205265055
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/31.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/31.edn_smoke.2896634194
Short name T441
Test name
Test status
Simulation time 21017608 ps
CPU time 1.15 seconds
Started Aug 29 12:24:08 AM UTC 24
Finished Aug 29 12:24:12 AM UTC 24
Peak memory 226180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896634194 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 31.edn_smoke.2896634194
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/31.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/31.edn_stress_all.78741596
Short name T444
Test name
Test status
Simulation time 83795128 ps
CPU time 2.09 seconds
Started Aug 29 12:24:08 AM UTC 24
Finished Aug 29 12:24:13 AM UTC 24
Peak memory 229712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78741596 -assert nopostproc +UVM_TESTNAME=edn_s
tress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.78741596
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/31.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/32.edn_alert_test.952313404
Short name T450
Test name
Test status
Simulation time 22636210 ps
CPU time 1.38 seconds
Started Aug 29 12:24:13 AM UTC 24
Finished Aug 29 12:24:17 AM UTC 24
Peak memory 217048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952313404 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.952313404
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/32.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/32.edn_disable.3366156399
Short name T237
Test name
Test status
Simulation time 30713593 ps
CPU time 0.97 seconds
Started Aug 29 12:24:13 AM UTC 24
Finished Aug 29 12:24:16 AM UTC 24
Peak memory 226368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366156399 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3366156399
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/32.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/32.edn_disable_auto_req_mode.1926638710
Short name T446
Test name
Test status
Simulation time 50072625 ps
CPU time 1.08 seconds
Started Aug 29 12:24:13 AM UTC 24
Finished Aug 29 12:24:16 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926638710 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable_auto_req_mode.1926638710
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/32.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/32.edn_err.1345283032
Short name T447
Test name
Test status
Simulation time 23977274 ps
CPU time 1.26 seconds
Started Aug 29 12:24:13 AM UTC 24
Finished Aug 29 12:24:17 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345283032 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 32.edn_err.1345283032
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/32.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/32.edn_genbits.3845956117
Short name T455
Test name
Test status
Simulation time 128970219 ps
CPU time 1.37 seconds
Started Aug 29 12:24:12 AM UTC 24
Finished Aug 29 12:24:17 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845956117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3845956117
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/32.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/32.edn_intr.2853420916
Short name T454
Test name
Test status
Simulation time 26864998 ps
CPU time 1.05 seconds
Started Aug 29 12:24:12 AM UTC 24
Finished Aug 29 12:24:17 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853420916 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 32.edn_intr.2853420916
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/32.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/32.edn_smoke.2714086873
Short name T470
Test name
Test status
Simulation time 40174023 ps
CPU time 1.31 seconds
Started Aug 29 12:24:10 AM UTC 24
Finished Aug 29 12:24:22 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714086873 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 32.edn_smoke.2714086873
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/32.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/32.edn_stress_all.2543739297
Short name T458
Test name
Test status
Simulation time 151793811 ps
CPU time 1.85 seconds
Started Aug 29 12:24:12 AM UTC 24
Finished Aug 29 12:24:18 AM UTC 24
Peak memory 228308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543739297 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.2543739297
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/32.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/32.edn_stress_all_with_rand_reset.3163505863
Short name T606
Test name
Test status
Simulation time 11702284939 ps
CPU time 48.41 seconds
Started Aug 29 12:24:12 AM UTC 24
Finished Aug 29 12:25:05 AM UTC 24
Peak memory 233812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3163505863 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all
_with_rand_reset.3163505863
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/32.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/33.edn_alert.226865685
Short name T468
Test name
Test status
Simulation time 28683719 ps
CPU time 1.52 seconds
Started Aug 29 12:24:17 AM UTC 24
Finished Aug 29 12:24:22 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226865685 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 33.edn_alert.226865685
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/33.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/33.edn_alert_test.1533348028
Short name T475
Test name
Test status
Simulation time 62380779 ps
CPU time 1.18 seconds
Started Aug 29 12:24:18 AM UTC 24
Finished Aug 29 12:24:23 AM UTC 24
Peak memory 217036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533348028 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1533348028
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/33.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/33.edn_disable.535301871
Short name T476
Test name
Test status
Simulation time 29521825 ps
CPU time 1.39 seconds
Started Aug 29 12:24:18 AM UTC 24
Finished Aug 29 12:24:23 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535301871 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.535301871
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/33.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/33.edn_disable_auto_req_mode.3588809711
Short name T462
Test name
Test status
Simulation time 103753166 ps
CPU time 1.4 seconds
Started Aug 29 12:24:18 AM UTC 24
Finished Aug 29 12:24:21 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588809711 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable_auto_req_mode.3588809711
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/33.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/33.edn_err.398565449
Short name T144
Test name
Test status
Simulation time 25486900 ps
CPU time 1.46 seconds
Started Aug 29 12:24:18 AM UTC 24
Finished Aug 29 12:24:20 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398565449 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 33.edn_err.398565449
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/33.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/33.edn_genbits.2516879198
Short name T457
Test name
Test status
Simulation time 43416161 ps
CPU time 2 seconds
Started Aug 29 12:24:13 AM UTC 24
Finished Aug 29 12:24:18 AM UTC 24
Peak memory 230608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516879198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2516879198
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/33.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/33.edn_intr.115079565
Short name T113
Test name
Test status
Simulation time 22676105 ps
CPU time 1.15 seconds
Started Aug 29 12:24:16 AM UTC 24
Finished Aug 29 12:24:22 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115079565 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 33.edn_intr.115079565
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/33.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/33.edn_smoke.1052559699
Short name T448
Test name
Test status
Simulation time 47265261 ps
CPU time 1.13 seconds
Started Aug 29 12:24:13 AM UTC 24
Finished Aug 29 12:24:17 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052559699 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 33.edn_smoke.1052559699
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/33.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/33.edn_stress_all.1860321536
Short name T328
Test name
Test status
Simulation time 408224052 ps
CPU time 4.31 seconds
Started Aug 29 12:24:14 AM UTC 24
Finished Aug 29 12:24:20 AM UTC 24
Peak memory 229540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860321536 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.1860321536
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/33.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/33.edn_stress_all_with_rand_reset.1100429288
Short name T255
Test name
Test status
Simulation time 11577962823 ps
CPU time 96.64 seconds
Started Aug 29 12:24:15 AM UTC 24
Finished Aug 29 12:25:54 AM UTC 24
Peak memory 231828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1100429288 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all
_with_rand_reset.1100429288
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/33.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/34.edn_alert.2216928199
Short name T178
Test name
Test status
Simulation time 176392146 ps
CPU time 1.85 seconds
Started Aug 29 12:24:19 AM UTC 24
Finished Aug 29 12:24:22 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216928199 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 34.edn_alert.2216928199
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/34.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/34.edn_alert_test.154748498
Short name T467
Test name
Test status
Simulation time 35762565 ps
CPU time 1.07 seconds
Started Aug 29 12:24:20 AM UTC 24
Finished Aug 29 12:24:22 AM UTC 24
Peak memory 215868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154748498 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.154748498
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/34.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/34.edn_disable.3066594326
Short name T466
Test name
Test status
Simulation time 12043629 ps
CPU time 1.17 seconds
Started Aug 29 12:24:20 AM UTC 24
Finished Aug 29 12:24:22 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066594326 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3066594326
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/34.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/34.edn_disable_auto_req_mode.1029685637
Short name T471
Test name
Test status
Simulation time 28422271 ps
CPU time 1.61 seconds
Started Aug 29 12:24:20 AM UTC 24
Finished Aug 29 12:24:22 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029685637 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable_auto_req_mode.1029685637
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/34.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/34.edn_err.992773971
Short name T165
Test name
Test status
Simulation time 52167083 ps
CPU time 1.13 seconds
Started Aug 29 12:24:19 AM UTC 24
Finished Aug 29 12:24:22 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992773971 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 34.edn_err.992773971
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/34.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/34.edn_genbits.161706665
Short name T465
Test name
Test status
Simulation time 96469969 ps
CPU time 1.52 seconds
Started Aug 29 12:24:18 AM UTC 24
Finished Aug 29 12:24:22 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161706665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.edn_genbits.161706665
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/34.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/34.edn_smoke.1839618262
Short name T463
Test name
Test status
Simulation time 73184486 ps
CPU time 1.33 seconds
Started Aug 29 12:24:18 AM UTC 24
Finished Aug 29 12:24:21 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839618262 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 34.edn_smoke.1839618262
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/34.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/34.edn_stress_all.908379377
Short name T329
Test name
Test status
Simulation time 360034154 ps
CPU time 2.91 seconds
Started Aug 29 12:24:18 AM UTC 24
Finished Aug 29 12:24:23 AM UTC 24
Peak memory 227384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908379377 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.908379377
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/34.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/34.edn_stress_all_with_rand_reset.2304920679
Short name T614
Test name
Test status
Simulation time 3341464107 ps
CPU time 46.61 seconds
Started Aug 29 12:24:18 AM UTC 24
Finished Aug 29 12:25:07 AM UTC 24
Peak memory 233812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2304920679 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all
_with_rand_reset.2304920679
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/34.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/35.edn_alert.3354206584
Short name T154
Test name
Test status
Simulation time 339257085 ps
CPU time 1.37 seconds
Started Aug 29 12:24:21 AM UTC 24
Finished Aug 29 12:24:23 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354206584 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 35.edn_alert.3354206584
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/35.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/35.edn_alert_test.2828986323
Short name T482
Test name
Test status
Simulation time 15408845 ps
CPU time 1.25 seconds
Started Aug 29 12:24:22 AM UTC 24
Finished Aug 29 12:24:25 AM UTC 24
Peak memory 216988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828986323 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.2828986323
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/35.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/35.edn_disable.723433349
Short name T479
Test name
Test status
Simulation time 28801603 ps
CPU time 1.26 seconds
Started Aug 29 12:24:22 AM UTC 24
Finished Aug 29 12:24:25 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723433349 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.723433349
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/35.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/35.edn_disable_auto_req_mode.1041072402
Short name T480
Test name
Test status
Simulation time 66780436 ps
CPU time 1.28 seconds
Started Aug 29 12:24:22 AM UTC 24
Finished Aug 29 12:24:25 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041072402 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable_auto_req_mode.1041072402
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/35.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/35.edn_err.121204734
Short name T477
Test name
Test status
Simulation time 23410423 ps
CPU time 1.27 seconds
Started Aug 29 12:24:21 AM UTC 24
Finished Aug 29 12:24:23 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121204734 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 35.edn_err.121204734
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/35.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/35.edn_genbits.651392586
Short name T473
Test name
Test status
Simulation time 108114675 ps
CPU time 1.62 seconds
Started Aug 29 12:24:20 AM UTC 24
Finished Aug 29 12:24:22 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651392586 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.edn_genbits.651392586
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/35.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/35.edn_intr.2413947625
Short name T474
Test name
Test status
Simulation time 110287636 ps
CPU time 0.93 seconds
Started Aug 29 12:24:21 AM UTC 24
Finished Aug 29 12:24:23 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413947625 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 35.edn_intr.2413947625
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/35.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/35.edn_smoke.522921317
Short name T469
Test name
Test status
Simulation time 17879290 ps
CPU time 1.31 seconds
Started Aug 29 12:24:20 AM UTC 24
Finished Aug 29 12:24:22 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522921317 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 35.edn_smoke.522921317
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/35.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/35.edn_stress_all.745558221
Short name T478
Test name
Test status
Simulation time 458707308 ps
CPU time 3.03 seconds
Started Aug 29 12:24:20 AM UTC 24
Finished Aug 29 12:24:24 AM UTC 24
Peak memory 227472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745558221 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.745558221
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/35.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/35.edn_stress_all_with_rand_reset.2681290439
Short name T808
Test name
Test status
Simulation time 19385258822 ps
CPU time 112.01 seconds
Started Aug 29 12:24:21 AM UTC 24
Finished Aug 29 12:26:15 AM UTC 24
Peak memory 233956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2681290439 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all
_with_rand_reset.2681290439
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/35.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/36.edn_alert_test.3926564661
Short name T489
Test name
Test status
Simulation time 16750960 ps
CPU time 1.37 seconds
Started Aug 29 12:24:24 AM UTC 24
Finished Aug 29 12:24:27 AM UTC 24
Peak memory 216856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926564661 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3926564661
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/36.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/36.edn_disable.3328386042
Short name T226
Test name
Test status
Simulation time 19415252 ps
CPU time 1.1 seconds
Started Aug 29 12:24:24 AM UTC 24
Finished Aug 29 12:24:26 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328386042 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3328386042
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/36.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/36.edn_disable_auto_req_mode.2980955760
Short name T484
Test name
Test status
Simulation time 57322474 ps
CPU time 1.2 seconds
Started Aug 29 12:24:24 AM UTC 24
Finished Aug 29 12:24:26 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980955760 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable_auto_req_mode.2980955760
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/36.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/36.edn_err.3585568709
Short name T485
Test name
Test status
Simulation time 23401957 ps
CPU time 1.56 seconds
Started Aug 29 12:24:24 AM UTC 24
Finished Aug 29 12:24:27 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585568709 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 36.edn_err.3585568709
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/36.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/36.edn_genbits.1688695648
Short name T331
Test name
Test status
Simulation time 240270423 ps
CPU time 4.48 seconds
Started Aug 29 12:24:22 AM UTC 24
Finished Aug 29 12:24:28 AM UTC 24
Peak memory 229516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688695648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1688695648
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/36.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/36.edn_intr.2206591202
Short name T483
Test name
Test status
Simulation time 21143023 ps
CPU time 1.47 seconds
Started Aug 29 12:24:23 AM UTC 24
Finished Aug 29 12:24:25 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206591202 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 36.edn_intr.2206591202
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/36.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/36.edn_smoke.3184722246
Short name T481
Test name
Test status
Simulation time 27133618 ps
CPU time 1.16 seconds
Started Aug 29 12:24:22 AM UTC 24
Finished Aug 29 12:24:25 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184722246 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 36.edn_smoke.3184722246
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/36.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/36.edn_stress_all.3385483456
Short name T498
Test name
Test status
Simulation time 301821990 ps
CPU time 6.29 seconds
Started Aug 29 12:24:22 AM UTC 24
Finished Aug 29 12:24:30 AM UTC 24
Peak memory 227424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385483456 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.3385483456
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/36.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/37.edn_alert.1921187818
Short name T488
Test name
Test status
Simulation time 67310798 ps
CPU time 1.18 seconds
Started Aug 29 12:24:24 AM UTC 24
Finished Aug 29 12:24:27 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921187818 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 37.edn_alert.1921187818
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/37.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/37.edn_alert_test.893417414
Short name T487
Test name
Test status
Simulation time 26464880 ps
CPU time 0.91 seconds
Started Aug 29 12:24:24 AM UTC 24
Finished Aug 29 12:24:27 AM UTC 24
Peak memory 216928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893417414 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.893417414
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/37.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/37.edn_disable.713732625
Short name T490
Test name
Test status
Simulation time 31466539 ps
CPU time 1.14 seconds
Started Aug 29 12:24:24 AM UTC 24
Finished Aug 29 12:24:27 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713732625 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.713732625
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/37.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/37.edn_disable_auto_req_mode.780131276
Short name T326
Test name
Test status
Simulation time 28142728 ps
CPU time 1.6 seconds
Started Aug 29 12:24:24 AM UTC 24
Finished Aug 29 12:24:27 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780131276 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable_auto_req_mode.780131276
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/37.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/37.edn_err.462218141
Short name T492
Test name
Test status
Simulation time 18426831 ps
CPU time 1.28 seconds
Started Aug 29 12:24:24 AM UTC 24
Finished Aug 29 12:24:27 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462218141 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 37.edn_err.462218141
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/37.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/37.edn_genbits.1653583964
Short name T333
Test name
Test status
Simulation time 38431436 ps
CPU time 1.71 seconds
Started Aug 29 12:24:24 AM UTC 24
Finished Aug 29 12:24:27 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653583964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1653583964
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/37.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/37.edn_intr.3292027807
Short name T491
Test name
Test status
Simulation time 22477251 ps
CPU time 1.32 seconds
Started Aug 29 12:24:24 AM UTC 24
Finished Aug 29 12:24:27 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292027807 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 37.edn_intr.3292027807
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/37.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/37.edn_smoke.3722135804
Short name T486
Test name
Test status
Simulation time 119986047 ps
CPU time 1.23 seconds
Started Aug 29 12:24:24 AM UTC 24
Finished Aug 29 12:24:27 AM UTC 24
Peak memory 226184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722135804 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 37.edn_smoke.3722135804
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/37.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/37.edn_stress_all.932327621
Short name T499
Test name
Test status
Simulation time 427159099 ps
CPU time 4.75 seconds
Started Aug 29 12:24:24 AM UTC 24
Finished Aug 29 12:24:30 AM UTC 24
Peak memory 227520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932327621 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.932327621
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/37.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/37.edn_stress_all_with_rand_reset.836386418
Short name T792
Test name
Test status
Simulation time 19490059985 ps
CPU time 100.46 seconds
Started Aug 29 12:24:24 AM UTC 24
Finished Aug 29 12:26:07 AM UTC 24
Peak memory 229816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=836386418 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_
with_rand_reset.836386418
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/37.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/38.edn_alert.217545450
Short name T495
Test name
Test status
Simulation time 267607275 ps
CPU time 1.27 seconds
Started Aug 29 12:24:26 AM UTC 24
Finished Aug 29 12:24:28 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217545450 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 38.edn_alert.217545450
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/38.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/38.edn_alert_test.4069572903
Short name T453
Test name
Test status
Simulation time 24016041 ps
CPU time 1.16 seconds
Started Aug 29 12:24:28 AM UTC 24
Finished Aug 29 12:24:31 AM UTC 24
Peak memory 216512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069572903 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.4069572903
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/38.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/38.edn_disable_auto_req_mode.3485640467
Short name T497
Test name
Test status
Simulation time 143399905 ps
CPU time 1.09 seconds
Started Aug 29 12:24:27 AM UTC 24
Finished Aug 29 12:24:29 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485640467 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable_auto_req_mode.3485640467
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/38.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/38.edn_err.71394986
Short name T193
Test name
Test status
Simulation time 53320456 ps
CPU time 1.67 seconds
Started Aug 29 12:24:27 AM UTC 24
Finished Aug 29 12:24:30 AM UTC 24
Peak memory 242076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71394986 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 38.edn_err.71394986
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/38.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/38.edn_genbits.2891757554
Short name T496
Test name
Test status
Simulation time 36992019 ps
CPU time 1.46 seconds
Started Aug 29 12:24:25 AM UTC 24
Finished Aug 29 12:24:28 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891757554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2891757554
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/38.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/38.edn_intr.1347876673
Short name T494
Test name
Test status
Simulation time 35110680 ps
CPU time 1.28 seconds
Started Aug 29 12:24:26 AM UTC 24
Finished Aug 29 12:24:28 AM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347876673 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 38.edn_intr.1347876673
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/38.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/38.edn_smoke.1198978241
Short name T493
Test name
Test status
Simulation time 108304544 ps
CPU time 1.16 seconds
Started Aug 29 12:24:24 AM UTC 24
Finished Aug 29 12:24:27 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198978241 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 38.edn_smoke.1198978241
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/38.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/38.edn_stress_all.2665176586
Short name T269
Test name
Test status
Simulation time 494284557 ps
CPU time 3.01 seconds
Started Aug 29 12:24:26 AM UTC 24
Finished Aug 29 12:24:30 AM UTC 24
Peak memory 227352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665176586 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2665176586
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/38.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/38.edn_stress_all_with_rand_reset.2858612699
Short name T608
Test name
Test status
Simulation time 2182065884 ps
CPU time 38.21 seconds
Started Aug 29 12:24:26 AM UTC 24
Finished Aug 29 12:25:05 AM UTC 24
Peak memory 229816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2858612699 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all
_with_rand_reset.2858612699
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/38.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/39.edn_alert.1307383196
Short name T195
Test name
Test status
Simulation time 84896533 ps
CPU time 1.35 seconds
Started Aug 29 12:24:28 AM UTC 24
Finished Aug 29 12:24:32 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307383196 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 39.edn_alert.1307383196
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/39.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/39.edn_alert_test.767722132
Short name T501
Test name
Test status
Simulation time 31074882 ps
CPU time 1.32 seconds
Started Aug 29 12:24:29 AM UTC 24
Finished Aug 29 12:24:32 AM UTC 24
Peak memory 216244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767722132 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.767722132
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/39.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/39.edn_disable.676857006
Short name T445
Test name
Test status
Simulation time 22371339 ps
CPU time 1.23 seconds
Started Aug 29 12:24:28 AM UTC 24
Finished Aug 29 12:24:32 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676857006 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.676857006
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/39.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/39.edn_disable_auto_req_mode.3224304470
Short name T502
Test name
Test status
Simulation time 61698007 ps
CPU time 1.53 seconds
Started Aug 29 12:24:29 AM UTC 24
Finished Aug 29 12:24:32 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224304470 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable_auto_req_mode.3224304470
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/39.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/39.edn_err.1734377581
Short name T503
Test name
Test status
Simulation time 19402333 ps
CPU time 1.54 seconds
Started Aug 29 12:24:28 AM UTC 24
Finished Aug 29 12:24:32 AM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734377581 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 39.edn_err.1734377581
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/39.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/39.edn_genbits.1406314760
Short name T350
Test name
Test status
Simulation time 56485721 ps
CPU time 1.58 seconds
Started Aug 29 12:24:28 AM UTC 24
Finished Aug 29 12:24:32 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406314760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1406314760
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/39.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/39.edn_intr.3623585114
Short name T451
Test name
Test status
Simulation time 20412091 ps
CPU time 1.42 seconds
Started Aug 29 12:24:28 AM UTC 24
Finished Aug 29 12:24:32 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623585114 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 39.edn_intr.3623585114
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/39.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/39.edn_smoke.1256621957
Short name T449
Test name
Test status
Simulation time 25046865 ps
CPU time 1.39 seconds
Started Aug 29 12:24:28 AM UTC 24
Finished Aug 29 12:24:32 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256621957 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 39.edn_smoke.1256621957
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/39.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/39.edn_stress_all.3100561921
Short name T505
Test name
Test status
Simulation time 497692795 ps
CPU time 4.51 seconds
Started Aug 29 12:24:28 AM UTC 24
Finished Aug 29 12:24:35 AM UTC 24
Peak memory 227580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100561921 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3100561921
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/39.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/4.edn_alert_test.2835779770
Short name T273
Test name
Test status
Simulation time 35385722 ps
CPU time 1.19 seconds
Started Aug 29 12:22:55 AM UTC 24
Finished Aug 29 12:22:57 AM UTC 24
Peak memory 216748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835779770 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2835779770
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/4.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/4.edn_disable.50950324
Short name T68
Test name
Test status
Simulation time 17540970 ps
CPU time 1.06 seconds
Started Aug 29 12:22:53 AM UTC 24
Finished Aug 29 12:22:56 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50950324 -assert nopostproc +UVM_TESTNAME=edn_disab
le_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.50950324
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/4.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/4.edn_disable_auto_req_mode.196478409
Short name T42
Test name
Test status
Simulation time 102209801 ps
CPU time 1.15 seconds
Started Aug 29 12:22:55 AM UTC 24
Finished Aug 29 12:22:57 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196478409 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable_auto_req_mode.196478409
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/4.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/4.edn_err.3804319517
Short name T15
Test name
Test status
Simulation time 23459967 ps
CPU time 1.44 seconds
Started Aug 29 12:22:53 AM UTC 24
Finished Aug 29 12:22:56 AM UTC 24
Peak memory 236732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804319517 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 4.edn_err.3804319517
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/4.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/4.edn_genbits.302921210
Short name T87
Test name
Test status
Simulation time 105231986 ps
CPU time 1.78 seconds
Started Aug 29 12:22:53 AM UTC 24
Finished Aug 29 12:22:56 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302921210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.edn_genbits.302921210
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/4.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/4.edn_intr.1919967366
Short name T69
Test name
Test status
Simulation time 27001108 ps
CPU time 1.05 seconds
Started Aug 29 12:22:53 AM UTC 24
Finished Aug 29 12:22:56 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919967366 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 4.edn_intr.1919967366
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/4.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/4.edn_regwen.3108185564
Short name T70
Test name
Test status
Simulation time 79348548 ps
CPU time 1.4 seconds
Started Aug 29 12:22:53 AM UTC 24
Finished Aug 29 12:22:56 AM UTC 24
Peak memory 216032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108185564 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 4.edn_regwen.3108185564
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/4.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/4.edn_sec_cm.2474326385
Short name T63
Test name
Test status
Simulation time 281244746 ps
CPU time 5.36 seconds
Started Aug 29 12:22:55 AM UTC 24
Finished Aug 29 12:23:01 AM UTC 24
Peak memory 258316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474326385 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.2474326385
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/4.edn_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/4.edn_smoke.3933426593
Short name T71
Test name
Test status
Simulation time 15793774 ps
CPU time 1.39 seconds
Started Aug 29 12:22:53 AM UTC 24
Finished Aug 29 12:22:56 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933426593 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 4.edn_smoke.3933426593
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/4.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/4.edn_stress_all.2771456019
Short name T72
Test name
Test status
Simulation time 165905863 ps
CPU time 1.54 seconds
Started Aug 29 12:22:53 AM UTC 24
Finished Aug 29 12:22:56 AM UTC 24
Peak memory 226300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771456019 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2771456019
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/4.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/4.edn_stress_all_with_rand_reset.531519813
Short name T36
Test name
Test status
Simulation time 840486380 ps
CPU time 18.95 seconds
Started Aug 29 12:22:53 AM UTC 24
Finished Aug 29 12:23:14 AM UTC 24
Peak memory 231716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=531519813 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_w
ith_rand_reset.531519813
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/4.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/40.edn_alert.84061428
Short name T155
Test name
Test status
Simulation time 25882392 ps
CPU time 1.56 seconds
Started Aug 29 12:24:30 AM UTC 24
Finished Aug 29 12:24:43 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84061428 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a
lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 40.edn_alert.84061428
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/40.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/40.edn_alert_test.3361306215
Short name T506
Test name
Test status
Simulation time 36953940 ps
CPU time 1.04 seconds
Started Aug 29 12:24:31 AM UTC 24
Finished Aug 29 12:24:36 AM UTC 24
Peak memory 216412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361306215 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3361306215
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/40.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/40.edn_disable.3144546848
Short name T523
Test name
Test status
Simulation time 28132948 ps
CPU time 1.13 seconds
Started Aug 29 12:24:30 AM UTC 24
Finished Aug 29 12:24:42 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144546848 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.3144546848
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/40.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/40.edn_disable_auto_req_mode.88353537
Short name T153
Test name
Test status
Simulation time 46604920 ps
CPU time 1.54 seconds
Started Aug 29 12:24:30 AM UTC 24
Finished Aug 29 12:24:53 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88353537 -assert nopostproc +UVM_TESTNAME=edn_disab
le_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable_auto_req_mode.88353537
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/40.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/40.edn_err.3076014022
Short name T524
Test name
Test status
Simulation time 19958075 ps
CPU time 1.51 seconds
Started Aug 29 12:24:30 AM UTC 24
Finished Aug 29 12:24:43 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076014022 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 40.edn_err.3076014022
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/40.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/40.edn_genbits.2641227145
Short name T522
Test name
Test status
Simulation time 64875587 ps
CPU time 1.39 seconds
Started Aug 29 12:24:30 AM UTC 24
Finished Aug 29 12:24:42 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641227145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_genbits.2641227145
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/40.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/40.edn_intr.2477908012
Short name T141
Test name
Test status
Simulation time 22516980 ps
CPU time 1.64 seconds
Started Aug 29 12:24:30 AM UTC 24
Finished Aug 29 12:24:43 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477908012 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 40.edn_intr.2477908012
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/40.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/40.edn_smoke.821752359
Short name T500
Test name
Test status
Simulation time 31684714 ps
CPU time 1.13 seconds
Started Aug 29 12:24:29 AM UTC 24
Finished Aug 29 12:24:32 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821752359 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 40.edn_smoke.821752359
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/40.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/40.edn_stress_all.87650594
Short name T270
Test name
Test status
Simulation time 307631323 ps
CPU time 3.68 seconds
Started Aug 29 12:24:30 AM UTC 24
Finished Aug 29 12:24:35 AM UTC 24
Peak memory 227412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87650594 -assert nopostproc +UVM_TESTNAME=edn_s
tress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.87650594
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/40.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/41.edn_alert.4130452953
Short name T172
Test name
Test status
Simulation time 44438924 ps
CPU time 1.34 seconds
Started Aug 29 12:24:33 AM UTC 24
Finished Aug 29 12:24:38 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130452953 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 41.edn_alert.4130452953
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/41.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/41.edn_alert_test.2873846410
Short name T516
Test name
Test status
Simulation time 52215612 ps
CPU time 1.26 seconds
Started Aug 29 12:24:33 AM UTC 24
Finished Aug 29 12:24:38 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873846410 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2873846410
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/41.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/41.edn_disable.1623251973
Short name T515
Test name
Test status
Simulation time 27476749 ps
CPU time 1.24 seconds
Started Aug 29 12:24:33 AM UTC 24
Finished Aug 29 12:24:38 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623251973 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.1623251973
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/41.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/41.edn_disable_auto_req_mode.3036769684
Short name T517
Test name
Test status
Simulation time 35430936 ps
CPU time 1.78 seconds
Started Aug 29 12:24:33 AM UTC 24
Finished Aug 29 12:24:39 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036769684 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable_auto_req_mode.3036769684
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/41.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/41.edn_err.940205780
Short name T185
Test name
Test status
Simulation time 23156532 ps
CPU time 1.04 seconds
Started Aug 29 12:24:33 AM UTC 24
Finished Aug 29 12:24:38 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940205780 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 41.edn_err.940205780
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/41.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/41.edn_genbits.3780892878
Short name T510
Test name
Test status
Simulation time 30599618 ps
CPU time 1.6 seconds
Started Aug 29 12:24:31 AM UTC 24
Finished Aug 29 12:24:37 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780892878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_genbits.3780892878
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/41.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/41.edn_intr.3797093117
Short name T513
Test name
Test status
Simulation time 27688011 ps
CPU time 0.92 seconds
Started Aug 29 12:24:33 AM UTC 24
Finished Aug 29 12:24:38 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797093117 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 41.edn_intr.3797093117
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/41.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/41.edn_smoke.3677879141
Short name T508
Test name
Test status
Simulation time 21402460 ps
CPU time 1.12 seconds
Started Aug 29 12:24:31 AM UTC 24
Finished Aug 29 12:24:37 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677879141 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 41.edn_smoke.3677879141
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/41.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/41.edn_stress_all.2641667093
Short name T514
Test name
Test status
Simulation time 237655550 ps
CPU time 2.55 seconds
Started Aug 29 12:24:31 AM UTC 24
Finished Aug 29 12:24:38 AM UTC 24
Peak memory 227492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641667093 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.2641667093
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/41.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/41.edn_stress_all_with_rand_reset.1575863285
Short name T256
Test name
Test status
Simulation time 4359865890 ps
CPU time 90.44 seconds
Started Aug 29 12:24:33 AM UTC 24
Finished Aug 29 12:26:08 AM UTC 24
Peak memory 229720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1575863285 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all
_with_rand_reset.1575863285
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/41.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/42.edn_alert.999413133
Short name T512
Test name
Test status
Simulation time 126852452 ps
CPU time 1.28 seconds
Started Aug 29 12:24:35 AM UTC 24
Finished Aug 29 12:24:38 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999413133 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 42.edn_alert.999413133
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/42.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/42.edn_alert_test.360474809
Short name T528
Test name
Test status
Simulation time 55270956 ps
CPU time 1.38 seconds
Started Aug 29 12:24:37 AM UTC 24
Finished Aug 29 12:24:46 AM UTC 24
Peak memory 216244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360474809 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.360474809
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/42.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/42.edn_disable_auto_req_mode.2548528124
Short name T533
Test name
Test status
Simulation time 54507014 ps
CPU time 1.42 seconds
Started Aug 29 12:24:37 AM UTC 24
Finished Aug 29 12:24:47 AM UTC 24
Peak memory 230348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548528124 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable_auto_req_mode.2548528124
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/42.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/42.edn_err.2566006536
Short name T148
Test name
Test status
Simulation time 20615876 ps
CPU time 1.5 seconds
Started Aug 29 12:24:37 AM UTC 24
Finished Aug 29 12:24:41 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566006536 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 42.edn_err.2566006536
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/42.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/42.edn_genbits.702738945
Short name T509
Test name
Test status
Simulation time 37009056 ps
CPU time 1.71 seconds
Started Aug 29 12:24:33 AM UTC 24
Finished Aug 29 12:24:37 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702738945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.edn_genbits.702738945
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/42.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/42.edn_intr.1201506591
Short name T511
Test name
Test status
Simulation time 45040437 ps
CPU time 0.87 seconds
Started Aug 29 12:24:35 AM UTC 24
Finished Aug 29 12:24:37 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201506591 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 42.edn_intr.1201506591
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/42.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/42.edn_smoke.893590971
Short name T507
Test name
Test status
Simulation time 25703377 ps
CPU time 1.43 seconds
Started Aug 29 12:24:33 AM UTC 24
Finished Aug 29 12:24:37 AM UTC 24
Peak memory 226152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893590971 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 42.edn_smoke.893590971
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/42.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/42.edn_stress_all.4216740056
Short name T518
Test name
Test status
Simulation time 328717371 ps
CPU time 4.01 seconds
Started Aug 29 12:24:33 AM UTC 24
Finished Aug 29 12:24:39 AM UTC 24
Peak memory 229456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216740056 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.4216740056
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/42.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/43.edn_alert_test.3755588039
Short name T559
Test name
Test status
Simulation time 55742308 ps
CPU time 1.2 seconds
Started Aug 29 12:24:40 AM UTC 24
Finished Aug 29 12:24:52 AM UTC 24
Peak memory 226908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755588039 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3755588039
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/43.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/43.edn_disable.2303290612
Short name T520
Test name
Test status
Simulation time 38638769 ps
CPU time 1.2 seconds
Started Aug 29 12:24:39 AM UTC 24
Finished Aug 29 12:24:41 AM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303290612 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2303290612
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/43.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/43.edn_disable_auto_req_mode.297462367
Short name T300
Test name
Test status
Simulation time 34985776 ps
CPU time 1.65 seconds
Started Aug 29 12:24:39 AM UTC 24
Finished Aug 29 12:24:42 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297462367 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable_auto_req_mode.297462367
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/43.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/43.edn_genbits.2178816871
Short name T525
Test name
Test status
Simulation time 122274500 ps
CPU time 2.14 seconds
Started Aug 29 12:24:39 AM UTC 24
Finished Aug 29 12:24:43 AM UTC 24
Peak memory 231512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178816871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2178816871
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/43.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/43.edn_smoke.1707299048
Short name T521
Test name
Test status
Simulation time 47891799 ps
CPU time 1.39 seconds
Started Aug 29 12:24:39 AM UTC 24
Finished Aug 29 12:24:42 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707299048 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 43.edn_smoke.1707299048
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/43.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/43.edn_stress_all.1586631028
Short name T271
Test name
Test status
Simulation time 179383119 ps
CPU time 3 seconds
Started Aug 29 12:24:39 AM UTC 24
Finished Aug 29 12:24:44 AM UTC 24
Peak memory 227416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586631028 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1586631028
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/43.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/44.edn_alert.1214471490
Short name T541
Test name
Test status
Simulation time 24366537 ps
CPU time 1.44 seconds
Started Aug 29 12:24:43 AM UTC 24
Finished Aug 29 12:24:48 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214471490 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 44.edn_alert.1214471490
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/44.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/44.edn_alert_test.1448515233
Short name T530
Test name
Test status
Simulation time 16455587 ps
CPU time 1.29 seconds
Started Aug 29 12:24:44 AM UTC 24
Finished Aug 29 12:24:46 AM UTC 24
Peak memory 217052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448515233 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.1448515233
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/44.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/44.edn_disable.568410774
Short name T529
Test name
Test status
Simulation time 103881989 ps
CPU time 1.21 seconds
Started Aug 29 12:24:44 AM UTC 24
Finished Aug 29 12:24:46 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568410774 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ed
n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.568410774
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/44.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/44.edn_disable_auto_req_mode.2610725012
Short name T536
Test name
Test status
Simulation time 29033795 ps
CPU time 1.5 seconds
Started Aug 29 12:24:44 AM UTC 24
Finished Aug 29 12:24:48 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610725012 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable_auto_req_mode.2610725012
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/44.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/44.edn_err.3270408950
Short name T539
Test name
Test status
Simulation time 113984646 ps
CPU time 1.08 seconds
Started Aug 29 12:24:43 AM UTC 24
Finished Aug 29 12:24:48 AM UTC 24
Peak memory 228308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270408950 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 44.edn_err.3270408950
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/44.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/44.edn_genbits.667118516
Short name T534
Test name
Test status
Simulation time 58344661 ps
CPU time 1.73 seconds
Started Aug 29 12:24:41 AM UTC 24
Finished Aug 29 12:24:47 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667118516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.edn_genbits.667118516
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/44.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/44.edn_intr.584726432
Short name T538
Test name
Test status
Simulation time 48839939 ps
CPU time 1.19 seconds
Started Aug 29 12:24:43 AM UTC 24
Finished Aug 29 12:24:48 AM UTC 24
Peak memory 236696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584726432 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 44.edn_intr.584726432
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/44.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/44.edn_smoke.3857256621
Short name T560
Test name
Test status
Simulation time 28364645 ps
CPU time 1.32 seconds
Started Aug 29 12:24:40 AM UTC 24
Finished Aug 29 12:24:53 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857256621 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 44.edn_smoke.3857256621
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/44.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/44.edn_stress_all.1737467418
Short name T548
Test name
Test status
Simulation time 516775915 ps
CPU time 5.3 seconds
Started Aug 29 12:24:41 AM UTC 24
Finished Aug 29 12:24:51 AM UTC 24
Peak memory 227572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737467418 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1737467418
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/44.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/44.edn_stress_all_with_rand_reset.338600057
Short name T807
Test name
Test status
Simulation time 6612690537 ps
CPU time 84.07 seconds
Started Aug 29 12:24:43 AM UTC 24
Finished Aug 29 12:26:12 AM UTC 24
Peak memory 233944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=338600057 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_
with_rand_reset.338600057
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/44.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/45.edn_alert.1496527654
Short name T542
Test name
Test status
Simulation time 32166502 ps
CPU time 1.7 seconds
Started Aug 29 12:24:45 AM UTC 24
Finished Aug 29 12:24:48 AM UTC 24
Peak memory 228144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496527654 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 45.edn_alert.1496527654
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/45.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/45.edn_alert_test.654532482
Short name T545
Test name
Test status
Simulation time 33862683 ps
CPU time 1.33 seconds
Started Aug 29 12:24:47 AM UTC 24
Finished Aug 29 12:24:49 AM UTC 24
Peak memory 216928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654532482 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.654532482
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/45.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/45.edn_disable.2847900831
Short name T537
Test name
Test status
Simulation time 11733637 ps
CPU time 1.2 seconds
Started Aug 29 12:24:46 AM UTC 24
Finished Aug 29 12:24:48 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847900831 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2847900831
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/45.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/45.edn_disable_auto_req_mode.1733716984
Short name T547
Test name
Test status
Simulation time 108121011 ps
CPU time 1.62 seconds
Started Aug 29 12:24:47 AM UTC 24
Finished Aug 29 12:24:49 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733716984 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable_auto_req_mode.1733716984
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/45.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/45.edn_err.3919986174
Short name T540
Test name
Test status
Simulation time 49129128 ps
CPU time 1.6 seconds
Started Aug 29 12:24:45 AM UTC 24
Finished Aug 29 12:24:48 AM UTC 24
Peak memory 230144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919986174 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 45.edn_err.3919986174
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/45.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/45.edn_genbits.2511819921
Short name T352
Test name
Test status
Simulation time 59671388 ps
CPU time 1.36 seconds
Started Aug 29 12:24:44 AM UTC 24
Finished Aug 29 12:24:46 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511819921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_genbits.2511819921
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/45.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/45.edn_intr.3379367998
Short name T532
Test name
Test status
Simulation time 21411410 ps
CPU time 1.63 seconds
Started Aug 29 12:24:44 AM UTC 24
Finished Aug 29 12:24:47 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379367998 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 45.edn_intr.3379367998
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/45.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/45.edn_smoke.3197158659
Short name T531
Test name
Test status
Simulation time 139148513 ps
CPU time 1.28 seconds
Started Aug 29 12:24:44 AM UTC 24
Finished Aug 29 12:24:46 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197158659 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 45.edn_smoke.3197158659
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/45.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/45.edn_stress_all.1335829838
Short name T543
Test name
Test status
Simulation time 126087561 ps
CPU time 3.24 seconds
Started Aug 29 12:24:44 AM UTC 24
Finished Aug 29 12:24:48 AM UTC 24
Peak memory 229524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335829838 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1335829838
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/45.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/45.edn_stress_all_with_rand_reset.1778600887
Short name T252
Test name
Test status
Simulation time 853728827 ps
CPU time 20.34 seconds
Started Aug 29 12:24:44 AM UTC 24
Finished Aug 29 12:25:06 AM UTC 24
Peak memory 231908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1778600887 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all
_with_rand_reset.1778600887
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/45.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/46.edn_alert.634500546
Short name T557
Test name
Test status
Simulation time 83825160 ps
CPU time 1.77 seconds
Started Aug 29 12:24:48 AM UTC 24
Finished Aug 29 12:24:52 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634500546 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 46.edn_alert.634500546
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/46.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/46.edn_alert_test.2273618711
Short name T552
Test name
Test status
Simulation time 56646291 ps
CPU time 1.41 seconds
Started Aug 29 12:24:49 AM UTC 24
Finished Aug 29 12:24:52 AM UTC 24
Peak memory 216248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273618711 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2273618711
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/46.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/46.edn_disable.3649119444
Short name T550
Test name
Test status
Simulation time 38648519 ps
CPU time 1.2 seconds
Started Aug 29 12:24:48 AM UTC 24
Finished Aug 29 12:24:51 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649119444 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3649119444
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/46.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/46.edn_disable_auto_req_mode.266850226
Short name T553
Test name
Test status
Simulation time 41490175 ps
CPU time 1.46 seconds
Started Aug 29 12:24:49 AM UTC 24
Finished Aug 29 12:24:52 AM UTC 24
Peak memory 230348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266850226 -assert nopostproc +UVM_TESTNAME=edn_disa
ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable_auto_req_mode.266850226
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/46.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/46.edn_err.2656878203
Short name T551
Test name
Test status
Simulation time 27880851 ps
CPU time 1.31 seconds
Started Aug 29 12:24:48 AM UTC 24
Finished Aug 29 12:24:52 AM UTC 24
Peak memory 236344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656878203 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 46.edn_err.2656878203
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/46.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/46.edn_genbits.4028548840
Short name T546
Test name
Test status
Simulation time 88712678 ps
CPU time 1.41 seconds
Started Aug 29 12:24:47 AM UTC 24
Finished Aug 29 12:24:49 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028548840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_genbits.4028548840
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/46.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/46.edn_intr.2174305150
Short name T554
Test name
Test status
Simulation time 23193278 ps
CPU time 1.76 seconds
Started Aug 29 12:24:48 AM UTC 24
Finished Aug 29 12:24:52 AM UTC 24
Peak memory 237940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174305150 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 46.edn_intr.2174305150
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/46.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/46.edn_smoke.1887484355
Short name T544
Test name
Test status
Simulation time 18311815 ps
CPU time 1.22 seconds
Started Aug 29 12:24:47 AM UTC 24
Finished Aug 29 12:24:49 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887484355 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 46.edn_smoke.1887484355
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/46.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/46.edn_stress_all.2443026480
Short name T564
Test name
Test status
Simulation time 101675690 ps
CPU time 3.02 seconds
Started Aug 29 12:24:47 AM UTC 24
Finished Aug 29 12:24:54 AM UTC 24
Peak memory 227428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443026480 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2443026480
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/46.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/47.edn_alert.766028773
Short name T215
Test name
Test status
Simulation time 73232739 ps
CPU time 1.68 seconds
Started Aug 29 12:24:50 AM UTC 24
Finished Aug 29 12:24:52 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766028773 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 47.edn_alert.766028773
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/47.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/47.edn_alert_test.3895807794
Short name T562
Test name
Test status
Simulation time 13726566 ps
CPU time 1.31 seconds
Started Aug 29 12:24:51 AM UTC 24
Finished Aug 29 12:24:53 AM UTC 24
Peak memory 216692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895807794 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3895807794
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/47.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/47.edn_disable.1215733471
Short name T561
Test name
Test status
Simulation time 36509349 ps
CPU time 1.26 seconds
Started Aug 29 12:24:51 AM UTC 24
Finished Aug 29 12:24:53 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215733471 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1215733471
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/47.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/47.edn_disable_auto_req_mode.3947734445
Short name T563
Test name
Test status
Simulation time 330213881 ps
CPU time 1.56 seconds
Started Aug 29 12:24:51 AM UTC 24
Finished Aug 29 12:24:53 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947734445 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable_auto_req_mode.3947734445
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/47.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/47.edn_err.2777466425
Short name T556
Test name
Test status
Simulation time 35600819 ps
CPU time 1.13 seconds
Started Aug 29 12:24:50 AM UTC 24
Finished Aug 29 12:24:52 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777466425 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 47.edn_err.2777466425
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/47.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/47.edn_intr.4035939426
Short name T558
Test name
Test status
Simulation time 28218217 ps
CPU time 1.64 seconds
Started Aug 29 12:24:50 AM UTC 24
Finished Aug 29 12:24:52 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035939426 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 47.edn_intr.4035939426
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/47.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/47.edn_smoke.1309386083
Short name T555
Test name
Test status
Simulation time 25625105 ps
CPU time 1.44 seconds
Started Aug 29 12:24:49 AM UTC 24
Finished Aug 29 12:24:52 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309386083 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 47.edn_smoke.1309386083
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/47.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/47.edn_stress_all.3792825289
Short name T566
Test name
Test status
Simulation time 2214604334 ps
CPU time 4.87 seconds
Started Aug 29 12:24:49 AM UTC 24
Finished Aug 29 12:24:55 AM UTC 24
Peak memory 227540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792825289 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3792825289
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/47.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/48.edn_alert.2825827187
Short name T572
Test name
Test status
Simulation time 28756927 ps
CPU time 1.76 seconds
Started Aug 29 12:24:53 AM UTC 24
Finished Aug 29 12:24:56 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825827187 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 48.edn_alert.2825827187
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/48.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/48.edn_alert_test.81776741
Short name T569
Test name
Test status
Simulation time 14416367 ps
CPU time 1.25 seconds
Started Aug 29 12:24:54 AM UTC 24
Finished Aug 29 12:24:56 AM UTC 24
Peak memory 217052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81776741 -assert nopostproc +UVM_TESTNAME=edn_base
_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.81776741
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/48.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/48.edn_disable.1133188591
Short name T567
Test name
Test status
Simulation time 37307356 ps
CPU time 1.14 seconds
Started Aug 29 12:24:54 AM UTC 24
Finished Aug 29 12:24:56 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133188591 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.1133188591
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/48.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/48.edn_disable_auto_req_mode.2436701043
Short name T571
Test name
Test status
Simulation time 48997697 ps
CPU time 1.47 seconds
Started Aug 29 12:24:54 AM UTC 24
Finished Aug 29 12:24:56 AM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436701043 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable_auto_req_mode.2436701043
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/48.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/48.edn_err.580074319
Short name T201
Test name
Test status
Simulation time 30857967 ps
CPU time 1.32 seconds
Started Aug 29 12:24:53 AM UTC 24
Finished Aug 29 12:24:56 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580074319 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 48.edn_err.580074319
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/48.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/48.edn_intr.4240061426
Short name T568
Test name
Test status
Simulation time 38110132 ps
CPU time 1.23 seconds
Started Aug 29 12:24:53 AM UTC 24
Finished Aug 29 12:24:56 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240061426 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 48.edn_intr.4240061426
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/48.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/48.edn_smoke.1556138155
Short name T565
Test name
Test status
Simulation time 22139160 ps
CPU time 1.25 seconds
Started Aug 29 12:24:52 AM UTC 24
Finished Aug 29 12:24:54 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556138155 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 48.edn_smoke.1556138155
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/48.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/48.edn_stress_all.1866012394
Short name T272
Test name
Test status
Simulation time 441174595 ps
CPU time 2.84 seconds
Started Aug 29 12:24:52 AM UTC 24
Finished Aug 29 12:24:56 AM UTC 24
Peak memory 231524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866012394 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1866012394
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/48.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/48.edn_stress_all_with_rand_reset.3874730601
Short name T257
Test name
Test status
Simulation time 4614084734 ps
CPU time 95.89 seconds
Started Aug 29 12:24:53 AM UTC 24
Finished Aug 29 12:26:31 AM UTC 24
Peak memory 233888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3874730601 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all
_with_rand_reset.3874730601
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/48.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/49.edn_alert.3176053195
Short name T573
Test name
Test status
Simulation time 70115285 ps
CPU time 1.5 seconds
Started Aug 29 12:24:54 AM UTC 24
Finished Aug 29 12:24:56 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176053195 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 49.edn_alert.3176053195
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/49.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/49.edn_alert_test.3850086208
Short name T574
Test name
Test status
Simulation time 51997606 ps
CPU time 1.17 seconds
Started Aug 29 12:24:55 AM UTC 24
Finished Aug 29 12:24:57 AM UTC 24
Peak memory 215872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850086208 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3850086208
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/49.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/49.edn_disable_auto_req_mode.3331266444
Short name T576
Test name
Test status
Simulation time 62112067 ps
CPU time 1.72 seconds
Started Aug 29 12:24:55 AM UTC 24
Finished Aug 29 12:24:58 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331266444 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable_auto_req_mode.3331266444
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/49.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/49.edn_err.3738194161
Short name T549
Test name
Test status
Simulation time 18364313 ps
CPU time 1.57 seconds
Started Aug 29 12:24:55 AM UTC 24
Finished Aug 29 12:24:58 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738194161 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 49.edn_err.3738194161
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/49.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/49.edn_genbits.1261683870
Short name T580
Test name
Test status
Simulation time 129204338 ps
CPU time 4.03 seconds
Started Aug 29 12:24:54 AM UTC 24
Finished Aug 29 12:24:59 AM UTC 24
Peak memory 231580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261683870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1261683870
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/49.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/49.edn_intr.719529612
Short name T114
Test name
Test status
Simulation time 32997538 ps
CPU time 1.27 seconds
Started Aug 29 12:24:54 AM UTC 24
Finished Aug 29 12:24:56 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719529612 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i
ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 49.edn_intr.719529612
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/49.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/49.edn_smoke.2926186683
Short name T570
Test name
Test status
Simulation time 44891901 ps
CPU time 1.37 seconds
Started Aug 29 12:24:54 AM UTC 24
Finished Aug 29 12:24:56 AM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926186683 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 49.edn_smoke.2926186683
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/49.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/49.edn_stress_all.423406046
Short name T575
Test name
Test status
Simulation time 1245163457 ps
CPU time 2.73 seconds
Started Aug 29 12:24:54 AM UTC 24
Finished Aug 29 12:24:58 AM UTC 24
Peak memory 229684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423406046 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.423406046
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/49.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/49.edn_stress_all_with_rand_reset.154821399
Short name T253
Test name
Test status
Simulation time 871026575 ps
CPU time 16.66 seconds
Started Aug 29 12:24:54 AM UTC 24
Finished Aug 29 12:25:12 AM UTC 24
Peak memory 229908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=154821399 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_
with_rand_reset.154821399
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/49.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/5.edn_alert_test.2541058273
Short name T76
Test name
Test status
Simulation time 139017153 ps
CPU time 0.88 seconds
Started Aug 29 12:22:56 AM UTC 24
Finished Aug 29 12:22:58 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541058273 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2541058273
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/5.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/5.edn_disable.1391763690
Short name T73
Test name
Test status
Simulation time 28693023 ps
CPU time 1.15 seconds
Started Aug 29 12:22:55 AM UTC 24
Finished Aug 29 12:22:57 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391763690 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1391763690
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/5.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/5.edn_disable_auto_req_mode.1603752314
Short name T20
Test name
Test status
Simulation time 86106788 ps
CPU time 1.25 seconds
Started Aug 29 12:22:55 AM UTC 24
Finished Aug 29 12:22:58 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603752314 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable_auto_req_mode.1603752314
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/5.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/5.edn_err.1283092211
Short name T120
Test name
Test status
Simulation time 35415890 ps
CPU time 1.2 seconds
Started Aug 29 12:22:55 AM UTC 24
Finished Aug 29 12:22:57 AM UTC 24
Peak memory 230276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283092211 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 5.edn_err.1283092211
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/5.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/5.edn_genbits.2322260654
Short name T74
Test name
Test status
Simulation time 41894278 ps
CPU time 1.49 seconds
Started Aug 29 12:22:55 AM UTC 24
Finished Aug 29 12:22:58 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322260654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_genbits.2322260654
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/5.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/5.edn_regwen.2586714874
Short name T118
Test name
Test status
Simulation time 15595281 ps
CPU time 1.4 seconds
Started Aug 29 12:22:55 AM UTC 24
Finished Aug 29 12:22:57 AM UTC 24
Peak memory 216032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586714874 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 5.edn_regwen.2586714874
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/5.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/5.edn_smoke.3507175800
Short name T116
Test name
Test status
Simulation time 53680805 ps
CPU time 1.39 seconds
Started Aug 29 12:22:55 AM UTC 24
Finished Aug 29 12:22:57 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507175800 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 5.edn_smoke.3507175800
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/5.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/5.edn_stress_all_with_rand_reset.1666721846
Short name T250
Test name
Test status
Simulation time 4166137809 ps
CPU time 91.09 seconds
Started Aug 29 12:22:55 AM UTC 24
Finished Aug 29 12:24:28 AM UTC 24
Peak memory 229720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1666721846 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_
with_rand_reset.1666721846
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/5.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/50.edn_alert.3262979442
Short name T581
Test name
Test status
Simulation time 105939220 ps
CPU time 1.5 seconds
Started Aug 29 12:24:56 AM UTC 24
Finished Aug 29 12:24:59 AM UTC 24
Peak memory 228344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262979442 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 50.edn_alert.3262979442
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/50.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/50.edn_err.1740353931
Short name T579
Test name
Test status
Simulation time 23598378 ps
CPU time 1.32 seconds
Started Aug 29 12:24:57 AM UTC 24
Finished Aug 29 12:24:59 AM UTC 24
Peak memory 228216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740353931 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 50.edn_err.1740353931
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/50.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/50.edn_genbits.2878533748
Short name T578
Test name
Test status
Simulation time 71953615 ps
CPU time 2.03 seconds
Started Aug 29 12:24:55 AM UTC 24
Finished Aug 29 12:24:58 AM UTC 24
Peak memory 231832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878533748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2878533748
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/50.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/51.edn_alert.3116970765
Short name T182
Test name
Test status
Simulation time 39235256 ps
CPU time 1.81 seconds
Started Aug 29 12:24:57 AM UTC 24
Finished Aug 29 12:25:00 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116970765 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 51.edn_alert.3116970765
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/51.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/51.edn_err.2925367971
Short name T583
Test name
Test status
Simulation time 18721911 ps
CPU time 1.75 seconds
Started Aug 29 12:24:57 AM UTC 24
Finished Aug 29 12:24:59 AM UTC 24
Peak memory 236968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925367971 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 51.edn_err.2925367971
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/51.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/51.edn_genbits.2914735706
Short name T582
Test name
Test status
Simulation time 44437783 ps
CPU time 1.62 seconds
Started Aug 29 12:24:57 AM UTC 24
Finished Aug 29 12:24:59 AM UTC 24
Peak memory 228328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914735706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2914735706
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/51.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/52.edn_alert.991631965
Short name T586
Test name
Test status
Simulation time 125572568 ps
CPU time 1.9 seconds
Started Aug 29 12:24:57 AM UTC 24
Finished Aug 29 12:25:00 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991631965 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 52.edn_alert.991631965
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/52.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/52.edn_err.3221262263
Short name T584
Test name
Test status
Simulation time 63386719 ps
CPU time 1.55 seconds
Started Aug 29 12:24:57 AM UTC 24
Finished Aug 29 12:24:59 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221262263 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 52.edn_err.3221262263
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/52.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/52.edn_genbits.3220015374
Short name T341
Test name
Test status
Simulation time 152693526 ps
CPU time 1.93 seconds
Started Aug 29 12:24:57 AM UTC 24
Finished Aug 29 12:25:00 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220015374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3220015374
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/52.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/53.edn_alert.1953563656
Short name T589
Test name
Test status
Simulation time 28071022 ps
CPU time 1.56 seconds
Started Aug 29 12:24:58 AM UTC 24
Finished Aug 29 12:25:01 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953563656 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 53.edn_alert.1953563656
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/53.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/53.edn_err.1566816723
Short name T587
Test name
Test status
Simulation time 22639461 ps
CPU time 1.3 seconds
Started Aug 29 12:24:58 AM UTC 24
Finished Aug 29 12:25:00 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566816723 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 53.edn_err.1566816723
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/53.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/53.edn_genbits.2139961032
Short name T588
Test name
Test status
Simulation time 159703047 ps
CPU time 1.44 seconds
Started Aug 29 12:24:58 AM UTC 24
Finished Aug 29 12:25:00 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139961032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 53.edn_genbits.2139961032
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/53.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/54.edn_alert.770964135
Short name T166
Test name
Test status
Simulation time 41158206 ps
CPU time 1.74 seconds
Started Aug 29 12:24:58 AM UTC 24
Finished Aug 29 12:25:01 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770964135 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 54.edn_alert.770964135
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/54.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/54.edn_err.2200019993
Short name T590
Test name
Test status
Simulation time 125642317 ps
CPU time 1.57 seconds
Started Aug 29 12:24:58 AM UTC 24
Finished Aug 29 12:25:01 AM UTC 24
Peak memory 230656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200019993 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 54.edn_err.2200019993
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/54.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/54.edn_genbits.3134920916
Short name T314
Test name
Test status
Simulation time 99982506 ps
CPU time 1.47 seconds
Started Aug 29 12:24:58 AM UTC 24
Finished Aug 29 12:25:01 AM UTC 24
Peak memory 228356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134920916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 54.edn_genbits.3134920916
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/54.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/55.edn_alert.1721557933
Short name T597
Test name
Test status
Simulation time 279762776 ps
CPU time 2.09 seconds
Started Aug 29 12:24:59 AM UTC 24
Finished Aug 29 12:25:03 AM UTC 24
Peak memory 232112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721557933 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 55.edn_alert.1721557933
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/55.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/55.edn_err.2778371302
Short name T592
Test name
Test status
Simulation time 41027744 ps
CPU time 1.18 seconds
Started Aug 29 12:25:00 AM UTC 24
Finished Aug 29 12:25:02 AM UTC 24
Peak memory 228308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778371302 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 55.edn_err.2778371302
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/55.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/55.edn_genbits.3407306541
Short name T591
Test name
Test status
Simulation time 46098742 ps
CPU time 2.2 seconds
Started Aug 29 12:24:58 AM UTC 24
Finished Aug 29 12:25:02 AM UTC 24
Peak memory 227544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407306541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3407306541
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/55.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/56.edn_alert.760703851
Short name T596
Test name
Test status
Simulation time 29896785 ps
CPU time 1.93 seconds
Started Aug 29 12:25:00 AM UTC 24
Finished Aug 29 12:25:03 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760703851 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 56.edn_alert.760703851
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/56.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/56.edn_err.1192953405
Short name T593
Test name
Test status
Simulation time 40837449 ps
CPU time 1.35 seconds
Started Aug 29 12:25:00 AM UTC 24
Finished Aug 29 12:25:02 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192953405 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 56.edn_err.1192953405
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/56.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/56.edn_genbits.2484119127
Short name T594
Test name
Test status
Simulation time 73804670 ps
CPU time 1.76 seconds
Started Aug 29 12:25:00 AM UTC 24
Finished Aug 29 12:25:02 AM UTC 24
Peak memory 230348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484119127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2484119127
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/56.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/57.edn_alert.2496446285
Short name T598
Test name
Test status
Simulation time 86057539 ps
CPU time 1.26 seconds
Started Aug 29 12:25:01 AM UTC 24
Finished Aug 29 12:25:03 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496446285 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 57.edn_alert.2496446285
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/57.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/57.edn_err.3982096096
Short name T188
Test name
Test status
Simulation time 35391538 ps
CPU time 1.31 seconds
Started Aug 29 12:25:01 AM UTC 24
Finished Aug 29 12:25:03 AM UTC 24
Peak memory 237028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982096096 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 57.edn_err.3982096096
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/57.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/57.edn_genbits.3621692769
Short name T602
Test name
Test status
Simulation time 219660733 ps
CPU time 2.12 seconds
Started Aug 29 12:25:01 AM UTC 24
Finished Aug 29 12:25:04 AM UTC 24
Peak memory 231820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621692769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3621692769
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/57.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/58.edn_alert.593229221
Short name T183
Test name
Test status
Simulation time 95507256 ps
CPU time 1.7 seconds
Started Aug 29 12:25:01 AM UTC 24
Finished Aug 29 12:25:04 AM UTC 24
Peak memory 230196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593229221 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 58.edn_alert.593229221
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/58.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/58.edn_err.3440859389
Short name T603
Test name
Test status
Simulation time 43812739 ps
CPU time 1.82 seconds
Started Aug 29 12:25:01 AM UTC 24
Finished Aug 29 12:25:04 AM UTC 24
Peak memory 242136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440859389 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 58.edn_err.3440859389
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/58.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/58.edn_genbits.683778069
Short name T599
Test name
Test status
Simulation time 61991062 ps
CPU time 1.54 seconds
Started Aug 29 12:25:01 AM UTC 24
Finished Aug 29 12:25:04 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683778069 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 58.edn_genbits.683778069
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/58.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/59.edn_alert.2909021083
Short name T216
Test name
Test status
Simulation time 22544753 ps
CPU time 1.69 seconds
Started Aug 29 12:25:01 AM UTC 24
Finished Aug 29 12:25:04 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909021083 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 59.edn_alert.2909021083
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/59.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/59.edn_err.3602030925
Short name T601
Test name
Test status
Simulation time 18951214 ps
CPU time 1.56 seconds
Started Aug 29 12:25:01 AM UTC 24
Finished Aug 29 12:25:04 AM UTC 24
Peak memory 237164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602030925 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 59.edn_err.3602030925
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/59.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/59.edn_genbits.2836722188
Short name T600
Test name
Test status
Simulation time 94211662 ps
CPU time 1.68 seconds
Started Aug 29 12:25:01 AM UTC 24
Finished Aug 29 12:25:04 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836722188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2836722188
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/59.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/6.edn_alert.2462252234
Short name T131
Test name
Test status
Simulation time 48579759 ps
CPU time 1.65 seconds
Started Aug 29 12:22:57 AM UTC 24
Finished Aug 29 12:22:59 AM UTC 24
Peak memory 230372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462252234 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 6.edn_alert.2462252234
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/6.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/6.edn_alert_test.612739501
Short name T356
Test name
Test status
Simulation time 17983124 ps
CPU time 1.04 seconds
Started Aug 29 12:22:57 AM UTC 24
Finished Aug 29 12:22:59 AM UTC 24
Peak memory 216692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612739501 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.612739501
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/6.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/6.edn_err.1294081743
Short name T62
Test name
Test status
Simulation time 20375409 ps
CPU time 1.27 seconds
Started Aug 29 12:22:57 AM UTC 24
Finished Aug 29 12:22:59 AM UTC 24
Peak memory 237328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294081743 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 6.edn_err.1294081743
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/6.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/6.edn_genbits.4149146351
Short name T44
Test name
Test status
Simulation time 70861559 ps
CPU time 1.35 seconds
Started Aug 29 12:22:57 AM UTC 24
Finished Aug 29 12:22:59 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149146351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_genbits.4149146351
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/6.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/6.edn_intr.1670095563
Short name T53
Test name
Test status
Simulation time 37525245 ps
CPU time 1.38 seconds
Started Aug 29 12:22:57 AM UTC 24
Finished Aug 29 12:22:59 AM UTC 24
Peak memory 237004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670095563 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 6.edn_intr.1670095563
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/6.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/6.edn_regwen.3302000477
Short name T77
Test name
Test status
Simulation time 93184289 ps
CPU time 1 seconds
Started Aug 29 12:22:57 AM UTC 24
Finished Aug 29 12:22:59 AM UTC 24
Peak memory 216032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302000477 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 6.edn_regwen.3302000477
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/6.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/6.edn_smoke.2691606577
Short name T78
Test name
Test status
Simulation time 17721637 ps
CPU time 1.09 seconds
Started Aug 29 12:22:56 AM UTC 24
Finished Aug 29 12:22:59 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691606577 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 6.edn_smoke.2691606577
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/6.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/6.edn_stress_all.559241009
Short name T126
Test name
Test status
Simulation time 340294177 ps
CPU time 2.24 seconds
Started Aug 29 12:22:57 AM UTC 24
Finished Aug 29 12:23:00 AM UTC 24
Peak memory 229516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559241009 -assert nopostproc +UVM_TESTNAME=edn_
stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.559241009
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/6.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/60.edn_alert.319177216
Short name T604
Test name
Test status
Simulation time 40689174 ps
CPU time 1.45 seconds
Started Aug 29 12:25:03 AM UTC 24
Finished Aug 29 12:25:05 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319177216 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 60.edn_alert.319177216
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/60.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/60.edn_err.4100185898
Short name T605
Test name
Test status
Simulation time 25262548 ps
CPU time 1.49 seconds
Started Aug 29 12:25:03 AM UTC 24
Finished Aug 29 12:25:05 AM UTC 24
Peak memory 243744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100185898 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 60.edn_err.4100185898
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/60.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/60.edn_genbits.3963041376
Short name T607
Test name
Test status
Simulation time 70892648 ps
CPU time 1.58 seconds
Started Aug 29 12:25:02 AM UTC 24
Finished Aug 29 12:25:05 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963041376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3963041376
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/60.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/61.edn_alert.3298196957
Short name T611
Test name
Test status
Simulation time 303402003 ps
CPU time 1.97 seconds
Started Aug 29 12:25:03 AM UTC 24
Finished Aug 29 12:25:06 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298196957 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 61.edn_alert.3298196957
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/61.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/61.edn_genbits.2174119240
Short name T609
Test name
Test status
Simulation time 39698677 ps
CPU time 1.96 seconds
Started Aug 29 12:25:03 AM UTC 24
Finished Aug 29 12:25:06 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174119240 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 61.edn_genbits.2174119240
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/61.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/62.edn_alert.658410711
Short name T167
Test name
Test status
Simulation time 55576370 ps
CPU time 1.47 seconds
Started Aug 29 12:25:04 AM UTC 24
Finished Aug 29 12:25:06 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658410711 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 62.edn_alert.658410711
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/62.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/62.edn_err.2667991264
Short name T612
Test name
Test status
Simulation time 36616277 ps
CPU time 1.4 seconds
Started Aug 29 12:25:04 AM UTC 24
Finished Aug 29 12:25:06 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667991264 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 62.edn_err.2667991264
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/62.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/62.edn_genbits.3553889918
Short name T623
Test name
Test status
Simulation time 312973387 ps
CPU time 4.21 seconds
Started Aug 29 12:25:04 AM UTC 24
Finished Aug 29 12:25:09 AM UTC 24
Peak memory 229708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553889918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 62.edn_genbits.3553889918
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/62.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/63.edn_alert.1825139674
Short name T168
Test name
Test status
Simulation time 40130908 ps
CPU time 1.58 seconds
Started Aug 29 12:25:04 AM UTC 24
Finished Aug 29 12:25:07 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825139674 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 63.edn_alert.1825139674
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/63.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/63.edn_err.2564609280
Short name T189
Test name
Test status
Simulation time 19915333 ps
CPU time 1.51 seconds
Started Aug 29 12:25:04 AM UTC 24
Finished Aug 29 12:25:07 AM UTC 24
Peak memory 236968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564609280 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 63.edn_err.2564609280
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/63.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/63.edn_genbits.2203030112
Short name T346
Test name
Test status
Simulation time 42035945 ps
CPU time 1.68 seconds
Started Aug 29 12:25:04 AM UTC 24
Finished Aug 29 12:25:07 AM UTC 24
Peak memory 228696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203030112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2203030112
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/63.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/64.edn_alert.4087288835
Short name T142
Test name
Test status
Simulation time 48884842 ps
CPU time 1.75 seconds
Started Aug 29 12:25:05 AM UTC 24
Finished Aug 29 12:25:08 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087288835 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 64.edn_alert.4087288835
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/64.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/64.edn_err.3175911491
Short name T617
Test name
Test status
Simulation time 78848598 ps
CPU time 1.52 seconds
Started Aug 29 12:25:05 AM UTC 24
Finished Aug 29 12:25:08 AM UTC 24
Peak memory 230388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175911491 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 64.edn_err.3175911491
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/64.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/64.edn_genbits.2140279437
Short name T335
Test name
Test status
Simulation time 165651549 ps
CPU time 2.67 seconds
Started Aug 29 12:25:04 AM UTC 24
Finished Aug 29 12:25:08 AM UTC 24
Peak memory 231580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140279437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2140279437
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/64.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/65.edn_alert.2286444187
Short name T615
Test name
Test status
Simulation time 127206062 ps
CPU time 1.3 seconds
Started Aug 29 12:25:05 AM UTC 24
Finished Aug 29 12:25:08 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286444187 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 65.edn_alert.2286444187
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/65.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/65.edn_err.15065068
Short name T616
Test name
Test status
Simulation time 34928387 ps
CPU time 1.29 seconds
Started Aug 29 12:25:05 AM UTC 24
Finished Aug 29 12:25:08 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15065068 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 65.edn_err.15065068
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/65.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/65.edn_genbits.3573350074
Short name T620
Test name
Test status
Simulation time 68867112 ps
CPU time 1.81 seconds
Started Aug 29 12:25:05 AM UTC 24
Finished Aug 29 12:25:08 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573350074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3573350074
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/65.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/66.edn_alert.3490291044
Short name T622
Test name
Test status
Simulation time 135355893 ps
CPU time 2.1 seconds
Started Aug 29 12:25:06 AM UTC 24
Finished Aug 29 12:25:09 AM UTC 24
Peak memory 230012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490291044 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 66.edn_alert.3490291044
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/66.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/66.edn_err.4244694232
Short name T206
Test name
Test status
Simulation time 22809956 ps
CPU time 1.49 seconds
Started Aug 29 12:25:06 AM UTC 24
Finished Aug 29 12:25:08 AM UTC 24
Peak memory 236968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244694232 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 66.edn_err.4244694232
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/66.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/66.edn_genbits.1964488981
Short name T618
Test name
Test status
Simulation time 72106645 ps
CPU time 1.45 seconds
Started Aug 29 12:25:05 AM UTC 24
Finished Aug 29 12:25:08 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964488981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 66.edn_genbits.1964488981
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/66.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/67.edn_alert.2564744291
Short name T301
Test name
Test status
Simulation time 46683434 ps
CPU time 1.3 seconds
Started Aug 29 12:25:07 AM UTC 24
Finished Aug 29 12:25:09 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564744291 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 67.edn_alert.2564744291
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/67.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/67.edn_err.2393379778
Short name T624
Test name
Test status
Simulation time 18931477 ps
CPU time 1.48 seconds
Started Aug 29 12:25:07 AM UTC 24
Finished Aug 29 12:25:09 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393379778 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 67.edn_err.2393379778
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/67.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/67.edn_genbits.3705932118
Short name T619
Test name
Test status
Simulation time 79669030 ps
CPU time 1.4 seconds
Started Aug 29 12:25:06 AM UTC 24
Finished Aug 29 12:25:08 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705932118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3705932118
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/67.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/68.edn_alert.457514735
Short name T626
Test name
Test status
Simulation time 26688941 ps
CPU time 1.37 seconds
Started Aug 29 12:25:07 AM UTC 24
Finished Aug 29 12:25:09 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457514735 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 68.edn_alert.457514735
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/68.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/68.edn_err.2431459872
Short name T628
Test name
Test status
Simulation time 20808082 ps
CPU time 1.42 seconds
Started Aug 29 12:25:07 AM UTC 24
Finished Aug 29 12:25:09 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431459872 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 68.edn_err.2431459872
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/68.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/68.edn_genbits.3787430536
Short name T627
Test name
Test status
Simulation time 24445719 ps
CPU time 1.57 seconds
Started Aug 29 12:25:07 AM UTC 24
Finished Aug 29 12:25:09 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787430536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 68.edn_genbits.3787430536
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/68.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/69.edn_alert.2734820506
Short name T199
Test name
Test status
Simulation time 52304027 ps
CPU time 1.59 seconds
Started Aug 29 12:25:07 AM UTC 24
Finished Aug 29 12:25:10 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734820506 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 69.edn_alert.2734820506
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/69.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/69.edn_err.1917277271
Short name T625
Test name
Test status
Simulation time 19726089 ps
CPU time 1.22 seconds
Started Aug 29 12:25:07 AM UTC 24
Finished Aug 29 12:25:09 AM UTC 24
Peak memory 228308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917277271 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 69.edn_err.1917277271
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/69.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/69.edn_genbits.360046217
Short name T629
Test name
Test status
Simulation time 42587800 ps
CPU time 2.01 seconds
Started Aug 29 12:25:07 AM UTC 24
Finished Aug 29 12:25:10 AM UTC 24
Peak memory 229460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360046217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 69.edn_genbits.360046217
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/69.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/7.edn_alert_test.1920544659
Short name T354
Test name
Test status
Simulation time 23004210 ps
CPU time 1.08 seconds
Started Aug 29 12:22:59 AM UTC 24
Finished Aug 29 12:23:01 AM UTC 24
Peak memory 217168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920544659 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1920544659
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/7.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/7.edn_err.2018631334
Short name T57
Test name
Test status
Simulation time 21775341 ps
CPU time 1.31 seconds
Started Aug 29 12:22:59 AM UTC 24
Finished Aug 29 12:23:01 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018631334 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 7.edn_err.2018631334
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/7.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/7.edn_intr.1560707862
Short name T32
Test name
Test status
Simulation time 21829957 ps
CPU time 1.2 seconds
Started Aug 29 12:22:59 AM UTC 24
Finished Aug 29 12:23:01 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560707862 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 7.edn_intr.1560707862
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/7.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/7.edn_regwen.3420164820
Short name T324
Test name
Test status
Simulation time 18909380 ps
CPU time 1.09 seconds
Started Aug 29 12:22:59 AM UTC 24
Finished Aug 29 12:23:01 AM UTC 24
Peak memory 216032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420164820 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 7.edn_regwen.3420164820
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/7.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/7.edn_smoke.2167294125
Short name T357
Test name
Test status
Simulation time 22503557 ps
CPU time 1.05 seconds
Started Aug 29 12:22:57 AM UTC 24
Finished Aug 29 12:22:59 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167294125 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 7.edn_smoke.2167294125
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/7.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/7.edn_stress_all.1814241574
Short name T122
Test name
Test status
Simulation time 333202220 ps
CPU time 6.44 seconds
Started Aug 29 12:22:59 AM UTC 24
Finished Aug 29 12:23:06 AM UTC 24
Peak memory 229528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814241574 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1814241574
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/7.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/7.edn_stress_all_with_rand_reset.3096204643
Short name T240
Test name
Test status
Simulation time 6742463748 ps
CPU time 37.61 seconds
Started Aug 29 12:22:59 AM UTC 24
Finished Aug 29 12:23:38 AM UTC 24
Peak memory 229792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3096204643 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_
with_rand_reset.3096204643
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/7.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/70.edn_alert.710464176
Short name T634
Test name
Test status
Simulation time 42034627 ps
CPU time 1.65 seconds
Started Aug 29 12:25:09 AM UTC 24
Finished Aug 29 12:25:11 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710464176 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 70.edn_alert.710464176
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/70.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/70.edn_err.3948507003
Short name T231
Test name
Test status
Simulation time 75602904 ps
CPU time 1.09 seconds
Started Aug 29 12:25:09 AM UTC 24
Finished Aug 29 12:25:11 AM UTC 24
Peak memory 246152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948507003 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 70.edn_err.3948507003
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/70.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/70.edn_genbits.4206921918
Short name T638
Test name
Test status
Simulation time 37119375 ps
CPU time 1.78 seconds
Started Aug 29 12:25:09 AM UTC 24
Finished Aug 29 12:25:12 AM UTC 24
Peak memory 228636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206921918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 70.edn_genbits.4206921918
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/70.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/71.edn_alert.1403922730
Short name T639
Test name
Test status
Simulation time 50544400 ps
CPU time 1.74 seconds
Started Aug 29 12:25:09 AM UTC 24
Finished Aug 29 12:25:12 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403922730 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 71.edn_alert.1403922730
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/71.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/71.edn_err.926350985
Short name T631
Test name
Test status
Simulation time 34036817 ps
CPU time 1.24 seconds
Started Aug 29 12:25:09 AM UTC 24
Finished Aug 29 12:25:11 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926350985 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 71.edn_err.926350985
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/71.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/71.edn_genbits.1294439953
Short name T632
Test name
Test status
Simulation time 45956691 ps
CPU time 1.55 seconds
Started Aug 29 12:25:09 AM UTC 24
Finished Aug 29 12:25:11 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294439953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 71.edn_genbits.1294439953
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/71.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/72.edn_alert.867517505
Short name T636
Test name
Test status
Simulation time 66429701 ps
CPU time 1.37 seconds
Started Aug 29 12:25:09 AM UTC 24
Finished Aug 29 12:25:11 AM UTC 24
Peak memory 232520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867517505 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 72.edn_alert.867517505
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/72.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/72.edn_err.3794627039
Short name T197
Test name
Test status
Simulation time 30281143 ps
CPU time 1.22 seconds
Started Aug 29 12:25:09 AM UTC 24
Finished Aug 29 12:25:11 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794627039 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 72.edn_err.3794627039
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/72.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/72.edn_genbits.2246081187
Short name T630
Test name
Test status
Simulation time 40661457 ps
CPU time 1.24 seconds
Started Aug 29 12:25:09 AM UTC 24
Finished Aug 29 12:25:11 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246081187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2246081187
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/72.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/73.edn_alert.2045494317
Short name T633
Test name
Test status
Simulation time 85237810 ps
CPU time 1.29 seconds
Started Aug 29 12:25:09 AM UTC 24
Finished Aug 29 12:25:11 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045494317 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 73.edn_alert.2045494317
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/73.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/73.edn_err.3602949642
Short name T635
Test name
Test status
Simulation time 35973306 ps
CPU time 1.1 seconds
Started Aug 29 12:25:09 AM UTC 24
Finished Aug 29 12:25:11 AM UTC 24
Peak memory 230396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602949642 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 73.edn_err.3602949642
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/73.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/73.edn_genbits.546507904
Short name T640
Test name
Test status
Simulation time 93622353 ps
CPU time 1.7 seconds
Started Aug 29 12:25:09 AM UTC 24
Finished Aug 29 12:25:12 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546507904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 73.edn_genbits.546507904
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/73.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/74.edn_alert.164884243
Short name T637
Test name
Test status
Simulation time 45945362 ps
CPU time 1.19 seconds
Started Aug 29 12:25:09 AM UTC 24
Finished Aug 29 12:25:11 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164884243 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 74.edn_alert.164884243
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/74.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/74.edn_err.3899522808
Short name T149
Test name
Test status
Simulation time 21772057 ps
CPU time 1.27 seconds
Started Aug 29 12:25:09 AM UTC 24
Finished Aug 29 12:25:12 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899522808 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 74.edn_err.3899522808
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/74.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/74.edn_genbits.1240711733
Short name T643
Test name
Test status
Simulation time 123548421 ps
CPU time 2.82 seconds
Started Aug 29 12:25:09 AM UTC 24
Finished Aug 29 12:25:13 AM UTC 24
Peak memory 229532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240711733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 74.edn_genbits.1240711733
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/74.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/75.edn_alert.380589529
Short name T644
Test name
Test status
Simulation time 201935655 ps
CPU time 1.59 seconds
Started Aug 29 12:25:10 AM UTC 24
Finished Aug 29 12:25:13 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380589529 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 75.edn_alert.380589529
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/75.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/75.edn_err.2210770904
Short name T210
Test name
Test status
Simulation time 54812150 ps
CPU time 1.29 seconds
Started Aug 29 12:25:10 AM UTC 24
Finished Aug 29 12:25:13 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210770904 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 75.edn_err.2210770904
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/75.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/75.edn_genbits.1101659638
Short name T641
Test name
Test status
Simulation time 63002213 ps
CPU time 1.14 seconds
Started Aug 29 12:25:10 AM UTC 24
Finished Aug 29 12:25:13 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101659638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 75.edn_genbits.1101659638
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/75.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/76.edn_alert.1582350336
Short name T642
Test name
Test status
Simulation time 21815091 ps
CPU time 1.31 seconds
Started Aug 29 12:25:11 AM UTC 24
Finished Aug 29 12:25:13 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582350336 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 76.edn_alert.1582350336
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/76.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/76.edn_err.3077518492
Short name T647
Test name
Test status
Simulation time 71340862 ps
CPU time 1.7 seconds
Started Aug 29 12:25:11 AM UTC 24
Finished Aug 29 12:25:14 AM UTC 24
Peak memory 242136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077518492 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 76.edn_err.3077518492
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/76.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/76.edn_genbits.974500858
Short name T648
Test name
Test status
Simulation time 176115928 ps
CPU time 1.85 seconds
Started Aug 29 12:25:10 AM UTC 24
Finished Aug 29 12:25:14 AM UTC 24
Peak memory 230384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974500858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 76.edn_genbits.974500858
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/76.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/77.edn_alert.1707672990
Short name T646
Test name
Test status
Simulation time 28144367 ps
CPU time 1.49 seconds
Started Aug 29 12:25:11 AM UTC 24
Finished Aug 29 12:25:13 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707672990 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 77.edn_alert.1707672990
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/77.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/77.edn_err.2717881413
Short name T169
Test name
Test status
Simulation time 19067760 ps
CPU time 1.33 seconds
Started Aug 29 12:25:11 AM UTC 24
Finished Aug 29 12:25:13 AM UTC 24
Peak memory 228308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717881413 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 77.edn_err.2717881413
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/77.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/77.edn_genbits.3003309947
Short name T645
Test name
Test status
Simulation time 99069845 ps
CPU time 1.5 seconds
Started Aug 29 12:25:11 AM UTC 24
Finished Aug 29 12:25:13 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003309947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3003309947
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/77.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/78.edn_alert.1729288351
Short name T621
Test name
Test status
Simulation time 76039068 ps
CPU time 1.6 seconds
Started Aug 29 12:25:12 AM UTC 24
Finished Aug 29 12:25:15 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729288351 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 78.edn_alert.1729288351
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/78.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/78.edn_err.3100702477
Short name T577
Test name
Test status
Simulation time 26952615 ps
CPU time 1.13 seconds
Started Aug 29 12:25:12 AM UTC 24
Finished Aug 29 12:25:14 AM UTC 24
Peak memory 246152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100702477 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 78.edn_err.3100702477
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/78.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/78.edn_genbits.28999405
Short name T650
Test name
Test status
Simulation time 32491026 ps
CPU time 1.69 seconds
Started Aug 29 12:25:12 AM UTC 24
Finished Aug 29 12:25:15 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28999405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn
_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 78.edn_genbits.28999405
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/78.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/79.edn_err.1563608043
Short name T610
Test name
Test status
Simulation time 20546099 ps
CPU time 1.43 seconds
Started Aug 29 12:25:12 AM UTC 24
Finished Aug 29 12:25:15 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563608043 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 79.edn_err.1563608043
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/79.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/79.edn_genbits.3523838105
Short name T652
Test name
Test status
Simulation time 106612892 ps
CPU time 1.69 seconds
Started Aug 29 12:25:12 AM UTC 24
Finished Aug 29 12:25:15 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523838105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3523838105
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/79.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/8.edn_alert_test.167263080
Short name T359
Test name
Test status
Simulation time 37964652 ps
CPU time 1.38 seconds
Started Aug 29 12:23:01 AM UTC 24
Finished Aug 29 12:23:03 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167263080 -assert nopostproc +UVM_TESTNAME=edn_bas
e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.167263080
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/8.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/8.edn_disable.2950346380
Short name T46
Test name
Test status
Simulation time 36661797 ps
CPU time 1.04 seconds
Started Aug 29 12:23:00 AM UTC 24
Finished Aug 29 12:23:03 AM UTC 24
Peak memory 216132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950346380 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2950346380
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/8.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/8.edn_disable_auto_req_mode.3034989041
Short name T102
Test name
Test status
Simulation time 64931509 ps
CPU time 1.46 seconds
Started Aug 29 12:23:01 AM UTC 24
Finished Aug 29 12:23:03 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034989041 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable_auto_req_mode.3034989041
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/8.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/8.edn_err.3372558385
Short name T65
Test name
Test status
Simulation time 22887831 ps
CPU time 1.24 seconds
Started Aug 29 12:23:00 AM UTC 24
Finished Aug 29 12:23:03 AM UTC 24
Peak memory 237364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372558385 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 8.edn_err.3372558385
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/8.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/8.edn_genbits.526314943
Short name T134
Test name
Test status
Simulation time 39334748 ps
CPU time 1.13 seconds
Started Aug 29 12:22:59 AM UTC 24
Finished Aug 29 12:23:01 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526314943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.edn_genbits.526314943
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/8.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/8.edn_intr.3240166856
Short name T121
Test name
Test status
Simulation time 22508063 ps
CPU time 1.1 seconds
Started Aug 29 12:22:59 AM UTC 24
Finished Aug 29 12:23:01 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240166856 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 8.edn_intr.3240166856
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/8.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/8.edn_regwen.210220551
Short name T130
Test name
Test status
Simulation time 53007868 ps
CPU time 1.05 seconds
Started Aug 29 12:22:59 AM UTC 24
Finished Aug 29 12:23:01 AM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210220551 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 8.edn_regwen.210220551
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/8.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/8.edn_smoke.2055930850
Short name T355
Test name
Test status
Simulation time 50217368 ps
CPU time 1.15 seconds
Started Aug 29 12:22:59 AM UTC 24
Finished Aug 29 12:23:01 AM UTC 24
Peak memory 226224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055930850 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 8.edn_smoke.2055930850
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/8.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/80.edn_alert.2472123245
Short name T651
Test name
Test status
Simulation time 39838458 ps
CPU time 1.45 seconds
Started Aug 29 12:25:12 AM UTC 24
Finished Aug 29 12:25:15 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472123245 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 80.edn_alert.2472123245
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/80.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/80.edn_err.3851600992
Short name T202
Test name
Test status
Simulation time 27002766 ps
CPU time 0.87 seconds
Started Aug 29 12:25:12 AM UTC 24
Finished Aug 29 12:25:14 AM UTC 24
Peak memory 228608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851600992 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 80.edn_err.3851600992
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/80.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/80.edn_genbits.4003507970
Short name T653
Test name
Test status
Simulation time 71407341 ps
CPU time 1.96 seconds
Started Aug 29 12:25:12 AM UTC 24
Finished Aug 29 12:25:15 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003507970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 80.edn_genbits.4003507970
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/80.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/81.edn_alert.2773038872
Short name T649
Test name
Test status
Simulation time 84808716 ps
CPU time 1.28 seconds
Started Aug 29 12:25:12 AM UTC 24
Finished Aug 29 12:25:15 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773038872 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 81.edn_alert.2773038872
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/81.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/81.edn_err.938114769
Short name T655
Test name
Test status
Simulation time 58915359 ps
CPU time 1.31 seconds
Started Aug 29 12:25:13 AM UTC 24
Finished Aug 29 12:25:16 AM UTC 24
Peak memory 236960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938114769 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 81.edn_err.938114769
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/81.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/81.edn_genbits.3419859781
Short name T348
Test name
Test status
Simulation time 70142835 ps
CPU time 1.72 seconds
Started Aug 29 12:25:12 AM UTC 24
Finished Aug 29 12:25:15 AM UTC 24
Peak memory 230320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419859781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3419859781
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/81.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/82.edn_alert.3116860116
Short name T212
Test name
Test status
Simulation time 164460908 ps
CPU time 1.59 seconds
Started Aug 29 12:25:14 AM UTC 24
Finished Aug 29 12:25:16 AM UTC 24
Peak memory 226356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116860116 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 82.edn_alert.3116860116
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/82.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/82.edn_err.153736035
Short name T656
Test name
Test status
Simulation time 19214671 ps
CPU time 1.49 seconds
Started Aug 29 12:25:14 AM UTC 24
Finished Aug 29 12:25:16 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153736035 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 82.edn_err.153736035
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/82.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/82.edn_genbits.3204110336
Short name T659
Test name
Test status
Simulation time 55583637 ps
CPU time 1.93 seconds
Started Aug 29 12:25:13 AM UTC 24
Finished Aug 29 12:25:16 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204110336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3204110336
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/82.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/83.edn_alert.2461722728
Short name T311
Test name
Test status
Simulation time 181685242 ps
CPU time 1.15 seconds
Started Aug 29 12:25:14 AM UTC 24
Finished Aug 29 12:25:16 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461722728 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 83.edn_alert.2461722728
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/83.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/83.edn_err.242806603
Short name T654
Test name
Test status
Simulation time 32595059 ps
CPU time 0.93 seconds
Started Aug 29 12:25:14 AM UTC 24
Finished Aug 29 12:25:16 AM UTC 24
Peak memory 230408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242806603 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 83.edn_err.242806603
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/83.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/83.edn_genbits.2325758115
Short name T657
Test name
Test status
Simulation time 45732432 ps
CPU time 1.6 seconds
Started Aug 29 12:25:14 AM UTC 24
Finished Aug 29 12:25:16 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325758115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 83.edn_genbits.2325758115
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/83.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/84.edn_alert.1214632812
Short name T660
Test name
Test status
Simulation time 127779782 ps
CPU time 1.3 seconds
Started Aug 29 12:25:15 AM UTC 24
Finished Aug 29 12:25:17 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214632812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 84.edn_alert.1214632812
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/84.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/84.edn_err.509144433
Short name T661
Test name
Test status
Simulation time 24558822 ps
CPU time 1.44 seconds
Started Aug 29 12:25:15 AM UTC 24
Finished Aug 29 12:25:18 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509144433 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 84.edn_err.509144433
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/84.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/84.edn_genbits.2003999003
Short name T658
Test name
Test status
Simulation time 42910585 ps
CPU time 1.64 seconds
Started Aug 29 12:25:14 AM UTC 24
Finished Aug 29 12:25:16 AM UTC 24
Peak memory 230608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003999003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2003999003
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/84.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/85.edn_alert.794774366
Short name T200
Test name
Test status
Simulation time 46372665 ps
CPU time 1.21 seconds
Started Aug 29 12:25:15 AM UTC 24
Finished Aug 29 12:25:17 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794774366 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 85.edn_alert.794774366
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/85.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/85.edn_err.3341773025
Short name T662
Test name
Test status
Simulation time 22182137 ps
CPU time 1.33 seconds
Started Aug 29 12:25:15 AM UTC 24
Finished Aug 29 12:25:18 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341773025 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 85.edn_err.3341773025
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/85.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/85.edn_genbits.3335513329
Short name T663
Test name
Test status
Simulation time 72309014 ps
CPU time 1.44 seconds
Started Aug 29 12:25:15 AM UTC 24
Finished Aug 29 12:25:18 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335513329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3335513329
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/85.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/86.edn_alert.1307352531
Short name T669
Test name
Test status
Simulation time 102868648 ps
CPU time 1.74 seconds
Started Aug 29 12:25:15 AM UTC 24
Finished Aug 29 12:25:18 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307352531 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 86.edn_alert.1307352531
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/86.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/86.edn_err.3828543434
Short name T145
Test name
Test status
Simulation time 27199856 ps
CPU time 1.38 seconds
Started Aug 29 12:25:15 AM UTC 24
Finished Aug 29 12:25:18 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828543434 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 86.edn_err.3828543434
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/86.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/86.edn_genbits.419602148
Short name T670
Test name
Test status
Simulation time 51686429 ps
CPU time 1.79 seconds
Started Aug 29 12:25:15 AM UTC 24
Finished Aug 29 12:25:18 AM UTC 24
Peak memory 228548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419602148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 86.edn_genbits.419602148
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/86.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/87.edn_alert.2577000895
Short name T666
Test name
Test status
Simulation time 22891853 ps
CPU time 1.46 seconds
Started Aug 29 12:25:15 AM UTC 24
Finished Aug 29 12:25:18 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577000895 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 87.edn_alert.2577000895
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/87.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/87.edn_err.473125797
Short name T664
Test name
Test status
Simulation time 33917032 ps
CPU time 1.19 seconds
Started Aug 29 12:25:16 AM UTC 24
Finished Aug 29 12:25:18 AM UTC 24
Peak memory 228660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473125797 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 87.edn_err.473125797
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/87.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/87.edn_genbits.1682504258
Short name T665
Test name
Test status
Simulation time 85711054 ps
CPU time 1.24 seconds
Started Aug 29 12:25:15 AM UTC 24
Finished Aug 29 12:25:18 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682504258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 87.edn_genbits.1682504258
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/87.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/88.edn_alert.2412668348
Short name T320
Test name
Test status
Simulation time 120730542 ps
CPU time 1.85 seconds
Started Aug 29 12:25:16 AM UTC 24
Finished Aug 29 12:25:19 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412668348 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 88.edn_alert.2412668348
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/88.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/88.edn_err.4008211498
Short name T161
Test name
Test status
Simulation time 26226147 ps
CPU time 1.4 seconds
Started Aug 29 12:25:16 AM UTC 24
Finished Aug 29 12:25:18 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008211498 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 88.edn_err.4008211498
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/88.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/88.edn_genbits.447261701
Short name T667
Test name
Test status
Simulation time 38709087 ps
CPU time 1.42 seconds
Started Aug 29 12:25:16 AM UTC 24
Finished Aug 29 12:25:18 AM UTC 24
Peak memory 230412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447261701 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 88.edn_genbits.447261701
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/88.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/89.edn_alert.2037080773
Short name T668
Test name
Test status
Simulation time 26206009 ps
CPU time 1.34 seconds
Started Aug 29 12:25:16 AM UTC 24
Finished Aug 29 12:25:18 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037080773 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 89.edn_alert.2037080773
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/89.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/89.edn_err.1908366054
Short name T671
Test name
Test status
Simulation time 25319403 ps
CPU time 1.38 seconds
Started Aug 29 12:25:16 AM UTC 24
Finished Aug 29 12:25:18 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908366054 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 89.edn_err.1908366054
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/89.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/89.edn_genbits.2684233690
Short name T672
Test name
Test status
Simulation time 33834685 ps
CPU time 1.78 seconds
Started Aug 29 12:25:16 AM UTC 24
Finished Aug 29 12:25:19 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684233690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 89.edn_genbits.2684233690
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/89.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/9.edn_alert.3206715230
Short name T133
Test name
Test status
Simulation time 49319208 ps
CPU time 1.3 seconds
Started Aug 29 12:23:01 AM UTC 24
Finished Aug 29 12:23:03 AM UTC 24
Peak memory 230476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206715230 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 9.edn_alert.3206715230
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/9.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/9.edn_alert_test.1165370783
Short name T361
Test name
Test status
Simulation time 47676869 ps
CPU time 1.25 seconds
Started Aug 29 12:23:02 AM UTC 24
Finished Aug 29 12:23:04 AM UTC 24
Peak memory 226532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165370783 -assert nopostproc +UVM_TESTNAME=edn_ba
se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1165370783
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/9.edn_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/9.edn_disable.3096093060
Short name T103
Test name
Test status
Simulation time 50173112 ps
CPU time 0.95 seconds
Started Aug 29 12:23:02 AM UTC 24
Finished Aug 29 12:23:04 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096093060 -assert nopostproc +UVM_TESTNAME=edn_dis
able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/e
dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.3096093060
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/9.edn_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/9.edn_disable_auto_req_mode.3197408423
Short name T85
Test name
Test status
Simulation time 112009329 ps
CPU time 1.13 seconds
Started Aug 29 12:23:02 AM UTC 24
Finished Aug 29 12:23:04 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197408423 -assert nopostproc +UVM_TESTNAME=edn_dis
able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable_auto_req_mode.3197408423
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/9.edn_disable_auto_req_mode/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/9.edn_err.1573830049
Short name T190
Test name
Test status
Simulation time 20642327 ps
CPU time 1.38 seconds
Started Aug 29 12:23:02 AM UTC 24
Finished Aug 29 12:23:05 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573830049 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 9.edn_err.1573830049
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/9.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/9.edn_genbits.4001298363
Short name T310
Test name
Test status
Simulation time 62415501 ps
CPU time 1.51 seconds
Started Aug 29 12:23:01 AM UTC 24
Finished Aug 29 12:23:03 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001298363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_genbits.4001298363
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/9.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/9.edn_intr.1097598041
Short name T35
Test name
Test status
Simulation time 32509600 ps
CPU time 1.08 seconds
Started Aug 29 12:23:01 AM UTC 24
Finished Aug 29 12:23:03 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097598041 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_
intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 9.edn_intr.1097598041
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/9.edn_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/9.edn_regwen.3290653690
Short name T127
Test name
Test status
Simulation time 52610976 ps
CPU time 1.42 seconds
Started Aug 29 12:23:01 AM UTC 24
Finished Aug 29 12:23:03 AM UTC 24
Peak memory 216032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290653690 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed
n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 9.edn_regwen.3290653690
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/9.edn_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/9.edn_smoke.866699534
Short name T358
Test name
Test status
Simulation time 17496027 ps
CPU time 1.01 seconds
Started Aug 29 12:23:01 AM UTC 24
Finished Aug 29 12:23:03 AM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866699534 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 9.edn_smoke.866699534
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/9.edn_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/9.edn_stress_all.1936746752
Short name T360
Test name
Test status
Simulation time 34199222 ps
CPU time 1.56 seconds
Started Aug 29 12:23:01 AM UTC 24
Finished Aug 29 12:23:03 AM UTC 24
Peak memory 226676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936746752 -assert nopostproc +UVM_TESTNAME=edn
_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1936746752
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/9.edn_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/9.edn_stress_all_with_rand_reset.4291558642
Short name T238
Test name
Test status
Simulation time 2493274602 ps
CPU time 30.45 seconds
Started Aug 29 12:23:01 AM UTC 24
Finished Aug 29 12:23:33 AM UTC 24
Peak memory 231912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed
n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=4291558642 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_
with_rand_reset.4291558642
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/9.edn_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/90.edn_alert.3322404556
Short name T159
Test name
Test status
Simulation time 60046320 ps
CPU time 1.81 seconds
Started Aug 29 12:25:17 AM UTC 24
Finished Aug 29 12:25:20 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322404556 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 90.edn_alert.3322404556
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/90.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/90.edn_err.2837253155
Short name T146
Test name
Test status
Simulation time 153423383 ps
CPU time 1.23 seconds
Started Aug 29 12:25:17 AM UTC 24
Finished Aug 29 12:25:19 AM UTC 24
Peak memory 244224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837253155 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 90.edn_err.2837253155
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/90.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/90.edn_genbits.3339139260
Short name T679
Test name
Test status
Simulation time 93099717 ps
CPU time 1.96 seconds
Started Aug 29 12:25:17 AM UTC 24
Finished Aug 29 12:25:20 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339139260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3339139260
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/90.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/91.edn_alert.2858596630
Short name T673
Test name
Test status
Simulation time 26667433 ps
CPU time 1.34 seconds
Started Aug 29 12:25:17 AM UTC 24
Finished Aug 29 12:25:19 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858596630 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 91.edn_alert.2858596630
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/91.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/91.edn_err.208579303
Short name T674
Test name
Test status
Simulation time 38888940 ps
CPU time 1.26 seconds
Started Aug 29 12:25:17 AM UTC 24
Finished Aug 29 12:25:19 AM UTC 24
Peak memory 228360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208579303 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 91.edn_err.208579303
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/91.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/91.edn_genbits.1871035483
Short name T680
Test name
Test status
Simulation time 58132800 ps
CPU time 1.85 seconds
Started Aug 29 12:25:17 AM UTC 24
Finished Aug 29 12:25:20 AM UTC 24
Peak memory 230608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871035483 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 91.edn_genbits.1871035483
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/91.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/92.edn_alert.331401294
Short name T678
Test name
Test status
Simulation time 39466786 ps
CPU time 1.57 seconds
Started Aug 29 12:25:17 AM UTC 24
Finished Aug 29 12:25:20 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331401294 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 92.edn_alert.331401294
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/92.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/92.edn_err.1804555853
Short name T676
Test name
Test status
Simulation time 19320241 ps
CPU time 1.38 seconds
Started Aug 29 12:25:17 AM UTC 24
Finished Aug 29 12:25:20 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804555853 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 92.edn_err.1804555853
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/92.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/92.edn_genbits.415072339
Short name T677
Test name
Test status
Simulation time 48403158 ps
CPU time 1.48 seconds
Started Aug 29 12:25:17 AM UTC 24
Finished Aug 29 12:25:20 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415072339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 92.edn_genbits.415072339
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/92.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/93.edn_alert.2309249144
Short name T213
Test name
Test status
Simulation time 83396052 ps
CPU time 1.34 seconds
Started Aug 29 12:25:19 AM UTC 24
Finished Aug 29 12:25:21 AM UTC 24
Peak memory 230288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309249144 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 93.edn_alert.2309249144
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/93.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/93.edn_err.3089401061
Short name T180
Test name
Test status
Simulation time 63364824 ps
CPU time 1.68 seconds
Started Aug 29 12:25:19 AM UTC 24
Finished Aug 29 12:25:21 AM UTC 24
Peak memory 243804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089401061 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 93.edn_err.3089401061
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/93.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/93.edn_genbits.2191420980
Short name T675
Test name
Test status
Simulation time 69093208 ps
CPU time 1.25 seconds
Started Aug 29 12:25:17 AM UTC 24
Finished Aug 29 12:25:20 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191420980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2191420980
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/93.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/94.edn_alert.4005685268
Short name T682
Test name
Test status
Simulation time 95843562 ps
CPU time 1.24 seconds
Started Aug 29 12:25:19 AM UTC 24
Finished Aug 29 12:25:21 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005685268 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 94.edn_alert.4005685268
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/94.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/94.edn_err.2335187877
Short name T686
Test name
Test status
Simulation time 44795328 ps
CPU time 1.82 seconds
Started Aug 29 12:25:19 AM UTC 24
Finished Aug 29 12:25:22 AM UTC 24
Peak memory 242196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335187877 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 94.edn_err.2335187877
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/94.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/94.edn_genbits.4273725260
Short name T681
Test name
Test status
Simulation time 102432947 ps
CPU time 1.18 seconds
Started Aug 29 12:25:19 AM UTC 24
Finished Aug 29 12:25:21 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273725260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 94.edn_genbits.4273725260
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/94.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/95.edn_alert.1809948427
Short name T312
Test name
Test status
Simulation time 101337690 ps
CPU time 1.61 seconds
Started Aug 29 12:25:19 AM UTC 24
Finished Aug 29 12:25:21 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809948427 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 95.edn_alert.1809948427
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/95.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/95.edn_err.2391297707
Short name T683
Test name
Test status
Simulation time 19872052 ps
CPU time 1.24 seconds
Started Aug 29 12:25:19 AM UTC 24
Finished Aug 29 12:25:21 AM UTC 24
Peak memory 228308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391297707 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 95.edn_err.2391297707
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/95.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/95.edn_genbits.3951858029
Short name T684
Test name
Test status
Simulation time 33927185 ps
CPU time 1.44 seconds
Started Aug 29 12:25:19 AM UTC 24
Finished Aug 29 12:25:21 AM UTC 24
Peak memory 226296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951858029 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 95.edn_genbits.3951858029
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/95.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/96.edn_alert.1751569054
Short name T688
Test name
Test status
Simulation time 43850506 ps
CPU time 1.68 seconds
Started Aug 29 12:25:19 AM UTC 24
Finished Aug 29 12:25:22 AM UTC 24
Peak memory 228424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751569054 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 96.edn_alert.1751569054
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/96.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/96.edn_err.4185672324
Short name T689
Test name
Test status
Simulation time 25662152 ps
CPU time 1.69 seconds
Started Aug 29 12:25:19 AM UTC 24
Finished Aug 29 12:25:22 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185672324 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 96.edn_err.4185672324
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/96.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/96.edn_genbits.1841543545
Short name T342
Test name
Test status
Simulation time 45026996 ps
CPU time 1.63 seconds
Started Aug 29 12:25:19 AM UTC 24
Finished Aug 29 12:25:22 AM UTC 24
Peak memory 230684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841543545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 96.edn_genbits.1841543545
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/96.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/97.edn_alert.3748165011
Short name T685
Test name
Test status
Simulation time 53970394 ps
CPU time 1.32 seconds
Started Aug 29 12:25:19 AM UTC 24
Finished Aug 29 12:25:21 AM UTC 24
Peak memory 230204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748165011 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 97.edn_alert.3748165011
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/97.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/97.edn_err.256358402
Short name T230
Test name
Test status
Simulation time 35864069 ps
CPU time 1.36 seconds
Started Aug 29 12:25:19 AM UTC 24
Finished Aug 29 12:25:22 AM UTC 24
Peak memory 241936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256358402 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 97.edn_err.256358402
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/97.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/97.edn_genbits.1152315281
Short name T687
Test name
Test status
Simulation time 78669322 ps
CPU time 1.53 seconds
Started Aug 29 12:25:19 AM UTC 24
Finished Aug 29 12:25:22 AM UTC 24
Peak memory 226316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152315281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 97.edn_genbits.1152315281
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/97.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/98.edn_alert.1767253754
Short name T691
Test name
Test status
Simulation time 25156504 ps
CPU time 1.35 seconds
Started Aug 29 12:25:20 AM UTC 24
Finished Aug 29 12:25:23 AM UTC 24
Peak memory 230472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767253754 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn
_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 98.edn_alert.1767253754
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/98.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/98.edn_err.4028905768
Short name T150
Test name
Test status
Simulation time 45416366 ps
CPU time 1.11 seconds
Started Aug 29 12:25:20 AM UTC 24
Finished Aug 29 12:25:23 AM UTC 24
Peak memory 230416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028905768 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 98.edn_err.4028905768
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/98.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/98.edn_genbits.2354887899
Short name T690
Test name
Test status
Simulation time 34977546 ps
CPU time 1.77 seconds
Started Aug 29 12:25:19 AM UTC 24
Finished Aug 29 12:25:22 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354887899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e
dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2354887899
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/98.edn_genbits/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/99.edn_alert.212990405
Short name T163
Test name
Test status
Simulation time 225778595 ps
CPU time 1.65 seconds
Started Aug 29 12:25:20 AM UTC 24
Finished Aug 29 12:25:23 AM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212990405 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_
alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 99.edn_alert.212990405
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/99.edn_alert/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/99.edn_err.1460060574
Short name T692
Test name
Test status
Simulation time 32602207 ps
CPU time 1.31 seconds
Started Aug 29 12:25:21 AM UTC 24
Finished Aug 29 12:25:23 AM UTC 24
Peak memory 228368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460060574 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e
rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 99.edn_err.1460060574
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/99.edn_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/default/99.edn_genbits.200933824
Short name T698
Test name
Test status
Simulation time 45066198 ps
CPU time 1.91 seconds
Started Aug 29 12:25:20 AM UTC 24
Finished Aug 29 12:25:23 AM UTC 24
Peak memory 228364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200933824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed
n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 99.edn_genbits.200933824
Directory /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/99.edn_genbits/latest
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