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 LINE       302
 EXPRESSION (csrng_cmd_i.csrng_rsp_ack && sw_cmd_mode)
             ------------1------------    -----2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT23,T10,T17
11CoveredT1,T2,T3

 LINE       307
 EXPRESSION (sfifo_rescmd_int_err || sfifo_gencmd_int_err || edn_cntr_err_sum || edn_main_sm_err_sum || edn_ack_sm_err_sum)
             ----------1---------    ----------2---------    --------3-------    ---------4---------    ---------5--------
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001CoveredT5,T16,T71
00010CoveredT33,T16,T18
00100CoveredT4,T7,T16
01000CoveredT16,T18,T19
10000CoveredT16,T18,T19

 LINE       314
 EXPRESSION ((edn_enable_fo[FatalErr] && (sfifo_rescmd_err_sum || sfifo_gencmd_err_sum)) || fatal_loc_events)
             -------------------------------------1-------------------------------------    --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T33
10CoveredT32,T31,T61

 LINE       314
 SUB-EXPRESSION (edn_enable_fo[FatalErr] && (sfifo_rescmd_err_sum || sfifo_gencmd_err_sum))
                 -----------1-----------    -----------------------2----------------------
-1--2-StatusTests
01CoveredT16,T18,T32
10CoveredT1,T2,T3
11CoveredT16,T18,T32

 LINE       314
 SUB-EXPRESSION (sfifo_rescmd_err_sum || sfifo_gencmd_err_sum)
                 ----------1---------    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT16,T18,T32
10CoveredT16,T18,T31

 LINE       320
 EXPRESSION (((|sfifo_rescmd_err)) || err_code_test_bit[0])
             ----------1----------    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT16,T18,T31

 LINE       322
 EXPRESSION (((|sfifo_gencmd_err)) || err_code_test_bit[1])
             ----------1----------    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT16,T18,T32

 LINE       324
 EXPRESSION (((|edn_ack_sm_err)) || err_code_test_bit[20])
             ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT4,T5,T33

 LINE       326
 EXPRESSION (edn_main_sm_err || err_code_test_bit[21])
             -------1-------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT4,T5,T33

 LINE       328
 EXPRESSION (edn_cntr_err || err_code_test_bit[22])
             ------1-----    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT4,T7,T16

 LINE       331
 EXPRESSION (sfifo_rescmd_err[2] || sfifo_gencmd_err[2] || err_code_test_bit[28])
             ---------1---------    ---------2---------    ----------3----------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010CoveredT32,T34,T35
100Not Covered

 LINE       335
 EXPRESSION (sfifo_rescmd_err[1] || sfifo_gencmd_err[1] || err_code_test_bit[29])
             ---------1---------    ---------2---------    ----------3----------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010CoveredT37
100CoveredT31,T36,T115

 LINE       339
 EXPRESSION (sfifo_rescmd_err[0] || sfifo_gencmd_err[0] || err_code_test_bit[30])
             ---------1---------    ---------2---------    ----------3----------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010CoveredT16,T18,T32
100CoveredT16,T18,T19

 LINE       347
 EXPRESSION (edn_enable_fo[ReseedCmdErr] && sfifo_rescmd_err_sum)
             -------------1-------------    ----------2---------
-1--2-StatusTests
01CoveredT16,T18,T31
10CoveredT1,T2,T3
11CoveredT16,T18,T31

 LINE       350
 EXPRESSION (edn_enable_fo[GenCmdErr] && sfifo_gencmd_err_sum)
             ------------1-----------    ----------2---------
-1--2-StatusTests
01CoveredT16,T18,T32
10CoveredT1,T2,T3
11CoveredT16,T18,T32

 LINE       367
 EXPRESSION (edn_enable_fo[FifoWrErr] && fifo_write_err_sum)
             ------------1-----------    ---------2--------
-1--2-StatusTests
01CoveredT32,T35
10CoveredT1,T2,T3
11CoveredT32,T34,T35

 LINE       370
 EXPRESSION (edn_enable_fo[FifoRdErr] && fifo_read_err_sum)
             ------------1-----------    --------2--------
-1--2-StatusTests
01CoveredT31,T36,T37
10CoveredT1,T2,T3
11CoveredT31,T36,T37

 LINE       373
 EXPRESSION (edn_enable_fo[FifoStErr] && fifo_status_err_sum)
             ------------1-----------    ---------2---------
-1--2-StatusTests
01CoveredT16,T18,T32
10CoveredT1,T2,T3
11CoveredT16,T18,T32

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 0) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T23
10CoveredT1,T2,T3
11Not Covered

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 0)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 1) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T23
10Not Covered
11Not Covered

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 1)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 2) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T23
10CoveredT116,T117,T118
11CoveredT116,T117,T118

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 2)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT116,T117,T118

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 3) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T23
10CoveredT64,T8,T51
11CoveredT64,T8,T51

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 3)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT64,T8,T51

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 4) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T23
10CoveredT64,T94,T119
11CoveredT64,T94,T119

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 4)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT64,T94,T119

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 5) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T23
10CoveredT32,T120,T121
11CoveredT32,T120,T121

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 5)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT32,T120,T121

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 6) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T23
10CoveredT122,T70,T53
11CoveredT122,T70,T53

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 6)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT122,T70,T53

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 7) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T23,T5
10CoveredT2,T6,T71
11CoveredT2,T6,T71

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 7)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T6,T71

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 8) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T23
10CoveredT5,T123,T124
11CoveredT5,T123,T124

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 8)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T123,T124

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 9) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T23,T5
10CoveredT1,T120,T125
11CoveredT1,T120,T125

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 9)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T120,T125

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 10) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T23
10CoveredT106,T31,T122
11CoveredT106,T31,T122

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 10)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT106,T31,T122

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 11) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T23
10CoveredT41,T123,T121
11CoveredT41,T123,T121

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 11)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT41,T123,T121

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 12) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T23
10CoveredT6,T80,T38
11CoveredT6,T80,T38

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 12)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T80,T38

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 13) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T23
10CoveredT10,T6,T64
11CoveredT10,T6,T64

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 13)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T6,T64

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 14) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T23
10CoveredT22,T70,T56
11CoveredT22,T70,T56

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 14)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT22,T70,T56

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 15) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT23,T6,T126
11CoveredT23,T6,T126

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 15)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT23,T6,T126

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 16) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T23
10CoveredT10,T64,T21
11CoveredT10,T64,T21

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 16)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T64,T21

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 17) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T23
10CoveredT105,T106,T123
11CoveredT105,T106,T123

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 17)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT105,T106,T123

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 18) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T23
10CoveredT122,T53,T79
11CoveredT122,T53,T79

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 18)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT122,T53,T79

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 19) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T23
10CoveredT33,T64,T7
11CoveredT33,T64,T7

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 19)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT33,T64,T7

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 20) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T23
10Not Covered
11Not Covered

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 20)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 21) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T23
10Not Covered
11Not Covered

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 21)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 22) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T23
10Not Covered
11Not Covered

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 22)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 23) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T23
10CoveredT84,T127,T128
11CoveredT84,T127,T128

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 23)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT84,T127,T128

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 24) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T23
10CoveredT5,T32,T45
11CoveredT5,T32,T45

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 24)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T32,T45

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 25) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T23
10CoveredT31,T51,T129
11CoveredT31,T51,T129

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 25)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT31,T51,T129

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 26) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T23
10CoveredT117,T130,T39
11CoveredT117,T130,T39

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 26)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT117,T130,T39

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 27) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T23
10CoveredT33,T71,T66
11CoveredT33,T71,T66

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 27)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT33,T71,T66

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 28) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T23
10Not Covered
11Not Covered

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 28)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 29) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T23
10Not Covered
11Not Covered

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 29)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       378
 EXPRESSION ((reg2hw.err_code_test.q == 30) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T23
10Not Covered
11Not Covered

 LINE       378
 SUB-EXPRESSION (reg2hw.err_code_test.q == 30)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       382
 EXPRESSION (edn_enable_fo[CsrngAckErr] && csrng_cmd_i.csrng_rsp_ack && (csrng_cmd_i.csrng_rsp_sts != CMD_STS_SUCCESS))
             -------------1------------    ------------2------------    -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT17,T45,T111
101Not Covered
110CoveredT1,T2,T3
111CoveredT17,T12,T30

 LINE       382
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_sts != CMD_STS_SUCCESS)
                -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T12,T30

 LINE       388
 EXPRESSION (edn_bus_cmp_alert || cmd_fifo_rst_pfa || auto_req_mode_pfa || boot_req_mode_pfa || edn_enable_pfa || csrng_ack_err)
             --------1--------    --------2-------    --------3--------    --------4--------    -------5------    ------6------
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T2,T3
000001CoveredT17,T12,T30
000010CoveredT131,T132,T86
000100CoveredT12,T45,T46
001000CoveredT30,T133,T134
010000CoveredT17,T111,T127
100000CoveredT17,T12,T30

 LINE       407
 EXPRESSION (event_edn_fatal_err || sfifo_rescmd_int_err || sfifo_gencmd_int_err)
             ---------1---------    ----------2---------    ----------3---------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Not Covered
100CoveredT4,T5,T33

 LINE       410
 SUB-EXPRESSION (reg2hw.alert_test.recov_alert.q && reg2hw.alert_test.recov_alert.qe)
                 ---------------1---------------    ----------------2---------------
-1--2-StatusTests
01CoveredT24,T75,T72
10CoveredT1,T2,T3
11CoveredT24,T75,T72

 LINE       414
 SUB-EXPRESSION (reg2hw.alert_test.fatal_alert.q && reg2hw.alert_test.fatal_alert.qe)
                 ---------------1---------------    ----------------2---------------
-1--2-StatusTests
01CoveredT24,T75,T72
10CoveredT1,T2,T3
11CoveredT24,T75,T72

 LINE       490
 EXPRESSION (reg2hw.sw_cmd_req.qe && cmd_reg_rdy_q)
             ----------1---------    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT11,T22,T48
11CoveredT1,T2,T3

 LINE       502
 EXPRESSION (cs_cmd_req_vld_out_q && send_cs_cmd_gated)
             ----------1---------    --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       503
 EXPRESSION (cs_cmd_req_vld_out_q && send_gencmd_gated)
             ----------1---------    --------2--------
-1--2-StatusTests
01CoveredT10,T11,T12
10CoveredT1,T2,T3
11CoveredT10,T11,T12

 LINE       504
 EXPRESSION (cs_cmd_req_vld_out_q && send_rescmd_gated)
             ----------1---------    --------2--------
-1--2-StatusTests
01CoveredT10,T11,T12
10CoveredT1,T2,T3
11CoveredT10,T11,T12

 LINE       507
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CsrngCmdReq])) ? '0 : (boot_wr_ins_cmd ? boot_ins_cmd : (boot_wr_gen_cmd ? boot_gen_cmd : (boot_wr_uni_cmd ? 32'b00000000000000000000000000000101 : (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       507
 SUB-EXPRESSION 
 Number  Term
      1  boot_wr_ins_cmd ? boot_ins_cmd : (boot_wr_gen_cmd ? boot_gen_cmd : (boot_wr_uni_cmd ? 32'b00000000000000000000000000000101 : (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT23,T17,T28

 LINE       507
 SUB-EXPRESSION (boot_wr_gen_cmd ? boot_gen_cmd : (boot_wr_uni_cmd ? 32'b00000000000000000000000000000101 : (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q)))
                 -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT23,T17,T28

 LINE       507
 SUB-EXPRESSION (boot_wr_uni_cmd ? 32'b00000000000000000000000000000101 : (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q))
                 -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT45,T46,T43

 LINE       507
 SUB-EXPRESSION (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q)
                 -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       516
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CsrngCmdReqValid])) ? '0 : (cs_cmd_handshake ? '0 : ((sw_cmd_req_load || boot_wr_ins_cmd || boot_wr_gen_cmd || boot_wr_uni_cmd) ? 1'b1 : cs_cmd_req_vld_q)))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       516
 SUB-EXPRESSION (cs_cmd_handshake ? '0 : ((sw_cmd_req_load || boot_wr_ins_cmd || boot_wr_gen_cmd || boot_wr_uni_cmd) ? 1'b1 : cs_cmd_req_vld_q))
                 --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       516
 SUB-EXPRESSION ((sw_cmd_req_load || boot_wr_ins_cmd || boot_wr_gen_cmd || boot_wr_uni_cmd) ? 1'b1 : cs_cmd_req_vld_q)
                 -------------------------------------1------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       516
 SUB-EXPRESSION (sw_cmd_req_load || boot_wr_ins_cmd || boot_wr_gen_cmd || boot_wr_uni_cmd)
                 -------1-------    -------2-------    -------3-------    -------4-------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT45,T46,T43
0010CoveredT23,T17,T28
0100CoveredT23,T17,T28
1000CoveredT1,T2,T3

 LINE       523
 EXPRESSION (cs_cmd_req_vld_q && csrng_cmd_i.csrng_req_ready)
             --------1-------    -------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       527
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CsrngCmdReqOut])) ? '0 : ((send_rescmd || capt_rescmd_fifo_cnt) ? (sfifo_rescmd_pop ? sfifo_rescmd_rdata : cs_cmd_req_out_q) : ((send_gencmd || capt_gencmd_fifo_cnt) ? (sfifo_gencmd_pop ? sfifo_gencmd_rdata : cs_cmd_req_out_q) : ((cs_cmd_req_vld_q && ((!cs_cmd_handshake))) ? cs_cmd_req_q : cs_cmd_req_out_q))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       527
 SUB-EXPRESSION 
 Number  Term
      1  (send_rescmd || capt_rescmd_fifo_cnt) ? (sfifo_rescmd_pop ? sfifo_rescmd_rdata : cs_cmd_req_out_q) : ((send_gencmd || capt_gencmd_fifo_cnt) ? (sfifo_gencmd_pop ? sfifo_gencmd_rdata : cs_cmd_req_out_q) : ((cs_cmd_req_vld_q && ((!cs_cmd_handshake))) ? cs_cmd_req_q : cs_cmd_req_out_q)))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T12

 LINE       527
 SUB-EXPRESSION (send_rescmd || capt_rescmd_fifo_cnt)
                 -----1-----    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT10,T11,T12
10CoveredT10,T11,T12

 LINE       527
 SUB-EXPRESSION (sfifo_rescmd_pop ? sfifo_rescmd_rdata : cs_cmd_req_out_q)
                 --------1-------
-1-StatusTests
0CoveredT10,T11,T12
1CoveredT10,T11,T12

 LINE       527
 SUB-EXPRESSION 
 Number  Term
      1  (send_gencmd || capt_gencmd_fifo_cnt) ? (sfifo_gencmd_pop ? sfifo_gencmd_rdata : cs_cmd_req_out_q) : ((cs_cmd_req_vld_q && ((!cs_cmd_handshake))) ? cs_cmd_req_q : cs_cmd_req_out_q))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T12

 LINE       527
 SUB-EXPRESSION (send_gencmd || capt_gencmd_fifo_cnt)
                 -----1-----    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT10,T11,T12
10CoveredT10,T11,T12

 LINE       527
 SUB-EXPRESSION (sfifo_gencmd_pop ? sfifo_gencmd_rdata : cs_cmd_req_out_q)
                 --------1-------
-1-StatusTests
0CoveredT10,T11,T12
1CoveredT10,T11,T12

 LINE       527
 SUB-EXPRESSION ((cs_cmd_req_vld_q && ((!cs_cmd_handshake))) ? cs_cmd_req_q : cs_cmd_req_out_q)
                 ---------------------1---------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       527
 SUB-EXPRESSION (cs_cmd_req_vld_q && ((!cs_cmd_handshake)))
                 --------1-------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       543
 EXPRESSION (((!edn_enable_fo[CsrngCmdReqValidOut])) ? 1'b0 : ((cs_cmd_req_vld_hold_q || cs_cmd_req_vld_out_q) && ((!csrng_cmd_i.csrng_req_ready))))
             -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       543
 SUB-EXPRESSION ((cs_cmd_req_vld_hold_q || cs_cmd_req_vld_out_q) && ((!csrng_cmd_i.csrng_req_ready)))
                 -----------------------1-----------------------    ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       543
 SUB-EXPRESSION (cs_cmd_req_vld_hold_q || cs_cmd_req_vld_out_q)
                 ----------1----------    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT100,T135,T136

 LINE       550
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CsrngCmdReqValidOut])) ? '0 : (cmd_sent ? '0 : ((send_rescmd || capt_rescmd_fifo_cnt) ? 1'b1 : ((send_gencmd || capt_gencmd_fifo_cnt) ? 1'b1 : (cs_cmd_req_vld_q && ((!cs_cmd_handshake)))))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       550
 SUB-EXPRESSION 
 Number  Term
      1  cmd_sent ? '0 : ((send_rescmd || capt_rescmd_fifo_cnt) ? 1'b1 : ((send_gencmd || capt_gencmd_fifo_cnt) ? 1'b1 : (cs_cmd_req_vld_q && ((!cs_cmd_handshake))))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T12

 LINE       550
 SUB-EXPRESSION ((send_rescmd || capt_rescmd_fifo_cnt) ? 1'b1 : ((send_gencmd || capt_gencmd_fifo_cnt) ? 1'b1 : (cs_cmd_req_vld_q && ((!cs_cmd_handshake)))))
                 ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T12

 LINE       550
 SUB-EXPRESSION (send_rescmd || capt_rescmd_fifo_cnt)
                 -----1-----    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT10,T11,T12
10CoveredT10,T11,T7

 LINE       550
 SUB-EXPRESSION ((send_gencmd || capt_gencmd_fifo_cnt) ? 1'b1 : (cs_cmd_req_vld_q && ((!cs_cmd_handshake))))
                 ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T12

 LINE       550
 SUB-EXPRESSION (send_gencmd || capt_gencmd_fifo_cnt)
                 -----1-----    ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT10,T11,T12
10CoveredT10,T11,T20

 LINE       550
 SUB-EXPRESSION (cs_cmd_req_vld_q && ((!cs_cmd_handshake)))
                 --------1-------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       558
 EXPRESSION ((cs_cmd_req_vld_out_q && ((!reject_csrng_entropy))) || cs_cmd_req_vld_hold_q)
             -------------------------1-------------------------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT131,T100,T135
10CoveredT1,T2,T3

 LINE       558
 SUB-EXPRESSION (cs_cmd_req_vld_out_q && ((!reject_csrng_entropy)))
                 ----------1---------    ------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT45,T46,T131
11CoveredT1,T2,T3

 LINE       566
 EXPRESSION (((!sw_cmd_req_load)) && cmd_rdy_d && cmd_reg_rdy_d)
             ----------1---------    ----2----    ------3------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110CoveredT17,T30,T45
111CoveredT1,T2,T3

 LINE       570
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[SwCmdSts])) ? 1'b0 : (((!sw_cmd_mode)) ? 1'b0 : (reject_csrng_entropy ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q))))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       570
 SUB-EXPRESSION 
 Number  Term
      1  ((!sw_cmd_mode)) ? 1'b0 : (reject_csrng_entropy ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT23,T4,T5

 LINE       570
 SUB-EXPRESSION (reject_csrng_entropy ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q))))
                 ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       570
 SUB-EXPRESSION (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q)))
                 -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       570
 SUB-EXPRESSION (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q))
                 ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       570
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q)
                 ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       582
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[SwCmdSts])) ? 1'b0 : (((!sw_cmd_mode)) ? 1'b0 : (reject_csrng_entropy ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q))))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       582
 SUB-EXPRESSION 
 Number  Term
      1  ((!sw_cmd_mode)) ? 1'b0 : (reject_csrng_entropy ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT23,T4,T5

 LINE       582
 SUB-EXPRESSION (reject_csrng_entropy ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q))))
                 ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       582
 SUB-EXPRESSION (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q)))
                 -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       582
 SUB-EXPRESSION (accept_sw_cmds_pulse ? 1'b1 : (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q))
                 ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       582
 SUB-EXPRESSION (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q)
                 --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%