| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 95.66 | 98.25 | 93.73 | 97.02 | 91.28 | 96.37 | 99.77 | 93.18 |
| T1011 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_rw.662773821 | Sep 01 12:29:34 PM UTC 24 | Sep 01 12:29:36 PM UTC 24 | 12450531 ps | ||
| T1012 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2256997324 | Sep 01 12:29:34 PM UTC 24 | Sep 01 12:29:37 PM UTC 24 | 114266303 ps | ||
| T1013 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.419885429 | Sep 01 12:29:34 PM UTC 24 | Sep 01 12:29:37 PM UTC 24 | 68465137 ps | ||
| T1014 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_errors.1463224237 | Sep 01 12:29:32 PM UTC 24 | Sep 01 12:29:38 PM UTC 24 | 321762649 ps | ||
| T324 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_intg_err.302184260 | Sep 01 12:29:34 PM UTC 24 | Sep 01 12:29:38 PM UTC 24 | 48084233 ps | ||
| T1015 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_bit_bash.2862221605 | Sep 01 12:29:29 PM UTC 24 | Sep 01 12:29:38 PM UTC 24 | 1197863793 ps | ||
| T1016 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/7.edn_intr_test.3394961974 | Sep 01 12:29:35 PM UTC 24 | Sep 01 12:29:38 PM UTC 24 | 16786051 ps | ||
| T289 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_rw.1540888460 | Sep 01 12:29:35 PM UTC 24 | Sep 01 12:29:38 PM UTC 24 | 27048428 ps | ||
| T1017 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_errors.1384653963 | Sep 01 12:29:34 PM UTC 24 | Sep 01 12:29:38 PM UTC 24 | 74481005 ps | ||
| T290 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_rw.2822008916 | Sep 01 12:29:36 PM UTC 24 | Sep 01 12:29:38 PM UTC 24 | 16992717 ps | ||
| T1018 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_errors.2990338618 | Sep 01 12:29:34 PM UTC 24 | Sep 01 12:29:38 PM UTC 24 | 61083248 ps | ||
| T1019 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.847773056 | Sep 01 12:29:36 PM UTC 24 | Sep 01 12:29:38 PM UTC 24 | 17537790 ps | ||
| T1020 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/8.edn_intr_test.2100383647 | Sep 01 12:29:36 PM UTC 24 | Sep 01 12:29:38 PM UTC 24 | 14997444 ps | ||
| T1021 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/7.edn_same_csr_outstanding.3111279173 | Sep 01 12:29:35 PM UTC 24 | Sep 01 12:29:39 PM UTC 24 | 29215420 ps | ||
| T1022 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/8.edn_same_csr_outstanding.3227246188 | Sep 01 12:29:37 PM UTC 24 | Sep 01 12:29:39 PM UTC 24 | 25886667 ps | ||
| T1023 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_intg_err.492706748 | Sep 01 12:29:36 PM UTC 24 | Sep 01 12:29:39 PM UTC 24 | 145701359 ps | ||
| T1024 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/9.edn_intr_test.1671930549 | Sep 01 12:29:37 PM UTC 24 | Sep 01 12:29:39 PM UTC 24 | 17209733 ps | ||
| T1025 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_rw.2419589229 | Sep 01 12:29:37 PM UTC 24 | Sep 01 12:29:40 PM UTC 24 | 29401934 ps | ||
| T1026 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3205360438 | Sep 01 12:29:37 PM UTC 24 | Sep 01 12:29:40 PM UTC 24 | 44250990 ps | ||
| T320 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_intg_err.1551070924 | Sep 01 12:29:34 PM UTC 24 | Sep 01 12:29:40 PM UTC 24 | 353125167 ps | ||
| T1027 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_errors.396580687 | Sep 01 12:29:37 PM UTC 24 | Sep 01 12:29:41 PM UTC 24 | 47364480 ps | ||
| T1028 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/9.edn_same_csr_outstanding.1083890015 | Sep 01 12:29:38 PM UTC 24 | Sep 01 12:29:41 PM UTC 24 | 63090110 ps | ||
| T1029 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/10.edn_same_csr_outstanding.1877585738 | Sep 01 12:29:39 PM UTC 24 | Sep 01 12:29:41 PM UTC 24 | 13053891 ps | ||
| T1030 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_errors.4030243061 | Sep 01 12:29:36 PM UTC 24 | Sep 01 12:29:41 PM UTC 24 | 178068325 ps | ||
| T1031 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_intg_err.3183623838 | Sep 01 12:29:38 PM UTC 24 | Sep 01 12:29:41 PM UTC 24 | 47632292 ps | ||
| T1032 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_intg_err.4290651182 | Sep 01 12:29:37 PM UTC 24 | Sep 01 12:29:41 PM UTC 24 | 100804854 ps | ||
| T1033 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3854874896 | Sep 01 12:29:38 PM UTC 24 | Sep 01 12:29:41 PM UTC 24 | 57070481 ps | ||
| T1034 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/11.edn_intr_test.3636366706 | Sep 01 12:29:40 PM UTC 24 | Sep 01 12:29:42 PM UTC 24 | 13877164 ps | ||
| T1035 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_errors.1735566429 | Sep 01 12:29:38 PM UTC 24 | Sep 01 12:29:43 PM UTC 24 | 462750671 ps | ||
| T291 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_rw.3253338219 | Sep 01 12:29:40 PM UTC 24 | Sep 01 12:29:43 PM UTC 24 | 14655039 ps | ||
| T1036 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/11.edn_same_csr_outstanding.2594723371 | Sep 01 12:29:40 PM UTC 24 | Sep 01 12:29:43 PM UTC 24 | 16802943 ps | ||
| T1037 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3616369803 | Sep 01 12:29:40 PM UTC 24 | Sep 01 12:29:43 PM UTC 24 | 27559005 ps | ||
| T1038 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/12.edn_intr_test.3077190320 | Sep 01 12:29:41 PM UTC 24 | Sep 01 12:29:43 PM UTC 24 | 20257965 ps | ||
| T1039 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.212063804 | Sep 01 12:29:40 PM UTC 24 | Sep 01 12:29:43 PM UTC 24 | 21282759 ps | ||
| T1040 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_intg_err.3834419538 | Sep 01 12:29:40 PM UTC 24 | Sep 01 12:29:44 PM UTC 24 | 72031123 ps | ||
| T1041 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/12.edn_same_csr_outstanding.1079942030 | Sep 01 12:29:41 PM UTC 24 | Sep 01 12:29:44 PM UTC 24 | 35943764 ps | ||
| T1042 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2663267238 | Sep 01 12:29:41 PM UTC 24 | Sep 01 12:29:44 PM UTC 24 | 123468711 ps | ||
| T325 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_intg_err.4159166952 | Sep 01 12:29:40 PM UTC 24 | Sep 01 12:29:44 PM UTC 24 | 88220992 ps | ||
| T1043 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/13.edn_intr_test.1995991215 | Sep 01 12:29:43 PM UTC 24 | Sep 01 12:29:45 PM UTC 24 | 15665304 ps | ||
| T1044 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_errors.1984926054 | Sep 01 12:29:40 PM UTC 24 | Sep 01 12:29:45 PM UTC 24 | 75700529 ps | ||
| T1045 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_rw.733628596 | Sep 01 12:29:43 PM UTC 24 | Sep 01 12:29:45 PM UTC 24 | 42979214 ps | ||
| T1046 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_intg_err.1547044382 | Sep 01 12:29:42 PM UTC 24 | Sep 01 12:29:45 PM UTC 24 | 293952695 ps | ||
| T1047 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_errors.3263152275 | Sep 01 12:29:40 PM UTC 24 | Sep 01 12:29:45 PM UTC 24 | 38397406 ps | ||
| T1048 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2797735868 | Sep 01 12:29:43 PM UTC 24 | Sep 01 12:29:46 PM UTC 24 | 28009601 ps | ||
| T1049 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/13.edn_same_csr_outstanding.2784986291 | Sep 01 12:29:43 PM UTC 24 | Sep 01 12:29:46 PM UTC 24 | 173918586 ps | ||
| T1050 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_intg_err.1539660281 | Sep 01 12:29:43 PM UTC 24 | Sep 01 12:29:46 PM UTC 24 | 59535647 ps | ||
| T1051 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_errors.1554206841 | Sep 01 12:29:43 PM UTC 24 | Sep 01 12:29:47 PM UTC 24 | 169130920 ps | ||
| T1052 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_rw.178507753 | Sep 01 12:29:44 PM UTC 24 | Sep 01 12:29:47 PM UTC 24 | 47529773 ps | ||
| T1053 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/14.edn_intr_test.1296140085 | Sep 01 12:29:44 PM UTC 24 | Sep 01 12:29:47 PM UTC 24 | 202744272 ps | ||
| T1054 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/15.edn_intr_test.2167455681 | Sep 01 12:29:45 PM UTC 24 | Sep 01 12:29:47 PM UTC 24 | 24293271 ps | ||
| T1055 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/14.edn_same_csr_outstanding.3745629206 | Sep 01 12:29:44 PM UTC 24 | Sep 01 12:29:47 PM UTC 24 | 15591189 ps | ||
| T1056 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.4215838643 | Sep 01 12:29:44 PM UTC 24 | Sep 01 12:29:47 PM UTC 24 | 30600398 ps | ||
| T1057 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_errors.2297512433 | Sep 01 12:29:41 PM UTC 24 | Sep 01 12:29:47 PM UTC 24 | 389666102 ps | ||
| T1058 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1887733695 | Sep 01 12:29:45 PM UTC 24 | Sep 01 12:29:48 PM UTC 24 | 90187191 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_rw.4145391945 | Sep 01 12:29:45 PM UTC 24 | Sep 01 12:29:48 PM UTC 24 | 137732672 ps | ||
| T1059 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/15.edn_same_csr_outstanding.1454088469 | Sep 01 12:29:45 PM UTC 24 | Sep 01 12:29:48 PM UTC 24 | 162740037 ps | ||
| T1060 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/16.edn_intr_test.2043524162 | Sep 01 12:29:46 PM UTC 24 | Sep 01 12:29:49 PM UTC 24 | 17319530 ps | ||
| T1061 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_rw.702848181 | Sep 01 12:29:47 PM UTC 24 | Sep 01 12:29:49 PM UTC 24 | 13549989 ps | ||
| T292 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_rw.2689791360 | Sep 01 12:29:46 PM UTC 24 | Sep 01 12:29:49 PM UTC 24 | 13906744 ps | ||
| T1062 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/17.edn_intr_test.1078486368 | Sep 01 12:29:46 PM UTC 24 | Sep 01 12:29:49 PM UTC 24 | 23761639 ps | ||
| T321 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_intg_err.3477124040 | Sep 01 12:29:45 PM UTC 24 | Sep 01 12:29:49 PM UTC 24 | 180918972 ps | ||
| T1063 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/16.edn_same_csr_outstanding.1312680811 | Sep 01 12:29:46 PM UTC 24 | Sep 01 12:29:50 PM UTC 24 | 125749809 ps | ||
| T1064 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1111626371 | Sep 01 12:29:46 PM UTC 24 | Sep 01 12:29:50 PM UTC 24 | 50056059 ps | ||
| T1065 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_intg_err.3565042924 | Sep 01 12:29:46 PM UTC 24 | Sep 01 12:29:50 PM UTC 24 | 70593207 ps | ||
| T1066 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_errors.1519431551 | Sep 01 12:29:45 PM UTC 24 | Sep 01 12:29:50 PM UTC 24 | 81031218 ps | ||
| T1067 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/17.edn_same_csr_outstanding.1863975943 | Sep 01 12:29:47 PM UTC 24 | Sep 01 12:29:50 PM UTC 24 | 39577209 ps | ||
| T1068 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/18.edn_intr_test.2353620702 | Sep 01 12:29:48 PM UTC 24 | Sep 01 12:29:51 PM UTC 24 | 11937864 ps | ||
| T1069 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_rw.3589234029 | Sep 01 12:29:48 PM UTC 24 | Sep 01 12:29:51 PM UTC 24 | 26127360 ps | ||
| T1070 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2856101790 | Sep 01 12:29:48 PM UTC 24 | Sep 01 12:29:51 PM UTC 24 | 41228044 ps | ||
| T1071 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3112833078 | Sep 01 12:29:48 PM UTC 24 | Sep 01 12:29:51 PM UTC 24 | 24199553 ps | ||
| T1072 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_intg_err.796512845 | Sep 01 12:29:46 PM UTC 24 | Sep 01 12:29:51 PM UTC 24 | 158809842 ps | ||
| T1073 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_errors.1376328835 | Sep 01 12:29:45 PM UTC 24 | Sep 01 12:29:51 PM UTC 24 | 109221417 ps | ||
| T1074 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/18.edn_same_csr_outstanding.3428256034 | Sep 01 12:29:48 PM UTC 24 | Sep 01 12:29:51 PM UTC 24 | 67729696 ps | ||
| T1075 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_rw.220905474 | Sep 01 12:29:49 PM UTC 24 | Sep 01 12:29:51 PM UTC 24 | 13027210 ps | ||
| T1076 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_errors.4124214465 | Sep 01 12:29:46 PM UTC 24 | Sep 01 12:29:52 PM UTC 24 | 71109061 ps | ||
| T1077 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/19.edn_intr_test.834537304 | Sep 01 12:29:49 PM UTC 24 | Sep 01 12:29:52 PM UTC 24 | 17049165 ps | ||
| T322 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_intg_err.2395914819 | Sep 01 12:29:48 PM UTC 24 | Sep 01 12:29:52 PM UTC 24 | 141078545 ps | ||
| T1078 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_intg_err.2650543462 | Sep 01 12:29:49 PM UTC 24 | Sep 01 12:29:53 PM UTC 24 | 302425101 ps | ||
| T1079 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/24.edn_intr_test.3573122301 | Sep 01 12:29:51 PM UTC 24 | Sep 01 12:29:53 PM UTC 24 | 41600534 ps | ||
| T1080 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/21.edn_intr_test.4076125608 | Sep 01 12:29:51 PM UTC 24 | Sep 01 12:29:53 PM UTC 24 | 16457100 ps | ||
| T1081 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/22.edn_intr_test.974283684 | Sep 01 12:29:51 PM UTC 24 | Sep 01 12:29:53 PM UTC 24 | 40192432 ps | ||
| T1082 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/20.edn_intr_test.3899308431 | Sep 01 12:29:51 PM UTC 24 | Sep 01 12:29:53 PM UTC 24 | 134197280 ps | ||
| T1083 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/26.edn_intr_test.2208903210 | Sep 01 12:29:51 PM UTC 24 | Sep 01 12:29:53 PM UTC 24 | 11751785 ps | ||
| T1084 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/23.edn_intr_test.1547890062 | Sep 01 12:29:51 PM UTC 24 | Sep 01 12:29:53 PM UTC 24 | 47348613 ps | ||
| T1085 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/25.edn_intr_test.2043191794 | Sep 01 12:29:51 PM UTC 24 | Sep 01 12:29:53 PM UTC 24 | 13323037 ps | ||
| T1086 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/19.edn_same_csr_outstanding.4121657770 | Sep 01 12:29:50 PM UTC 24 | Sep 01 12:29:53 PM UTC 24 | 28702763 ps | ||
| T1087 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/27.edn_intr_test.1298998378 | Sep 01 12:29:51 PM UTC 24 | Sep 01 12:29:53 PM UTC 24 | 34597549 ps | ||
| T1088 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_errors.3233113082 | Sep 01 12:29:48 PM UTC 24 | Sep 01 12:29:54 PM UTC 24 | 126318852 ps | ||
| T1089 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/34.edn_intr_test.736571033 | Sep 01 12:29:52 PM UTC 24 | Sep 01 12:29:54 PM UTC 24 | 63817819 ps | ||
| T1090 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/32.edn_intr_test.1693931135 | Sep 01 12:29:52 PM UTC 24 | Sep 01 12:29:54 PM UTC 24 | 14045622 ps | ||
| T1091 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/28.edn_intr_test.3560145490 | Sep 01 12:29:52 PM UTC 24 | Sep 01 12:29:54 PM UTC 24 | 15789098 ps | ||
| T1092 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/29.edn_intr_test.3822937174 | Sep 01 12:29:52 PM UTC 24 | Sep 01 12:29:54 PM UTC 24 | 24123578 ps | ||
| T1093 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/31.edn_intr_test.134361959 | Sep 01 12:29:52 PM UTC 24 | Sep 01 12:29:54 PM UTC 24 | 36699435 ps | ||
| T1094 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/30.edn_intr_test.1765086137 | Sep 01 12:29:52 PM UTC 24 | Sep 01 12:29:54 PM UTC 24 | 63348410 ps | ||
| T1095 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3506713504 | Sep 01 12:29:50 PM UTC 24 | Sep 01 12:29:55 PM UTC 24 | 28763941 ps | ||
| T1096 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/33.edn_intr_test.3056581568 | Sep 01 12:29:52 PM UTC 24 | Sep 01 12:29:55 PM UTC 24 | 26483525 ps | ||
| T1097 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/36.edn_intr_test.3581574603 | Sep 01 12:29:52 PM UTC 24 | Sep 01 12:29:55 PM UTC 24 | 41017946 ps | ||
| T1098 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/35.edn_intr_test.130426300 | Sep 01 12:29:52 PM UTC 24 | Sep 01 12:29:55 PM UTC 24 | 32362973 ps | ||
| T1099 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/38.edn_intr_test.2206731968 | Sep 01 12:29:53 PM UTC 24 | Sep 01 12:29:55 PM UTC 24 | 30351182 ps | ||
| T1100 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/37.edn_intr_test.1969346318 | Sep 01 12:29:53 PM UTC 24 | Sep 01 12:29:55 PM UTC 24 | 53892156 ps | ||
| T1101 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_errors.3209864784 | Sep 01 12:29:49 PM UTC 24 | Sep 01 12:29:55 PM UTC 24 | 222444169 ps | ||
| T1102 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/41.edn_intr_test.1805186738 | Sep 01 12:29:54 PM UTC 24 | Sep 01 12:29:56 PM UTC 24 | 15775255 ps | ||
| T1103 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/39.edn_intr_test.3721646939 | Sep 01 12:29:54 PM UTC 24 | Sep 01 12:29:56 PM UTC 24 | 12611261 ps | ||
| T1104 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/43.edn_intr_test.2091181471 | Sep 01 12:29:54 PM UTC 24 | Sep 01 12:29:56 PM UTC 24 | 12875205 ps | ||
| T1105 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/42.edn_intr_test.1961920453 | Sep 01 12:29:54 PM UTC 24 | Sep 01 12:29:56 PM UTC 24 | 14118832 ps | ||
| T1106 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/40.edn_intr_test.3262456436 | Sep 01 12:29:54 PM UTC 24 | Sep 01 12:29:56 PM UTC 24 | 51950097 ps | ||
| T1107 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/45.edn_intr_test.688018456 | Sep 01 12:29:54 PM UTC 24 | Sep 01 12:29:56 PM UTC 24 | 62576820 ps | ||
| T1108 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/46.edn_intr_test.1604941722 | Sep 01 12:29:54 PM UTC 24 | Sep 01 12:29:56 PM UTC 24 | 59127474 ps | ||
| T1109 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/44.edn_intr_test.1615041407 | Sep 01 12:29:54 PM UTC 24 | Sep 01 12:29:56 PM UTC 24 | 14389078 ps | ||
| T1110 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/48.edn_intr_test.3961434194 | Sep 01 12:29:54 PM UTC 24 | Sep 01 12:29:56 PM UTC 24 | 31370981 ps | ||
| T1111 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/47.edn_intr_test.3031196846 | Sep 01 12:29:54 PM UTC 24 | Sep 01 12:29:56 PM UTC 24 | 12241808 ps | ||
| T1112 | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/49.edn_intr_test.664504034 | Sep 01 12:29:55 PM UTC 24 | Sep 01 12:29:57 PM UTC 24 | 57797230 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/0.edn_disable_auto_req_mode.3750562701 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 60921469 ps |
| CPU time | 1.65 seconds |
| Started | Sep 01 09:43:48 AM UTC 24 |
| Finished | Sep 01 09:43:51 AM UTC 24 |
| Peak memory | 228304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750562701 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable_auto_req_mode.3750562701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/0.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/1.edn_sec_cm.3282468523 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 515812113 ps |
| CPU time | 6.74 seconds |
| Started | Sep 01 09:43:53 AM UTC 24 |
| Finished | Sep 01 09:44:01 AM UTC 24 |
| Peak memory | 260356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282468523 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.3282468523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/1.edn_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/5.edn_genbits.3183199326 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 68479964 ps |
| CPU time | 2.06 seconds |
| Started | Sep 01 09:44:08 AM UTC 24 |
| Finished | Sep 01 09:44:11 AM UTC 24 |
| Peak memory | 231568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183199326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3183199326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/5.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/0.edn_alert.1311667601 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 58739439 ps |
| CPU time | 2.01 seconds |
| Started | Sep 01 09:43:48 AM UTC 24 |
| Finished | Sep 01 09:43:51 AM UTC 24 |
| Peak memory | 226380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311667601 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.edn_alert.1311667601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/0.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/0.edn_stress_all.1302191069 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 419368708 ps |
| CPU time | 4.73 seconds |
| Started | Sep 01 09:43:46 AM UTC 24 |
| Finished | Sep 01 09:43:52 AM UTC 24 |
| Peak memory | 231584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302191069 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.1302191069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/0.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/1.edn_stress_all_with_rand_reset.3064431720 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 6640242486 ps |
| CPU time | 63.64 seconds |
| Started | Sep 01 09:43:51 AM UTC 24 |
| Finished | Sep 01 09:44:56 AM UTC 24 |
| Peak memory | 233880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064431720 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_ with_rand_reset.3064431720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/1.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/1.edn_alert.248705365 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 29451918 ps |
| CPU time | 1.73 seconds |
| Started | Sep 01 09:43:52 AM UTC 24 |
| Finished | Sep 01 09:43:55 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248705365 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 1.edn_alert.248705365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/1.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/9.edn_genbits.3075506745 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 68550162 ps |
| CPU time | 2.17 seconds |
| Started | Sep 01 09:44:20 AM UTC 24 |
| Finished | Sep 01 09:44:24 AM UTC 24 |
| Peak memory | 231844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075506745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 9.edn_genbits.3075506745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/9.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/3.edn_regwen.3524980654 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 52732091 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 09:43:57 AM UTC 24 |
| Finished | Sep 01 09:44:00 AM UTC 24 |
| Peak memory | 216020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524980654 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 3.edn_regwen.3524980654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/3.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/13.edn_alert.1264027270 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 46232859 ps |
| CPU time | 1.55 seconds |
| Started | Sep 01 09:44:35 AM UTC 24 |
| Finished | Sep 01 09:44:38 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264027270 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 13.edn_alert.1264027270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/13.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/1.edn_disable_auto_req_mode.3807365549 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 90466178 ps |
| CPU time | 1.58 seconds |
| Started | Sep 01 09:43:53 AM UTC 24 |
| Finished | Sep 01 09:43:56 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807365549 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable_auto_req_mode.3807365549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/1.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/18.edn_alert.1105571365 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 35601968 ps |
| CPU time | 1.53 seconds |
| Started | Sep 01 09:44:56 AM UTC 24 |
| Finished | Sep 01 09:44:59 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105571365 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 18.edn_alert.1105571365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/18.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/7.edn_disable.3920325716 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 11693972 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 09:44:17 AM UTC 24 |
| Finished | Sep 01 09:44:20 AM UTC 24 |
| Peak memory | 226376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920325716 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3920325716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/7.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/0.edn_alert_test.665293219 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 98932718 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 09:43:49 AM UTC 24 |
| Finished | Sep 01 09:43:52 AM UTC 24 |
| Peak memory | 216988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665293219 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.665293219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/0.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_intg_err.302184260 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 48084233 ps |
| CPU time | 2.42 seconds |
| Started | Sep 01 12:29:34 PM UTC 24 |
| Finished | Sep 01 12:29:38 PM UTC 24 |
| Peak memory | 217568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302184260 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.302184260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/7.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_hw_reset.346478270 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 32394200 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 12:29:25 PM UTC 24 |
| Finished | Sep 01 12:29:27 PM UTC 24 |
| Peak memory | 215460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346478270 -assert nopostproc +UVM_TESTNAME=edn _base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.346478270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/1.edn_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/2.edn_disable.4148400099 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 28274844 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 09:43:56 AM UTC 24 |
| Finished | Sep 01 09:43:58 AM UTC 24 |
| Peak memory | 226376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148400099 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.4148400099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/2.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/17.edn_stress_all_with_rand_reset.2633707733 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 7755822981 ps |
| CPU time | 50.7 seconds |
| Started | Sep 01 09:44:52 AM UTC 24 |
| Finished | Sep 01 09:45:44 AM UTC 24 |
| Peak memory | 233948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633707733 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all _with_rand_reset.2633707733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/17.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/44.edn_intr.2370911497 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 23535320 ps |
| CPU time | 1.66 seconds |
| Started | Sep 01 09:47:26 AM UTC 24 |
| Finished | Sep 01 09:47:29 AM UTC 24 |
| Peak memory | 228016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370911497 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.2370911497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/44.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/22.edn_alert.517097638 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 110394670 ps |
| CPU time | 1.62 seconds |
| Started | Sep 01 09:45:16 AM UTC 24 |
| Finished | Sep 01 09:45:19 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517097638 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 22.edn_alert.517097638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/22.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/5.edn_disable_auto_req_mode.2370972357 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 105966889 ps |
| CPU time | 1.73 seconds |
| Started | Sep 01 09:44:09 AM UTC 24 |
| Finished | Sep 01 09:44:11 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370972357 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable_auto_req_mode.2370972357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/5.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/26.edn_disable.947670037 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 22375233 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 09:45:42 AM UTC 24 |
| Finished | Sep 01 09:45:44 AM UTC 24 |
| Peak memory | 226376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947670037 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.947670037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/26.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/15.edn_disable.1746542107 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 35575105 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 09:44:45 AM UTC 24 |
| Finished | Sep 01 09:44:47 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746542107 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1746542107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/15.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/25.edn_disable_auto_req_mode.3874984771 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 70194982 ps |
| CPU time | 1.47 seconds |
| Started | Sep 01 09:45:36 AM UTC 24 |
| Finished | Sep 01 09:45:39 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874984771 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable_auto_req_mode.3874984771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/25.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/11.edn_stress_all.2018190185 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1058342071 ps |
| CPU time | 7.24 seconds |
| Started | Sep 01 09:44:28 AM UTC 24 |
| Finished | Sep 01 09:44:36 AM UTC 24 |
| Peak memory | 229588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018190185 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2018190185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/11.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/21.edn_alert.516996637 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 44887715 ps |
| CPU time | 1.76 seconds |
| Started | Sep 01 09:45:11 AM UTC 24 |
| Finished | Sep 01 09:45:14 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516996637 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 21.edn_alert.516996637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/21.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/2.edn_disable_auto_req_mode.2157241069 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 202970759 ps |
| CPU time | 1.51 seconds |
| Started | Sep 01 09:43:57 AM UTC 24 |
| Finished | Sep 01 09:43:59 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157241069 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable_auto_req_mode.2157241069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/2.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/23.edn_alert.638505622 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 24193938 ps |
| CPU time | 1.6 seconds |
| Started | Sep 01 09:45:23 AM UTC 24 |
| Finished | Sep 01 09:45:26 AM UTC 24 |
| Peak memory | 232192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638505622 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 23.edn_alert.638505622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/23.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/29.edn_alert.26106047 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 24397523 ps |
| CPU time | 1.71 seconds |
| Started | Sep 01 09:45:58 AM UTC 24 |
| Finished | Sep 01 09:46:01 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26106047 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.26106047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/29.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/105.edn_alert.2671329805 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 27701201 ps |
| CPU time | 1.88 seconds |
| Started | Sep 01 09:49:19 AM UTC 24 |
| Finished | Sep 01 09:49:22 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671329805 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 105.edn_alert.2671329805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/105.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/21.edn_disable.1511694509 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 82300648 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 09:45:11 AM UTC 24 |
| Finished | Sep 01 09:45:14 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511694509 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1511694509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/21.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/23.edn_intr.1640788730 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 24870088 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 09:45:22 AM UTC 24 |
| Finished | Sep 01 09:45:24 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640788730 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1640788730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/23.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/16.edn_genbits.893049789 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 210975602 ps |
| CPU time | 3.18 seconds |
| Started | Sep 01 09:44:46 AM UTC 24 |
| Finished | Sep 01 09:44:50 AM UTC 24 |
| Peak memory | 231772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893049789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 16.edn_genbits.893049789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/16.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/55.edn_genbits.613818971 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 85113035 ps |
| CPU time | 1.81 seconds |
| Started | Sep 01 09:48:18 AM UTC 24 |
| Finished | Sep 01 09:48:21 AM UTC 24 |
| Peak memory | 230416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613818971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 55.edn_genbits.613818971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/55.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/10.edn_alert.2636299210 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 42243850 ps |
| CPU time | 1.59 seconds |
| Started | Sep 01 09:44:24 AM UTC 24 |
| Finished | Sep 01 09:44:27 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636299210 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 10.edn_alert.2636299210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/10.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/10.edn_disable.1766130218 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 17789518 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 09:44:26 AM UTC 24 |
| Finished | Sep 01 09:44:28 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766130218 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1766130218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/10.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/101.edn_alert.1258474607 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 58260849 ps |
| CPU time | 1.46 seconds |
| Started | Sep 01 09:49:16 AM UTC 24 |
| Finished | Sep 01 09:49:19 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258474607 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 101.edn_alert.1258474607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/101.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/103.edn_alert.1934177457 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 118498025 ps |
| CPU time | 1.35 seconds |
| Started | Sep 01 09:49:18 AM UTC 24 |
| Finished | Sep 01 09:49:20 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934177457 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 103.edn_alert.1934177457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/103.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/11.edn_err.3904044656 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 29793485 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 09:44:29 AM UTC 24 |
| Finished | Sep 01 09:44:31 AM UTC 24 |
| Peak memory | 230408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904044656 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 11.edn_err.3904044656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/11.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/14.edn_disable_auto_req_mode.3731347579 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 71547683 ps |
| CPU time | 1.8 seconds |
| Started | Sep 01 09:44:41 AM UTC 24 |
| Finished | Sep 01 09:44:44 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731347579 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable_auto_req_mode.3731347579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/14.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/146.edn_alert.3240815223 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 24762778 ps |
| CPU time | 1.34 seconds |
| Started | Sep 01 09:49:44 AM UTC 24 |
| Finished | Sep 01 09:49:47 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240815223 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 146.edn_alert.3240815223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/146.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/156.edn_alert.2071132614 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 359499824 ps |
| CPU time | 1.65 seconds |
| Started | Sep 01 09:49:50 AM UTC 24 |
| Finished | Sep 01 09:49:52 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071132614 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 156.edn_alert.2071132614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/156.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/16.edn_disable.1465382562 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 12047766 ps |
| CPU time | 1.26 seconds |
| Started | Sep 01 09:44:48 AM UTC 24 |
| Finished | Sep 01 09:44:51 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465382562 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.1465382562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/16.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/160.edn_alert.4035393893 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 41349865 ps |
| CPU time | 1.66 seconds |
| Started | Sep 01 09:50:03 AM UTC 24 |
| Finished | Sep 01 09:50:06 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035393893 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 160.edn_alert.4035393893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/160.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/168.edn_alert.1608208844 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 23558628 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 09:50:07 AM UTC 24 |
| Finished | Sep 01 09:50:10 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608208844 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 168.edn_alert.1608208844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/168.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/32.edn_err.4002173049 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 33442078 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 09:46:15 AM UTC 24 |
| Finished | Sep 01 09:46:17 AM UTC 24 |
| Peak memory | 228360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002173049 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 32.edn_err.4002173049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/32.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/44.edn_disable.2634080488 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 14373373 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 09:47:27 AM UTC 24 |
| Finished | Sep 01 09:47:30 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634080488 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2634080488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/44.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/14.edn_alert.4018685722 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 82173354 ps |
| CPU time | 1.86 seconds |
| Started | Sep 01 09:44:39 AM UTC 24 |
| Finished | Sep 01 09:44:42 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018685722 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 14.edn_alert.4018685722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/14.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/45.edn_genbits.3346892819 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 44892994 ps |
| CPU time | 1.61 seconds |
| Started | Sep 01 09:47:30 AM UTC 24 |
| Finished | Sep 01 09:47:32 AM UTC 24 |
| Peak memory | 230612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346892819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3346892819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/45.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/37.edn_genbits.933669709 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 226355390 ps |
| CPU time | 1.92 seconds |
| Started | Sep 01 09:46:39 AM UTC 24 |
| Finished | Sep 01 09:46:42 AM UTC 24 |
| Peak memory | 230416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933669709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 37.edn_genbits.933669709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/37.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/14.edn_genbits.2827048565 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 46983968 ps |
| CPU time | 2.16 seconds |
| Started | Sep 01 09:44:38 AM UTC 24 |
| Finished | Sep 01 09:44:41 AM UTC 24 |
| Peak memory | 229748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827048565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2827048565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/14.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/8.edn_genbits.3494985095 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 137745898 ps |
| CPU time | 1.36 seconds |
| Started | Sep 01 09:44:19 AM UTC 24 |
| Finished | Sep 01 09:44:21 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494985095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3494985095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/8.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/9.edn_stress_all.592101708 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 418290855 ps |
| CPU time | 5.67 seconds |
| Started | Sep 01 09:44:22 AM UTC 24 |
| Finished | Sep 01 09:44:28 AM UTC 24 |
| Peak memory | 231580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592101708 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.592101708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/9.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/2.edn_err.3021979548 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 41178654 ps |
| CPU time | 1.72 seconds |
| Started | Sep 01 09:43:56 AM UTC 24 |
| Finished | Sep 01 09:43:59 AM UTC 24 |
| Peak memory | 247180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021979548 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 2.edn_err.3021979548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/2.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_rw.3689912784 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 58452582 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 12:29:25 PM UTC 24 |
| Finished | Sep 01 12:29:27 PM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689912784 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3689912784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/0.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_intg_err.3477124040 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 180918972 ps |
| CPU time | 3.32 seconds |
| Started | Sep 01 12:29:45 PM UTC 24 |
| Finished | Sep 01 12:29:49 PM UTC 24 |
| Peak memory | 228068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477124040 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.3477124040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/15.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/118.edn_genbits.1515988761 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 37139062 ps |
| CPU time | 1.66 seconds |
| Started | Sep 01 09:49:27 AM UTC 24 |
| Finished | Sep 01 09:49:29 AM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515988761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1515988761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/118.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/140.edn_genbits.2095515564 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 171560469 ps |
| CPU time | 2.15 seconds |
| Started | Sep 01 09:49:41 AM UTC 24 |
| Finished | Sep 01 09:49:44 AM UTC 24 |
| Peak memory | 229448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095515564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2095515564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/140.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/189.edn_genbits.597273386 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 113465835 ps |
| CPU time | 1.64 seconds |
| Started | Sep 01 09:50:20 AM UTC 24 |
| Finished | Sep 01 09:50:23 AM UTC 24 |
| Peak memory | 230416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597273386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 189.edn_genbits.597273386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/189.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/214.edn_genbits.324317696 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 40454026 ps |
| CPU time | 2.36 seconds |
| Started | Sep 01 09:50:31 AM UTC 24 |
| Finished | Sep 01 09:50:35 AM UTC 24 |
| Peak memory | 229512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324317696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 214.edn_genbits.324317696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/214.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/268.edn_genbits.2713669242 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 139286083 ps |
| CPU time | 3.36 seconds |
| Started | Sep 01 09:50:46 AM UTC 24 |
| Finished | Sep 01 09:50:50 AM UTC 24 |
| Peak memory | 231592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713669242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 268.edn_genbits.2713669242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/268.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/41.edn_disable_auto_req_mode.2764432176 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 44285406 ps |
| CPU time | 1.61 seconds |
| Started | Sep 01 09:47:09 AM UTC 24 |
| Finished | Sep 01 09:47:12 AM UTC 24 |
| Peak memory | 228300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764432176 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable_auto_req_mode.2764432176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/41.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/45.edn_disable_auto_req_mode.3514452126 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 48542401 ps |
| CPU time | 1.65 seconds |
| Started | Sep 01 09:47:33 AM UTC 24 |
| Finished | Sep 01 09:47:36 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514452126 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable_auto_req_mode.3514452126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/45.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/30.edn_intr.2697339169 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 25938802 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 09:46:04 AM UTC 24 |
| Finished | Sep 01 09:46:06 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697339169 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2697339169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/30.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/12.edn_intr.2684189723 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 19928370 ps |
| CPU time | 1.56 seconds |
| Started | Sep 01 09:44:32 AM UTC 24 |
| Finished | Sep 01 09:44:34 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684189723 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.2684189723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/12.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/13.edn_genbits.807053439 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 59685581 ps |
| CPU time | 1.89 seconds |
| Started | Sep 01 09:44:34 AM UTC 24 |
| Finished | Sep 01 09:44:37 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807053439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 13.edn_genbits.807053439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/13.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/11.edn_disable.1863206444 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 38046120 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 09:44:29 AM UTC 24 |
| Finished | Sep 01 09:44:31 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863206444 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.1863206444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/11.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/3.edn_intr.1327651913 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 94008119 ps |
| CPU time | 1.32 seconds |
| Started | Sep 01 09:43:59 AM UTC 24 |
| Finished | Sep 01 09:44:02 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327651913 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.1327651913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/3.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/36.edn_genbits.1026778021 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 68302468 ps |
| CPU time | 2.1 seconds |
| Started | Sep 01 09:46:33 AM UTC 24 |
| Finished | Sep 01 09:46:36 AM UTC 24 |
| Peak memory | 231588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026778021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1026778021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/36.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_aliasing.1201702778 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 82211070 ps |
| CPU time | 1.68 seconds |
| Started | Sep 01 12:29:25 PM UTC 24 |
| Finished | Sep 01 12:29:27 PM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201702778 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1201702778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/0.edn_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_bit_bash.4112960966 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 2075399177 ps |
| CPU time | 7.46 seconds |
| Started | Sep 01 12:29:25 PM UTC 24 |
| Finished | Sep 01 12:29:33 PM UTC 24 |
| Peak memory | 217628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112960966 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.4112960966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/0.edn_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_hw_reset.451921784 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 25790323 ps |
| CPU time | 1.35 seconds |
| Started | Sep 01 12:29:25 PM UTC 24 |
| Finished | Sep 01 12:29:27 PM UTC 24 |
| Peak memory | 215460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451921784 -assert nopostproc +UVM_TESTNAME=edn _base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.451921784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/0.edn_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2247901599 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 71863184 ps |
| CPU time | 1.69 seconds |
| Started | Sep 01 12:29:25 PM UTC 24 |
| Finished | Sep 01 12:29:28 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2247901599 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2247901599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/0.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/0.edn_intr_test.2170778967 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 16052092 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 12:29:24 PM UTC 24 |
| Finished | Sep 01 12:29:27 PM UTC 24 |
| Peak memory | 216968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170778967 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.2170778967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/0.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/0.edn_same_csr_outstanding.2407725103 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 75071307 ps |
| CPU time | 1.59 seconds |
| Started | Sep 01 12:29:25 PM UTC 24 |
| Finished | Sep 01 12:29:27 PM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407725103 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_outstanding.2407725103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/0.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/0.edn_tl_errors.1499846809 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 43929635 ps |
| CPU time | 3.62 seconds |
| Started | Sep 01 12:29:23 PM UTC 24 |
| Finished | Sep 01 12:29:28 PM UTC 24 |
| Peak memory | 227860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499846809 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1499846809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/0.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/0.edn_tl_intg_err.405816855 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 101911398 ps |
| CPU time | 3.83 seconds |
| Started | Sep 01 12:29:23 PM UTC 24 |
| Finished | Sep 01 12:29:28 PM UTC 24 |
| Peak memory | 227668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405816855 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.405816855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/0.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_aliasing.3607327534 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 15955515 ps |
| CPU time | 1.59 seconds |
| Started | Sep 01 12:29:25 PM UTC 24 |
| Finished | Sep 01 12:29:28 PM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607327534 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.3607327534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/1.edn_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_bit_bash.1440917003 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 518410056 ps |
| CPU time | 4.34 seconds |
| Started | Sep 01 12:29:25 PM UTC 24 |
| Finished | Sep 01 12:29:31 PM UTC 24 |
| Peak memory | 217436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440917003 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.1440917003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/1.edn_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1277787555 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 76120683 ps |
| CPU time | 1.36 seconds |
| Started | Sep 01 12:29:26 PM UTC 24 |
| Finished | Sep 01 12:29:29 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1277787555 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.1277787555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/1.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/1.edn_csr_rw.2230100102 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 13861508 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 12:29:25 PM UTC 24 |
| Finished | Sep 01 12:29:27 PM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230100102 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2230100102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/1.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/1.edn_intr_test.1506473369 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 16474498 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 12:29:25 PM UTC 24 |
| Finished | Sep 01 12:29:27 PM UTC 24 |
| Peak memory | 215392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506473369 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.1506473369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/1.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/1.edn_same_csr_outstanding.1200652913 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 64194622 ps |
| CPU time | 1.53 seconds |
| Started | Sep 01 12:29:26 PM UTC 24 |
| Finished | Sep 01 12:29:29 PM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200652913 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_outstanding.1200652913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/1.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/1.edn_tl_errors.3401824106 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 204183010 ps |
| CPU time | 3.1 seconds |
| Started | Sep 01 12:29:25 PM UTC 24 |
| Finished | Sep 01 12:29:29 PM UTC 24 |
| Peak memory | 231888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401824106 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3401824106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/1.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/1.edn_tl_intg_err.619669461 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 44193691 ps |
| CPU time | 1.9 seconds |
| Started | Sep 01 12:29:25 PM UTC 24 |
| Finished | Sep 01 12:29:28 PM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619669461 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.619669461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/1.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3616369803 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 27559005 ps |
| CPU time | 1.91 seconds |
| Started | Sep 01 12:29:40 PM UTC 24 |
| Finished | Sep 01 12:29:43 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3616369803 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3616369803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/10.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/10.edn_csr_rw.2440537194 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 16738294 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 12:29:39 PM UTC 24 |
| Finished | Sep 01 12:29:41 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440537194 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2440537194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/10.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/10.edn_intr_test.2978103618 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 18185626 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 12:29:38 PM UTC 24 |
| Finished | Sep 01 12:29:41 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978103618 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2978103618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/10.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/10.edn_same_csr_outstanding.1877585738 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 13053891 ps |
| CPU time | 1.45 seconds |
| Started | Sep 01 12:29:39 PM UTC 24 |
| Finished | Sep 01 12:29:41 PM UTC 24 |
| Peak memory | 215400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877585738 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_outstanding.1877585738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/10.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_errors.1735566429 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 462750671 ps |
| CPU time | 3.22 seconds |
| Started | Sep 01 12:29:38 PM UTC 24 |
| Finished | Sep 01 12:29:43 PM UTC 24 |
| Peak memory | 227852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735566429 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1735566429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/10.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/10.edn_tl_intg_err.3183623838 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 47632292 ps |
| CPU time | 1.85 seconds |
| Started | Sep 01 12:29:38 PM UTC 24 |
| Finished | Sep 01 12:29:41 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183623838 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3183623838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/10.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.212063804 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 21282759 ps |
| CPU time | 1.97 seconds |
| Started | Sep 01 12:29:40 PM UTC 24 |
| Finished | Sep 01 12:29:43 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =212063804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.212063804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/11.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/11.edn_csr_rw.3253338219 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 14655039 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 12:29:40 PM UTC 24 |
| Finished | Sep 01 12:29:43 PM UTC 24 |
| Peak memory | 215324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253338219 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3253338219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/11.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/11.edn_intr_test.3636366706 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 13877164 ps |
| CPU time | 1.06 seconds |
| Started | Sep 01 12:29:40 PM UTC 24 |
| Finished | Sep 01 12:29:42 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636366706 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.3636366706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/11.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/11.edn_same_csr_outstanding.2594723371 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 16802943 ps |
| CPU time | 1.58 seconds |
| Started | Sep 01 12:29:40 PM UTC 24 |
| Finished | Sep 01 12:29:43 PM UTC 24 |
| Peak memory | 215400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594723371 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_outstanding.2594723371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/11.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_errors.1984926054 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 75700529 ps |
| CPU time | 3.82 seconds |
| Started | Sep 01 12:29:40 PM UTC 24 |
| Finished | Sep 01 12:29:45 PM UTC 24 |
| Peak memory | 227856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984926054 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1984926054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/11.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/11.edn_tl_intg_err.3834419538 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 72031123 ps |
| CPU time | 2.23 seconds |
| Started | Sep 01 12:29:40 PM UTC 24 |
| Finished | Sep 01 12:29:44 PM UTC 24 |
| Peak memory | 217548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834419538 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.3834419538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/11.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2663267238 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 123468711 ps |
| CPU time | 1.57 seconds |
| Started | Sep 01 12:29:41 PM UTC 24 |
| Finished | Sep 01 12:29:44 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2663267238 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.2663267238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/12.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/12.edn_csr_rw.3444493688 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 24596582 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 12:29:41 PM UTC 24 |
| Finished | Sep 01 12:29:44 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444493688 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3444493688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/12.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/12.edn_intr_test.3077190320 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 20257965 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 12:29:41 PM UTC 24 |
| Finished | Sep 01 12:29:43 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077190320 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3077190320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/12.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/12.edn_same_csr_outstanding.1079942030 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 35943764 ps |
| CPU time | 1.51 seconds |
| Started | Sep 01 12:29:41 PM UTC 24 |
| Finished | Sep 01 12:29:44 PM UTC 24 |
| Peak memory | 215400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079942030 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_outstanding.1079942030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/12.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_errors.3263152275 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 38397406 ps |
| CPU time | 3.86 seconds |
| Started | Sep 01 12:29:40 PM UTC 24 |
| Finished | Sep 01 12:29:45 PM UTC 24 |
| Peak memory | 227644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263152275 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3263152275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/12.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/12.edn_tl_intg_err.4159166952 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 88220992 ps |
| CPU time | 2.86 seconds |
| Started | Sep 01 12:29:40 PM UTC 24 |
| Finished | Sep 01 12:29:44 PM UTC 24 |
| Peak memory | 227884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159166952 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.4159166952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/12.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2797735868 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 28009601 ps |
| CPU time | 1.69 seconds |
| Started | Sep 01 12:29:43 PM UTC 24 |
| Finished | Sep 01 12:29:46 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2797735868 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2797735868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/13.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/13.edn_csr_rw.733628596 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 42979214 ps |
| CPU time | 1.39 seconds |
| Started | Sep 01 12:29:43 PM UTC 24 |
| Finished | Sep 01 12:29:45 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733628596 -assert nopostproc +UVM_TESTNAME=edn_base_ test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.733628596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/13.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/13.edn_intr_test.1995991215 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 15665304 ps |
| CPU time | 0.93 seconds |
| Started | Sep 01 12:29:43 PM UTC 24 |
| Finished | Sep 01 12:29:45 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995991215 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1995991215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/13.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/13.edn_same_csr_outstanding.2784986291 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 173918586 ps |
| CPU time | 1.94 seconds |
| Started | Sep 01 12:29:43 PM UTC 24 |
| Finished | Sep 01 12:29:46 PM UTC 24 |
| Peak memory | 215400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784986291 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_outstanding.2784986291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/13.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_errors.2297512433 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 389666102 ps |
| CPU time | 4.9 seconds |
| Started | Sep 01 12:29:41 PM UTC 24 |
| Finished | Sep 01 12:29:47 PM UTC 24 |
| Peak memory | 227856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297512433 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2297512433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/13.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/13.edn_tl_intg_err.1547044382 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 293952695 ps |
| CPU time | 2.6 seconds |
| Started | Sep 01 12:29:42 PM UTC 24 |
| Finished | Sep 01 12:29:45 PM UTC 24 |
| Peak memory | 227924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547044382 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1547044382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/13.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.4215838643 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 30600398 ps |
| CPU time | 1.5 seconds |
| Started | Sep 01 12:29:44 PM UTC 24 |
| Finished | Sep 01 12:29:47 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4215838643 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.4215838643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/14.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/14.edn_csr_rw.178507753 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 47529773 ps |
| CPU time | 1.08 seconds |
| Started | Sep 01 12:29:44 PM UTC 24 |
| Finished | Sep 01 12:29:47 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178507753 -assert nopostproc +UVM_TESTNAME=edn_base_ test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.178507753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/14.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/14.edn_intr_test.1296140085 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 202744272 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 12:29:44 PM UTC 24 |
| Finished | Sep 01 12:29:47 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296140085 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.1296140085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/14.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/14.edn_same_csr_outstanding.3745629206 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 15591189 ps |
| CPU time | 1.4 seconds |
| Started | Sep 01 12:29:44 PM UTC 24 |
| Finished | Sep 01 12:29:47 PM UTC 24 |
| Peak memory | 215400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745629206 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_outstanding.3745629206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/14.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_errors.1554206841 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 169130920 ps |
| CPU time | 2.69 seconds |
| Started | Sep 01 12:29:43 PM UTC 24 |
| Finished | Sep 01 12:29:47 PM UTC 24 |
| Peak memory | 227856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554206841 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1554206841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/14.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/14.edn_tl_intg_err.1539660281 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 59535647 ps |
| CPU time | 1.99 seconds |
| Started | Sep 01 12:29:43 PM UTC 24 |
| Finished | Sep 01 12:29:46 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539660281 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1539660281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/14.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1887733695 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 90187191 ps |
| CPU time | 1.7 seconds |
| Started | Sep 01 12:29:45 PM UTC 24 |
| Finished | Sep 01 12:29:48 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1887733695 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1887733695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/15.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/15.edn_csr_rw.4145391945 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 137732672 ps |
| CPU time | 1.41 seconds |
| Started | Sep 01 12:29:45 PM UTC 24 |
| Finished | Sep 01 12:29:48 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145391945 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.4145391945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/15.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/15.edn_intr_test.2167455681 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 24293271 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 12:29:45 PM UTC 24 |
| Finished | Sep 01 12:29:47 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167455681 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.2167455681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/15.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/15.edn_same_csr_outstanding.1454088469 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 162740037 ps |
| CPU time | 2.17 seconds |
| Started | Sep 01 12:29:45 PM UTC 24 |
| Finished | Sep 01 12:29:48 PM UTC 24 |
| Peak memory | 217696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454088469 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_outstanding.1454088469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/15.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/15.edn_tl_errors.1376328835 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 109221417 ps |
| CPU time | 5.16 seconds |
| Started | Sep 01 12:29:45 PM UTC 24 |
| Finished | Sep 01 12:29:51 PM UTC 24 |
| Peak memory | 227980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376328835 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.1376328835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/15.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1111626371 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 50056059 ps |
| CPU time | 1.88 seconds |
| Started | Sep 01 12:29:46 PM UTC 24 |
| Finished | Sep 01 12:29:50 PM UTC 24 |
| Peak memory | 225356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1111626371 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1111626371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/16.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/16.edn_csr_rw.2689791360 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 13906744 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 12:29:46 PM UTC 24 |
| Finished | Sep 01 12:29:49 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689791360 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.2689791360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/16.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/16.edn_intr_test.2043524162 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 17319530 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 12:29:46 PM UTC 24 |
| Finished | Sep 01 12:29:49 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043524162 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.2043524162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/16.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/16.edn_same_csr_outstanding.1312680811 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 125749809 ps |
| CPU time | 1.64 seconds |
| Started | Sep 01 12:29:46 PM UTC 24 |
| Finished | Sep 01 12:29:50 PM UTC 24 |
| Peak memory | 215260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312680811 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_outstanding.1312680811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/16.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_errors.1519431551 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 81031218 ps |
| CPU time | 3.44 seconds |
| Started | Sep 01 12:29:45 PM UTC 24 |
| Finished | Sep 01 12:29:50 PM UTC 24 |
| Peak memory | 227856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519431551 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1519431551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/16.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/16.edn_tl_intg_err.796512845 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 158809842 ps |
| CPU time | 3.45 seconds |
| Started | Sep 01 12:29:46 PM UTC 24 |
| Finished | Sep 01 12:29:51 PM UTC 24 |
| Peak memory | 217672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796512845 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.796512845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/16.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2856101790 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 41228044 ps |
| CPU time | 1.58 seconds |
| Started | Sep 01 12:29:48 PM UTC 24 |
| Finished | Sep 01 12:29:51 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2856101790 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2856101790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/17.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/17.edn_csr_rw.702848181 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 13549989 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 12:29:47 PM UTC 24 |
| Finished | Sep 01 12:29:49 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702848181 -assert nopostproc +UVM_TESTNAME=edn_base_ test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.702848181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/17.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/17.edn_intr_test.1078486368 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 23761639 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 12:29:46 PM UTC 24 |
| Finished | Sep 01 12:29:49 PM UTC 24 |
| Peak memory | 216852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078486368 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1078486368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/17.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/17.edn_same_csr_outstanding.1863975943 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 39577209 ps |
| CPU time | 1.93 seconds |
| Started | Sep 01 12:29:47 PM UTC 24 |
| Finished | Sep 01 12:29:50 PM UTC 24 |
| Peak memory | 215400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863975943 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_outstanding.1863975943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/17.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_errors.4124214465 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 71109061 ps |
| CPU time | 3.57 seconds |
| Started | Sep 01 12:29:46 PM UTC 24 |
| Finished | Sep 01 12:29:52 PM UTC 24 |
| Peak memory | 227524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124214465 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.4124214465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/17.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/17.edn_tl_intg_err.3565042924 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 70593207 ps |
| CPU time | 1.81 seconds |
| Started | Sep 01 12:29:46 PM UTC 24 |
| Finished | Sep 01 12:29:50 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565042924 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3565042924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/17.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3112833078 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 24199553 ps |
| CPU time | 1.69 seconds |
| Started | Sep 01 12:29:48 PM UTC 24 |
| Finished | Sep 01 12:29:51 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3112833078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3112833078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/18.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/18.edn_csr_rw.3589234029 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 26127360 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 12:29:48 PM UTC 24 |
| Finished | Sep 01 12:29:51 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589234029 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.3589234029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/18.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/18.edn_intr_test.2353620702 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 11937864 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 12:29:48 PM UTC 24 |
| Finished | Sep 01 12:29:51 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353620702 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2353620702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/18.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/18.edn_same_csr_outstanding.3428256034 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 67729696 ps |
| CPU time | 1.94 seconds |
| Started | Sep 01 12:29:48 PM UTC 24 |
| Finished | Sep 01 12:29:51 PM UTC 24 |
| Peak memory | 215400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428256034 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_outstanding.3428256034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/18.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_errors.3233113082 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 126318852 ps |
| CPU time | 4.38 seconds |
| Started | Sep 01 12:29:48 PM UTC 24 |
| Finished | Sep 01 12:29:54 PM UTC 24 |
| Peak memory | 228052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233113082 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3233113082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/18.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/18.edn_tl_intg_err.2395914819 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 141078545 ps |
| CPU time | 2.23 seconds |
| Started | Sep 01 12:29:48 PM UTC 24 |
| Finished | Sep 01 12:29:52 PM UTC 24 |
| Peak memory | 217552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395914819 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.2395914819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/18.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3506713504 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 28763941 ps |
| CPU time | 2.65 seconds |
| Started | Sep 01 12:29:50 PM UTC 24 |
| Finished | Sep 01 12:29:55 PM UTC 24 |
| Peak memory | 228052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3506713504 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3506713504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/19.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/19.edn_csr_rw.220905474 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 13027210 ps |
| CPU time | 1.17 seconds |
| Started | Sep 01 12:29:49 PM UTC 24 |
| Finished | Sep 01 12:29:51 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220905474 -assert nopostproc +UVM_TESTNAME=edn_base_ test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.220905474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/19.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/19.edn_intr_test.834537304 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 17049165 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 12:29:49 PM UTC 24 |
| Finished | Sep 01 12:29:52 PM UTC 24 |
| Peak memory | 215392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834537304 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.834537304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/19.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/19.edn_same_csr_outstanding.4121657770 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 28702763 ps |
| CPU time | 1.39 seconds |
| Started | Sep 01 12:29:50 PM UTC 24 |
| Finished | Sep 01 12:29:53 PM UTC 24 |
| Peak memory | 215400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121657770 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_outstanding.4121657770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/19.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_errors.3209864784 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 222444169 ps |
| CPU time | 4.62 seconds |
| Started | Sep 01 12:29:49 PM UTC 24 |
| Finished | Sep 01 12:29:55 PM UTC 24 |
| Peak memory | 227696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209864784 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.3209864784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/19.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/19.edn_tl_intg_err.2650543462 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 302425101 ps |
| CPU time | 2.58 seconds |
| Started | Sep 01 12:29:49 PM UTC 24 |
| Finished | Sep 01 12:29:53 PM UTC 24 |
| Peak memory | 217336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650543462 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.2650543462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/19.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_aliasing.321441862 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 71110909 ps |
| CPU time | 2.28 seconds |
| Started | Sep 01 12:29:28 PM UTC 24 |
| Finished | Sep 01 12:29:31 PM UTC 24 |
| Peak memory | 217496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321441862 -assert nopostproc +UVM_TESTNAME=edn _base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.321441862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/2.edn_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_bit_bash.2595369654 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 211472051 ps |
| CPU time | 4.99 seconds |
| Started | Sep 01 12:29:28 PM UTC 24 |
| Finished | Sep 01 12:29:34 PM UTC 24 |
| Peak memory | 217436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595369654 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2595369654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/2.edn_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_hw_reset.2636433459 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 16394949 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 12:29:27 PM UTC 24 |
| Finished | Sep 01 12:29:29 PM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636433459 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2636433459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/2.edn_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3220942904 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 52906409 ps |
| CPU time | 2.52 seconds |
| Started | Sep 01 12:29:28 PM UTC 24 |
| Finished | Sep 01 12:29:32 PM UTC 24 |
| Peak memory | 227876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3220942904 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3220942904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/2.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/2.edn_csr_rw.2360343641 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 19877337 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 12:29:28 PM UTC 24 |
| Finished | Sep 01 12:29:30 PM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360343641 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2360343641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/2.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/2.edn_intr_test.1275729828 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 17775126 ps |
| CPU time | 1.32 seconds |
| Started | Sep 01 12:29:27 PM UTC 24 |
| Finished | Sep 01 12:29:29 PM UTC 24 |
| Peak memory | 215392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275729828 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1275729828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/2.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/2.edn_same_csr_outstanding.2936541826 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 16078353 ps |
| CPU time | 1.3 seconds |
| Started | Sep 01 12:29:28 PM UTC 24 |
| Finished | Sep 01 12:29:30 PM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936541826 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_outstanding.2936541826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/2.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/2.edn_tl_errors.1903439179 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 48656858 ps |
| CPU time | 2.7 seconds |
| Started | Sep 01 12:29:26 PM UTC 24 |
| Finished | Sep 01 12:29:30 PM UTC 24 |
| Peak memory | 227872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903439179 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1903439179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/2.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/2.edn_tl_intg_err.3457429585 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 1012911806 ps |
| CPU time | 3.06 seconds |
| Started | Sep 01 12:29:27 PM UTC 24 |
| Finished | Sep 01 12:29:31 PM UTC 24 |
| Peak memory | 217556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457429585 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3457429585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/2.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/20.edn_intr_test.3899308431 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 134197280 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 12:29:51 PM UTC 24 |
| Finished | Sep 01 12:29:53 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899308431 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3899308431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/20.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/21.edn_intr_test.4076125608 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 16457100 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 12:29:51 PM UTC 24 |
| Finished | Sep 01 12:29:53 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076125608 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.4076125608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/21.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/22.edn_intr_test.974283684 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 40192432 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 12:29:51 PM UTC 24 |
| Finished | Sep 01 12:29:53 PM UTC 24 |
| Peak memory | 215392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974283684 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.974283684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/22.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/23.edn_intr_test.1547890062 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 47348613 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 12:29:51 PM UTC 24 |
| Finished | Sep 01 12:29:53 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547890062 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.1547890062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/23.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/24.edn_intr_test.3573122301 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 41600534 ps |
| CPU time | 0.93 seconds |
| Started | Sep 01 12:29:51 PM UTC 24 |
| Finished | Sep 01 12:29:53 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573122301 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3573122301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/24.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/25.edn_intr_test.2043191794 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 13323037 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 12:29:51 PM UTC 24 |
| Finished | Sep 01 12:29:53 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043191794 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2043191794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/25.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/26.edn_intr_test.2208903210 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 11751785 ps |
| CPU time | 0.94 seconds |
| Started | Sep 01 12:29:51 PM UTC 24 |
| Finished | Sep 01 12:29:53 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208903210 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2208903210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/26.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/27.edn_intr_test.1298998378 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 34597549 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 12:29:51 PM UTC 24 |
| Finished | Sep 01 12:29:53 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298998378 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1298998378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/27.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/28.edn_intr_test.3560145490 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 15789098 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 12:29:52 PM UTC 24 |
| Finished | Sep 01 12:29:54 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560145490 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.3560145490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/28.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/29.edn_intr_test.3822937174 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 24123578 ps |
| CPU time | 1.33 seconds |
| Started | Sep 01 12:29:52 PM UTC 24 |
| Finished | Sep 01 12:29:54 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822937174 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3822937174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/29.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_aliasing.1688874162 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 69505680 ps |
| CPU time | 1.79 seconds |
| Started | Sep 01 12:29:29 PM UTC 24 |
| Finished | Sep 01 12:29:32 PM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688874162 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1688874162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/3.edn_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_bit_bash.2862221605 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 1197863793 ps |
| CPU time | 7.15 seconds |
| Started | Sep 01 12:29:29 PM UTC 24 |
| Finished | Sep 01 12:29:38 PM UTC 24 |
| Peak memory | 217644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862221605 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.2862221605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/3.edn_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_hw_reset.2601815088 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 13471650 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 12:29:29 PM UTC 24 |
| Finished | Sep 01 12:29:32 PM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601815088 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2601815088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/3.edn_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3537203742 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 18868506 ps |
| CPU time | 1.45 seconds |
| Started | Sep 01 12:29:30 PM UTC 24 |
| Finished | Sep 01 12:29:32 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3537203742 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3537203742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/3.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/3.edn_csr_rw.2187726202 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 13784783 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 12:29:29 PM UTC 24 |
| Finished | Sep 01 12:29:32 PM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187726202 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2187726202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/3.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/3.edn_intr_test.3536509902 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 26861721 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 12:29:28 PM UTC 24 |
| Finished | Sep 01 12:29:30 PM UTC 24 |
| Peak memory | 215392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536509902 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3536509902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/3.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/3.edn_same_csr_outstanding.3017652107 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 32143468 ps |
| CPU time | 1.5 seconds |
| Started | Sep 01 12:29:30 PM UTC 24 |
| Finished | Sep 01 12:29:32 PM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017652107 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_outstanding.3017652107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/3.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_errors.1064520633 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 178920560 ps |
| CPU time | 4.39 seconds |
| Started | Sep 01 12:29:28 PM UTC 24 |
| Finished | Sep 01 12:29:34 PM UTC 24 |
| Peak memory | 227680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064520633 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.1064520633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/3.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/3.edn_tl_intg_err.2377197935 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 130502421 ps |
| CPU time | 3.14 seconds |
| Started | Sep 01 12:29:28 PM UTC 24 |
| Finished | Sep 01 12:29:32 PM UTC 24 |
| Peak memory | 217420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377197935 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2377197935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/3.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/30.edn_intr_test.1765086137 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 63348410 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 12:29:52 PM UTC 24 |
| Finished | Sep 01 12:29:54 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765086137 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1765086137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/30.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/31.edn_intr_test.134361959 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 36699435 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 12:29:52 PM UTC 24 |
| Finished | Sep 01 12:29:54 PM UTC 24 |
| Peak memory | 215392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134361959 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.134361959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/31.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/32.edn_intr_test.1693931135 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 14045622 ps |
| CPU time | 0.95 seconds |
| Started | Sep 01 12:29:52 PM UTC 24 |
| Finished | Sep 01 12:29:54 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693931135 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1693931135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/32.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/33.edn_intr_test.3056581568 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 26483525 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 12:29:52 PM UTC 24 |
| Finished | Sep 01 12:29:55 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056581568 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3056581568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/33.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/34.edn_intr_test.736571033 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 63817819 ps |
| CPU time | 0.91 seconds |
| Started | Sep 01 12:29:52 PM UTC 24 |
| Finished | Sep 01 12:29:54 PM UTC 24 |
| Peak memory | 215392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736571033 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.736571033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/34.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/35.edn_intr_test.130426300 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 32362973 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 12:29:52 PM UTC 24 |
| Finished | Sep 01 12:29:55 PM UTC 24 |
| Peak memory | 215392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130426300 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.130426300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/35.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/36.edn_intr_test.3581574603 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 41017946 ps |
| CPU time | 0.99 seconds |
| Started | Sep 01 12:29:52 PM UTC 24 |
| Finished | Sep 01 12:29:55 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581574603 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3581574603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/36.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/37.edn_intr_test.1969346318 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 53892156 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 12:29:53 PM UTC 24 |
| Finished | Sep 01 12:29:55 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969346318 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1969346318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/37.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/38.edn_intr_test.2206731968 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 30351182 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 12:29:53 PM UTC 24 |
| Finished | Sep 01 12:29:55 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206731968 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.2206731968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/38.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/39.edn_intr_test.3721646939 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 12611261 ps |
| CPU time | 1.3 seconds |
| Started | Sep 01 12:29:54 PM UTC 24 |
| Finished | Sep 01 12:29:56 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721646939 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3721646939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/39.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_aliasing.2641701464 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 36130550 ps |
| CPU time | 1.48 seconds |
| Started | Sep 01 12:29:31 PM UTC 24 |
| Finished | Sep 01 12:29:34 PM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641701464 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.2641701464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/4.edn_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_bit_bash.2172766572 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 63688485 ps |
| CPU time | 2.54 seconds |
| Started | Sep 01 12:29:31 PM UTC 24 |
| Finished | Sep 01 12:29:35 PM UTC 24 |
| Peak memory | 217520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172766572 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2172766572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/4.edn_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_hw_reset.1057154102 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 75976073 ps |
| CPU time | 1.4 seconds |
| Started | Sep 01 12:29:31 PM UTC 24 |
| Finished | Sep 01 12:29:33 PM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057154102 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.1057154102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/4.edn_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3997146176 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 60513345 ps |
| CPU time | 1.48 seconds |
| Started | Sep 01 12:29:32 PM UTC 24 |
| Finished | Sep 01 12:29:35 PM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3997146176 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3997146176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/4.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/4.edn_csr_rw.198763233 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 37464128 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 12:29:31 PM UTC 24 |
| Finished | Sep 01 12:29:33 PM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198763233 -assert nopostproc +UVM_TESTNAME=edn_base_ test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.198763233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/4.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/4.edn_intr_test.2816427691 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 70459763 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 12:29:30 PM UTC 24 |
| Finished | Sep 01 12:29:32 PM UTC 24 |
| Peak memory | 215392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816427691 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2816427691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/4.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/4.edn_same_csr_outstanding.904303519 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 89481249 ps |
| CPU time | 1.61 seconds |
| Started | Sep 01 12:29:31 PM UTC 24 |
| Finished | Sep 01 12:29:34 PM UTC 24 |
| Peak memory | 215460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904303519 -assert nopostproc +UVM_ TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_outstanding.904303519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/4.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_errors.460168214 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 49551229 ps |
| CPU time | 4.82 seconds |
| Started | Sep 01 12:29:30 PM UTC 24 |
| Finished | Sep 01 12:29:35 PM UTC 24 |
| Peak memory | 227924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460168214 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.460168214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/4.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/4.edn_tl_intg_err.2580072054 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 77665896 ps |
| CPU time | 2.14 seconds |
| Started | Sep 01 12:29:30 PM UTC 24 |
| Finished | Sep 01 12:29:33 PM UTC 24 |
| Peak memory | 227816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580072054 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2580072054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/4.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/40.edn_intr_test.3262456436 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 51950097 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 12:29:54 PM UTC 24 |
| Finished | Sep 01 12:29:56 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262456436 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.3262456436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/40.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/41.edn_intr_test.1805186738 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 15775255 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 12:29:54 PM UTC 24 |
| Finished | Sep 01 12:29:56 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805186738 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1805186738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/41.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/42.edn_intr_test.1961920453 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 14118832 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 12:29:54 PM UTC 24 |
| Finished | Sep 01 12:29:56 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961920453 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.1961920453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/42.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/43.edn_intr_test.2091181471 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 12875205 ps |
| CPU time | 1.04 seconds |
| Started | Sep 01 12:29:54 PM UTC 24 |
| Finished | Sep 01 12:29:56 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091181471 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2091181471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/43.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/44.edn_intr_test.1615041407 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 14389078 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 12:29:54 PM UTC 24 |
| Finished | Sep 01 12:29:56 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615041407 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.1615041407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/44.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/45.edn_intr_test.688018456 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 62576820 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 12:29:54 PM UTC 24 |
| Finished | Sep 01 12:29:56 PM UTC 24 |
| Peak memory | 215392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688018456 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.688018456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/45.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/46.edn_intr_test.1604941722 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 59127474 ps |
| CPU time | 1.07 seconds |
| Started | Sep 01 12:29:54 PM UTC 24 |
| Finished | Sep 01 12:29:56 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604941722 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1604941722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/46.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/47.edn_intr_test.3031196846 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 12241808 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 12:29:54 PM UTC 24 |
| Finished | Sep 01 12:29:56 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031196846 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.3031196846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/47.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/48.edn_intr_test.3961434194 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 31370981 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 12:29:54 PM UTC 24 |
| Finished | Sep 01 12:29:56 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961434194 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3961434194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/48.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/49.edn_intr_test.664504034 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 57797230 ps |
| CPU time | 0.94 seconds |
| Started | Sep 01 12:29:55 PM UTC 24 |
| Finished | Sep 01 12:29:57 PM UTC 24 |
| Peak memory | 215392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664504034 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.664504034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/49.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2256997324 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 114266303 ps |
| CPU time | 2.03 seconds |
| Started | Sep 01 12:29:34 PM UTC 24 |
| Finished | Sep 01 12:29:37 PM UTC 24 |
| Peak memory | 228052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2256997324 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2256997324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/5.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/5.edn_csr_rw.993388271 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 17992344 ps |
| CPU time | 1.46 seconds |
| Started | Sep 01 12:29:33 PM UTC 24 |
| Finished | Sep 01 12:29:35 PM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993388271 -assert nopostproc +UVM_TESTNAME=edn_base_ test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.993388271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/5.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/5.edn_intr_test.1523752724 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 71268505 ps |
| CPU time | 1.17 seconds |
| Started | Sep 01 12:29:33 PM UTC 24 |
| Finished | Sep 01 12:29:35 PM UTC 24 |
| Peak memory | 215300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523752724 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1523752724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/5.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/5.edn_same_csr_outstanding.104465923 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 33056523 ps |
| CPU time | 2.02 seconds |
| Started | Sep 01 12:29:33 PM UTC 24 |
| Finished | Sep 01 12:29:36 PM UTC 24 |
| Peak memory | 217684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104465923 -assert nopostproc +UVM_ TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_outstanding.104465923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/5.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_errors.1463224237 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 321762649 ps |
| CPU time | 4.21 seconds |
| Started | Sep 01 12:29:32 PM UTC 24 |
| Finished | Sep 01 12:29:38 PM UTC 24 |
| Peak memory | 227832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463224237 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.1463224237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/5.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/5.edn_tl_intg_err.2360346941 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 93179577 ps |
| CPU time | 2.25 seconds |
| Started | Sep 01 12:29:32 PM UTC 24 |
| Finished | Sep 01 12:29:36 PM UTC 24 |
| Peak memory | 227740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360346941 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2360346941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/5.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.419885429 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 68465137 ps |
| CPU time | 2.07 seconds |
| Started | Sep 01 12:29:34 PM UTC 24 |
| Finished | Sep 01 12:29:37 PM UTC 24 |
| Peak memory | 226944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =419885429 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.419885429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/6.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/6.edn_csr_rw.662773821 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 12450531 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 12:29:34 PM UTC 24 |
| Finished | Sep 01 12:29:36 PM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662773821 -assert nopostproc +UVM_TESTNAME=edn_base_ test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.662773821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/6.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/6.edn_intr_test.903524616 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 103067627 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 12:29:34 PM UTC 24 |
| Finished | Sep 01 12:29:36 PM UTC 24 |
| Peak memory | 215400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903524616 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.903524616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/6.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/6.edn_same_csr_outstanding.182927496 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 21617285 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 12:29:34 PM UTC 24 |
| Finished | Sep 01 12:29:36 PM UTC 24 |
| Peak memory | 215460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182927496 -assert nopostproc +UVM_ TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_outstanding.182927496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/6.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_errors.2990338618 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 61083248 ps |
| CPU time | 3.29 seconds |
| Started | Sep 01 12:29:34 PM UTC 24 |
| Finished | Sep 01 12:29:38 PM UTC 24 |
| Peak memory | 229900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990338618 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2990338618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/6.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/6.edn_tl_intg_err.1551070924 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 353125167 ps |
| CPU time | 5.15 seconds |
| Started | Sep 01 12:29:34 PM UTC 24 |
| Finished | Sep 01 12:29:40 PM UTC 24 |
| Peak memory | 217692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551070924 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.1551070924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/6.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.847773056 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 17537790 ps |
| CPU time | 1.52 seconds |
| Started | Sep 01 12:29:36 PM UTC 24 |
| Finished | Sep 01 12:29:38 PM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =847773056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.847773056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/7.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/7.edn_csr_rw.1540888460 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 27048428 ps |
| CPU time | 1.33 seconds |
| Started | Sep 01 12:29:35 PM UTC 24 |
| Finished | Sep 01 12:29:38 PM UTC 24 |
| Peak memory | 215184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540888460 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1540888460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/7.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/7.edn_intr_test.3394961974 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 16786051 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 12:29:35 PM UTC 24 |
| Finished | Sep 01 12:29:38 PM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394961974 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.3394961974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/7.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/7.edn_same_csr_outstanding.3111279173 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 29215420 ps |
| CPU time | 1.99 seconds |
| Started | Sep 01 12:29:35 PM UTC 24 |
| Finished | Sep 01 12:29:39 PM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111279173 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_outstanding.3111279173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/7.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/7.edn_tl_errors.1384653963 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 74481005 ps |
| CPU time | 2.74 seconds |
| Started | Sep 01 12:29:34 PM UTC 24 |
| Finished | Sep 01 12:29:38 PM UTC 24 |
| Peak memory | 227856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384653963 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.1384653963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/7.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3205360438 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 44250990 ps |
| CPU time | 2.09 seconds |
| Started | Sep 01 12:29:37 PM UTC 24 |
| Finished | Sep 01 12:29:40 PM UTC 24 |
| Peak memory | 227792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3205360438 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3205360438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/8.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/8.edn_csr_rw.2822008916 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 16992717 ps |
| CPU time | 1.08 seconds |
| Started | Sep 01 12:29:36 PM UTC 24 |
| Finished | Sep 01 12:29:38 PM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822008916 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.2822008916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/8.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/8.edn_intr_test.2100383647 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 14997444 ps |
| CPU time | 1.33 seconds |
| Started | Sep 01 12:29:36 PM UTC 24 |
| Finished | Sep 01 12:29:38 PM UTC 24 |
| Peak memory | 215392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100383647 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2100383647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/8.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/8.edn_same_csr_outstanding.3227246188 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 25886667 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 12:29:37 PM UTC 24 |
| Finished | Sep 01 12:29:39 PM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227246188 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_outstanding.3227246188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/8.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_errors.4030243061 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 178068325 ps |
| CPU time | 4.44 seconds |
| Started | Sep 01 12:29:36 PM UTC 24 |
| Finished | Sep 01 12:29:41 PM UTC 24 |
| Peak memory | 227792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030243061 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.4030243061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/8.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/8.edn_tl_intg_err.492706748 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 145701359 ps |
| CPU time | 2.41 seconds |
| Started | Sep 01 12:29:36 PM UTC 24 |
| Finished | Sep 01 12:29:39 PM UTC 24 |
| Peak memory | 217684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492706748 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.492706748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/8.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3854874896 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 57070481 ps |
| CPU time | 2.05 seconds |
| Started | Sep 01 12:29:38 PM UTC 24 |
| Finished | Sep 01 12:29:41 PM UTC 24 |
| Peak memory | 227872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb= 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3854874896 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.3854874896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/9.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/9.edn_csr_rw.2419589229 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 29401934 ps |
| CPU time | 1.44 seconds |
| Started | Sep 01 12:29:37 PM UTC 24 |
| Finished | Sep 01 12:29:40 PM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419589229 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2419589229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/9.edn_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/9.edn_intr_test.1671930549 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 17209733 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 12:29:37 PM UTC 24 |
| Finished | Sep 01 12:29:39 PM UTC 24 |
| Peak memory | 215392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671930549 -assert nopostproc +UVM_TESTNAME=edn_base_te st +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1671930549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/9.edn_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/9.edn_same_csr_outstanding.1083890015 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 63090110 ps |
| CPU time | 1.66 seconds |
| Started | Sep 01 12:29:38 PM UTC 24 |
| Finished | Sep 01 12:29:41 PM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083890015 -assert nopostproc +UVM _TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_outstanding.1083890015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/9.edn_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_errors.396580687 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 47364480 ps |
| CPU time | 2.62 seconds |
| Started | Sep 01 12:29:37 PM UTC 24 |
| Finished | Sep 01 12:29:41 PM UTC 24 |
| Peak memory | 227860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396580687 -assert nopostproc +UVM_TESTNAME=edn_base_tes t +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.396580687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/9.edn_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/cover_reg_top/9.edn_tl_intg_err.4290651182 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 100804854 ps |
| CPU time | 3.39 seconds |
| Started | Sep 01 12:29:37 PM UTC 24 |
| Finished | Sep 01 12:29:41 PM UTC 24 |
| Peak memory | 227672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290651182 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/edn-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.4290651182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/9.edn_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/0.edn_disable.2382586297 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11280033 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 09:43:48 AM UTC 24 |
| Finished | Sep 01 09:43:50 AM UTC 24 |
| Peak memory | 226376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382586297 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2382586297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/0.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/0.edn_err.414307570 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 55298889 ps |
| CPU time | 1.33 seconds |
| Started | Sep 01 09:43:48 AM UTC 24 |
| Finished | Sep 01 09:43:50 AM UTC 24 |
| Peak memory | 237144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414307570 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 0.edn_err.414307570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/0.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/0.edn_genbits.1400773594 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 53126503 ps |
| CPU time | 1.64 seconds |
| Started | Sep 01 09:43:46 AM UTC 24 |
| Finished | Sep 01 09:43:49 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400773594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1400773594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/0.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/0.edn_intr.1159238345 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 22385607 ps |
| CPU time | 1.56 seconds |
| Started | Sep 01 09:43:48 AM UTC 24 |
| Finished | Sep 01 09:43:50 AM UTC 24 |
| Peak memory | 226316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159238345 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1159238345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/0.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/0.edn_regwen.1798579860 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 20161206 ps |
| CPU time | 1.37 seconds |
| Started | Sep 01 09:43:46 AM UTC 24 |
| Finished | Sep 01 09:43:48 AM UTC 24 |
| Peak memory | 216584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798579860 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 0.edn_regwen.1798579860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/0.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/0.edn_sec_cm.1674483910 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 483726853 ps |
| CPU time | 6.28 seconds |
| Started | Sep 01 09:43:49 AM UTC 24 |
| Finished | Sep 01 09:43:57 AM UTC 24 |
| Peak memory | 262348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674483910 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1674483910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/0.edn_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/0.edn_smoke.1880631395 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 66208341 ps |
| CPU time | 1.39 seconds |
| Started | Sep 01 09:43:46 AM UTC 24 |
| Finished | Sep 01 09:43:48 AM UTC 24 |
| Peak memory | 226816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880631395 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.edn_smoke.1880631395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/0.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/1.edn_alert_test.2558183615 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 49366313 ps |
| CPU time | 1.34 seconds |
| Started | Sep 01 09:43:53 AM UTC 24 |
| Finished | Sep 01 09:43:56 AM UTC 24 |
| Peak memory | 217048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558183615 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.2558183615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/1.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/1.edn_disable.2191715148 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 37227966 ps |
| CPU time | 1.12 seconds |
| Started | Sep 01 09:43:52 AM UTC 24 |
| Finished | Sep 01 09:43:54 AM UTC 24 |
| Peak memory | 226376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191715148 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2191715148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/1.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/1.edn_err.885361741 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 26050399 ps |
| CPU time | 1.93 seconds |
| Started | Sep 01 09:43:52 AM UTC 24 |
| Finished | Sep 01 09:43:55 AM UTC 24 |
| Peak memory | 244220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885361741 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 1.edn_err.885361741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/1.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/1.edn_genbits.1684806291 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 39961585 ps |
| CPU time | 2.18 seconds |
| Started | Sep 01 09:43:49 AM UTC 24 |
| Finished | Sep 01 09:43:53 AM UTC 24 |
| Peak memory | 231780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684806291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.edn_genbits.1684806291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/1.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/1.edn_intr.4064662798 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 29122784 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 09:43:51 AM UTC 24 |
| Finished | Sep 01 09:43:53 AM UTC 24 |
| Peak memory | 226316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064662798 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.4064662798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/1.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/1.edn_regwen.3711908508 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 18403334 ps |
| CPU time | 1.49 seconds |
| Started | Sep 01 09:43:49 AM UTC 24 |
| Finished | Sep 01 09:43:52 AM UTC 24 |
| Peak memory | 216020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711908508 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 1.edn_regwen.3711908508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/1.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/1.edn_smoke.1788581689 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 43587892 ps |
| CPU time | 1.35 seconds |
| Started | Sep 01 09:43:49 AM UTC 24 |
| Finished | Sep 01 09:43:52 AM UTC 24 |
| Peak memory | 226260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788581689 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.edn_smoke.1788581689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/1.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/1.edn_stress_all.2100505499 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1765149904 ps |
| CPU time | 3.98 seconds |
| Started | Sep 01 09:43:50 AM UTC 24 |
| Finished | Sep 01 09:43:55 AM UTC 24 |
| Peak memory | 229584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100505499 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2100505499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/1.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/10.edn_alert_test.3874846783 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 74342076 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 09:44:27 AM UTC 24 |
| Finished | Sep 01 09:44:29 AM UTC 24 |
| Peak memory | 216688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874846783 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.3874846783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/10.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/10.edn_disable_auto_req_mode.88070311 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 177237099 ps |
| CPU time | 1.55 seconds |
| Started | Sep 01 09:44:27 AM UTC 24 |
| Finished | Sep 01 09:44:29 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88070311 -assert nopostproc +UVM_TESTNAME=edn_disab le_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable_auto_req_mode.88070311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/10.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/10.edn_err.1381444265 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 28637361 ps |
| CPU time | 1.46 seconds |
| Started | Sep 01 09:44:25 AM UTC 24 |
| Finished | Sep 01 09:44:28 AM UTC 24 |
| Peak memory | 228300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381444265 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 10.edn_err.1381444265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/10.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/10.edn_genbits.4182992502 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 94294005 ps |
| CPU time | 2.29 seconds |
| Started | Sep 01 09:44:24 AM UTC 24 |
| Finished | Sep 01 09:44:27 AM UTC 24 |
| Peak memory | 231572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182992502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 10.edn_genbits.4182992502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/10.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/10.edn_intr.679894883 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 33140705 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 09:44:24 AM UTC 24 |
| Finished | Sep 01 09:44:27 AM UTC 24 |
| Peak memory | 226316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679894883 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.679894883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/10.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/10.edn_smoke.3099845861 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 16214322 ps |
| CPU time | 1.39 seconds |
| Started | Sep 01 09:44:23 AM UTC 24 |
| Finished | Sep 01 09:44:25 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099845861 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 10.edn_smoke.3099845861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/10.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/10.edn_stress_all.821321277 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 682366581 ps |
| CPU time | 3.36 seconds |
| Started | Sep 01 09:44:24 AM UTC 24 |
| Finished | Sep 01 09:44:29 AM UTC 24 |
| Peak memory | 227620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821321277 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.821321277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/10.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/10.edn_stress_all_with_rand_reset.2386157320 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 6139372975 ps |
| CPU time | 84.21 seconds |
| Started | Sep 01 09:44:24 AM UTC 24 |
| Finished | Sep 01 09:45:50 AM UTC 24 |
| Peak memory | 229860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386157320 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all _with_rand_reset.2386157320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/10.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/100.edn_alert.511669816 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 77105256 ps |
| CPU time | 1.88 seconds |
| Started | Sep 01 09:49:16 AM UTC 24 |
| Finished | Sep 01 09:49:19 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511669816 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 100.edn_alert.511669816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/100.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/100.edn_genbits.3389061440 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 36776470 ps |
| CPU time | 1.91 seconds |
| Started | Sep 01 09:49:16 AM UTC 24 |
| Finished | Sep 01 09:49:19 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389061440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 100.edn_genbits.3389061440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/100.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/101.edn_genbits.235908676 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 57752212 ps |
| CPU time | 2.62 seconds |
| Started | Sep 01 09:49:16 AM UTC 24 |
| Finished | Sep 01 09:49:20 AM UTC 24 |
| Peak memory | 229436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235908676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 101.edn_genbits.235908676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/101.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/102.edn_alert.3443095990 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 108886800 ps |
| CPU time | 1.85 seconds |
| Started | Sep 01 09:49:17 AM UTC 24 |
| Finished | Sep 01 09:49:19 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443095990 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 102.edn_alert.3443095990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/102.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/102.edn_genbits.1762242821 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 37688208 ps |
| CPU time | 1.79 seconds |
| Started | Sep 01 09:49:16 AM UTC 24 |
| Finished | Sep 01 09:49:19 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762242821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 102.edn_genbits.1762242821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/102.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/103.edn_genbits.2718653241 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 52496334 ps |
| CPU time | 1.85 seconds |
| Started | Sep 01 09:49:18 AM UTC 24 |
| Finished | Sep 01 09:49:20 AM UTC 24 |
| Peak memory | 230648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718653241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2718653241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/103.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/104.edn_alert.2125516680 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 50221436 ps |
| CPU time | 1.69 seconds |
| Started | Sep 01 09:49:18 AM UTC 24 |
| Finished | Sep 01 09:49:21 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125516680 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 104.edn_alert.2125516680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/104.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/104.edn_genbits.3367646512 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 25713926 ps |
| CPU time | 1.64 seconds |
| Started | Sep 01 09:49:18 AM UTC 24 |
| Finished | Sep 01 09:49:20 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367646512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 104.edn_genbits.3367646512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/104.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/105.edn_genbits.1723605211 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 58659857 ps |
| CPU time | 2.05 seconds |
| Started | Sep 01 09:49:18 AM UTC 24 |
| Finished | Sep 01 09:49:21 AM UTC 24 |
| Peak memory | 229532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723605211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1723605211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/105.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/106.edn_alert.3855364972 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 49916314 ps |
| CPU time | 1.56 seconds |
| Started | Sep 01 09:49:20 AM UTC 24 |
| Finished | Sep 01 09:49:23 AM UTC 24 |
| Peak memory | 230452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855364972 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 106.edn_alert.3855364972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/106.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/106.edn_genbits.2181499663 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 47988855 ps |
| CPU time | 1.76 seconds |
| Started | Sep 01 09:49:19 AM UTC 24 |
| Finished | Sep 01 09:49:22 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181499663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 106.edn_genbits.2181499663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/106.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/107.edn_alert.1323026106 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 25823294 ps |
| CPU time | 1.85 seconds |
| Started | Sep 01 09:49:20 AM UTC 24 |
| Finished | Sep 01 09:49:23 AM UTC 24 |
| Peak memory | 230464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323026106 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 107.edn_alert.1323026106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/107.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/107.edn_genbits.92305597 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 39712410 ps |
| CPU time | 1.79 seconds |
| Started | Sep 01 09:49:20 AM UTC 24 |
| Finished | Sep 01 09:49:23 AM UTC 24 |
| Peak memory | 228336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92305597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn _genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 107.edn_genbits.92305597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/107.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/108.edn_alert.2335492234 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 49526066 ps |
| CPU time | 1.73 seconds |
| Started | Sep 01 09:49:20 AM UTC 24 |
| Finished | Sep 01 09:49:23 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335492234 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 108.edn_alert.2335492234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/108.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/108.edn_genbits.2714466310 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 46723112 ps |
| CPU time | 2.05 seconds |
| Started | Sep 01 09:49:20 AM UTC 24 |
| Finished | Sep 01 09:49:23 AM UTC 24 |
| Peak memory | 229520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714466310 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2714466310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/108.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/109.edn_alert.2175627552 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 24195559 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 09:49:21 AM UTC 24 |
| Finished | Sep 01 09:49:24 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175627552 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 109.edn_alert.2175627552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/109.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/109.edn_genbits.2423776967 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 47457200 ps |
| CPU time | 2.25 seconds |
| Started | Sep 01 09:49:21 AM UTC 24 |
| Finished | Sep 01 09:49:25 AM UTC 24 |
| Peak memory | 229524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423776967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 109.edn_genbits.2423776967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/109.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/11.edn_alert.2830463660 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 28929101 ps |
| CPU time | 1.63 seconds |
| Started | Sep 01 09:44:29 AM UTC 24 |
| Finished | Sep 01 09:44:32 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830463660 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 11.edn_alert.2830463660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/11.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/11.edn_alert_test.4277880731 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 21165254 ps |
| CPU time | 1.45 seconds |
| Started | Sep 01 09:44:29 AM UTC 24 |
| Finished | Sep 01 09:44:32 AM UTC 24 |
| Peak memory | 216748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277880731 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.4277880731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/11.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/11.edn_disable_auto_req_mode.3269211823 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 83553442 ps |
| CPU time | 1.67 seconds |
| Started | Sep 01 09:44:29 AM UTC 24 |
| Finished | Sep 01 09:44:32 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269211823 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable_auto_req_mode.3269211823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/11.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/11.edn_genbits.3005074207 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 27005483 ps |
| CPU time | 1.67 seconds |
| Started | Sep 01 09:44:27 AM UTC 24 |
| Finished | Sep 01 09:44:29 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005074207 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.edn_genbits.3005074207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/11.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/11.edn_intr.1375055500 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 22230675 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 09:44:28 AM UTC 24 |
| Finished | Sep 01 09:44:30 AM UTC 24 |
| Peak memory | 226320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375055500 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1375055500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/11.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/11.edn_smoke.3009638016 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 55122466 ps |
| CPU time | 1.36 seconds |
| Started | Sep 01 09:44:27 AM UTC 24 |
| Finished | Sep 01 09:44:29 AM UTC 24 |
| Peak memory | 216016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009638016 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 11.edn_smoke.3009638016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/11.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/11.edn_stress_all_with_rand_reset.3769727675 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 2847129862 ps |
| CPU time | 21.18 seconds |
| Started | Sep 01 09:44:28 AM UTC 24 |
| Finished | Sep 01 09:44:50 AM UTC 24 |
| Peak memory | 232056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769727675 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all _with_rand_reset.3769727675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/11.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/110.edn_alert.152798162 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 27219052 ps |
| CPU time | 1.88 seconds |
| Started | Sep 01 09:49:22 AM UTC 24 |
| Finished | Sep 01 09:49:24 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152798162 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 110.edn_alert.152798162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/110.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/110.edn_genbits.1441468652 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 77390797 ps |
| CPU time | 2.72 seconds |
| Started | Sep 01 09:49:22 AM UTC 24 |
| Finished | Sep 01 09:49:25 AM UTC 24 |
| Peak memory | 229520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441468652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 110.edn_genbits.1441468652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/110.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/111.edn_alert.3041137782 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 404628895 ps |
| CPU time | 1.94 seconds |
| Started | Sep 01 09:49:22 AM UTC 24 |
| Finished | Sep 01 09:49:25 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041137782 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 111.edn_alert.3041137782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/111.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/111.edn_genbits.2662457512 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 52864982 ps |
| CPU time | 1.64 seconds |
| Started | Sep 01 09:49:22 AM UTC 24 |
| Finished | Sep 01 09:49:24 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662457512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 111.edn_genbits.2662457512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/111.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/112.edn_alert.941334260 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 85549607 ps |
| CPU time | 1.6 seconds |
| Started | Sep 01 09:49:23 AM UTC 24 |
| Finished | Sep 01 09:49:26 AM UTC 24 |
| Peak memory | 226376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941334260 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 112.edn_alert.941334260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/112.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/112.edn_genbits.1044045154 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 128203693 ps |
| CPU time | 2.24 seconds |
| Started | Sep 01 09:49:23 AM UTC 24 |
| Finished | Sep 01 09:49:26 AM UTC 24 |
| Peak memory | 231572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044045154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1044045154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/112.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/113.edn_alert.2947183005 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 123635972 ps |
| CPU time | 1.83 seconds |
| Started | Sep 01 09:49:24 AM UTC 24 |
| Finished | Sep 01 09:49:27 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947183005 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 113.edn_alert.2947183005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/113.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/113.edn_genbits.1161488468 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 35747741 ps |
| CPU time | 2.04 seconds |
| Started | Sep 01 09:49:24 AM UTC 24 |
| Finished | Sep 01 09:49:27 AM UTC 24 |
| Peak memory | 229524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161488468 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 113.edn_genbits.1161488468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/113.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/114.edn_alert.1542626397 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 51374041 ps |
| CPU time | 1.81 seconds |
| Started | Sep 01 09:49:24 AM UTC 24 |
| Finished | Sep 01 09:49:27 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542626397 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 114.edn_alert.1542626397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/114.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/114.edn_genbits.1805973257 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 74762361 ps |
| CPU time | 2.17 seconds |
| Started | Sep 01 09:49:24 AM UTC 24 |
| Finished | Sep 01 09:49:28 AM UTC 24 |
| Peak memory | 231572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805973257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1805973257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/114.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/115.edn_alert.1118897606 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 24803101 ps |
| CPU time | 1.84 seconds |
| Started | Sep 01 09:49:25 AM UTC 24 |
| Finished | Sep 01 09:49:28 AM UTC 24 |
| Peak memory | 230420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118897606 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 115.edn_alert.1118897606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/115.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/115.edn_genbits.2536599977 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 54954676 ps |
| CPU time | 1.61 seconds |
| Started | Sep 01 09:49:24 AM UTC 24 |
| Finished | Sep 01 09:49:27 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536599977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 115.edn_genbits.2536599977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/115.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/116.edn_alert.3350460137 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 98255220 ps |
| CPU time | 1.81 seconds |
| Started | Sep 01 09:49:25 AM UTC 24 |
| Finished | Sep 01 09:49:28 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350460137 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 116.edn_alert.3350460137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/116.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/116.edn_genbits.4189180781 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 75048173 ps |
| CPU time | 1.61 seconds |
| Started | Sep 01 09:49:25 AM UTC 24 |
| Finished | Sep 01 09:49:28 AM UTC 24 |
| Peak memory | 228288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189180781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 116.edn_genbits.4189180781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/116.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/117.edn_alert.1172208593 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 49324338 ps |
| CPU time | 1.77 seconds |
| Started | Sep 01 09:49:26 AM UTC 24 |
| Finished | Sep 01 09:49:29 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172208593 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 117.edn_alert.1172208593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/117.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/117.edn_genbits.3992339657 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 54176382 ps |
| CPU time | 2.16 seconds |
| Started | Sep 01 09:49:25 AM UTC 24 |
| Finished | Sep 01 09:49:29 AM UTC 24 |
| Peak memory | 229460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992339657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3992339657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/117.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/118.edn_alert.1993119058 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 97204175 ps |
| CPU time | 1.85 seconds |
| Started | Sep 01 09:49:27 AM UTC 24 |
| Finished | Sep 01 09:49:30 AM UTC 24 |
| Peak memory | 226352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993119058 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 118.edn_alert.1993119058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/118.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/119.edn_alert.1228779508 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 42017081 ps |
| CPU time | 1.49 seconds |
| Started | Sep 01 09:49:28 AM UTC 24 |
| Finished | Sep 01 09:49:31 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228779508 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 119.edn_alert.1228779508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/119.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/119.edn_genbits.1983004957 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 46882418 ps |
| CPU time | 2.26 seconds |
| Started | Sep 01 09:49:27 AM UTC 24 |
| Finished | Sep 01 09:49:30 AM UTC 24 |
| Peak memory | 229724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983004957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 119.edn_genbits.1983004957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/119.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/12.edn_alert.3930876675 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 49276494 ps |
| CPU time | 1.89 seconds |
| Started | Sep 01 09:44:32 AM UTC 24 |
| Finished | Sep 01 09:44:35 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930876675 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 12.edn_alert.3930876675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/12.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/12.edn_alert_test.205871709 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 73093840 ps |
| CPU time | 1.17 seconds |
| Started | Sep 01 09:44:33 AM UTC 24 |
| Finished | Sep 01 09:44:35 AM UTC 24 |
| Peak memory | 216688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205871709 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.205871709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/12.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/12.edn_disable.38155801 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 10711238 ps |
| CPU time | 1.37 seconds |
| Started | Sep 01 09:44:33 AM UTC 24 |
| Finished | Sep 01 09:44:35 AM UTC 24 |
| Peak memory | 216136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38155801 -assert nopostproc +UVM_TESTNAME=edn_disab le_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.38155801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/12.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/12.edn_disable_auto_req_mode.2567903063 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 43301794 ps |
| CPU time | 1.84 seconds |
| Started | Sep 01 09:44:33 AM UTC 24 |
| Finished | Sep 01 09:44:36 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567903063 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable_auto_req_mode.2567903063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/12.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/12.edn_err.2209533147 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 19941584 ps |
| CPU time | 1.53 seconds |
| Started | Sep 01 09:44:32 AM UTC 24 |
| Finished | Sep 01 09:44:34 AM UTC 24 |
| Peak memory | 236976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209533147 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 12.edn_err.2209533147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/12.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/12.edn_genbits.3298918186 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 22938395 ps |
| CPU time | 1.77 seconds |
| Started | Sep 01 09:44:30 AM UTC 24 |
| Finished | Sep 01 09:44:33 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298918186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 12.edn_genbits.3298918186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/12.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/12.edn_smoke.1249450790 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 34148812 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 09:44:30 AM UTC 24 |
| Finished | Sep 01 09:44:33 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249450790 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 12.edn_smoke.1249450790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/12.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/12.edn_stress_all.624992038 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 331999415 ps |
| CPU time | 3.4 seconds |
| Started | Sep 01 09:44:30 AM UTC 24 |
| Finished | Sep 01 09:44:35 AM UTC 24 |
| Peak memory | 227592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624992038 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.624992038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/12.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/12.edn_stress_all_with_rand_reset.380638670 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 9858894433 ps |
| CPU time | 60.36 seconds |
| Started | Sep 01 09:44:31 AM UTC 24 |
| Finished | Sep 01 09:45:33 AM UTC 24 |
| Peak memory | 229816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380638670 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_ with_rand_reset.380638670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/12.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/120.edn_alert.978992005 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 29456808 ps |
| CPU time | 1.86 seconds |
| Started | Sep 01 09:49:28 AM UTC 24 |
| Finished | Sep 01 09:49:31 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978992005 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 120.edn_alert.978992005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/120.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/120.edn_genbits.3767623272 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 50797540 ps |
| CPU time | 1.84 seconds |
| Started | Sep 01 09:49:28 AM UTC 24 |
| Finished | Sep 01 09:49:31 AM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767623272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3767623272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/120.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/121.edn_alert.2531325408 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 119378135 ps |
| CPU time | 1.91 seconds |
| Started | Sep 01 09:49:29 AM UTC 24 |
| Finished | Sep 01 09:49:32 AM UTC 24 |
| Peak memory | 228392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531325408 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 121.edn_alert.2531325408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/121.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/121.edn_genbits.1349367788 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 74798849 ps |
| CPU time | 1.89 seconds |
| Started | Sep 01 09:49:28 AM UTC 24 |
| Finished | Sep 01 09:49:31 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349367788 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1349367788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/121.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/122.edn_alert.136844252 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 74897701 ps |
| CPU time | 1.61 seconds |
| Started | Sep 01 09:49:29 AM UTC 24 |
| Finished | Sep 01 09:49:32 AM UTC 24 |
| Peak memory | 226300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136844252 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 122.edn_alert.136844252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/122.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/122.edn_genbits.1437924001 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 58993229 ps |
| CPU time | 1.9 seconds |
| Started | Sep 01 09:49:29 AM UTC 24 |
| Finished | Sep 01 09:49:32 AM UTC 24 |
| Peak memory | 228560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437924001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1437924001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/122.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/123.edn_alert.3608985758 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 73812767 ps |
| CPU time | 1.77 seconds |
| Started | Sep 01 09:49:29 AM UTC 24 |
| Finished | Sep 01 09:49:32 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608985758 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 123.edn_alert.3608985758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/123.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/123.edn_genbits.2071457838 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 78032339 ps |
| CPU time | 1.92 seconds |
| Started | Sep 01 09:49:29 AM UTC 24 |
| Finished | Sep 01 09:49:32 AM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071457838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2071457838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/123.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/124.edn_alert.726292431 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 98674912 ps |
| CPU time | 1.75 seconds |
| Started | Sep 01 09:49:31 AM UTC 24 |
| Finished | Sep 01 09:49:33 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726292431 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 124.edn_alert.726292431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/124.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/124.edn_genbits.812572108 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 76317195 ps |
| CPU time | 2.06 seconds |
| Started | Sep 01 09:49:30 AM UTC 24 |
| Finished | Sep 01 09:49:34 AM UTC 24 |
| Peak memory | 231488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812572108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 124.edn_genbits.812572108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/124.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/125.edn_alert.616410198 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 85749051 ps |
| CPU time | 1.81 seconds |
| Started | Sep 01 09:49:32 AM UTC 24 |
| Finished | Sep 01 09:49:35 AM UTC 24 |
| Peak memory | 226376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616410198 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 125.edn_alert.616410198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/125.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/125.edn_genbits.538767353 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 37598486 ps |
| CPU time | 1.69 seconds |
| Started | Sep 01 09:49:31 AM UTC 24 |
| Finished | Sep 01 09:49:33 AM UTC 24 |
| Peak memory | 230416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538767353 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 125.edn_genbits.538767353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/125.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/126.edn_alert.406235102 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 98504267 ps |
| CPU time | 1.6 seconds |
| Started | Sep 01 09:49:32 AM UTC 24 |
| Finished | Sep 01 09:49:35 AM UTC 24 |
| Peak memory | 226376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406235102 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 126.edn_alert.406235102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/126.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/126.edn_genbits.3822084279 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 65622429 ps |
| CPU time | 1.41 seconds |
| Started | Sep 01 09:49:32 AM UTC 24 |
| Finished | Sep 01 09:49:34 AM UTC 24 |
| Peak memory | 228244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822084279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3822084279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/126.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/127.edn_alert.2850581337 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 100817292 ps |
| CPU time | 1.5 seconds |
| Started | Sep 01 09:49:32 AM UTC 24 |
| Finished | Sep 01 09:49:35 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850581337 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 127.edn_alert.2850581337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/127.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/127.edn_genbits.1138188775 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 50212536 ps |
| CPU time | 2.86 seconds |
| Started | Sep 01 09:49:32 AM UTC 24 |
| Finished | Sep 01 09:49:36 AM UTC 24 |
| Peak memory | 229448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138188775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 127.edn_genbits.1138188775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/127.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/128.edn_alert.2161842921 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 118218451 ps |
| CPU time | 1.69 seconds |
| Started | Sep 01 09:49:33 AM UTC 24 |
| Finished | Sep 01 09:49:36 AM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161842921 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 128.edn_alert.2161842921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/128.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/128.edn_genbits.3546331304 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 71973469 ps |
| CPU time | 1.57 seconds |
| Started | Sep 01 09:49:33 AM UTC 24 |
| Finished | Sep 01 09:49:36 AM UTC 24 |
| Peak memory | 230384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546331304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 128.edn_genbits.3546331304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/128.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/129.edn_alert.3762653020 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 75413414 ps |
| CPU time | 1.66 seconds |
| Started | Sep 01 09:49:33 AM UTC 24 |
| Finished | Sep 01 09:49:36 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762653020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 129.edn_alert.3762653020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/129.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/129.edn_genbits.1610664829 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 33694870 ps |
| CPU time | 1.54 seconds |
| Started | Sep 01 09:49:33 AM UTC 24 |
| Finished | Sep 01 09:49:36 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610664829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 129.edn_genbits.1610664829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/129.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/13.edn_alert_test.2441225074 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 114938245 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 09:44:37 AM UTC 24 |
| Finished | Sep 01 09:44:39 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441225074 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2441225074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/13.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/13.edn_disable.727577171 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 16987525 ps |
| CPU time | 1.02 seconds |
| Started | Sep 01 09:44:37 AM UTC 24 |
| Finished | Sep 01 09:44:39 AM UTC 24 |
| Peak memory | 216136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727577171 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.727577171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/13.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/13.edn_disable_auto_req_mode.2362827988 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 217427597 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 09:44:37 AM UTC 24 |
| Finished | Sep 01 09:44:39 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362827988 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable_auto_req_mode.2362827988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/13.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/13.edn_err.309566421 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 181745435 ps |
| CPU time | 1.37 seconds |
| Started | Sep 01 09:44:37 AM UTC 24 |
| Finished | Sep 01 09:44:39 AM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309566421 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 13.edn_err.309566421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/13.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/13.edn_intr.479774084 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 39158875 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 09:44:35 AM UTC 24 |
| Finished | Sep 01 09:44:38 AM UTC 24 |
| Peak memory | 226316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479774084 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.479774084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/13.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/13.edn_smoke.4291958159 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 20562232 ps |
| CPU time | 1.36 seconds |
| Started | Sep 01 09:44:34 AM UTC 24 |
| Finished | Sep 01 09:44:36 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291958159 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 13.edn_smoke.4291958159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/13.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/13.edn_stress_all.2542823701 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 124297660 ps |
| CPU time | 3.38 seconds |
| Started | Sep 01 09:44:35 AM UTC 24 |
| Finished | Sep 01 09:44:39 AM UTC 24 |
| Peak memory | 229524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542823701 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.2542823701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/13.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/130.edn_alert.3469939308 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 35783253 ps |
| CPU time | 1.63 seconds |
| Started | Sep 01 09:49:34 AM UTC 24 |
| Finished | Sep 01 09:49:37 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469939308 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 130.edn_alert.3469939308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/130.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/130.edn_genbits.321769836 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 50590381 ps |
| CPU time | 1.59 seconds |
| Started | Sep 01 09:49:33 AM UTC 24 |
| Finished | Sep 01 09:49:36 AM UTC 24 |
| Peak memory | 230688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321769836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 130.edn_genbits.321769836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/130.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/131.edn_alert.1736636938 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 80947387 ps |
| CPU time | 1.71 seconds |
| Started | Sep 01 09:49:34 AM UTC 24 |
| Finished | Sep 01 09:49:37 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736636938 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 131.edn_alert.1736636938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/131.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/131.edn_genbits.1214401667 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 24568021 ps |
| CPU time | 1.57 seconds |
| Started | Sep 01 09:49:34 AM UTC 24 |
| Finished | Sep 01 09:49:37 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214401667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 131.edn_genbits.1214401667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/131.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/132.edn_alert.4108548852 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 233616619 ps |
| CPU time | 1.97 seconds |
| Started | Sep 01 09:49:36 AM UTC 24 |
| Finished | Sep 01 09:49:39 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108548852 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 132.edn_alert.4108548852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/132.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/132.edn_genbits.2802118462 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 57398429 ps |
| CPU time | 1.8 seconds |
| Started | Sep 01 09:49:35 AM UTC 24 |
| Finished | Sep 01 09:49:39 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802118462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2802118462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/132.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/133.edn_alert.3775572025 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 42827252 ps |
| CPU time | 1.68 seconds |
| Started | Sep 01 09:49:36 AM UTC 24 |
| Finished | Sep 01 09:49:39 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775572025 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 133.edn_alert.3775572025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/133.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/133.edn_genbits.833135500 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 43969625 ps |
| CPU time | 2.21 seconds |
| Started | Sep 01 09:49:36 AM UTC 24 |
| Finished | Sep 01 09:49:39 AM UTC 24 |
| Peak memory | 229448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833135500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 133.edn_genbits.833135500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/133.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/134.edn_alert.3255297802 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 24036366 ps |
| CPU time | 1.66 seconds |
| Started | Sep 01 09:49:37 AM UTC 24 |
| Finished | Sep 01 09:49:40 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255297802 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 134.edn_alert.3255297802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/134.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/134.edn_genbits.562265657 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 55935493 ps |
| CPU time | 1.72 seconds |
| Started | Sep 01 09:49:37 AM UTC 24 |
| Finished | Sep 01 09:49:40 AM UTC 24 |
| Peak memory | 230416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562265657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 134.edn_genbits.562265657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/134.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/135.edn_alert.1883547443 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 21867073 ps |
| CPU time | 1.57 seconds |
| Started | Sep 01 09:49:37 AM UTC 24 |
| Finished | Sep 01 09:49:40 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883547443 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 135.edn_alert.1883547443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/135.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/135.edn_genbits.3571610510 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 90266271 ps |
| CPU time | 2.24 seconds |
| Started | Sep 01 09:49:37 AM UTC 24 |
| Finished | Sep 01 09:49:40 AM UTC 24 |
| Peak memory | 231572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571610510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 135.edn_genbits.3571610510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/135.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/136.edn_alert.1145467280 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 70811406 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 09:49:37 AM UTC 24 |
| Finished | Sep 01 09:49:39 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145467280 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 136.edn_alert.1145467280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/136.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/136.edn_genbits.3133016783 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 99910647 ps |
| CPU time | 2.02 seconds |
| Started | Sep 01 09:49:37 AM UTC 24 |
| Finished | Sep 01 09:49:40 AM UTC 24 |
| Peak memory | 231592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133016783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3133016783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/136.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/137.edn_alert.162035254 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 23524853 ps |
| CPU time | 1.57 seconds |
| Started | Sep 01 09:49:38 AM UTC 24 |
| Finished | Sep 01 09:49:41 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162035254 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 137.edn_alert.162035254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/137.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/137.edn_genbits.3355193640 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 53619820 ps |
| CPU time | 1.75 seconds |
| Started | Sep 01 09:49:38 AM UTC 24 |
| Finished | Sep 01 09:49:41 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355193640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 137.edn_genbits.3355193640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/137.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/138.edn_alert.2282548360 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 28453267 ps |
| CPU time | 1.63 seconds |
| Started | Sep 01 09:49:39 AM UTC 24 |
| Finished | Sep 01 09:49:42 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282548360 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 138.edn_alert.2282548360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/138.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/138.edn_genbits.2661475082 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 100148478 ps |
| CPU time | 2.5 seconds |
| Started | Sep 01 09:49:38 AM UTC 24 |
| Finished | Sep 01 09:49:42 AM UTC 24 |
| Peak memory | 229444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661475082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 138.edn_genbits.2661475082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/138.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/139.edn_alert.2960398380 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 295507861 ps |
| CPU time | 1.91 seconds |
| Started | Sep 01 09:49:39 AM UTC 24 |
| Finished | Sep 01 09:49:42 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960398380 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 139.edn_alert.2960398380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/139.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/139.edn_genbits.1745872941 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 360539216 ps |
| CPU time | 5.75 seconds |
| Started | Sep 01 09:49:39 AM UTC 24 |
| Finished | Sep 01 09:49:46 AM UTC 24 |
| Peak memory | 231588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745872941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1745872941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/139.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/14.edn_alert_test.3726026526 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 28615489 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 09:44:41 AM UTC 24 |
| Finished | Sep 01 09:44:43 AM UTC 24 |
| Peak memory | 216244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726026526 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3726026526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/14.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/14.edn_disable.2624201866 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 29136743 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 09:44:41 AM UTC 24 |
| Finished | Sep 01 09:44:43 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624201866 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.2624201866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/14.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/14.edn_err.4283194860 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 29793439 ps |
| CPU time | 1.52 seconds |
| Started | Sep 01 09:44:41 AM UTC 24 |
| Finished | Sep 01 09:44:43 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283194860 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 14.edn_err.4283194860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/14.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/14.edn_intr.3746473548 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 37274054 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 09:44:39 AM UTC 24 |
| Finished | Sep 01 09:44:41 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746473548 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3746473548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/14.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/14.edn_smoke.971019209 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 23685989 ps |
| CPU time | 1.39 seconds |
| Started | Sep 01 09:44:37 AM UTC 24 |
| Finished | Sep 01 09:44:39 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971019209 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 14.edn_smoke.971019209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/14.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/14.edn_stress_all.3084165012 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 830662823 ps |
| CPU time | 7.3 seconds |
| Started | Sep 01 09:44:38 AM UTC 24 |
| Finished | Sep 01 09:44:46 AM UTC 24 |
| Peak memory | 227496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084165012 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3084165012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/14.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/14.edn_stress_all_with_rand_reset.3960659998 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 10485968929 ps |
| CPU time | 88.77 seconds |
| Started | Sep 01 09:44:39 AM UTC 24 |
| Finished | Sep 01 09:46:10 AM UTC 24 |
| Peak memory | 234144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960659998 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all _with_rand_reset.3960659998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/14.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/140.edn_alert.1901134823 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 125716746 ps |
| CPU time | 1.68 seconds |
| Started | Sep 01 09:49:41 AM UTC 24 |
| Finished | Sep 01 09:49:43 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901134823 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 140.edn_alert.1901134823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/140.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/141.edn_alert.2816582582 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 33610821 ps |
| CPU time | 1.9 seconds |
| Started | Sep 01 09:49:41 AM UTC 24 |
| Finished | Sep 01 09:49:44 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816582582 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 141.edn_alert.2816582582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/141.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/141.edn_genbits.890181851 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 29332048 ps |
| CPU time | 1.82 seconds |
| Started | Sep 01 09:49:41 AM UTC 24 |
| Finished | Sep 01 09:49:44 AM UTC 24 |
| Peak memory | 228564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890181851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 141.edn_genbits.890181851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/141.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/142.edn_alert.4027758455 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 23033015 ps |
| CPU time | 1.67 seconds |
| Started | Sep 01 09:49:41 AM UTC 24 |
| Finished | Sep 01 09:49:44 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027758455 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 142.edn_alert.4027758455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/142.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/142.edn_genbits.2882983704 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 57155965 ps |
| CPU time | 2.21 seconds |
| Started | Sep 01 09:49:41 AM UTC 24 |
| Finished | Sep 01 09:49:44 AM UTC 24 |
| Peak memory | 229468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882983704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2882983704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/142.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/143.edn_alert.1477441893 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 67437131 ps |
| CPU time | 1.75 seconds |
| Started | Sep 01 09:49:42 AM UTC 24 |
| Finished | Sep 01 09:49:45 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477441893 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 143.edn_alert.1477441893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/143.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/143.edn_genbits.509899446 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 48993241 ps |
| CPU time | 2.17 seconds |
| Started | Sep 01 09:49:41 AM UTC 24 |
| Finished | Sep 01 09:49:44 AM UTC 24 |
| Peak memory | 227672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509899446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 143.edn_genbits.509899446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/143.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/144.edn_alert.4294539350 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 89941546 ps |
| CPU time | 1.6 seconds |
| Started | Sep 01 09:49:43 AM UTC 24 |
| Finished | Sep 01 09:49:46 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294539350 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 144.edn_alert.4294539350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/144.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/144.edn_genbits.4109305702 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 174614330 ps |
| CPU time | 2.14 seconds |
| Started | Sep 01 09:49:42 AM UTC 24 |
| Finished | Sep 01 09:49:45 AM UTC 24 |
| Peak memory | 229452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109305702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 144.edn_genbits.4109305702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/144.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/145.edn_alert.2667800517 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 25918785 ps |
| CPU time | 1.8 seconds |
| Started | Sep 01 09:49:43 AM UTC 24 |
| Finished | Sep 01 09:49:46 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667800517 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 145.edn_alert.2667800517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/145.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/145.edn_genbits.1105578168 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 32608051 ps |
| CPU time | 1.84 seconds |
| Started | Sep 01 09:49:43 AM UTC 24 |
| Finished | Sep 01 09:49:46 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105578168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1105578168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/145.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/146.edn_genbits.3628742832 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 74679423 ps |
| CPU time | 1.47 seconds |
| Started | Sep 01 09:49:44 AM UTC 24 |
| Finished | Sep 01 09:49:47 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628742832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3628742832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/146.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/147.edn_alert.1174334848 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 141955764 ps |
| CPU time | 1.63 seconds |
| Started | Sep 01 09:49:45 AM UTC 24 |
| Finished | Sep 01 09:49:47 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174334848 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 147.edn_alert.1174334848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/147.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/147.edn_genbits.2191312870 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 38598210 ps |
| CPU time | 1.96 seconds |
| Started | Sep 01 09:49:44 AM UTC 24 |
| Finished | Sep 01 09:49:47 AM UTC 24 |
| Peak memory | 228560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191312870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 147.edn_genbits.2191312870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/147.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/148.edn_alert.1834444660 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 37536880 ps |
| CPU time | 1.54 seconds |
| Started | Sep 01 09:49:45 AM UTC 24 |
| Finished | Sep 01 09:49:47 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834444660 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 148.edn_alert.1834444660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/148.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/148.edn_genbits.2218570710 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 53849047 ps |
| CPU time | 2.22 seconds |
| Started | Sep 01 09:49:45 AM UTC 24 |
| Finished | Sep 01 09:49:48 AM UTC 24 |
| Peak memory | 229452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218570710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2218570710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/148.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/149.edn_alert.4057238785 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 34826558 ps |
| CPU time | 1.53 seconds |
| Started | Sep 01 09:49:46 AM UTC 24 |
| Finished | Sep 01 09:49:48 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057238785 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 149.edn_alert.4057238785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/149.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/149.edn_genbits.3758703521 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 120927701 ps |
| CPU time | 2.37 seconds |
| Started | Sep 01 09:49:46 AM UTC 24 |
| Finished | Sep 01 09:49:49 AM UTC 24 |
| Peak memory | 231584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758703521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 149.edn_genbits.3758703521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/149.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/15.edn_alert.1725359281 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 43686443 ps |
| CPU time | 1.85 seconds |
| Started | Sep 01 09:44:43 AM UTC 24 |
| Finished | Sep 01 09:44:46 AM UTC 24 |
| Peak memory | 232736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725359281 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 15.edn_alert.1725359281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/15.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/15.edn_alert_test.1259992024 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 71412028 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 09:44:45 AM UTC 24 |
| Finished | Sep 01 09:44:47 AM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259992024 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.1259992024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/15.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/15.edn_disable_auto_req_mode.2443827137 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 50973635 ps |
| CPU time | 1.61 seconds |
| Started | Sep 01 09:44:45 AM UTC 24 |
| Finished | Sep 01 09:44:47 AM UTC 24 |
| Peak memory | 228252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443827137 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable_auto_req_mode.2443827137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/15.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/15.edn_err.924431847 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 21128823 ps |
| CPU time | 1.56 seconds |
| Started | Sep 01 09:44:45 AM UTC 24 |
| Finished | Sep 01 09:44:47 AM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924431847 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 15.edn_err.924431847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/15.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/15.edn_genbits.1528581017 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 35296836 ps |
| CPU time | 1.79 seconds |
| Started | Sep 01 09:44:41 AM UTC 24 |
| Finished | Sep 01 09:44:44 AM UTC 24 |
| Peak memory | 230608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528581017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1528581017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/15.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/15.edn_intr.101257887 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 24277295 ps |
| CPU time | 1.5 seconds |
| Started | Sep 01 09:44:43 AM UTC 24 |
| Finished | Sep 01 09:44:46 AM UTC 24 |
| Peak memory | 237820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101257887 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.101257887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/15.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/15.edn_smoke.46625991 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 17660863 ps |
| CPU time | 1.4 seconds |
| Started | Sep 01 09:44:41 AM UTC 24 |
| Finished | Sep 01 09:44:44 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46625991 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.46625991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/15.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/15.edn_stress_all.2431357224 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1759240219 ps |
| CPU time | 5.76 seconds |
| Started | Sep 01 09:44:42 AM UTC 24 |
| Finished | Sep 01 09:44:49 AM UTC 24 |
| Peak memory | 229528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431357224 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2431357224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/15.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/15.edn_stress_all_with_rand_reset.408065719 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 3568463161 ps |
| CPU time | 88.31 seconds |
| Started | Sep 01 09:44:42 AM UTC 24 |
| Finished | Sep 01 09:46:13 AM UTC 24 |
| Peak memory | 229992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408065719 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_ with_rand_reset.408065719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/15.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/150.edn_alert.4097840906 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 24924345 ps |
| CPU time | 1.68 seconds |
| Started | Sep 01 09:49:47 AM UTC 24 |
| Finished | Sep 01 09:49:50 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097840906 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 150.edn_alert.4097840906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/150.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/150.edn_genbits.1645242408 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 65786766 ps |
| CPU time | 1.74 seconds |
| Started | Sep 01 09:49:46 AM UTC 24 |
| Finished | Sep 01 09:49:49 AM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645242408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 150.edn_genbits.1645242408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/150.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/151.edn_alert.4113918189 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 36117857 ps |
| CPU time | 1.55 seconds |
| Started | Sep 01 09:49:47 AM UTC 24 |
| Finished | Sep 01 09:49:50 AM UTC 24 |
| Peak memory | 230452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113918189 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 151.edn_alert.4113918189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/151.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/151.edn_genbits.2266402365 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 143173574 ps |
| CPU time | 1.62 seconds |
| Started | Sep 01 09:49:47 AM UTC 24 |
| Finished | Sep 01 09:49:50 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266402365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 151.edn_genbits.2266402365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/151.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/152.edn_alert.452121601 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 28218956 ps |
| CPU time | 1.86 seconds |
| Started | Sep 01 09:49:48 AM UTC 24 |
| Finished | Sep 01 09:49:51 AM UTC 24 |
| Peak memory | 230248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452121601 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 152.edn_alert.452121601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/152.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/152.edn_genbits.42055711 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 40912260 ps |
| CPU time | 1.54 seconds |
| Started | Sep 01 09:49:47 AM UTC 24 |
| Finished | Sep 01 09:49:50 AM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42055711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn _genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 152.edn_genbits.42055711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/152.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/153.edn_alert.2074694060 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 42836664 ps |
| CPU time | 1.71 seconds |
| Started | Sep 01 09:49:48 AM UTC 24 |
| Finished | Sep 01 09:49:51 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074694060 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 153.edn_alert.2074694060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/153.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/153.edn_genbits.4135014748 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 121009418 ps |
| CPU time | 1.97 seconds |
| Started | Sep 01 09:49:48 AM UTC 24 |
| Finished | Sep 01 09:49:51 AM UTC 24 |
| Peak memory | 230204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135014748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 153.edn_genbits.4135014748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/153.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/154.edn_alert.3700875702 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 23965996 ps |
| CPU time | 1.62 seconds |
| Started | Sep 01 09:49:48 AM UTC 24 |
| Finished | Sep 01 09:49:51 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700875702 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 154.edn_alert.3700875702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/154.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/154.edn_genbits.661022737 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 54767764 ps |
| CPU time | 1.86 seconds |
| Started | Sep 01 09:49:48 AM UTC 24 |
| Finished | Sep 01 09:49:51 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661022737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 154.edn_genbits.661022737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/154.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/155.edn_alert.2422722118 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 46611184 ps |
| CPU time | 1.32 seconds |
| Started | Sep 01 09:49:50 AM UTC 24 |
| Finished | Sep 01 09:49:52 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422722118 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 155.edn_alert.2422722118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/155.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/155.edn_genbits.4024762226 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 38310010 ps |
| CPU time | 1.87 seconds |
| Started | Sep 01 09:49:49 AM UTC 24 |
| Finished | Sep 01 09:49:51 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024762226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 155.edn_genbits.4024762226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/155.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/156.edn_genbits.204876854 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 32461489 ps |
| CPU time | 1.98 seconds |
| Started | Sep 01 09:49:50 AM UTC 24 |
| Finished | Sep 01 09:49:53 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204876854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 156.edn_genbits.204876854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/156.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/157.edn_alert.487912758 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 28369115 ps |
| CPU time | 1.93 seconds |
| Started | Sep 01 09:49:51 AM UTC 24 |
| Finished | Sep 01 09:49:54 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487912758 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 157.edn_alert.487912758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/157.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/157.edn_genbits.565255129 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 27372761 ps |
| CPU time | 1.71 seconds |
| Started | Sep 01 09:49:51 AM UTC 24 |
| Finished | Sep 01 09:49:54 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565255129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 157.edn_genbits.565255129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/157.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/158.edn_alert.37817514 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 42749967 ps |
| CPU time | 1.82 seconds |
| Started | Sep 01 09:49:51 AM UTC 24 |
| Finished | Sep 01 09:49:54 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37817514 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.37817514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/158.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/158.edn_genbits.1929227096 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 38069672 ps |
| CPU time | 2.52 seconds |
| Started | Sep 01 09:49:51 AM UTC 24 |
| Finished | Sep 01 09:49:55 AM UTC 24 |
| Peak memory | 229588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929227096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1929227096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/158.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/159.edn_alert.999535794 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 26783270 ps |
| CPU time | 1.65 seconds |
| Started | Sep 01 09:50:03 AM UTC 24 |
| Finished | Sep 01 09:50:06 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999535794 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 159.edn_alert.999535794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/159.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/159.edn_genbits.3856970012 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 29068699 ps |
| CPU time | 2.02 seconds |
| Started | Sep 01 09:50:03 AM UTC 24 |
| Finished | Sep 01 09:50:06 AM UTC 24 |
| Peak memory | 231580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856970012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3856970012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/159.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/16.edn_alert.732694050 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 28738716 ps |
| CPU time | 1.74 seconds |
| Started | Sep 01 09:44:48 AM UTC 24 |
| Finished | Sep 01 09:44:51 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732694050 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 16.edn_alert.732694050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/16.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/16.edn_alert_test.3446007383 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 24239170 ps |
| CPU time | 1.43 seconds |
| Started | Sep 01 09:44:48 AM UTC 24 |
| Finished | Sep 01 09:44:51 AM UTC 24 |
| Peak memory | 216528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446007383 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3446007383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/16.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/16.edn_disable_auto_req_mode.3517093276 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 93499032 ps |
| CPU time | 1.59 seconds |
| Started | Sep 01 09:44:48 AM UTC 24 |
| Finished | Sep 01 09:44:51 AM UTC 24 |
| Peak memory | 230348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517093276 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable_auto_req_mode.3517093276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/16.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/16.edn_err.4013686370 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 23942406 ps |
| CPU time | 1.53 seconds |
| Started | Sep 01 09:44:48 AM UTC 24 |
| Finished | Sep 01 09:44:51 AM UTC 24 |
| Peak memory | 237156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013686370 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 16.edn_err.4013686370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/16.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/16.edn_intr.1657012458 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 22719229 ps |
| CPU time | 1.49 seconds |
| Started | Sep 01 09:44:47 AM UTC 24 |
| Finished | Sep 01 09:44:50 AM UTC 24 |
| Peak memory | 226320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657012458 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.1657012458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/16.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/16.edn_smoke.3565741470 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 68657110 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 09:44:45 AM UTC 24 |
| Finished | Sep 01 09:44:47 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565741470 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 16.edn_smoke.3565741470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/16.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/16.edn_stress_all.2217340009 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 2584985509 ps |
| CPU time | 7.95 seconds |
| Started | Sep 01 09:44:47 AM UTC 24 |
| Finished | Sep 01 09:44:56 AM UTC 24 |
| Peak memory | 227800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217340009 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2217340009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/16.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/160.edn_genbits.2430986192 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 293840132 ps |
| CPU time | 1.77 seconds |
| Started | Sep 01 09:50:03 AM UTC 24 |
| Finished | Sep 01 09:50:06 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430986192 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 160.edn_genbits.2430986192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/160.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/161.edn_alert.3677144069 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 43455443 ps |
| CPU time | 1.65 seconds |
| Started | Sep 01 09:50:04 AM UTC 24 |
| Finished | Sep 01 09:50:06 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677144069 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 161.edn_alert.3677144069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/161.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/161.edn_genbits.3300947615 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 71965081 ps |
| CPU time | 1.64 seconds |
| Started | Sep 01 09:50:04 AM UTC 24 |
| Finished | Sep 01 09:50:06 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300947615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 161.edn_genbits.3300947615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/161.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/162.edn_alert.769963466 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 104922649 ps |
| CPU time | 1.83 seconds |
| Started | Sep 01 09:50:04 AM UTC 24 |
| Finished | Sep 01 09:50:07 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769963466 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 162.edn_alert.769963466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/162.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/162.edn_genbits.1374856320 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 57597625 ps |
| CPU time | 1.86 seconds |
| Started | Sep 01 09:50:04 AM UTC 24 |
| Finished | Sep 01 09:50:07 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374856320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1374856320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/162.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/163.edn_alert.1848904362 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 53174027 ps |
| CPU time | 1.79 seconds |
| Started | Sep 01 09:50:04 AM UTC 24 |
| Finished | Sep 01 09:50:07 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848904362 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 163.edn_alert.1848904362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/163.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/163.edn_genbits.1740313316 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 49393012 ps |
| CPU time | 1.71 seconds |
| Started | Sep 01 09:50:04 AM UTC 24 |
| Finished | Sep 01 09:50:07 AM UTC 24 |
| Peak memory | 228356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740313316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1740313316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/163.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/164.edn_alert.1792841224 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 130766650 ps |
| CPU time | 1.53 seconds |
| Started | Sep 01 09:50:04 AM UTC 24 |
| Finished | Sep 01 09:50:06 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792841224 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 164.edn_alert.1792841224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/164.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/164.edn_genbits.3301746018 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 42571777 ps |
| CPU time | 2 seconds |
| Started | Sep 01 09:50:04 AM UTC 24 |
| Finished | Sep 01 09:50:07 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301746018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3301746018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/164.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/165.edn_alert.4293035206 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 72881823 ps |
| CPU time | 1.63 seconds |
| Started | Sep 01 09:50:04 AM UTC 24 |
| Finished | Sep 01 09:50:07 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293035206 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 165.edn_alert.4293035206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/165.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/165.edn_genbits.1591681985 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 78982355 ps |
| CPU time | 2.05 seconds |
| Started | Sep 01 09:50:04 AM UTC 24 |
| Finished | Sep 01 09:50:07 AM UTC 24 |
| Peak memory | 231588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591681985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1591681985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/165.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/166.edn_alert.494261805 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 52737472 ps |
| CPU time | 1.59 seconds |
| Started | Sep 01 09:50:07 AM UTC 24 |
| Finished | Sep 01 09:50:10 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494261805 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 166.edn_alert.494261805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/166.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/166.edn_genbits.3719328894 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 142648066 ps |
| CPU time | 1.62 seconds |
| Started | Sep 01 09:50:07 AM UTC 24 |
| Finished | Sep 01 09:50:10 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719328894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 166.edn_genbits.3719328894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/166.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/167.edn_alert.3979293758 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 60784491 ps |
| CPU time | 1.71 seconds |
| Started | Sep 01 09:50:07 AM UTC 24 |
| Finished | Sep 01 09:50:10 AM UTC 24 |
| Peak memory | 230436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979293758 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 167.edn_alert.3979293758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/167.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/167.edn_genbits.120468361 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 79227142 ps |
| CPU time | 1.84 seconds |
| Started | Sep 01 09:50:07 AM UTC 24 |
| Finished | Sep 01 09:50:10 AM UTC 24 |
| Peak memory | 230416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120468361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 167.edn_genbits.120468361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/167.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/168.edn_genbits.1403412172 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 172331632 ps |
| CPU time | 3.17 seconds |
| Started | Sep 01 09:50:07 AM UTC 24 |
| Finished | Sep 01 09:50:12 AM UTC 24 |
| Peak memory | 231720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403412172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1403412172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/168.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/169.edn_alert.3635644511 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 390775814 ps |
| CPU time | 2.19 seconds |
| Started | Sep 01 09:50:08 AM UTC 24 |
| Finished | Sep 01 09:50:11 AM UTC 24 |
| Peak memory | 228020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635644511 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 169.edn_alert.3635644511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/169.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/169.edn_genbits.2765552273 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 60428496 ps |
| CPU time | 2.43 seconds |
| Started | Sep 01 09:50:08 AM UTC 24 |
| Finished | Sep 01 09:50:11 AM UTC 24 |
| Peak memory | 229524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765552273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2765552273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/169.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/17.edn_alert.1559083181 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 140848377 ps |
| CPU time | 1.81 seconds |
| Started | Sep 01 09:44:52 AM UTC 24 |
| Finished | Sep 01 09:44:55 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559083181 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 17.edn_alert.1559083181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/17.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/17.edn_alert_test.31275973 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 15366797 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 09:44:53 AM UTC 24 |
| Finished | Sep 01 09:44:55 AM UTC 24 |
| Peak memory | 217168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31275973 -assert nopostproc +UVM_TESTNAME=edn_base _test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.31275973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/17.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/17.edn_disable.1786344581 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 22105188 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 09:44:52 AM UTC 24 |
| Finished | Sep 01 09:44:54 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786344581 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.1786344581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/17.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/17.edn_disable_auto_req_mode.400925465 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 55972751 ps |
| CPU time | 1.57 seconds |
| Started | Sep 01 09:44:52 AM UTC 24 |
| Finished | Sep 01 09:44:55 AM UTC 24 |
| Peak memory | 228300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400925465 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable_auto_req_mode.400925465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/17.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/17.edn_err.3339992726 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 20335094 ps |
| CPU time | 1.5 seconds |
| Started | Sep 01 09:44:52 AM UTC 24 |
| Finished | Sep 01 09:44:55 AM UTC 24 |
| Peak memory | 230408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339992726 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 17.edn_err.3339992726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/17.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/17.edn_genbits.3854632099 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 30867498 ps |
| CPU time | 1.81 seconds |
| Started | Sep 01 09:44:51 AM UTC 24 |
| Finished | Sep 01 09:44:53 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854632099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3854632099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/17.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/17.edn_intr.1035894441 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 24164024 ps |
| CPU time | 1.6 seconds |
| Started | Sep 01 09:44:52 AM UTC 24 |
| Finished | Sep 01 09:44:54 AM UTC 24 |
| Peak memory | 236704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035894441 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1035894441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/17.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/17.edn_smoke.1638794367 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 21554964 ps |
| CPU time | 1.43 seconds |
| Started | Sep 01 09:44:50 AM UTC 24 |
| Finished | Sep 01 09:44:52 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638794367 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 17.edn_smoke.1638794367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/17.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/17.edn_stress_all.2666927716 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 82166676 ps |
| CPU time | 1.57 seconds |
| Started | Sep 01 09:44:51 AM UTC 24 |
| Finished | Sep 01 09:44:53 AM UTC 24 |
| Peak memory | 216020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666927716 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.2666927716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/17.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/170.edn_alert.1111544951 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 69421433 ps |
| CPU time | 1.65 seconds |
| Started | Sep 01 09:50:08 AM UTC 24 |
| Finished | Sep 01 09:50:11 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111544951 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 170.edn_alert.1111544951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/170.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/170.edn_genbits.1859889383 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 53240764 ps |
| CPU time | 2.03 seconds |
| Started | Sep 01 09:50:08 AM UTC 24 |
| Finished | Sep 01 09:50:11 AM UTC 24 |
| Peak memory | 229716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859889383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1859889383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/170.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/171.edn_alert.2357490076 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 28263500 ps |
| CPU time | 1.87 seconds |
| Started | Sep 01 09:50:08 AM UTC 24 |
| Finished | Sep 01 09:50:11 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357490076 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 171.edn_alert.2357490076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/171.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/171.edn_genbits.2376513755 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 34832554 ps |
| CPU time | 1.39 seconds |
| Started | Sep 01 09:50:08 AM UTC 24 |
| Finished | Sep 01 09:50:10 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376513755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 171.edn_genbits.2376513755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/171.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/172.edn_alert.2666813708 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 42819396 ps |
| CPU time | 1.93 seconds |
| Started | Sep 01 09:50:09 AM UTC 24 |
| Finished | Sep 01 09:50:12 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666813708 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 172.edn_alert.2666813708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/172.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/172.edn_genbits.2550737259 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 164436760 ps |
| CPU time | 4.4 seconds |
| Started | Sep 01 09:50:09 AM UTC 24 |
| Finished | Sep 01 09:50:14 AM UTC 24 |
| Peak memory | 231500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550737259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 172.edn_genbits.2550737259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/172.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/173.edn_alert.2128830313 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 78635139 ps |
| CPU time | 1.63 seconds |
| Started | Sep 01 09:50:11 AM UTC 24 |
| Finished | Sep 01 09:50:14 AM UTC 24 |
| Peak memory | 226344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128830313 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 173.edn_alert.2128830313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/173.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/173.edn_genbits.1555091327 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 63511945 ps |
| CPU time | 1.58 seconds |
| Started | Sep 01 09:50:11 AM UTC 24 |
| Finished | Sep 01 09:50:14 AM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555091327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1555091327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/173.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/174.edn_alert.3756566201 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 24707670 ps |
| CPU time | 1.86 seconds |
| Started | Sep 01 09:50:11 AM UTC 24 |
| Finished | Sep 01 09:50:14 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756566201 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 174.edn_alert.3756566201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/174.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/174.edn_genbits.3820755011 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 34801542 ps |
| CPU time | 2.28 seconds |
| Started | Sep 01 09:50:11 AM UTC 24 |
| Finished | Sep 01 09:50:15 AM UTC 24 |
| Peak memory | 231416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820755011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3820755011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/174.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/175.edn_alert.1235762721 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 70946782 ps |
| CPU time | 1.78 seconds |
| Started | Sep 01 09:50:11 AM UTC 24 |
| Finished | Sep 01 09:50:14 AM UTC 24 |
| Peak memory | 230392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235762721 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 175.edn_alert.1235762721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/175.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/175.edn_genbits.3876576873 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 218101545 ps |
| CPU time | 4.52 seconds |
| Started | Sep 01 09:50:11 AM UTC 24 |
| Finished | Sep 01 09:50:17 AM UTC 24 |
| Peak memory | 231228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876576873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 175.edn_genbits.3876576873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/175.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/176.edn_alert.412490302 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 105222057 ps |
| CPU time | 1.88 seconds |
| Started | Sep 01 09:50:13 AM UTC 24 |
| Finished | Sep 01 09:50:16 AM UTC 24 |
| Peak memory | 226356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412490302 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 176.edn_alert.412490302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/176.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/176.edn_genbits.3338375700 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 58632045 ps |
| CPU time | 1.82 seconds |
| Started | Sep 01 09:50:11 AM UTC 24 |
| Finished | Sep 01 09:50:14 AM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338375700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 176.edn_genbits.3338375700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/176.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/177.edn_alert.3639934401 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 30157374 ps |
| CPU time | 1.75 seconds |
| Started | Sep 01 09:50:13 AM UTC 24 |
| Finished | Sep 01 09:50:16 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639934401 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 177.edn_alert.3639934401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/177.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/177.edn_genbits.3390970164 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 79227269 ps |
| CPU time | 1.7 seconds |
| Started | Sep 01 09:50:13 AM UTC 24 |
| Finished | Sep 01 09:50:16 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390970164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 177.edn_genbits.3390970164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/177.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/178.edn_alert.3346167124 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 22266415 ps |
| CPU time | 1.8 seconds |
| Started | Sep 01 09:50:13 AM UTC 24 |
| Finished | Sep 01 09:50:16 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346167124 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 178.edn_alert.3346167124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/178.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/178.edn_genbits.1619958666 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 157488436 ps |
| CPU time | 2.35 seconds |
| Started | Sep 01 09:50:13 AM UTC 24 |
| Finished | Sep 01 09:50:16 AM UTC 24 |
| Peak memory | 231764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619958666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1619958666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/178.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/179.edn_alert.3396570201 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 79335865 ps |
| CPU time | 1.73 seconds |
| Started | Sep 01 09:50:15 AM UTC 24 |
| Finished | Sep 01 09:50:18 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396570201 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 179.edn_alert.3396570201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/179.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/179.edn_genbits.3511823414 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 65104294 ps |
| CPU time | 1.93 seconds |
| Started | Sep 01 09:50:13 AM UTC 24 |
| Finished | Sep 01 09:50:16 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511823414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3511823414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/179.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/18.edn_alert_test.3963750348 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 23312528 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 09:44:57 AM UTC 24 |
| Finished | Sep 01 09:44:59 AM UTC 24 |
| Peak memory | 216988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963750348 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.3963750348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/18.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/18.edn_disable.2066226666 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 19121456 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 09:44:57 AM UTC 24 |
| Finished | Sep 01 09:44:59 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066226666 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2066226666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/18.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/18.edn_disable_auto_req_mode.1892557254 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 56210509 ps |
| CPU time | 1.41 seconds |
| Started | Sep 01 09:44:57 AM UTC 24 |
| Finished | Sep 01 09:44:59 AM UTC 24 |
| Peak memory | 228300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892557254 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable_auto_req_mode.1892557254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/18.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/18.edn_err.864831603 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 31495187 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 09:44:57 AM UTC 24 |
| Finished | Sep 01 09:44:59 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864831603 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 18.edn_err.864831603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/18.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/18.edn_genbits.1037840245 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 85374703 ps |
| CPU time | 1.71 seconds |
| Started | Sep 01 09:44:54 AM UTC 24 |
| Finished | Sep 01 09:44:58 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037840245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1037840245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/18.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/18.edn_intr.3721147114 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 48936926 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 09:44:55 AM UTC 24 |
| Finished | Sep 01 09:44:58 AM UTC 24 |
| Peak memory | 226320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721147114 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.3721147114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/18.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/18.edn_smoke.4087462508 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 15552116 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 09:44:54 AM UTC 24 |
| Finished | Sep 01 09:44:57 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087462508 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 18.edn_smoke.4087462508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/18.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/18.edn_stress_all.889388986 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 95699945 ps |
| CPU time | 3.2 seconds |
| Started | Sep 01 09:44:55 AM UTC 24 |
| Finished | Sep 01 09:45:00 AM UTC 24 |
| Peak memory | 229712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889388986 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.889388986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/18.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/18.edn_stress_all_with_rand_reset.201966449 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 5394823112 ps |
| CPU time | 84.13 seconds |
| Started | Sep 01 09:44:55 AM UTC 24 |
| Finished | Sep 01 09:46:21 AM UTC 24 |
| Peak memory | 229796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201966449 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_ with_rand_reset.201966449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/18.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/180.edn_alert.2341524913 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 20867292 ps |
| CPU time | 1.63 seconds |
| Started | Sep 01 09:50:15 AM UTC 24 |
| Finished | Sep 01 09:50:18 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341524913 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 180.edn_alert.2341524913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/180.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/180.edn_genbits.2087618855 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 329448825 ps |
| CPU time | 1.66 seconds |
| Started | Sep 01 09:50:15 AM UTC 24 |
| Finished | Sep 01 09:50:18 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087618855 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 180.edn_genbits.2087618855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/180.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/181.edn_alert.1978365182 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 307763480 ps |
| CPU time | 1.51 seconds |
| Started | Sep 01 09:50:15 AM UTC 24 |
| Finished | Sep 01 09:50:18 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978365182 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 181.edn_alert.1978365182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/181.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/181.edn_genbits.1268497340 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 42612684 ps |
| CPU time | 2.3 seconds |
| Started | Sep 01 09:50:15 AM UTC 24 |
| Finished | Sep 01 09:50:19 AM UTC 24 |
| Peak memory | 231592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268497340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 181.edn_genbits.1268497340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/181.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/182.edn_alert.3452302855 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 28109343 ps |
| CPU time | 1.86 seconds |
| Started | Sep 01 09:50:16 AM UTC 24 |
| Finished | Sep 01 09:50:19 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452302855 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 182.edn_alert.3452302855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/182.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/182.edn_genbits.758363780 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 78359247 ps |
| CPU time | 2.08 seconds |
| Started | Sep 01 09:50:15 AM UTC 24 |
| Finished | Sep 01 09:50:18 AM UTC 24 |
| Peak memory | 229768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758363780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 182.edn_genbits.758363780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/182.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/183.edn_alert.931222107 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 37448704 ps |
| CPU time | 1.75 seconds |
| Started | Sep 01 09:50:16 AM UTC 24 |
| Finished | Sep 01 09:50:19 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931222107 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 183.edn_alert.931222107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/183.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/183.edn_genbits.1395250078 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 53357046 ps |
| CPU time | 1.62 seconds |
| Started | Sep 01 09:50:16 AM UTC 24 |
| Finished | Sep 01 09:50:19 AM UTC 24 |
| Peak memory | 228360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395250078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 183.edn_genbits.1395250078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/183.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/184.edn_alert.19283305 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 62538228 ps |
| CPU time | 1.59 seconds |
| Started | Sep 01 09:50:17 AM UTC 24 |
| Finished | Sep 01 09:50:20 AM UTC 24 |
| Peak memory | 229956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19283305 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.19283305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/184.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/184.edn_genbits.1615318058 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 63412474 ps |
| CPU time | 1.62 seconds |
| Started | Sep 01 09:50:17 AM UTC 24 |
| Finished | Sep 01 09:50:19 AM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615318058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1615318058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/184.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/185.edn_alert.816769090 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 154297518 ps |
| CPU time | 1.6 seconds |
| Started | Sep 01 09:50:18 AM UTC 24 |
| Finished | Sep 01 09:50:20 AM UTC 24 |
| Peak memory | 226376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816769090 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 185.edn_alert.816769090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/185.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/185.edn_genbits.2766270753 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 114169161 ps |
| CPU time | 1.78 seconds |
| Started | Sep 01 09:50:17 AM UTC 24 |
| Finished | Sep 01 09:50:20 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766270753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2766270753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/185.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/186.edn_alert.3085108095 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 43412321 ps |
| CPU time | 1.37 seconds |
| Started | Sep 01 09:50:19 AM UTC 24 |
| Finished | Sep 01 09:50:21 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085108095 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 186.edn_alert.3085108095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/186.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/186.edn_genbits.3160458009 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 78163129 ps |
| CPU time | 1.55 seconds |
| Started | Sep 01 09:50:18 AM UTC 24 |
| Finished | Sep 01 09:50:20 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160458009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3160458009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/186.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/187.edn_alert.1750066693 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 28520477 ps |
| CPU time | 1.69 seconds |
| Started | Sep 01 09:50:19 AM UTC 24 |
| Finished | Sep 01 09:50:22 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750066693 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 187.edn_alert.1750066693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/187.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/187.edn_genbits.3042358703 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 44648450 ps |
| CPU time | 2.17 seconds |
| Started | Sep 01 09:50:19 AM UTC 24 |
| Finished | Sep 01 09:50:22 AM UTC 24 |
| Peak memory | 229724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042358703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3042358703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/187.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/188.edn_alert.1137181020 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 24186055 ps |
| CPU time | 1.58 seconds |
| Started | Sep 01 09:50:19 AM UTC 24 |
| Finished | Sep 01 09:50:22 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137181020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 188.edn_alert.1137181020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/188.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/188.edn_genbits.3712491871 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 33375030 ps |
| CPU time | 1.97 seconds |
| Started | Sep 01 09:50:19 AM UTC 24 |
| Finished | Sep 01 09:50:22 AM UTC 24 |
| Peak memory | 230608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712491871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3712491871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/188.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/189.edn_alert.3390518798 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 38433184 ps |
| CPU time | 1.67 seconds |
| Started | Sep 01 09:50:20 AM UTC 24 |
| Finished | Sep 01 09:50:23 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390518798 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 189.edn_alert.3390518798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/189.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/19.edn_alert.1130998818 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 85962081 ps |
| CPU time | 1.35 seconds |
| Started | Sep 01 09:45:00 AM UTC 24 |
| Finished | Sep 01 09:45:03 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130998818 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 19.edn_alert.1130998818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/19.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/19.edn_alert_test.548815589 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 41813392 ps |
| CPU time | 1.37 seconds |
| Started | Sep 01 09:45:01 AM UTC 24 |
| Finished | Sep 01 09:45:04 AM UTC 24 |
| Peak memory | 227044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548815589 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.548815589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/19.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/19.edn_disable.850756108 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 13319416 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 09:45:00 AM UTC 24 |
| Finished | Sep 01 09:45:03 AM UTC 24 |
| Peak memory | 226376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850756108 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.850756108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/19.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/19.edn_disable_auto_req_mode.3291426807 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 29222128 ps |
| CPU time | 1.6 seconds |
| Started | Sep 01 09:45:00 AM UTC 24 |
| Finished | Sep 01 09:45:04 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291426807 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable_auto_req_mode.3291426807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/19.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/19.edn_err.3002646422 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 26105439 ps |
| CPU time | 1.65 seconds |
| Started | Sep 01 09:45:00 AM UTC 24 |
| Finished | Sep 01 09:45:04 AM UTC 24 |
| Peak memory | 230408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002646422 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 19.edn_err.3002646422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/19.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/19.edn_genbits.759244830 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 26684852 ps |
| CPU time | 1.74 seconds |
| Started | Sep 01 09:44:59 AM UTC 24 |
| Finished | Sep 01 09:45:02 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759244830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 19.edn_genbits.759244830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/19.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/19.edn_intr.124979105 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 26616503 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 09:45:00 AM UTC 24 |
| Finished | Sep 01 09:45:03 AM UTC 24 |
| Peak memory | 226316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124979105 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.124979105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/19.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/19.edn_smoke.899642172 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 38058057 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 09:44:58 AM UTC 24 |
| Finished | Sep 01 09:45:00 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899642172 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 19.edn_smoke.899642172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/19.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/19.edn_stress_all.2939512215 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 240146618 ps |
| CPU time | 4.2 seconds |
| Started | Sep 01 09:44:59 AM UTC 24 |
| Finished | Sep 01 09:45:05 AM UTC 24 |
| Peak memory | 227544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939512215 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.2939512215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/19.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/19.edn_stress_all_with_rand_reset.4146927048 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 2159808949 ps |
| CPU time | 41.77 seconds |
| Started | Sep 01 09:45:00 AM UTC 24 |
| Finished | Sep 01 09:45:44 AM UTC 24 |
| Peak memory | 229820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146927048 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all _with_rand_reset.4146927048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/19.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/190.edn_alert.3350413051 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 37254960 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 09:50:20 AM UTC 24 |
| Finished | Sep 01 09:50:23 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350413051 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 190.edn_alert.3350413051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/190.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/190.edn_genbits.4248731631 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 45392276 ps |
| CPU time | 2.13 seconds |
| Started | Sep 01 09:50:20 AM UTC 24 |
| Finished | Sep 01 09:50:23 AM UTC 24 |
| Peak memory | 229536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248731631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 190.edn_genbits.4248731631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/190.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/191.edn_alert.664406644 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 79822955 ps |
| CPU time | 1.77 seconds |
| Started | Sep 01 09:50:20 AM UTC 24 |
| Finished | Sep 01 09:50:23 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664406644 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 191.edn_alert.664406644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/191.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/191.edn_genbits.3264062871 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 75078753 ps |
| CPU time | 1.8 seconds |
| Started | Sep 01 09:50:20 AM UTC 24 |
| Finished | Sep 01 09:50:23 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264062871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 191.edn_genbits.3264062871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/191.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/192.edn_alert.1757090794 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 265284440 ps |
| CPU time | 1.6 seconds |
| Started | Sep 01 09:50:22 AM UTC 24 |
| Finished | Sep 01 09:50:24 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757090794 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 192.edn_alert.1757090794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/192.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/192.edn_genbits.2216966366 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 41973515 ps |
| CPU time | 1.97 seconds |
| Started | Sep 01 09:50:21 AM UTC 24 |
| Finished | Sep 01 09:50:24 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216966366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2216966366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/192.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/193.edn_alert.4228882123 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 46703390 ps |
| CPU time | 1.64 seconds |
| Started | Sep 01 09:50:22 AM UTC 24 |
| Finished | Sep 01 09:50:24 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228882123 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 193.edn_alert.4228882123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/193.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/193.edn_genbits.3188082099 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 38874005 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 09:50:22 AM UTC 24 |
| Finished | Sep 01 09:50:24 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188082099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3188082099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/193.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/194.edn_alert.3893795317 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 35436277 ps |
| CPU time | 1.68 seconds |
| Started | Sep 01 09:50:23 AM UTC 24 |
| Finished | Sep 01 09:50:26 AM UTC 24 |
| Peak memory | 228416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893795317 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 194.edn_alert.3893795317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/194.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/194.edn_genbits.2156460631 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 64697416 ps |
| CPU time | 2.05 seconds |
| Started | Sep 01 09:50:23 AM UTC 24 |
| Finished | Sep 01 09:50:26 AM UTC 24 |
| Peak memory | 229544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156460631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2156460631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/194.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/195.edn_alert.1124799875 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 196087796 ps |
| CPU time | 1.77 seconds |
| Started | Sep 01 09:50:23 AM UTC 24 |
| Finished | Sep 01 09:50:26 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124799875 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 195.edn_alert.1124799875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/195.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/195.edn_genbits.3070133623 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 61914717 ps |
| CPU time | 1.85 seconds |
| Started | Sep 01 09:50:23 AM UTC 24 |
| Finished | Sep 01 09:50:26 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070133623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3070133623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/195.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/196.edn_alert.2633008643 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 56619259 ps |
| CPU time | 1.56 seconds |
| Started | Sep 01 09:50:24 AM UTC 24 |
| Finished | Sep 01 09:50:27 AM UTC 24 |
| Peak memory | 230464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633008643 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 196.edn_alert.2633008643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/196.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/196.edn_genbits.471110452 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 349093985 ps |
| CPU time | 3.34 seconds |
| Started | Sep 01 09:50:24 AM UTC 24 |
| Finished | Sep 01 09:50:28 AM UTC 24 |
| Peak memory | 231480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471110452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 196.edn_genbits.471110452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/196.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/197.edn_alert.1828097122 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 44162606 ps |
| CPU time | 1.68 seconds |
| Started | Sep 01 09:50:24 AM UTC 24 |
| Finished | Sep 01 09:50:27 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828097122 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 197.edn_alert.1828097122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/197.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/197.edn_genbits.2753211319 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 75922985 ps |
| CPU time | 1.89 seconds |
| Started | Sep 01 09:50:24 AM UTC 24 |
| Finished | Sep 01 09:50:27 AM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753211319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 197.edn_genbits.2753211319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/197.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/198.edn_alert.4230008670 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 105558644 ps |
| CPU time | 2.02 seconds |
| Started | Sep 01 09:50:24 AM UTC 24 |
| Finished | Sep 01 09:50:27 AM UTC 24 |
| Peak memory | 227892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230008670 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 198.edn_alert.4230008670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/198.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/198.edn_genbits.2364952773 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 37161679 ps |
| CPU time | 2.05 seconds |
| Started | Sep 01 09:50:24 AM UTC 24 |
| Finished | Sep 01 09:50:27 AM UTC 24 |
| Peak memory | 231488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364952773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2364952773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/198.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/199.edn_alert.3616085294 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 37535864 ps |
| CPU time | 1.53 seconds |
| Started | Sep 01 09:50:28 AM UTC 24 |
| Finished | Sep 01 09:50:31 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616085294 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 199.edn_alert.3616085294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/199.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/199.edn_genbits.398828730 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 70844851 ps |
| CPU time | 1.62 seconds |
| Started | Sep 01 09:50:24 AM UTC 24 |
| Finished | Sep 01 09:50:27 AM UTC 24 |
| Peak memory | 228168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398828730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 199.edn_genbits.398828730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/199.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/2.edn_alert.2403228929 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 39374516 ps |
| CPU time | 1.52 seconds |
| Started | Sep 01 09:43:56 AM UTC 24 |
| Finished | Sep 01 09:43:58 AM UTC 24 |
| Peak memory | 228428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403228929 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 2.edn_alert.2403228929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/2.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/2.edn_alert_test.2508238024 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 27701466 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 09:43:57 AM UTC 24 |
| Finished | Sep 01 09:43:59 AM UTC 24 |
| Peak memory | 216748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508238024 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2508238024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/2.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/2.edn_genbits.1738737273 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 54441932 ps |
| CPU time | 1.33 seconds |
| Started | Sep 01 09:43:53 AM UTC 24 |
| Finished | Sep 01 09:43:56 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738737273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1738737273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/2.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/2.edn_intr.4071999686 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 22574924 ps |
| CPU time | 1.54 seconds |
| Started | Sep 01 09:43:55 AM UTC 24 |
| Finished | Sep 01 09:43:57 AM UTC 24 |
| Peak memory | 226316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071999686 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.4071999686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/2.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/2.edn_regwen.2437831012 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 41513865 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 09:43:53 AM UTC 24 |
| Finished | Sep 01 09:43:56 AM UTC 24 |
| Peak memory | 216020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437831012 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 2.edn_regwen.2437831012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/2.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/2.edn_sec_cm.1079504550 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 1753123266 ps |
| CPU time | 11.94 seconds |
| Started | Sep 01 09:43:57 AM UTC 24 |
| Finished | Sep 01 09:44:10 AM UTC 24 |
| Peak memory | 262580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079504550 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1079504550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/2.edn_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/2.edn_smoke.748683685 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 65439612 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 09:43:53 AM UTC 24 |
| Finished | Sep 01 09:43:56 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748683685 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.edn_smoke.748683685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/2.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/2.edn_stress_all.2521117 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 107785827 ps |
| CPU time | 3.93 seconds |
| Started | Sep 01 09:43:53 AM UTC 24 |
| Finished | Sep 01 09:43:58 AM UTC 24 |
| Peak memory | 227332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521117 -assert nopostproc +UVM_TESTNAME=edn_st ress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2521117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/2.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/20.edn_alert.3431120629 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 101307474 ps |
| CPU time | 1.72 seconds |
| Started | Sep 01 09:45:08 AM UTC 24 |
| Finished | Sep 01 09:45:10 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431120629 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 20.edn_alert.3431120629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/20.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/20.edn_alert_test.4047403207 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 14481015 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 09:45:08 AM UTC 24 |
| Finished | Sep 01 09:45:10 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047403207 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.4047403207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/20.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/20.edn_disable.1671267249 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 13318688 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 09:45:08 AM UTC 24 |
| Finished | Sep 01 09:45:10 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671267249 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1671267249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/20.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/20.edn_disable_auto_req_mode.3463628103 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 121941795 ps |
| CPU time | 1.91 seconds |
| Started | Sep 01 09:45:08 AM UTC 24 |
| Finished | Sep 01 09:45:11 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463628103 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable_auto_req_mode.3463628103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/20.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/20.edn_err.29597741 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 18663165 ps |
| CPU time | 1.48 seconds |
| Started | Sep 01 09:45:08 AM UTC 24 |
| Finished | Sep 01 09:45:10 AM UTC 24 |
| Peak memory | 228360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29597741 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 20.edn_err.29597741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/20.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/20.edn_genbits.3087943188 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 116910696 ps |
| CPU time | 1.49 seconds |
| Started | Sep 01 09:45:07 AM UTC 24 |
| Finished | Sep 01 09:45:10 AM UTC 24 |
| Peak memory | 228332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087943188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3087943188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/20.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/20.edn_intr.1900816102 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 21984577 ps |
| CPU time | 1.57 seconds |
| Started | Sep 01 09:45:08 AM UTC 24 |
| Finished | Sep 01 09:45:10 AM UTC 24 |
| Peak memory | 237164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900816102 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1900816102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/20.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/20.edn_smoke.2111273411 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 16392938 ps |
| CPU time | 1.49 seconds |
| Started | Sep 01 09:45:02 AM UTC 24 |
| Finished | Sep 01 09:45:05 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111273411 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 20.edn_smoke.2111273411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/20.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/20.edn_stress_all.661313282 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 130150223 ps |
| CPU time | 4.41 seconds |
| Started | Sep 01 09:45:07 AM UTC 24 |
| Finished | Sep 01 09:45:13 AM UTC 24 |
| Peak memory | 227388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661313282 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.661313282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/20.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/20.edn_stress_all_with_rand_reset.139293995 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 3261980093 ps |
| CPU time | 52.55 seconds |
| Started | Sep 01 09:45:08 AM UTC 24 |
| Finished | Sep 01 09:46:02 AM UTC 24 |
| Peak memory | 229800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139293995 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_ with_rand_reset.139293995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/20.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/200.edn_genbits.859935378 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 189833650 ps |
| CPU time | 3.06 seconds |
| Started | Sep 01 09:50:28 AM UTC 24 |
| Finished | Sep 01 09:50:32 AM UTC 24 |
| Peak memory | 229420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859935378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 200.edn_genbits.859935378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/200.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/201.edn_genbits.1761963469 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 49613666 ps |
| CPU time | 2.14 seconds |
| Started | Sep 01 09:50:28 AM UTC 24 |
| Finished | Sep 01 09:50:32 AM UTC 24 |
| Peak memory | 231528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761963469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 201.edn_genbits.1761963469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/201.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/202.edn_genbits.1385589854 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 44030929 ps |
| CPU time | 1.74 seconds |
| Started | Sep 01 09:50:28 AM UTC 24 |
| Finished | Sep 01 09:50:31 AM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385589854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 202.edn_genbits.1385589854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/202.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/203.edn_genbits.3292969776 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 52969126 ps |
| CPU time | 2.87 seconds |
| Started | Sep 01 09:50:28 AM UTC 24 |
| Finished | Sep 01 09:50:32 AM UTC 24 |
| Peak memory | 229716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292969776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 203.edn_genbits.3292969776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/203.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/204.edn_genbits.2052532537 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 32933006 ps |
| CPU time | 1.57 seconds |
| Started | Sep 01 09:50:29 AM UTC 24 |
| Finished | Sep 01 09:50:31 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052532537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 204.edn_genbits.2052532537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/204.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/205.edn_genbits.1486337152 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 35788757 ps |
| CPU time | 2.17 seconds |
| Started | Sep 01 09:50:29 AM UTC 24 |
| Finished | Sep 01 09:50:32 AM UTC 24 |
| Peak memory | 229732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486337152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1486337152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/205.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/206.edn_genbits.1501930775 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 36912989 ps |
| CPU time | 2.01 seconds |
| Started | Sep 01 09:50:29 AM UTC 24 |
| Finished | Sep 01 09:50:32 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501930775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 206.edn_genbits.1501930775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/206.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/207.edn_genbits.329367051 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 72319953 ps |
| CPU time | 1.8 seconds |
| Started | Sep 01 09:50:29 AM UTC 24 |
| Finished | Sep 01 09:50:32 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329367051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 207.edn_genbits.329367051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/207.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/208.edn_genbits.3390229519 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 77622879 ps |
| CPU time | 1.44 seconds |
| Started | Sep 01 09:50:29 AM UTC 24 |
| Finished | Sep 01 09:50:31 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390229519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 208.edn_genbits.3390229519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/208.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/209.edn_genbits.2222694243 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 48428550 ps |
| CPU time | 1.82 seconds |
| Started | Sep 01 09:50:29 AM UTC 24 |
| Finished | Sep 01 09:50:32 AM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222694243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2222694243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/209.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/21.edn_alert_test.3939750931 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 29680544 ps |
| CPU time | 1.26 seconds |
| Started | Sep 01 09:45:14 AM UTC 24 |
| Finished | Sep 01 09:45:16 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939750931 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3939750931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/21.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/21.edn_disable_auto_req_mode.2425548977 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 26447204 ps |
| CPU time | 1.54 seconds |
| Started | Sep 01 09:45:13 AM UTC 24 |
| Finished | Sep 01 09:45:15 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425548977 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable_auto_req_mode.2425548977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/21.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/21.edn_err.3777124297 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 26129576 ps |
| CPU time | 1.36 seconds |
| Started | Sep 01 09:45:11 AM UTC 24 |
| Finished | Sep 01 09:45:14 AM UTC 24 |
| Peak memory | 230192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777124297 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 21.edn_err.3777124297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/21.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/21.edn_genbits.2831833623 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 41351358 ps |
| CPU time | 1.72 seconds |
| Started | Sep 01 09:45:11 AM UTC 24 |
| Finished | Sep 01 09:45:14 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831833623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2831833623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/21.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/21.edn_intr.3574290550 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 23324368 ps |
| CPU time | 1.78 seconds |
| Started | Sep 01 09:45:11 AM UTC 24 |
| Finished | Sep 01 09:45:14 AM UTC 24 |
| Peak memory | 237596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574290550 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3574290550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/21.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/21.edn_smoke.3898311544 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 17464985 ps |
| CPU time | 1.52 seconds |
| Started | Sep 01 09:45:08 AM UTC 24 |
| Finished | Sep 01 09:45:11 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898311544 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 21.edn_smoke.3898311544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/21.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/21.edn_stress_all.1163102809 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 225836863 ps |
| CPU time | 6.34 seconds |
| Started | Sep 01 09:45:11 AM UTC 24 |
| Finished | Sep 01 09:45:19 AM UTC 24 |
| Peak memory | 231688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163102809 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.1163102809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/21.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/21.edn_stress_all_with_rand_reset.3624133361 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 9090990823 ps |
| CPU time | 97.46 seconds |
| Started | Sep 01 09:45:11 AM UTC 24 |
| Finished | Sep 01 09:46:51 AM UTC 24 |
| Peak memory | 229728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624133361 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all _with_rand_reset.3624133361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/21.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/210.edn_genbits.3884733386 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 72000700 ps |
| CPU time | 1.94 seconds |
| Started | Sep 01 09:50:29 AM UTC 24 |
| Finished | Sep 01 09:50:32 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884733386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 210.edn_genbits.3884733386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/210.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/211.edn_genbits.2584742898 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 255105291 ps |
| CPU time | 2.02 seconds |
| Started | Sep 01 09:50:29 AM UTC 24 |
| Finished | Sep 01 09:50:32 AM UTC 24 |
| Peak memory | 231648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584742898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2584742898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/211.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/212.edn_genbits.1490160685 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 69138768 ps |
| CPU time | 1.58 seconds |
| Started | Sep 01 09:50:29 AM UTC 24 |
| Finished | Sep 01 09:50:32 AM UTC 24 |
| Peak memory | 226316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490160685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1490160685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/212.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/213.edn_genbits.4008049428 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 55837397 ps |
| CPU time | 2.81 seconds |
| Started | Sep 01 09:50:30 AM UTC 24 |
| Finished | Sep 01 09:50:34 AM UTC 24 |
| Peak memory | 229520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008049428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 213.edn_genbits.4008049428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/213.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/215.edn_genbits.2386493563 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 46348612 ps |
| CPU time | 2.19 seconds |
| Started | Sep 01 09:50:32 AM UTC 24 |
| Finished | Sep 01 09:50:36 AM UTC 24 |
| Peak memory | 229520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386493563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 215.edn_genbits.2386493563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/215.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/216.edn_genbits.1849667228 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 88165072 ps |
| CPU time | 2.24 seconds |
| Started | Sep 01 09:50:32 AM UTC 24 |
| Finished | Sep 01 09:50:36 AM UTC 24 |
| Peak memory | 231512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849667228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1849667228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/216.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/217.edn_genbits.1200758746 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 48173568 ps |
| CPU time | 1.78 seconds |
| Started | Sep 01 09:50:32 AM UTC 24 |
| Finished | Sep 01 09:50:35 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200758746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 217.edn_genbits.1200758746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/217.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/218.edn_genbits.355022209 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 43551053 ps |
| CPU time | 2.2 seconds |
| Started | Sep 01 09:50:32 AM UTC 24 |
| Finished | Sep 01 09:50:36 AM UTC 24 |
| Peak memory | 229456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355022209 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 218.edn_genbits.355022209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/218.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/219.edn_genbits.2888955891 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 28692262 ps |
| CPU time | 1.79 seconds |
| Started | Sep 01 09:50:33 AM UTC 24 |
| Finished | Sep 01 09:50:35 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888955891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 219.edn_genbits.2888955891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/219.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/22.edn_alert_test.588763779 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 56566259 ps |
| CPU time | 1.26 seconds |
| Started | Sep 01 09:45:19 AM UTC 24 |
| Finished | Sep 01 09:45:22 AM UTC 24 |
| Peak memory | 226532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588763779 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.588763779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/22.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/22.edn_disable.3184558234 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 11672680 ps |
| CPU time | 1.02 seconds |
| Started | Sep 01 09:45:18 AM UTC 24 |
| Finished | Sep 01 09:45:20 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184558234 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3184558234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/22.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/22.edn_disable_auto_req_mode.953070468 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 30411303 ps |
| CPU time | 1.77 seconds |
| Started | Sep 01 09:45:18 AM UTC 24 |
| Finished | Sep 01 09:45:22 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953070468 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable_auto_req_mode.953070468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/22.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/22.edn_err.4128799268 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 24164578 ps |
| CPU time | 1.54 seconds |
| Started | Sep 01 09:45:17 AM UTC 24 |
| Finished | Sep 01 09:45:20 AM UTC 24 |
| Peak memory | 228360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128799268 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 22.edn_err.4128799268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/22.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/22.edn_genbits.2566025154 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 64557574 ps |
| CPU time | 1.39 seconds |
| Started | Sep 01 09:45:15 AM UTC 24 |
| Finished | Sep 01 09:45:17 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566025154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2566025154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/22.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/22.edn_intr.3478049477 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 33467620 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 09:45:16 AM UTC 24 |
| Finished | Sep 01 09:45:18 AM UTC 24 |
| Peak memory | 226320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478049477 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3478049477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/22.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/22.edn_smoke.1851947070 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 45254909 ps |
| CPU time | 1.36 seconds |
| Started | Sep 01 09:45:15 AM UTC 24 |
| Finished | Sep 01 09:45:17 AM UTC 24 |
| Peak memory | 226220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851947070 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 22.edn_smoke.1851947070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/22.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/22.edn_stress_all.89565348 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 299575985 ps |
| CPU time | 2.4 seconds |
| Started | Sep 01 09:45:15 AM UTC 24 |
| Finished | Sep 01 09:45:18 AM UTC 24 |
| Peak memory | 227488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89565348 -assert nopostproc +UVM_TESTNAME=edn_s tress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.89565348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/22.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/22.edn_stress_all_with_rand_reset.2655266216 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 1924906797 ps |
| CPU time | 69.95 seconds |
| Started | Sep 01 09:45:15 AM UTC 24 |
| Finished | Sep 01 09:46:27 AM UTC 24 |
| Peak memory | 229840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655266216 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all _with_rand_reset.2655266216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/22.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/220.edn_genbits.233899762 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 52702859 ps |
| CPU time | 1.63 seconds |
| Started | Sep 01 09:50:33 AM UTC 24 |
| Finished | Sep 01 09:50:35 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233899762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 220.edn_genbits.233899762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/220.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/221.edn_genbits.3085346575 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 74733288 ps |
| CPU time | 1.78 seconds |
| Started | Sep 01 09:50:33 AM UTC 24 |
| Finished | Sep 01 09:50:35 AM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085346575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3085346575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/221.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/222.edn_genbits.3031265287 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 66771124 ps |
| CPU time | 1.56 seconds |
| Started | Sep 01 09:50:33 AM UTC 24 |
| Finished | Sep 01 09:50:35 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031265287 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3031265287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/222.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/223.edn_genbits.412695625 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 84109303 ps |
| CPU time | 2.06 seconds |
| Started | Sep 01 09:50:33 AM UTC 24 |
| Finished | Sep 01 09:50:36 AM UTC 24 |
| Peak memory | 229596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412695625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 223.edn_genbits.412695625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/223.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/224.edn_genbits.560709078 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 108474490 ps |
| CPU time | 1.87 seconds |
| Started | Sep 01 09:50:33 AM UTC 24 |
| Finished | Sep 01 09:50:36 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560709078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 224.edn_genbits.560709078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/224.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/225.edn_genbits.305182654 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 75470599 ps |
| CPU time | 1.39 seconds |
| Started | Sep 01 09:50:34 AM UTC 24 |
| Finished | Sep 01 09:50:36 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305182654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 225.edn_genbits.305182654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/225.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/226.edn_genbits.274579793 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 147081321 ps |
| CPU time | 1.53 seconds |
| Started | Sep 01 09:50:34 AM UTC 24 |
| Finished | Sep 01 09:50:36 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274579793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 226.edn_genbits.274579793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/226.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/227.edn_genbits.2208564416 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 87911251 ps |
| CPU time | 1.83 seconds |
| Started | Sep 01 09:50:34 AM UTC 24 |
| Finished | Sep 01 09:50:37 AM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208564416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 227.edn_genbits.2208564416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/227.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/228.edn_genbits.744899281 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 95454209 ps |
| CPU time | 1.98 seconds |
| Started | Sep 01 09:50:35 AM UTC 24 |
| Finished | Sep 01 09:50:38 AM UTC 24 |
| Peak memory | 230416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744899281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 228.edn_genbits.744899281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/228.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/229.edn_genbits.1392578394 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 96942191 ps |
| CPU time | 2.06 seconds |
| Started | Sep 01 09:50:35 AM UTC 24 |
| Finished | Sep 01 09:50:38 AM UTC 24 |
| Peak memory | 231756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392578394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1392578394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/229.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/23.edn_alert_test.416670446 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 28298443 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 09:45:24 AM UTC 24 |
| Finished | Sep 01 09:45:26 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416670446 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.416670446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/23.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/23.edn_disable.3475005210 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 39302360 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 09:45:23 AM UTC 24 |
| Finished | Sep 01 09:45:25 AM UTC 24 |
| Peak memory | 226204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475005210 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3475005210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/23.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/23.edn_disable_auto_req_mode.3552053126 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 147083139 ps |
| CPU time | 1.83 seconds |
| Started | Sep 01 09:45:24 AM UTC 24 |
| Finished | Sep 01 09:45:27 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552053126 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable_auto_req_mode.3552053126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/23.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/23.edn_err.2745269926 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 78672838 ps |
| CPU time | 1.64 seconds |
| Started | Sep 01 09:45:23 AM UTC 24 |
| Finished | Sep 01 09:45:26 AM UTC 24 |
| Peak memory | 242068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745269926 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 23.edn_err.2745269926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/23.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/23.edn_genbits.1192427623 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 87973599 ps |
| CPU time | 2.54 seconds |
| Started | Sep 01 09:45:19 AM UTC 24 |
| Finished | Sep 01 09:45:23 AM UTC 24 |
| Peak memory | 231588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192427623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 23.edn_genbits.1192427623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/23.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/23.edn_smoke.13772789 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 15715348 ps |
| CPU time | 1.4 seconds |
| Started | Sep 01 09:45:19 AM UTC 24 |
| Finished | Sep 01 09:45:22 AM UTC 24 |
| Peak memory | 216016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13772789 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.13772789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/23.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/23.edn_stress_all.308419253 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 217501854 ps |
| CPU time | 6.09 seconds |
| Started | Sep 01 09:45:21 AM UTC 24 |
| Finished | Sep 01 09:45:28 AM UTC 24 |
| Peak memory | 229464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308419253 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.308419253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/23.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/23.edn_stress_all_with_rand_reset.278477836 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 21289534020 ps |
| CPU time | 141.29 seconds |
| Started | Sep 01 09:45:21 AM UTC 24 |
| Finished | Sep 01 09:47:45 AM UTC 24 |
| Peak memory | 233952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278477836 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_ with_rand_reset.278477836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/23.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/230.edn_genbits.1264210596 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 49450109 ps |
| CPU time | 1.82 seconds |
| Started | Sep 01 09:50:36 AM UTC 24 |
| Finished | Sep 01 09:50:39 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264210596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 230.edn_genbits.1264210596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/230.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/231.edn_genbits.2877012389 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 76434864 ps |
| CPU time | 2.3 seconds |
| Started | Sep 01 09:50:36 AM UTC 24 |
| Finished | Sep 01 09:50:40 AM UTC 24 |
| Peak memory | 231580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877012389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 231.edn_genbits.2877012389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/231.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/232.edn_genbits.1336170043 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 44592507 ps |
| CPU time | 2.21 seconds |
| Started | Sep 01 09:50:36 AM UTC 24 |
| Finished | Sep 01 09:50:40 AM UTC 24 |
| Peak memory | 229708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336170043 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 232.edn_genbits.1336170043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/232.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/233.edn_genbits.2838153711 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 33856982 ps |
| CPU time | 1.63 seconds |
| Started | Sep 01 09:50:36 AM UTC 24 |
| Finished | Sep 01 09:50:39 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838153711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 233.edn_genbits.2838153711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/233.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/234.edn_genbits.3215573968 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 55396548 ps |
| CPU time | 3.24 seconds |
| Started | Sep 01 09:50:37 AM UTC 24 |
| Finished | Sep 01 09:50:41 AM UTC 24 |
| Peak memory | 229460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215573968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 234.edn_genbits.3215573968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/234.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/235.edn_genbits.4277389552 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 28883417 ps |
| CPU time | 1.69 seconds |
| Started | Sep 01 09:50:37 AM UTC 24 |
| Finished | Sep 01 09:50:39 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277389552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 235.edn_genbits.4277389552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/235.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/236.edn_genbits.3996699369 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 32409965 ps |
| CPU time | 1.72 seconds |
| Started | Sep 01 09:50:37 AM UTC 24 |
| Finished | Sep 01 09:50:39 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996699369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3996699369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/236.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/237.edn_genbits.2390312081 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 81678261 ps |
| CPU time | 2.09 seconds |
| Started | Sep 01 09:50:37 AM UTC 24 |
| Finished | Sep 01 09:50:40 AM UTC 24 |
| Peak memory | 231588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390312081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 237.edn_genbits.2390312081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/237.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/238.edn_genbits.456242065 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 47083684 ps |
| CPU time | 2.45 seconds |
| Started | Sep 01 09:50:37 AM UTC 24 |
| Finished | Sep 01 09:50:40 AM UTC 24 |
| Peak memory | 229640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456242065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 238.edn_genbits.456242065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/238.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/239.edn_genbits.4064385268 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 246744182 ps |
| CPU time | 5.18 seconds |
| Started | Sep 01 09:50:37 AM UTC 24 |
| Finished | Sep 01 09:50:43 AM UTC 24 |
| Peak memory | 231780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064385268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 239.edn_genbits.4064385268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/239.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/24.edn_alert.153013044 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 44704688 ps |
| CPU time | 1.49 seconds |
| Started | Sep 01 09:45:27 AM UTC 24 |
| Finished | Sep 01 09:45:30 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153013044 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 24.edn_alert.153013044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/24.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/24.edn_alert_test.1148565950 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 32488881 ps |
| CPU time | 1.4 seconds |
| Started | Sep 01 09:45:31 AM UTC 24 |
| Finished | Sep 01 09:45:33 AM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148565950 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.1148565950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/24.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/24.edn_disable.1469812459 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 12844041 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 09:45:29 AM UTC 24 |
| Finished | Sep 01 09:45:31 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469812459 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1469812459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/24.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/24.edn_disable_auto_req_mode.1815092969 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 61936702 ps |
| CPU time | 1.44 seconds |
| Started | Sep 01 09:45:30 AM UTC 24 |
| Finished | Sep 01 09:45:32 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815092969 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable_auto_req_mode.1815092969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/24.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/24.edn_err.3929450911 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 33876857 ps |
| CPU time | 1.52 seconds |
| Started | Sep 01 09:45:29 AM UTC 24 |
| Finished | Sep 01 09:45:31 AM UTC 24 |
| Peak memory | 236960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929450911 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 24.edn_err.3929450911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/24.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/24.edn_genbits.2732311657 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 65773099 ps |
| CPU time | 1.55 seconds |
| Started | Sep 01 09:45:26 AM UTC 24 |
| Finished | Sep 01 09:45:29 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732311657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 24.edn_genbits.2732311657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/24.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/24.edn_intr.1389002765 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 31756445 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 09:45:27 AM UTC 24 |
| Finished | Sep 01 09:45:30 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389002765 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.1389002765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/24.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/24.edn_smoke.1632763393 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 16385084 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 09:45:25 AM UTC 24 |
| Finished | Sep 01 09:45:27 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632763393 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 24.edn_smoke.1632763393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/24.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/24.edn_stress_all.4183138594 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 442777380 ps |
| CPU time | 7.56 seconds |
| Started | Sep 01 09:45:26 AM UTC 24 |
| Finished | Sep 01 09:45:35 AM UTC 24 |
| Peak memory | 229524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183138594 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.4183138594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/24.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/240.edn_genbits.1543628677 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 56084877 ps |
| CPU time | 1.4 seconds |
| Started | Sep 01 09:50:38 AM UTC 24 |
| Finished | Sep 01 09:50:40 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543628677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 240.edn_genbits.1543628677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/240.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/241.edn_genbits.893467847 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 36718638 ps |
| CPU time | 1.87 seconds |
| Started | Sep 01 09:50:38 AM UTC 24 |
| Finished | Sep 01 09:50:41 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893467847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 241.edn_genbits.893467847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/241.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/242.edn_genbits.4234925802 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 31677786 ps |
| CPU time | 1.88 seconds |
| Started | Sep 01 09:50:38 AM UTC 24 |
| Finished | Sep 01 09:50:41 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234925802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 242.edn_genbits.4234925802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/242.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/243.edn_genbits.1179565992 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 82911338 ps |
| CPU time | 1.74 seconds |
| Started | Sep 01 09:50:39 AM UTC 24 |
| Finished | Sep 01 09:50:42 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179565992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 243.edn_genbits.1179565992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/243.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/244.edn_genbits.2219793813 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 313839425 ps |
| CPU time | 1.61 seconds |
| Started | Sep 01 09:50:39 AM UTC 24 |
| Finished | Sep 01 09:50:42 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219793813 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 244.edn_genbits.2219793813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/244.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/245.edn_genbits.4129599461 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 52421239 ps |
| CPU time | 1.8 seconds |
| Started | Sep 01 09:50:40 AM UTC 24 |
| Finished | Sep 01 09:50:43 AM UTC 24 |
| Peak memory | 230608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129599461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 245.edn_genbits.4129599461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/245.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/246.edn_genbits.1565012951 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 63819494 ps |
| CPU time | 1.98 seconds |
| Started | Sep 01 09:50:40 AM UTC 24 |
| Finished | Sep 01 09:50:43 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565012951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1565012951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/246.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/247.edn_genbits.432196776 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 47184494 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 09:50:40 AM UTC 24 |
| Finished | Sep 01 09:50:43 AM UTC 24 |
| Peak memory | 226320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432196776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 247.edn_genbits.432196776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/247.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/248.edn_genbits.996526475 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 53314233 ps |
| CPU time | 2.52 seconds |
| Started | Sep 01 09:50:40 AM UTC 24 |
| Finished | Sep 01 09:50:44 AM UTC 24 |
| Peak memory | 229520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996526475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 248.edn_genbits.996526475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/248.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/249.edn_genbits.4159855538 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 57849805 ps |
| CPU time | 2.05 seconds |
| Started | Sep 01 09:50:41 AM UTC 24 |
| Finished | Sep 01 09:50:44 AM UTC 24 |
| Peak memory | 229468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159855538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 249.edn_genbits.4159855538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/249.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/25.edn_alert.1050349010 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 102881789 ps |
| CPU time | 1.36 seconds |
| Started | Sep 01 09:45:34 AM UTC 24 |
| Finished | Sep 01 09:45:37 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050349010 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 25.edn_alert.1050349010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/25.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/25.edn_alert_test.2799423348 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 40640433 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 09:45:36 AM UTC 24 |
| Finished | Sep 01 09:45:39 AM UTC 24 |
| Peak memory | 216312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799423348 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2799423348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/25.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/25.edn_disable.1798560987 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 11644783 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 09:45:35 AM UTC 24 |
| Finished | Sep 01 09:45:38 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798560987 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.1798560987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/25.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/25.edn_err.453049686 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 18131586 ps |
| CPU time | 1.45 seconds |
| Started | Sep 01 09:45:34 AM UTC 24 |
| Finished | Sep 01 09:45:37 AM UTC 24 |
| Peak memory | 228304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453049686 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 25.edn_err.453049686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/25.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/25.edn_genbits.600861251 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 387501386 ps |
| CPU time | 2.74 seconds |
| Started | Sep 01 09:45:32 AM UTC 24 |
| Finished | Sep 01 09:45:36 AM UTC 24 |
| Peak memory | 229532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600861251 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 25.edn_genbits.600861251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/25.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/25.edn_intr.2184203686 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 20872291 ps |
| CPU time | 1.71 seconds |
| Started | Sep 01 09:45:34 AM UTC 24 |
| Finished | Sep 01 09:45:37 AM UTC 24 |
| Peak memory | 236704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184203686 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2184203686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/25.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/25.edn_smoke.1561429069 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 15512438 ps |
| CPU time | 1.46 seconds |
| Started | Sep 01 09:45:31 AM UTC 24 |
| Finished | Sep 01 09:45:33 AM UTC 24 |
| Peak memory | 215996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561429069 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 25.edn_smoke.1561429069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/25.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/25.edn_stress_all.4016644494 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 287550639 ps |
| CPU time | 1.4 seconds |
| Started | Sep 01 09:45:32 AM UTC 24 |
| Finished | Sep 01 09:45:34 AM UTC 24 |
| Peak memory | 226260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016644494 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.4016644494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/25.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/25.edn_stress_all_with_rand_reset.1317732257 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 3963833586 ps |
| CPU time | 112.15 seconds |
| Started | Sep 01 09:45:33 AM UTC 24 |
| Finished | Sep 01 09:47:28 AM UTC 24 |
| Peak memory | 234144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317732257 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all _with_rand_reset.1317732257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/25.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/250.edn_genbits.4155595019 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 57000304 ps |
| CPU time | 1.78 seconds |
| Started | Sep 01 09:50:41 AM UTC 24 |
| Finished | Sep 01 09:50:43 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155595019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 250.edn_genbits.4155595019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/250.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/251.edn_genbits.4078364115 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 106216635 ps |
| CPU time | 1.56 seconds |
| Started | Sep 01 09:50:41 AM UTC 24 |
| Finished | Sep 01 09:50:43 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078364115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 251.edn_genbits.4078364115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/251.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/252.edn_genbits.1402323794 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 54839354 ps |
| CPU time | 2.02 seconds |
| Started | Sep 01 09:50:42 AM UTC 24 |
| Finished | Sep 01 09:50:45 AM UTC 24 |
| Peak memory | 229748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402323794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1402323794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/252.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/253.edn_genbits.2608062233 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 68330418 ps |
| CPU time | 1.77 seconds |
| Started | Sep 01 09:50:42 AM UTC 24 |
| Finished | Sep 01 09:50:44 AM UTC 24 |
| Peak memory | 228332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608062233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 253.edn_genbits.2608062233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/253.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/254.edn_genbits.2394611252 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 32912607 ps |
| CPU time | 2.3 seconds |
| Started | Sep 01 09:50:42 AM UTC 24 |
| Finished | Sep 01 09:50:45 AM UTC 24 |
| Peak memory | 229728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394611252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2394611252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/254.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/255.edn_genbits.4281368285 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 28408596 ps |
| CPU time | 1.8 seconds |
| Started | Sep 01 09:50:42 AM UTC 24 |
| Finished | Sep 01 09:50:45 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281368285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 255.edn_genbits.4281368285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/255.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/256.edn_genbits.2219650268 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 92964187 ps |
| CPU time | 2.76 seconds |
| Started | Sep 01 09:50:42 AM UTC 24 |
| Finished | Sep 01 09:50:46 AM UTC 24 |
| Peak memory | 229776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219650268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 256.edn_genbits.2219650268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/256.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/257.edn_genbits.1915100121 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 27004190 ps |
| CPU time | 1.7 seconds |
| Started | Sep 01 09:50:43 AM UTC 24 |
| Finished | Sep 01 09:50:46 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915100121 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1915100121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/257.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/258.edn_genbits.301844469 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 49450481 ps |
| CPU time | 1.63 seconds |
| Started | Sep 01 09:50:43 AM UTC 24 |
| Finished | Sep 01 09:50:46 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301844469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 258.edn_genbits.301844469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/258.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/259.edn_genbits.1072376426 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 127082223 ps |
| CPU time | 3.29 seconds |
| Started | Sep 01 09:50:44 AM UTC 24 |
| Finished | Sep 01 09:50:49 AM UTC 24 |
| Peak memory | 231580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072376426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1072376426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/259.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/26.edn_alert.4127418672 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 29225832 ps |
| CPU time | 1.8 seconds |
| Started | Sep 01 09:45:40 AM UTC 24 |
| Finished | Sep 01 09:45:43 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127418672 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 26.edn_alert.4127418672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/26.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/26.edn_alert_test.778566905 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 34799775 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 09:45:43 AM UTC 24 |
| Finished | Sep 01 09:45:45 AM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778566905 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.778566905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/26.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/26.edn_disable_auto_req_mode.552261486 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 120648741 ps |
| CPU time | 1.58 seconds |
| Started | Sep 01 09:45:43 AM UTC 24 |
| Finished | Sep 01 09:45:46 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552261486 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable_auto_req_mode.552261486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/26.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/26.edn_err.1842011512 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 53289526 ps |
| CPU time | 1.67 seconds |
| Started | Sep 01 09:45:41 AM UTC 24 |
| Finished | Sep 01 09:45:44 AM UTC 24 |
| Peak memory | 230408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842011512 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 26.edn_err.1842011512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/26.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/26.edn_genbits.224253067 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 79829381 ps |
| CPU time | 2.39 seconds |
| Started | Sep 01 09:45:38 AM UTC 24 |
| Finished | Sep 01 09:45:41 AM UTC 24 |
| Peak memory | 231652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224253067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 26.edn_genbits.224253067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/26.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/26.edn_intr.1212675140 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 22006908 ps |
| CPU time | 1.61 seconds |
| Started | Sep 01 09:45:40 AM UTC 24 |
| Finished | Sep 01 09:45:43 AM UTC 24 |
| Peak memory | 236704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212675140 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.1212675140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/26.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/26.edn_smoke.1228384597 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 38652966 ps |
| CPU time | 1.4 seconds |
| Started | Sep 01 09:45:38 AM UTC 24 |
| Finished | Sep 01 09:45:40 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228384597 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 26.edn_smoke.1228384597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/26.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/26.edn_stress_all.3687520990 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 1511573922 ps |
| CPU time | 5.98 seconds |
| Started | Sep 01 09:45:38 AM UTC 24 |
| Finished | Sep 01 09:45:45 AM UTC 24 |
| Peak memory | 227504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687520990 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3687520990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/26.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/26.edn_stress_all_with_rand_reset.2342045908 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 2239895062 ps |
| CPU time | 57.72 seconds |
| Started | Sep 01 09:45:39 AM UTC 24 |
| Finished | Sep 01 09:46:38 AM UTC 24 |
| Peak memory | 232184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342045908 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all _with_rand_reset.2342045908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/26.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/260.edn_genbits.1947598930 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 23743560 ps |
| CPU time | 1.67 seconds |
| Started | Sep 01 09:50:44 AM UTC 24 |
| Finished | Sep 01 09:50:47 AM UTC 24 |
| Peak memory | 226316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947598930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 260.edn_genbits.1947598930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/260.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/261.edn_genbits.1551065859 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 28468659 ps |
| CPU time | 1.62 seconds |
| Started | Sep 01 09:50:44 AM UTC 24 |
| Finished | Sep 01 09:50:47 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551065859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1551065859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/261.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/262.edn_genbits.3221597338 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 36755771 ps |
| CPU time | 2.14 seconds |
| Started | Sep 01 09:50:44 AM UTC 24 |
| Finished | Sep 01 09:50:47 AM UTC 24 |
| Peak memory | 231520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221597338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3221597338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/262.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/263.edn_genbits.1284387415 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 137900102 ps |
| CPU time | 1.68 seconds |
| Started | Sep 01 09:50:44 AM UTC 24 |
| Finished | Sep 01 09:50:47 AM UTC 24 |
| Peak memory | 228356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284387415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1284387415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/263.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/264.edn_genbits.3047873352 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 265391557 ps |
| CPU time | 1.52 seconds |
| Started | Sep 01 09:50:45 AM UTC 24 |
| Finished | Sep 01 09:50:47 AM UTC 24 |
| Peak memory | 228356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047873352 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 264.edn_genbits.3047873352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/264.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/265.edn_genbits.2087377488 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 66924443 ps |
| CPU time | 3.17 seconds |
| Started | Sep 01 09:50:45 AM UTC 24 |
| Finished | Sep 01 09:50:49 AM UTC 24 |
| Peak memory | 229436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087377488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2087377488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/265.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/266.edn_genbits.1386300695 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 56805959 ps |
| CPU time | 1.77 seconds |
| Started | Sep 01 09:50:46 AM UTC 24 |
| Finished | Sep 01 09:50:48 AM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386300695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1386300695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/266.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/267.edn_genbits.4281975587 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 47958082 ps |
| CPU time | 1.67 seconds |
| Started | Sep 01 09:50:46 AM UTC 24 |
| Finished | Sep 01 09:50:48 AM UTC 24 |
| Peak memory | 226316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281975587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 267.edn_genbits.4281975587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/267.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/269.edn_genbits.923827548 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 81179143 ps |
| CPU time | 1.98 seconds |
| Started | Sep 01 09:50:46 AM UTC 24 |
| Finished | Sep 01 09:50:49 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923827548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 269.edn_genbits.923827548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/269.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/27.edn_alert.1755869553 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 109926898 ps |
| CPU time | 1.89 seconds |
| Started | Sep 01 09:45:47 AM UTC 24 |
| Finished | Sep 01 09:45:50 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755869553 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 27.edn_alert.1755869553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/27.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/27.edn_alert_test.2839503134 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 93500370 ps |
| CPU time | 0.99 seconds |
| Started | Sep 01 09:45:49 AM UTC 24 |
| Finished | Sep 01 09:45:51 AM UTC 24 |
| Peak memory | 216852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839503134 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2839503134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/27.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/27.edn_disable.3830027949 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 29017105 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 09:45:48 AM UTC 24 |
| Finished | Sep 01 09:45:50 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830027949 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3830027949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/27.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/27.edn_disable_auto_req_mode.63111951 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 46080815 ps |
| CPU time | 1.56 seconds |
| Started | Sep 01 09:45:48 AM UTC 24 |
| Finished | Sep 01 09:45:50 AM UTC 24 |
| Peak memory | 228300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63111951 -assert nopostproc +UVM_TESTNAME=edn_disab le_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable_auto_req_mode.63111951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/27.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/27.edn_err.156930213 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 23295477 ps |
| CPU time | 1.32 seconds |
| Started | Sep 01 09:45:47 AM UTC 24 |
| Finished | Sep 01 09:45:49 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156930213 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 27.edn_err.156930213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/27.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/27.edn_genbits.607351703 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 73658566 ps |
| CPU time | 1.56 seconds |
| Started | Sep 01 09:45:44 AM UTC 24 |
| Finished | Sep 01 09:45:47 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607351703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 27.edn_genbits.607351703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/27.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/27.edn_intr.3787106880 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 43190127 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 09:45:46 AM UTC 24 |
| Finished | Sep 01 09:45:48 AM UTC 24 |
| Peak memory | 226500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787106880 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.3787106880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/27.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/27.edn_smoke.1724774876 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 34745735 ps |
| CPU time | 1.36 seconds |
| Started | Sep 01 09:45:44 AM UTC 24 |
| Finished | Sep 01 09:45:47 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724774876 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 27.edn_smoke.1724774876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/27.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/27.edn_stress_all.1567491853 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 177160016 ps |
| CPU time | 4.71 seconds |
| Started | Sep 01 09:45:45 AM UTC 24 |
| Finished | Sep 01 09:45:51 AM UTC 24 |
| Peak memory | 227424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567491853 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1567491853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/27.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/27.edn_stress_all_with_rand_reset.2754434619 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 25044206749 ps |
| CPU time | 134.05 seconds |
| Started | Sep 01 09:45:45 AM UTC 24 |
| Finished | Sep 01 09:48:03 AM UTC 24 |
| Peak memory | 229720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754434619 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all _with_rand_reset.2754434619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/27.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/270.edn_genbits.3628715878 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 82214017 ps |
| CPU time | 2.45 seconds |
| Started | Sep 01 09:50:46 AM UTC 24 |
| Finished | Sep 01 09:50:49 AM UTC 24 |
| Peak memory | 231500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628715878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 270.edn_genbits.3628715878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/270.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/271.edn_genbits.1792340395 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 100004180 ps |
| CPU time | 3.04 seconds |
| Started | Sep 01 09:50:47 AM UTC 24 |
| Finished | Sep 01 09:50:51 AM UTC 24 |
| Peak memory | 229428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792340395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 271.edn_genbits.1792340395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/271.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/272.edn_genbits.78299629 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 209674137 ps |
| CPU time | 4.13 seconds |
| Started | Sep 01 09:50:47 AM UTC 24 |
| Finished | Sep 01 09:50:52 AM UTC 24 |
| Peak memory | 231484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78299629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn _genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 272.edn_genbits.78299629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/272.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/273.edn_genbits.2485165812 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 43864074 ps |
| CPU time | 1.67 seconds |
| Started | Sep 01 09:50:47 AM UTC 24 |
| Finished | Sep 01 09:50:50 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485165812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2485165812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/273.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/274.edn_genbits.586254983 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 64511302 ps |
| CPU time | 2.75 seconds |
| Started | Sep 01 09:50:48 AM UTC 24 |
| Finished | Sep 01 09:50:52 AM UTC 24 |
| Peak memory | 229444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586254983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 274.edn_genbits.586254983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/274.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/275.edn_genbits.1902143006 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 71221443 ps |
| CPU time | 1.96 seconds |
| Started | Sep 01 09:50:48 AM UTC 24 |
| Finished | Sep 01 09:50:51 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902143006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 275.edn_genbits.1902143006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/275.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/276.edn_genbits.557944826 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 128602383 ps |
| CPU time | 1.61 seconds |
| Started | Sep 01 09:50:48 AM UTC 24 |
| Finished | Sep 01 09:50:51 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557944826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 276.edn_genbits.557944826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/276.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/277.edn_genbits.3810688106 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 65708731 ps |
| CPU time | 2.13 seconds |
| Started | Sep 01 09:50:48 AM UTC 24 |
| Finished | Sep 01 09:50:52 AM UTC 24 |
| Peak memory | 229448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810688106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 277.edn_genbits.3810688106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/277.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/278.edn_genbits.2478799088 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 40769891 ps |
| CPU time | 2.57 seconds |
| Started | Sep 01 09:50:48 AM UTC 24 |
| Finished | Sep 01 09:50:52 AM UTC 24 |
| Peak memory | 229532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478799088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 278.edn_genbits.2478799088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/278.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/279.edn_genbits.857980544 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 54986373 ps |
| CPU time | 1.73 seconds |
| Started | Sep 01 09:50:50 AM UTC 24 |
| Finished | Sep 01 09:50:52 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857980544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 279.edn_genbits.857980544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/279.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/28.edn_alert.3474572600 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 28920919 ps |
| CPU time | 1.58 seconds |
| Started | Sep 01 09:45:52 AM UTC 24 |
| Finished | Sep 01 09:45:55 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474572600 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 28.edn_alert.3474572600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/28.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/28.edn_alert_test.3899910687 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 40408974 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 09:45:55 AM UTC 24 |
| Finished | Sep 01 09:45:57 AM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899910687 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3899910687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/28.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/28.edn_disable.1557095384 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 10256452 ps |
| CPU time | 1.35 seconds |
| Started | Sep 01 09:45:55 AM UTC 24 |
| Finished | Sep 01 09:45:57 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557095384 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1557095384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/28.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/28.edn_disable_auto_req_mode.3283433355 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 58295600 ps |
| CPU time | 1.72 seconds |
| Started | Sep 01 09:45:55 AM UTC 24 |
| Finished | Sep 01 09:45:58 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283433355 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable_auto_req_mode.3283433355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/28.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/28.edn_err.4273767913 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 25285997 ps |
| CPU time | 1.6 seconds |
| Started | Sep 01 09:45:52 AM UTC 24 |
| Finished | Sep 01 09:45:55 AM UTC 24 |
| Peak memory | 230408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273767913 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 28.edn_err.4273767913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/28.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/28.edn_genbits.2758984307 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 36055100 ps |
| CPU time | 1.53 seconds |
| Started | Sep 01 09:45:51 AM UTC 24 |
| Finished | Sep 01 09:45:54 AM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758984307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2758984307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/28.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/28.edn_intr.2400802988 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 36035259 ps |
| CPU time | 1.26 seconds |
| Started | Sep 01 09:45:51 AM UTC 24 |
| Finished | Sep 01 09:45:54 AM UTC 24 |
| Peak memory | 226320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400802988 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2400802988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/28.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/28.edn_smoke.4149647026 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 43662525 ps |
| CPU time | 1.44 seconds |
| Started | Sep 01 09:45:50 AM UTC 24 |
| Finished | Sep 01 09:45:52 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149647026 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 28.edn_smoke.4149647026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/28.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/28.edn_stress_all.1590845119 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 419042848 ps |
| CPU time | 3.05 seconds |
| Started | Sep 01 09:45:51 AM UTC 24 |
| Finished | Sep 01 09:45:55 AM UTC 24 |
| Peak memory | 231592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590845119 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1590845119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/28.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/280.edn_genbits.3346064608 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 67424679 ps |
| CPU time | 1.84 seconds |
| Started | Sep 01 09:50:50 AM UTC 24 |
| Finished | Sep 01 09:50:52 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346064608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3346064608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/280.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/281.edn_genbits.82008501 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 72301755 ps |
| CPU time | 1.9 seconds |
| Started | Sep 01 09:50:50 AM UTC 24 |
| Finished | Sep 01 09:50:52 AM UTC 24 |
| Peak memory | 230608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82008501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn _genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 281.edn_genbits.82008501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/281.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/282.edn_genbits.2873327746 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 40239475 ps |
| CPU time | 1.64 seconds |
| Started | Sep 01 09:50:50 AM UTC 24 |
| Finished | Sep 01 09:50:52 AM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873327746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2873327746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/282.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/283.edn_genbits.1667064843 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 29220392 ps |
| CPU time | 1.87 seconds |
| Started | Sep 01 09:50:50 AM UTC 24 |
| Finished | Sep 01 09:50:53 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667064843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1667064843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/283.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/284.edn_genbits.1068260124 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 47399358 ps |
| CPU time | 1.55 seconds |
| Started | Sep 01 09:50:51 AM UTC 24 |
| Finished | Sep 01 09:50:53 AM UTC 24 |
| Peak memory | 228276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068260124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1068260124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/284.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/285.edn_genbits.2337881793 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 26377227 ps |
| CPU time | 1.84 seconds |
| Started | Sep 01 09:50:51 AM UTC 24 |
| Finished | Sep 01 09:50:54 AM UTC 24 |
| Peak memory | 228312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337881793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2337881793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/285.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/286.edn_genbits.303411105 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 30113376 ps |
| CPU time | 1.76 seconds |
| Started | Sep 01 09:50:51 AM UTC 24 |
| Finished | Sep 01 09:50:54 AM UTC 24 |
| Peak memory | 230416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303411105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 286.edn_genbits.303411105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/286.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/287.edn_genbits.299704368 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 41501016 ps |
| CPU time | 1.7 seconds |
| Started | Sep 01 09:50:52 AM UTC 24 |
| Finished | Sep 01 09:50:55 AM UTC 24 |
| Peak memory | 226320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299704368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 287.edn_genbits.299704368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/287.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/288.edn_genbits.2397044452 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 226318519 ps |
| CPU time | 1.98 seconds |
| Started | Sep 01 09:50:52 AM UTC 24 |
| Finished | Sep 01 09:50:55 AM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397044452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2397044452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/288.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/289.edn_genbits.638161187 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 59270275 ps |
| CPU time | 1.53 seconds |
| Started | Sep 01 09:50:52 AM UTC 24 |
| Finished | Sep 01 09:50:55 AM UTC 24 |
| Peak memory | 230416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638161187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 289.edn_genbits.638161187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/289.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/29.edn_alert_test.3715721928 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 28750755 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 09:46:02 AM UTC 24 |
| Finished | Sep 01 09:46:04 AM UTC 24 |
| Peak memory | 216868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715721928 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3715721928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/29.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/29.edn_disable.3377966170 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 41052987 ps |
| CPU time | 1.3 seconds |
| Started | Sep 01 09:45:58 AM UTC 24 |
| Finished | Sep 01 09:46:01 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377966170 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.3377966170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/29.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/29.edn_disable_auto_req_mode.1695350953 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 80826809 ps |
| CPU time | 1.62 seconds |
| Started | Sep 01 09:46:00 AM UTC 24 |
| Finished | Sep 01 09:46:03 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695350953 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable_auto_req_mode.1695350953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/29.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/29.edn_err.2101846525 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 76325471 ps |
| CPU time | 1.83 seconds |
| Started | Sep 01 09:45:58 AM UTC 24 |
| Finished | Sep 01 09:46:01 AM UTC 24 |
| Peak memory | 242068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101846525 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 29.edn_err.2101846525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/29.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/29.edn_genbits.3967423675 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 98984829 ps |
| CPU time | 2.46 seconds |
| Started | Sep 01 09:45:56 AM UTC 24 |
| Finished | Sep 01 09:45:59 AM UTC 24 |
| Peak memory | 229688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967423675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3967423675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/29.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/29.edn_intr.1209022325 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 24937435 ps |
| CPU time | 1.33 seconds |
| Started | Sep 01 09:45:58 AM UTC 24 |
| Finished | Sep 01 09:46:01 AM UTC 24 |
| Peak memory | 226320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209022325 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.1209022325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/29.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/29.edn_smoke.2489693281 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 18875178 ps |
| CPU time | 1.56 seconds |
| Started | Sep 01 09:45:55 AM UTC 24 |
| Finished | Sep 01 09:45:58 AM UTC 24 |
| Peak memory | 216016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489693281 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 29.edn_smoke.2489693281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/29.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/29.edn_stress_all.1659192001 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 465677308 ps |
| CPU time | 6.62 seconds |
| Started | Sep 01 09:45:56 AM UTC 24 |
| Finished | Sep 01 09:46:04 AM UTC 24 |
| Peak memory | 229452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659192001 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1659192001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/29.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/29.edn_stress_all_with_rand_reset.3239407121 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 2154476302 ps |
| CPU time | 50.33 seconds |
| Started | Sep 01 09:45:56 AM UTC 24 |
| Finished | Sep 01 09:46:48 AM UTC 24 |
| Peak memory | 231804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239407121 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all _with_rand_reset.3239407121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/29.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/290.edn_genbits.3348431459 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 28890919 ps |
| CPU time | 1.63 seconds |
| Started | Sep 01 09:50:52 AM UTC 24 |
| Finished | Sep 01 09:50:55 AM UTC 24 |
| Peak memory | 228636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348431459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 290.edn_genbits.3348431459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/290.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/291.edn_genbits.2176432464 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 60637153 ps |
| CPU time | 1.69 seconds |
| Started | Sep 01 09:50:53 AM UTC 24 |
| Finished | Sep 01 09:50:56 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176432464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2176432464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/291.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/292.edn_genbits.1238715027 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 75007277 ps |
| CPU time | 2.64 seconds |
| Started | Sep 01 09:50:53 AM UTC 24 |
| Finished | Sep 01 09:50:57 AM UTC 24 |
| Peak memory | 229524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238715027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 292.edn_genbits.1238715027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/292.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/293.edn_genbits.1205971304 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 60380996 ps |
| CPU time | 1.91 seconds |
| Started | Sep 01 09:50:53 AM UTC 24 |
| Finished | Sep 01 09:50:56 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205971304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1205971304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/293.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/294.edn_genbits.2378609981 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 44954075 ps |
| CPU time | 2.04 seconds |
| Started | Sep 01 09:50:54 AM UTC 24 |
| Finished | Sep 01 09:50:57 AM UTC 24 |
| Peak memory | 231584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378609981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 294.edn_genbits.2378609981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/294.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/295.edn_genbits.4010463748 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 51168652 ps |
| CPU time | 2.03 seconds |
| Started | Sep 01 09:50:54 AM UTC 24 |
| Finished | Sep 01 09:50:57 AM UTC 24 |
| Peak memory | 229736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010463748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 295.edn_genbits.4010463748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/295.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/296.edn_genbits.3492467171 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 39172391 ps |
| CPU time | 2.05 seconds |
| Started | Sep 01 09:50:54 AM UTC 24 |
| Finished | Sep 01 09:50:57 AM UTC 24 |
| Peak memory | 229472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492467171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3492467171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/296.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/297.edn_genbits.3561600657 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 42302848 ps |
| CPU time | 1.81 seconds |
| Started | Sep 01 09:50:54 AM UTC 24 |
| Finished | Sep 01 09:50:57 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561600657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 297.edn_genbits.3561600657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/297.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/298.edn_genbits.4190335905 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 37034088 ps |
| CPU time | 1.97 seconds |
| Started | Sep 01 09:50:54 AM UTC 24 |
| Finished | Sep 01 09:50:57 AM UTC 24 |
| Peak memory | 230608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190335905 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 298.edn_genbits.4190335905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/298.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/299.edn_genbits.1197934625 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 30899248 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 09:50:55 AM UTC 24 |
| Finished | Sep 01 09:50:57 AM UTC 24 |
| Peak memory | 226316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197934625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1197934625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/299.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/3.edn_alert.342818463 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 56862049 ps |
| CPU time | 1.8 seconds |
| Started | Sep 01 09:44:00 AM UTC 24 |
| Finished | Sep 01 09:44:02 AM UTC 24 |
| Peak memory | 232516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342818463 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 3.edn_alert.342818463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/3.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/3.edn_alert_test.1499433963 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 40600596 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 09:44:01 AM UTC 24 |
| Finished | Sep 01 09:44:03 AM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499433963 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.1499433963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/3.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/3.edn_disable.4084669243 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 10172392 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 09:44:00 AM UTC 24 |
| Finished | Sep 01 09:44:02 AM UTC 24 |
| Peak memory | 226368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084669243 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.4084669243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/3.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/3.edn_disable_auto_req_mode.2851563889 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 46534221 ps |
| CPU time | 1.43 seconds |
| Started | Sep 01 09:44:01 AM UTC 24 |
| Finished | Sep 01 09:44:03 AM UTC 24 |
| Peak memory | 228304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851563889 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable_auto_req_mode.2851563889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/3.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/3.edn_err.3542965142 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 23359016 ps |
| CPU time | 1.87 seconds |
| Started | Sep 01 09:44:00 AM UTC 24 |
| Finished | Sep 01 09:44:03 AM UTC 24 |
| Peak memory | 230364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542965142 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 3.edn_err.3542965142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/3.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/3.edn_genbits.920871722 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 83638556 ps |
| CPU time | 4.05 seconds |
| Started | Sep 01 09:43:58 AM UTC 24 |
| Finished | Sep 01 09:44:03 AM UTC 24 |
| Peak memory | 231608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920871722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 3.edn_genbits.920871722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/3.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/3.edn_sec_cm.3711082046 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1101757743 ps |
| CPU time | 8.03 seconds |
| Started | Sep 01 09:44:01 AM UTC 24 |
| Finished | Sep 01 09:44:10 AM UTC 24 |
| Peak memory | 260460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711082046 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3711082046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/3.edn_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/3.edn_smoke.1177746857 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 39585198 ps |
| CPU time | 1.32 seconds |
| Started | Sep 01 09:43:57 AM UTC 24 |
| Finished | Sep 01 09:43:59 AM UTC 24 |
| Peak memory | 226260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177746857 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 3.edn_smoke.1177746857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/3.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/3.edn_stress_all.2654838533 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 870309980 ps |
| CPU time | 5.91 seconds |
| Started | Sep 01 09:43:58 AM UTC 24 |
| Finished | Sep 01 09:44:05 AM UTC 24 |
| Peak memory | 227540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654838533 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2654838533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/3.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/3.edn_stress_all_with_rand_reset.940045712 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 3082441955 ps |
| CPU time | 81.6 seconds |
| Started | Sep 01 09:43:59 AM UTC 24 |
| Finished | Sep 01 09:45:23 AM UTC 24 |
| Peak memory | 229992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940045712 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_w ith_rand_reset.940045712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/3.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/30.edn_alert.4229315818 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 36784580 ps |
| CPU time | 1.61 seconds |
| Started | Sep 01 09:46:05 AM UTC 24 |
| Finished | Sep 01 09:46:08 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229315818 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 30.edn_alert.4229315818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/30.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/30.edn_alert_test.832784388 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 16814366 ps |
| CPU time | 1.42 seconds |
| Started | Sep 01 09:46:06 AM UTC 24 |
| Finished | Sep 01 09:46:09 AM UTC 24 |
| Peak memory | 216688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832784388 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.832784388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/30.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/30.edn_disable.1661256865 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 22574594 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 09:46:05 AM UTC 24 |
| Finished | Sep 01 09:46:07 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661256865 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1661256865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/30.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/30.edn_disable_auto_req_mode.3180468301 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 66068644 ps |
| CPU time | 1.69 seconds |
| Started | Sep 01 09:46:06 AM UTC 24 |
| Finished | Sep 01 09:46:09 AM UTC 24 |
| Peak memory | 230348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180468301 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable_auto_req_mode.3180468301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/30.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/30.edn_err.3505585080 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 27777351 ps |
| CPU time | 1.43 seconds |
| Started | Sep 01 09:46:05 AM UTC 24 |
| Finished | Sep 01 09:46:07 AM UTC 24 |
| Peak memory | 236960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505585080 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 30.edn_err.3505585080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/30.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/30.edn_genbits.2508548107 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 38584222 ps |
| CPU time | 1.95 seconds |
| Started | Sep 01 09:46:02 AM UTC 24 |
| Finished | Sep 01 09:46:05 AM UTC 24 |
| Peak memory | 228340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508548107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2508548107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/30.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/30.edn_smoke.2714104185 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 21616073 ps |
| CPU time | 1.3 seconds |
| Started | Sep 01 09:46:02 AM UTC 24 |
| Finished | Sep 01 09:46:04 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714104185 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 30.edn_smoke.2714104185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/30.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/30.edn_stress_all.337132697 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 507085666 ps |
| CPU time | 6.88 seconds |
| Started | Sep 01 09:46:02 AM UTC 24 |
| Finished | Sep 01 09:46:10 AM UTC 24 |
| Peak memory | 231452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337132697 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.337132697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/30.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/31.edn_alert.1092935269 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 41716163 ps |
| CPU time | 1.65 seconds |
| Started | Sep 01 09:46:10 AM UTC 24 |
| Finished | Sep 01 09:46:12 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092935269 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 31.edn_alert.1092935269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/31.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/31.edn_alert_test.3124647922 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 120005228 ps |
| CPU time | 1.24 seconds |
| Started | Sep 01 09:46:11 AM UTC 24 |
| Finished | Sep 01 09:46:13 AM UTC 24 |
| Peak memory | 226532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124647922 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3124647922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/31.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/31.edn_disable.1437661933 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 155947703 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 09:46:11 AM UTC 24 |
| Finished | Sep 01 09:46:13 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437661933 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.1437661933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/31.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/31.edn_disable_auto_req_mode.1632939322 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 56897767 ps |
| CPU time | 1.69 seconds |
| Started | Sep 01 09:46:11 AM UTC 24 |
| Finished | Sep 01 09:46:14 AM UTC 24 |
| Peak memory | 228360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632939322 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable_auto_req_mode.1632939322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/31.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/31.edn_err.2664160329 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 30699415 ps |
| CPU time | 1.98 seconds |
| Started | Sep 01 09:46:11 AM UTC 24 |
| Finished | Sep 01 09:46:14 AM UTC 24 |
| Peak memory | 242068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664160329 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 31.edn_err.2664160329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/31.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/31.edn_genbits.944063836 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 85828486 ps |
| CPU time | 1.78 seconds |
| Started | Sep 01 09:46:08 AM UTC 24 |
| Finished | Sep 01 09:46:11 AM UTC 24 |
| Peak memory | 230416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944063836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 31.edn_genbits.944063836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/31.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/31.edn_intr.1351096237 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 20103514 ps |
| CPU time | 1.65 seconds |
| Started | Sep 01 09:46:10 AM UTC 24 |
| Finished | Sep 01 09:46:12 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351096237 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.1351096237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/31.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/31.edn_smoke.2943729804 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 14363576 ps |
| CPU time | 1.47 seconds |
| Started | Sep 01 09:46:07 AM UTC 24 |
| Finished | Sep 01 09:46:10 AM UTC 24 |
| Peak memory | 226260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943729804 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 31.edn_smoke.2943729804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/31.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/31.edn_stress_all.3388304402 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 50280741 ps |
| CPU time | 1.77 seconds |
| Started | Sep 01 09:46:09 AM UTC 24 |
| Finished | Sep 01 09:46:11 AM UTC 24 |
| Peak memory | 226676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388304402 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3388304402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/31.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/32.edn_alert.2280675874 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 45342164 ps |
| CPU time | 1.78 seconds |
| Started | Sep 01 09:46:14 AM UTC 24 |
| Finished | Sep 01 09:46:17 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280675874 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 32.edn_alert.2280675874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/32.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/32.edn_alert_test.2722105769 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 30684459 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 09:46:16 AM UTC 24 |
| Finished | Sep 01 09:46:18 AM UTC 24 |
| Peak memory | 226728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722105769 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2722105769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/32.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/32.edn_disable.2292435472 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 39189434 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 09:46:15 AM UTC 24 |
| Finished | Sep 01 09:46:17 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292435472 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2292435472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/32.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/32.edn_disable_auto_req_mode.2835339280 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 59852222 ps |
| CPU time | 1.32 seconds |
| Started | Sep 01 09:46:15 AM UTC 24 |
| Finished | Sep 01 09:46:17 AM UTC 24 |
| Peak memory | 228300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835339280 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable_auto_req_mode.2835339280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/32.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/32.edn_genbits.2909363458 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 77330903 ps |
| CPU time | 1.68 seconds |
| Started | Sep 01 09:46:12 AM UTC 24 |
| Finished | Sep 01 09:46:15 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909363458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2909363458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/32.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/32.edn_intr.3017727352 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 40002374 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 09:46:13 AM UTC 24 |
| Finished | Sep 01 09:46:16 AM UTC 24 |
| Peak memory | 226320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017727352 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3017727352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/32.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/32.edn_smoke.3471915000 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 132869857 ps |
| CPU time | 1.32 seconds |
| Started | Sep 01 09:46:12 AM UTC 24 |
| Finished | Sep 01 09:46:15 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471915000 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 32.edn_smoke.3471915000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/32.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/32.edn_stress_all.80018154 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 401876967 ps |
| CPU time | 10.3 seconds |
| Started | Sep 01 09:46:13 AM UTC 24 |
| Finished | Sep 01 09:46:25 AM UTC 24 |
| Peak memory | 229732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80018154 -assert nopostproc +UVM_TESTNAME=edn_s tress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.80018154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/32.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/32.edn_stress_all_with_rand_reset.450707051 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 24305293211 ps |
| CPU time | 115.82 seconds |
| Started | Sep 01 09:46:13 AM UTC 24 |
| Finished | Sep 01 09:48:11 AM UTC 24 |
| Peak memory | 229796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450707051 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_ with_rand_reset.450707051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/32.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/33.edn_alert.2229223423 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 42172055 ps |
| CPU time | 1.88 seconds |
| Started | Sep 01 09:46:18 AM UTC 24 |
| Finished | Sep 01 09:46:21 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229223423 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 33.edn_alert.2229223423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/33.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/33.edn_alert_test.2969765366 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 35318437 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 09:46:22 AM UTC 24 |
| Finished | Sep 01 09:46:24 AM UTC 24 |
| Peak memory | 216504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969765366 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2969765366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/33.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/33.edn_disable.3734213815 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 59227787 ps |
| CPU time | 1.26 seconds |
| Started | Sep 01 09:46:19 AM UTC 24 |
| Finished | Sep 01 09:46:21 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734213815 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.3734213815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/33.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/33.edn_disable_auto_req_mode.470788387 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 35162959 ps |
| CPU time | 1.83 seconds |
| Started | Sep 01 09:46:21 AM UTC 24 |
| Finished | Sep 01 09:46:24 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470788387 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable_auto_req_mode.470788387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/33.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/33.edn_err.2344373340 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 33831861 ps |
| CPU time | 1.8 seconds |
| Started | Sep 01 09:46:19 AM UTC 24 |
| Finished | Sep 01 09:46:22 AM UTC 24 |
| Peak memory | 230408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344373340 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 33.edn_err.2344373340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/33.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/33.edn_genbits.2304877313 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 596717126 ps |
| CPU time | 9.07 seconds |
| Started | Sep 01 09:46:17 AM UTC 24 |
| Finished | Sep 01 09:46:27 AM UTC 24 |
| Peak memory | 231584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304877313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2304877313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/33.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/33.edn_intr.1533720718 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 27420976 ps |
| CPU time | 1.4 seconds |
| Started | Sep 01 09:46:18 AM UTC 24 |
| Finished | Sep 01 09:46:20 AM UTC 24 |
| Peak memory | 226320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533720718 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.1533720718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/33.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/33.edn_smoke.3562306004 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 52125040 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 09:46:16 AM UTC 24 |
| Finished | Sep 01 09:46:18 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562306004 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 33.edn_smoke.3562306004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/33.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/33.edn_stress_all.532210557 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 276164641 ps |
| CPU time | 7.9 seconds |
| Started | Sep 01 09:46:18 AM UTC 24 |
| Finished | Sep 01 09:46:27 AM UTC 24 |
| Peak memory | 227384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532210557 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.532210557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/33.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/34.edn_alert.3815144068 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 32283585 ps |
| CPU time | 2.06 seconds |
| Started | Sep 01 09:46:26 AM UTC 24 |
| Finished | Sep 01 09:46:29 AM UTC 24 |
| Peak memory | 228224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815144068 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 34.edn_alert.3815144068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/34.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/34.edn_alert_test.1254893676 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 45475762 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 09:46:28 AM UTC 24 |
| Finished | Sep 01 09:46:31 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254893676 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1254893676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/34.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/34.edn_disable.4288362266 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 32211204 ps |
| CPU time | 1.33 seconds |
| Started | Sep 01 09:46:26 AM UTC 24 |
| Finished | Sep 01 09:46:28 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288362266 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.4288362266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/34.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/34.edn_disable_auto_req_mode.3979780138 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 91970270 ps |
| CPU time | 1.57 seconds |
| Started | Sep 01 09:46:28 AM UTC 24 |
| Finished | Sep 01 09:46:31 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979780138 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable_auto_req_mode.3979780138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/34.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/34.edn_err.3030735144 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 75000133 ps |
| CPU time | 1.71 seconds |
| Started | Sep 01 09:46:26 AM UTC 24 |
| Finished | Sep 01 09:46:29 AM UTC 24 |
| Peak memory | 242180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030735144 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 34.edn_err.3030735144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/34.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/34.edn_genbits.886940527 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 70534452 ps |
| CPU time | 1.63 seconds |
| Started | Sep 01 09:46:22 AM UTC 24 |
| Finished | Sep 01 09:46:25 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886940527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 34.edn_genbits.886940527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/34.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/34.edn_intr.2366735390 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 22641690 ps |
| CPU time | 1.61 seconds |
| Started | Sep 01 09:46:26 AM UTC 24 |
| Finished | Sep 01 09:46:28 AM UTC 24 |
| Peak memory | 226320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366735390 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.2366735390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/34.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/34.edn_smoke.1895245904 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 38150098 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 09:46:22 AM UTC 24 |
| Finished | Sep 01 09:46:25 AM UTC 24 |
| Peak memory | 216016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895245904 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 34.edn_smoke.1895245904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/34.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/34.edn_stress_all.1598170941 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 987690874 ps |
| CPU time | 5.72 seconds |
| Started | Sep 01 09:46:23 AM UTC 24 |
| Finished | Sep 01 09:46:29 AM UTC 24 |
| Peak memory | 229460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598170941 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1598170941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/34.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/34.edn_stress_all_with_rand_reset.3581081971 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 8681277350 ps |
| CPU time | 55.42 seconds |
| Started | Sep 01 09:46:25 AM UTC 24 |
| Finished | Sep 01 09:47:22 AM UTC 24 |
| Peak memory | 230072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581081971 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all _with_rand_reset.3581081971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/34.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/35.edn_alert.20475385 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 24902703 ps |
| CPU time | 1.69 seconds |
| Started | Sep 01 09:46:30 AM UTC 24 |
| Finished | Sep 01 09:46:33 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20475385 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.20475385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/35.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/35.edn_alert_test.2803016910 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 29350966 ps |
| CPU time | 1.46 seconds |
| Started | Sep 01 09:46:32 AM UTC 24 |
| Finished | Sep 01 09:46:34 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803016910 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.2803016910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/35.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/35.edn_disable.1070205783 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 19882566 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 09:46:32 AM UTC 24 |
| Finished | Sep 01 09:46:34 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070205783 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1070205783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/35.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/35.edn_disable_auto_req_mode.2658721987 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 98068694 ps |
| CPU time | 1.71 seconds |
| Started | Sep 01 09:46:32 AM UTC 24 |
| Finished | Sep 01 09:46:35 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658721987 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable_auto_req_mode.2658721987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/35.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/35.edn_err.1754717868 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 106518842 ps |
| CPU time | 1.53 seconds |
| Started | Sep 01 09:46:31 AM UTC 24 |
| Finished | Sep 01 09:46:33 AM UTC 24 |
| Peak memory | 226244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754717868 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 35.edn_err.1754717868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/35.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/35.edn_genbits.370586986 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 49534098 ps |
| CPU time | 1.74 seconds |
| Started | Sep 01 09:46:28 AM UTC 24 |
| Finished | Sep 01 09:46:31 AM UTC 24 |
| Peak memory | 230612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370586986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 35.edn_genbits.370586986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/35.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/35.edn_intr.3010313174 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 47769305 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 09:46:29 AM UTC 24 |
| Finished | Sep 01 09:46:32 AM UTC 24 |
| Peak memory | 226500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010313174 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3010313174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/35.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/35.edn_smoke.3343804204 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 35001488 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 09:46:28 AM UTC 24 |
| Finished | Sep 01 09:46:31 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343804204 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 35.edn_smoke.3343804204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/35.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/35.edn_stress_all.1829460378 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 1390776856 ps |
| CPU time | 4.66 seconds |
| Started | Sep 01 09:46:29 AM UTC 24 |
| Finished | Sep 01 09:46:35 AM UTC 24 |
| Peak memory | 227736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829460378 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1829460378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/35.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/35.edn_stress_all_with_rand_reset.3545649800 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 7667923549 ps |
| CPU time | 52.02 seconds |
| Started | Sep 01 09:46:29 AM UTC 24 |
| Finished | Sep 01 09:47:23 AM UTC 24 |
| Peak memory | 232036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545649800 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all _with_rand_reset.3545649800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/35.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/36.edn_alert.804791612 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 25419054 ps |
| CPU time | 1.62 seconds |
| Started | Sep 01 09:46:35 AM UTC 24 |
| Finished | Sep 01 09:46:38 AM UTC 24 |
| Peak memory | 226376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804791612 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 36.edn_alert.804791612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/36.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/36.edn_alert_test.3119178894 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 70623218 ps |
| CPU time | 1.09 seconds |
| Started | Sep 01 09:46:36 AM UTC 24 |
| Finished | Sep 01 09:46:38 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119178894 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3119178894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/36.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/36.edn_disable.2394836987 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 15080656 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 09:46:35 AM UTC 24 |
| Finished | Sep 01 09:46:38 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394836987 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2394836987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/36.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/36.edn_disable_auto_req_mode.1046620109 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 37704326 ps |
| CPU time | 1.78 seconds |
| Started | Sep 01 09:46:36 AM UTC 24 |
| Finished | Sep 01 09:46:39 AM UTC 24 |
| Peak memory | 228300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046620109 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable_auto_req_mode.1046620109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/36.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/36.edn_err.569872852 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 40369693 ps |
| CPU time | 1.66 seconds |
| Started | Sep 01 09:46:35 AM UTC 24 |
| Finished | Sep 01 09:46:38 AM UTC 24 |
| Peak memory | 246148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569872852 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 36.edn_err.569872852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/36.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/36.edn_intr.1525905452 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 25134450 ps |
| CPU time | 1.32 seconds |
| Started | Sep 01 09:46:35 AM UTC 24 |
| Finished | Sep 01 09:46:38 AM UTC 24 |
| Peak memory | 226320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525905452 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.1525905452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/36.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/36.edn_smoke.2892083056 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 51372575 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 09:46:32 AM UTC 24 |
| Finished | Sep 01 09:46:34 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892083056 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 36.edn_smoke.2892083056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/36.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/36.edn_stress_all.651092973 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 1762666757 ps |
| CPU time | 8.4 seconds |
| Started | Sep 01 09:46:34 AM UTC 24 |
| Finished | Sep 01 09:46:44 AM UTC 24 |
| Peak memory | 229540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651092973 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.651092973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/36.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/36.edn_stress_all_with_rand_reset.4077752357 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 12308449300 ps |
| CPU time | 154.69 seconds |
| Started | Sep 01 09:46:34 AM UTC 24 |
| Finished | Sep 01 09:49:12 AM UTC 24 |
| Peak memory | 229760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077752357 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all _with_rand_reset.4077752357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/36.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/37.edn_alert.3344919431 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 41213921 ps |
| CPU time | 1.67 seconds |
| Started | Sep 01 09:46:40 AM UTC 24 |
| Finished | Sep 01 09:46:43 AM UTC 24 |
| Peak memory | 228428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344919431 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 37.edn_alert.3344919431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/37.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/37.edn_alert_test.1225252090 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 43485871 ps |
| CPU time | 1.26 seconds |
| Started | Sep 01 09:46:43 AM UTC 24 |
| Finished | Sep 01 09:46:46 AM UTC 24 |
| Peak memory | 216928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225252090 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.1225252090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/37.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/37.edn_disable.2355238917 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 13731182 ps |
| CPU time | 1.39 seconds |
| Started | Sep 01 09:46:42 AM UTC 24 |
| Finished | Sep 01 09:46:45 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355238917 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.2355238917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/37.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/37.edn_disable_auto_req_mode.3578438559 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 43845162 ps |
| CPU time | 1.62 seconds |
| Started | Sep 01 09:46:42 AM UTC 24 |
| Finished | Sep 01 09:46:45 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578438559 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable_auto_req_mode.3578438559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/37.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/37.edn_err.3113121555 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 21997741 ps |
| CPU time | 1.36 seconds |
| Started | Sep 01 09:46:40 AM UTC 24 |
| Finished | Sep 01 09:46:42 AM UTC 24 |
| Peak memory | 228360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113121555 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 37.edn_err.3113121555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/37.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/37.edn_intr.2345016254 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 49948767 ps |
| CPU time | 1.33 seconds |
| Started | Sep 01 09:46:39 AM UTC 24 |
| Finished | Sep 01 09:46:42 AM UTC 24 |
| Peak memory | 226300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345016254 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2345016254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/37.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/37.edn_smoke.3608828776 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 19218585 ps |
| CPU time | 1.37 seconds |
| Started | Sep 01 09:46:39 AM UTC 24 |
| Finished | Sep 01 09:46:41 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608828776 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 37.edn_smoke.3608828776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/37.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/37.edn_stress_all.1426151298 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 291062573 ps |
| CPU time | 4.94 seconds |
| Started | Sep 01 09:46:39 AM UTC 24 |
| Finished | Sep 01 09:46:45 AM UTC 24 |
| Peak memory | 229452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426151298 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1426151298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/37.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/37.edn_stress_all_with_rand_reset.1975356142 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 2805960479 ps |
| CPU time | 39.25 seconds |
| Started | Sep 01 09:46:39 AM UTC 24 |
| Finished | Sep 01 09:47:20 AM UTC 24 |
| Peak memory | 228008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975356142 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all _with_rand_reset.1975356142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/37.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/38.edn_alert.3904595720 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 144599422 ps |
| CPU time | 1.93 seconds |
| Started | Sep 01 09:46:47 AM UTC 24 |
| Finished | Sep 01 09:46:50 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904595720 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 38.edn_alert.3904595720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/38.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/38.edn_alert_test.432076788 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 35090131 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 09:46:48 AM UTC 24 |
| Finished | Sep 01 09:46:50 AM UTC 24 |
| Peak memory | 216312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432076788 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.432076788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/38.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/38.edn_disable.2226814907 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 11006847 ps |
| CPU time | 1.26 seconds |
| Started | Sep 01 09:46:47 AM UTC 24 |
| Finished | Sep 01 09:46:49 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226814907 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2226814907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/38.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/38.edn_disable_auto_req_mode.3165864876 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 50544480 ps |
| CPU time | 2.12 seconds |
| Started | Sep 01 09:46:48 AM UTC 24 |
| Finished | Sep 01 09:46:51 AM UTC 24 |
| Peak memory | 227864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165864876 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable_auto_req_mode.3165864876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/38.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/38.edn_err.2186599256 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 32894360 ps |
| CPU time | 1.37 seconds |
| Started | Sep 01 09:46:47 AM UTC 24 |
| Finished | Sep 01 09:46:50 AM UTC 24 |
| Peak memory | 228360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186599256 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 38.edn_err.2186599256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/38.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/38.edn_genbits.719388657 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 53300696 ps |
| CPU time | 2.03 seconds |
| Started | Sep 01 09:46:43 AM UTC 24 |
| Finished | Sep 01 09:46:47 AM UTC 24 |
| Peak memory | 229772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719388657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 38.edn_genbits.719388657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/38.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/38.edn_intr.184186994 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 24297899 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 09:46:45 AM UTC 24 |
| Finished | Sep 01 09:46:48 AM UTC 24 |
| Peak memory | 226316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184186994 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.184186994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/38.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/38.edn_smoke.1063670659 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 40921165 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 09:46:43 AM UTC 24 |
| Finished | Sep 01 09:46:46 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063670659 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 38.edn_smoke.1063670659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/38.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/38.edn_stress_all.4227025650 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 45448650 ps |
| CPU time | 1.63 seconds |
| Started | Sep 01 09:46:44 AM UTC 24 |
| Finished | Sep 01 09:46:47 AM UTC 24 |
| Peak memory | 226260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227025650 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.4227025650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/38.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/38.edn_stress_all_with_rand_reset.3843533829 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 3378738401 ps |
| CPU time | 95.56 seconds |
| Started | Sep 01 09:46:45 AM UTC 24 |
| Finished | Sep 01 09:48:24 AM UTC 24 |
| Peak memory | 229808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843533829 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all _with_rand_reset.3843533829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/38.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/39.edn_alert.2914833940 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 31721916 ps |
| CPU time | 1.63 seconds |
| Started | Sep 01 09:46:51 AM UTC 24 |
| Finished | Sep 01 09:46:54 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914833940 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 39.edn_alert.2914833940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/39.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/39.edn_alert_test.274199750 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 26592395 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 09:46:53 AM UTC 24 |
| Finished | Sep 01 09:46:56 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274199750 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.274199750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/39.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/39.edn_disable.2744031379 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 52401335 ps |
| CPU time | 1.33 seconds |
| Started | Sep 01 09:46:52 AM UTC 24 |
| Finished | Sep 01 09:46:55 AM UTC 24 |
| Peak memory | 226376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744031379 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2744031379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/39.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/39.edn_disable_auto_req_mode.2278799672 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 47222706 ps |
| CPU time | 1.62 seconds |
| Started | Sep 01 09:46:52 AM UTC 24 |
| Finished | Sep 01 09:46:55 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278799672 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable_auto_req_mode.2278799672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/39.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/39.edn_err.1594459094 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 23395330 ps |
| CPU time | 1.67 seconds |
| Started | Sep 01 09:46:52 AM UTC 24 |
| Finished | Sep 01 09:46:55 AM UTC 24 |
| Peak memory | 228720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594459094 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 39.edn_err.1594459094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/39.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/39.edn_genbits.3514361721 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 66887750 ps |
| CPU time | 1.64 seconds |
| Started | Sep 01 09:46:49 AM UTC 24 |
| Finished | Sep 01 09:46:52 AM UTC 24 |
| Peak memory | 230416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514361721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3514361721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/39.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/39.edn_intr.2011348119 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 27327994 ps |
| CPU time | 1.35 seconds |
| Started | Sep 01 09:46:51 AM UTC 24 |
| Finished | Sep 01 09:46:53 AM UTC 24 |
| Peak memory | 237644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011348119 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.2011348119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/39.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/39.edn_smoke.2969104525 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 30642440 ps |
| CPU time | 1.3 seconds |
| Started | Sep 01 09:46:49 AM UTC 24 |
| Finished | Sep 01 09:46:52 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969104525 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 39.edn_smoke.2969104525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/39.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/39.edn_stress_all.2434011162 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 930919901 ps |
| CPU time | 6.98 seconds |
| Started | Sep 01 09:46:50 AM UTC 24 |
| Finished | Sep 01 09:46:58 AM UTC 24 |
| Peak memory | 227432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434011162 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2434011162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/39.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/39.edn_stress_all_with_rand_reset.709007923 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 7340947180 ps |
| CPU time | 92.72 seconds |
| Started | Sep 01 09:46:50 AM UTC 24 |
| Finished | Sep 01 09:48:25 AM UTC 24 |
| Peak memory | 229784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709007923 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_ with_rand_reset.709007923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/39.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/4.edn_alert.1184238151 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 92727075 ps |
| CPU time | 1.57 seconds |
| Started | Sep 01 09:44:03 AM UTC 24 |
| Finished | Sep 01 09:44:06 AM UTC 24 |
| Peak memory | 230476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184238151 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 4.edn_alert.1184238151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/4.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/4.edn_alert_test.2699190920 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 42570630 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 09:44:05 AM UTC 24 |
| Finished | Sep 01 09:44:07 AM UTC 24 |
| Peak memory | 216688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699190920 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2699190920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/4.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/4.edn_disable.491874114 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 14666474 ps |
| CPU time | 1.26 seconds |
| Started | Sep 01 09:44:05 AM UTC 24 |
| Finished | Sep 01 09:44:07 AM UTC 24 |
| Peak memory | 216132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491874114 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.491874114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/4.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/4.edn_disable_auto_req_mode.3688022910 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 103431854 ps |
| CPU time | 1.82 seconds |
| Started | Sep 01 09:44:05 AM UTC 24 |
| Finished | Sep 01 09:44:07 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688022910 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable_auto_req_mode.3688022910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/4.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/4.edn_err.659794342 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 26059852 ps |
| CPU time | 1.32 seconds |
| Started | Sep 01 09:44:05 AM UTC 24 |
| Finished | Sep 01 09:44:07 AM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659794342 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 4.edn_err.659794342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/4.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/4.edn_genbits.1628861093 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 34097136 ps |
| CPU time | 1.71 seconds |
| Started | Sep 01 09:44:02 AM UTC 24 |
| Finished | Sep 01 09:44:05 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628861093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1628861093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/4.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/4.edn_intr.2067008548 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 37300065 ps |
| CPU time | 1.3 seconds |
| Started | Sep 01 09:44:03 AM UTC 24 |
| Finished | Sep 01 09:44:06 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067008548 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2067008548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/4.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/4.edn_regwen.2345865010 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 15898519 ps |
| CPU time | 1.37 seconds |
| Started | Sep 01 09:44:01 AM UTC 24 |
| Finished | Sep 01 09:44:03 AM UTC 24 |
| Peak memory | 216020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345865010 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 4.edn_regwen.2345865010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/4.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/4.edn_sec_cm.1105470433 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1766913251 ps |
| CPU time | 8.71 seconds |
| Started | Sep 01 09:44:05 AM UTC 24 |
| Finished | Sep 01 09:44:15 AM UTC 24 |
| Peak memory | 262492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105470433 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.1105470433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/4.edn_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/4.edn_smoke.248051590 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 66987051 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 09:44:01 AM UTC 24 |
| Finished | Sep 01 09:44:03 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248051590 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 4.edn_smoke.248051590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/4.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/4.edn_stress_all.916440868 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 314796372 ps |
| CPU time | 5.59 seconds |
| Started | Sep 01 09:44:03 AM UTC 24 |
| Finished | Sep 01 09:44:10 AM UTC 24 |
| Peak memory | 227616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916440868 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.916440868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/4.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/40.edn_alert.2286650546 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 50546034 ps |
| CPU time | 1.87 seconds |
| Started | Sep 01 09:46:57 AM UTC 24 |
| Finished | Sep 01 09:47:00 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286650546 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 40.edn_alert.2286650546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/40.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/40.edn_alert_test.2688939522 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 18617476 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 09:47:06 AM UTC 24 |
| Finished | Sep 01 09:47:08 AM UTC 24 |
| Peak memory | 216312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688939522 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2688939522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/40.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/40.edn_disable.1149743736 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 11663262 ps |
| CPU time | 1.3 seconds |
| Started | Sep 01 09:46:58 AM UTC 24 |
| Finished | Sep 01 09:47:01 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149743736 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1149743736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/40.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/40.edn_disable_auto_req_mode.454260044 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 130403028 ps |
| CPU time | 1.48 seconds |
| Started | Sep 01 09:47:06 AM UTC 24 |
| Finished | Sep 01 09:47:08 AM UTC 24 |
| Peak memory | 228300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454260044 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable_auto_req_mode.454260044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/40.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/40.edn_err.509754426 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 18476927 ps |
| CPU time | 1.6 seconds |
| Started | Sep 01 09:46:58 AM UTC 24 |
| Finished | Sep 01 09:47:01 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509754426 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 40.edn_err.509754426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/40.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/40.edn_genbits.4191013060 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 75633631 ps |
| CPU time | 1.48 seconds |
| Started | Sep 01 09:46:55 AM UTC 24 |
| Finished | Sep 01 09:46:57 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191013060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 40.edn_genbits.4191013060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/40.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/40.edn_intr.1930055515 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 25319775 ps |
| CPU time | 1.54 seconds |
| Started | Sep 01 09:46:56 AM UTC 24 |
| Finished | Sep 01 09:46:58 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930055515 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.1930055515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/40.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/40.edn_smoke.597524787 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 32185164 ps |
| CPU time | 1.34 seconds |
| Started | Sep 01 09:46:55 AM UTC 24 |
| Finished | Sep 01 09:46:57 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597524787 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 40.edn_smoke.597524787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/40.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/40.edn_stress_all.1413055014 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 368449941 ps |
| CPU time | 5.65 seconds |
| Started | Sep 01 09:46:56 AM UTC 24 |
| Finished | Sep 01 09:47:03 AM UTC 24 |
| Peak memory | 229448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413055014 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.1413055014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/40.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/41.edn_alert.2224474583 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 28628099 ps |
| CPU time | 1.7 seconds |
| Started | Sep 01 09:47:09 AM UTC 24 |
| Finished | Sep 01 09:47:12 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224474583 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 41.edn_alert.2224474583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/41.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/41.edn_alert_test.1410123170 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 56982619 ps |
| CPU time | 1.37 seconds |
| Started | Sep 01 09:47:09 AM UTC 24 |
| Finished | Sep 01 09:47:12 AM UTC 24 |
| Peak memory | 216508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410123170 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1410123170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/41.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/41.edn_disable.3723887461 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 35070076 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 09:47:09 AM UTC 24 |
| Finished | Sep 01 09:47:11 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723887461 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3723887461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/41.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/41.edn_err.1399596327 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 21628474 ps |
| CPU time | 1.59 seconds |
| Started | Sep 01 09:47:09 AM UTC 24 |
| Finished | Sep 01 09:47:12 AM UTC 24 |
| Peak memory | 230408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399596327 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 41.edn_err.1399596327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/41.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/41.edn_genbits.2441332282 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 28222315 ps |
| CPU time | 1.34 seconds |
| Started | Sep 01 09:47:06 AM UTC 24 |
| Finished | Sep 01 09:47:09 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441332282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2441332282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/41.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/41.edn_intr.3100557220 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 30569237 ps |
| CPU time | 1.48 seconds |
| Started | Sep 01 09:47:06 AM UTC 24 |
| Finished | Sep 01 09:47:09 AM UTC 24 |
| Peak memory | 226320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100557220 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.3100557220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/41.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/41.edn_smoke.2880716196 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 17059318 ps |
| CPU time | 1.4 seconds |
| Started | Sep 01 09:47:06 AM UTC 24 |
| Finished | Sep 01 09:47:08 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880716196 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 41.edn_smoke.2880716196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/41.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/41.edn_stress_all.332809128 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 256972154 ps |
| CPU time | 6.82 seconds |
| Started | Sep 01 09:47:06 AM UTC 24 |
| Finished | Sep 01 09:47:14 AM UTC 24 |
| Peak memory | 227668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332809128 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.332809128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/41.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/42.edn_alert.1204074339 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 53343082 ps |
| CPU time | 1.58 seconds |
| Started | Sep 01 09:47:15 AM UTC 24 |
| Finished | Sep 01 09:47:17 AM UTC 24 |
| Peak memory | 226376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204074339 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 42.edn_alert.1204074339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/42.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/42.edn_alert_test.890938110 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 23404507 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 09:47:18 AM UTC 24 |
| Finished | Sep 01 09:47:20 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890938110 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.890938110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/42.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/42.edn_disable.1828299971 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 130155733 ps |
| CPU time | 1.4 seconds |
| Started | Sep 01 09:47:16 AM UTC 24 |
| Finished | Sep 01 09:47:18 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828299971 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1828299971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/42.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/42.edn_disable_auto_req_mode.1368927521 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 42522466 ps |
| CPU time | 1.73 seconds |
| Started | Sep 01 09:47:16 AM UTC 24 |
| Finished | Sep 01 09:47:19 AM UTC 24 |
| Peak memory | 230348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368927521 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable_auto_req_mode.1368927521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/42.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/42.edn_err.4165737108 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 35879735 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 09:47:16 AM UTC 24 |
| Finished | Sep 01 09:47:18 AM UTC 24 |
| Peak memory | 236960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165737108 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 42.edn_err.4165737108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/42.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/42.edn_genbits.2491731710 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 72103521 ps |
| CPU time | 2 seconds |
| Started | Sep 01 09:47:13 AM UTC 24 |
| Finished | Sep 01 09:47:16 AM UTC 24 |
| Peak memory | 230416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491731710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 42.edn_genbits.2491731710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/42.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/42.edn_intr.2390489350 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 24075767 ps |
| CPU time | 1.43 seconds |
| Started | Sep 01 09:47:13 AM UTC 24 |
| Finished | Sep 01 09:47:15 AM UTC 24 |
| Peak memory | 226320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390489350 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.2390489350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/42.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/42.edn_smoke.1932970648 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 82892566 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 09:47:13 AM UTC 24 |
| Finished | Sep 01 09:47:15 AM UTC 24 |
| Peak memory | 226260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932970648 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 42.edn_smoke.1932970648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/42.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/42.edn_stress_all.4290891389 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 194822059 ps |
| CPU time | 5.99 seconds |
| Started | Sep 01 09:47:13 AM UTC 24 |
| Finished | Sep 01 09:47:20 AM UTC 24 |
| Peak memory | 229452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290891389 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.4290891389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/42.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/43.edn_alert.3071317285 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 71513232 ps |
| CPU time | 1.88 seconds |
| Started | Sep 01 09:47:22 AM UTC 24 |
| Finished | Sep 01 09:47:24 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071317285 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 43.edn_alert.3071317285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/43.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/43.edn_alert_test.1389687866 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 23419896 ps |
| CPU time | 1.23 seconds |
| Started | Sep 01 09:47:24 AM UTC 24 |
| Finished | Sep 01 09:47:26 AM UTC 24 |
| Peak memory | 217288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389687866 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1389687866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/43.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/43.edn_disable.3411701076 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 13140814 ps |
| CPU time | 1.35 seconds |
| Started | Sep 01 09:47:23 AM UTC 24 |
| Finished | Sep 01 09:47:25 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411701076 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.3411701076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/43.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/43.edn_disable_auto_req_mode.3350465433 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 46525127 ps |
| CPU time | 1.56 seconds |
| Started | Sep 01 09:47:23 AM UTC 24 |
| Finished | Sep 01 09:47:25 AM UTC 24 |
| Peak memory | 230348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350465433 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable_auto_req_mode.3350465433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/43.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/43.edn_err.3896468012 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 78254674 ps |
| CPU time | 1.6 seconds |
| Started | Sep 01 09:47:23 AM UTC 24 |
| Finished | Sep 01 09:47:25 AM UTC 24 |
| Peak memory | 244516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896468012 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 43.edn_err.3896468012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/43.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/43.edn_genbits.1515586676 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 177197281 ps |
| CPU time | 1.53 seconds |
| Started | Sep 01 09:47:19 AM UTC 24 |
| Finished | Sep 01 09:47:22 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515586676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 43.edn_genbits.1515586676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/43.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/43.edn_intr.2355247382 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 21819193 ps |
| CPU time | 1.61 seconds |
| Started | Sep 01 09:47:20 AM UTC 24 |
| Finished | Sep 01 09:47:23 AM UTC 24 |
| Peak memory | 228488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355247382 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2355247382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/43.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/43.edn_smoke.801220423 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 19320413 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 09:47:19 AM UTC 24 |
| Finished | Sep 01 09:47:21 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801220423 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 43.edn_smoke.801220423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/43.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/43.edn_stress_all.1640996194 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 93488895 ps |
| CPU time | 3.12 seconds |
| Started | Sep 01 09:47:19 AM UTC 24 |
| Finished | Sep 01 09:47:23 AM UTC 24 |
| Peak memory | 229524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640996194 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1640996194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/43.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/44.edn_alert.3229206739 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 53370432 ps |
| CPU time | 1.82 seconds |
| Started | Sep 01 09:47:26 AM UTC 24 |
| Finished | Sep 01 09:47:29 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229206739 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 44.edn_alert.3229206739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/44.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/44.edn_alert_test.924328674 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 51163550 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 09:47:29 AM UTC 24 |
| Finished | Sep 01 09:47:31 AM UTC 24 |
| Peak memory | 216528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924328674 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.924328674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/44.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/44.edn_disable_auto_req_mode.713196098 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 61815217 ps |
| CPU time | 1.79 seconds |
| Started | Sep 01 09:47:27 AM UTC 24 |
| Finished | Sep 01 09:47:30 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713196098 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable_auto_req_mode.713196098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/44.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/44.edn_err.2463979347 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 135448089 ps |
| CPU time | 1.5 seconds |
| Started | Sep 01 09:47:27 AM UTC 24 |
| Finished | Sep 01 09:47:30 AM UTC 24 |
| Peak memory | 230408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463979347 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 44.edn_err.2463979347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/44.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/44.edn_genbits.476480310 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 116039770 ps |
| CPU time | 1.68 seconds |
| Started | Sep 01 09:47:24 AM UTC 24 |
| Finished | Sep 01 09:47:27 AM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476480310 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 44.edn_genbits.476480310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/44.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/44.edn_smoke.4157710492 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 47555186 ps |
| CPU time | 1.39 seconds |
| Started | Sep 01 09:47:24 AM UTC 24 |
| Finished | Sep 01 09:47:26 AM UTC 24 |
| Peak memory | 226220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157710492 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 44.edn_smoke.4157710492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/44.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/44.edn_stress_all.360905207 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 112103558 ps |
| CPU time | 3.74 seconds |
| Started | Sep 01 09:47:25 AM UTC 24 |
| Finished | Sep 01 09:47:30 AM UTC 24 |
| Peak memory | 231568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360905207 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.360905207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/44.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/44.edn_stress_all_with_rand_reset.4157599020 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 3143825591 ps |
| CPU time | 85.82 seconds |
| Started | Sep 01 09:47:26 AM UTC 24 |
| Finished | Sep 01 09:48:54 AM UTC 24 |
| Peak memory | 229924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157599020 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all _with_rand_reset.4157599020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/44.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/45.edn_alert.917964224 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 143183225 ps |
| CPU time | 1.77 seconds |
| Started | Sep 01 09:47:31 AM UTC 24 |
| Finished | Sep 01 09:47:34 AM UTC 24 |
| Peak memory | 226376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917964224 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 45.edn_alert.917964224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/45.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/45.edn_alert_test.3187742631 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 44289923 ps |
| CPU time | 1.13 seconds |
| Started | Sep 01 09:47:34 AM UTC 24 |
| Finished | Sep 01 09:47:36 AM UTC 24 |
| Peak memory | 216852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187742631 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3187742631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/45.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/45.edn_disable.2207205207 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 29343641 ps |
| CPU time | 1.22 seconds |
| Started | Sep 01 09:47:33 AM UTC 24 |
| Finished | Sep 01 09:47:35 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207205207 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2207205207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/45.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/45.edn_err.3756861983 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 18435037 ps |
| CPU time | 1.46 seconds |
| Started | Sep 01 09:47:32 AM UTC 24 |
| Finished | Sep 01 09:47:34 AM UTC 24 |
| Peak memory | 228360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756861983 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 45.edn_err.3756861983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/45.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/45.edn_intr.673198195 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 35484377 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 09:47:31 AM UTC 24 |
| Finished | Sep 01 09:47:33 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673198195 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.673198195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/45.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/45.edn_smoke.1408252768 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 111590226 ps |
| CPU time | 1.37 seconds |
| Started | Sep 01 09:47:30 AM UTC 24 |
| Finished | Sep 01 09:47:32 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408252768 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 45.edn_smoke.1408252768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/45.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/45.edn_stress_all.2090827407 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 58368123 ps |
| CPU time | 2.22 seconds |
| Started | Sep 01 09:47:31 AM UTC 24 |
| Finished | Sep 01 09:47:34 AM UTC 24 |
| Peak memory | 227484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090827407 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2090827407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/45.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/46.edn_alert.2673076812 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 254950676 ps |
| CPU time | 2.22 seconds |
| Started | Sep 01 09:47:38 AM UTC 24 |
| Finished | Sep 01 09:47:41 AM UTC 24 |
| Peak memory | 230080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673076812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 46.edn_alert.2673076812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/46.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/46.edn_alert_test.1707656134 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 40990463 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 09:47:41 AM UTC 24 |
| Finished | Sep 01 09:47:43 AM UTC 24 |
| Peak memory | 226532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707656134 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.1707656134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/46.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/46.edn_disable.2788141329 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 14477441 ps |
| CPU time | 1.26 seconds |
| Started | Sep 01 09:47:40 AM UTC 24 |
| Finished | Sep 01 09:47:42 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788141329 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.2788141329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/46.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/46.edn_disable_auto_req_mode.1025554312 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 108264914 ps |
| CPU time | 1.53 seconds |
| Started | Sep 01 09:47:40 AM UTC 24 |
| Finished | Sep 01 09:47:42 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025554312 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable_auto_req_mode.1025554312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/46.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/46.edn_err.1031001789 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 25296065 ps |
| CPU time | 1.82 seconds |
| Started | Sep 01 09:47:38 AM UTC 24 |
| Finished | Sep 01 09:47:41 AM UTC 24 |
| Peak memory | 228360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031001789 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 46.edn_err.1031001789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/46.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/46.edn_genbits.186634212 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 250821287 ps |
| CPU time | 2.41 seconds |
| Started | Sep 01 09:47:35 AM UTC 24 |
| Finished | Sep 01 09:47:39 AM UTC 24 |
| Peak memory | 229448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186634212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 46.edn_genbits.186634212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/46.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/46.edn_intr.2887625878 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 41104035 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 09:47:37 AM UTC 24 |
| Finished | Sep 01 09:47:39 AM UTC 24 |
| Peak memory | 226320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887625878 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.2887625878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/46.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/46.edn_smoke.1563464996 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 21782813 ps |
| CPU time | 1.33 seconds |
| Started | Sep 01 09:47:34 AM UTC 24 |
| Finished | Sep 01 09:47:37 AM UTC 24 |
| Peak memory | 216016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563464996 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 46.edn_smoke.1563464996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/46.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/46.edn_stress_all.2417299998 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 365155253 ps |
| CPU time | 9.2 seconds |
| Started | Sep 01 09:47:35 AM UTC 24 |
| Finished | Sep 01 09:47:46 AM UTC 24 |
| Peak memory | 227640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417299998 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2417299998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/46.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/47.edn_alert.284424927 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 22486477 ps |
| CPU time | 1.63 seconds |
| Started | Sep 01 09:47:45 AM UTC 24 |
| Finished | Sep 01 09:47:48 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284424927 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 47.edn_alert.284424927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/47.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/47.edn_alert_test.1095223226 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 11978291 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 09:47:49 AM UTC 24 |
| Finished | Sep 01 09:47:51 AM UTC 24 |
| Peak memory | 216096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095223226 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1095223226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/47.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/47.edn_disable.1653566030 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 13766853 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 09:47:48 AM UTC 24 |
| Finished | Sep 01 09:47:50 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653566030 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1653566030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/47.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/47.edn_disable_auto_req_mode.931108862 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 77054061 ps |
| CPU time | 1.64 seconds |
| Started | Sep 01 09:47:49 AM UTC 24 |
| Finished | Sep 01 09:47:51 AM UTC 24 |
| Peak memory | 226224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931108862 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable_auto_req_mode.931108862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/47.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/47.edn_err.1521595412 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 49366042 ps |
| CPU time | 1.56 seconds |
| Started | Sep 01 09:47:46 AM UTC 24 |
| Finished | Sep 01 09:47:49 AM UTC 24 |
| Peak memory | 230408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521595412 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 47.edn_err.1521595412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/47.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/47.edn_genbits.1572565280 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 146132333 ps |
| CPU time | 1.92 seconds |
| Started | Sep 01 09:47:43 AM UTC 24 |
| Finished | Sep 01 09:47:46 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572565280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1572565280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/47.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/47.edn_intr.3138329245 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 27028577 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 09:47:45 AM UTC 24 |
| Finished | Sep 01 09:47:48 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138329245 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.3138329245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/47.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/47.edn_smoke.3378612065 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 29780504 ps |
| CPU time | 1.33 seconds |
| Started | Sep 01 09:47:42 AM UTC 24 |
| Finished | Sep 01 09:47:44 AM UTC 24 |
| Peak memory | 226260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378612065 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 47.edn_smoke.3378612065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/47.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/47.edn_stress_all.1307246639 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 545932383 ps |
| CPU time | 6.93 seconds |
| Started | Sep 01 09:47:43 AM UTC 24 |
| Finished | Sep 01 09:47:51 AM UTC 24 |
| Peak memory | 227832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307246639 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1307246639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/47.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/47.edn_stress_all_with_rand_reset.2028200750 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 6029040020 ps |
| CPU time | 75.35 seconds |
| Started | Sep 01 09:47:44 AM UTC 24 |
| Finished | Sep 01 09:49:01 AM UTC 24 |
| Peak memory | 229720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028200750 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all _with_rand_reset.2028200750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/47.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/48.edn_alert.3558634205 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 122633346 ps |
| CPU time | 1.78 seconds |
| Started | Sep 01 09:47:53 AM UTC 24 |
| Finished | Sep 01 09:47:56 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558634205 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 48.edn_alert.3558634205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/48.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/48.edn_alert_test.3589064072 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 33586731 ps |
| CPU time | 1.42 seconds |
| Started | Sep 01 09:47:58 AM UTC 24 |
| Finished | Sep 01 09:48:01 AM UTC 24 |
| Peak memory | 216748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589064072 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.3589064072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/48.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/48.edn_disable.3874765591 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 92760722 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 09:47:55 AM UTC 24 |
| Finished | Sep 01 09:47:58 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874765591 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3874765591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/48.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/48.edn_disable_auto_req_mode.3214420555 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 73405164 ps |
| CPU time | 1.53 seconds |
| Started | Sep 01 09:47:56 AM UTC 24 |
| Finished | Sep 01 09:47:59 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214420555 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable_auto_req_mode.3214420555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/48.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/48.edn_err.2422279743 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 27512681 ps |
| CPU time | 1.55 seconds |
| Started | Sep 01 09:47:55 AM UTC 24 |
| Finished | Sep 01 09:47:58 AM UTC 24 |
| Peak memory | 246084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422279743 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 48.edn_err.2422279743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/48.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/48.edn_genbits.3613995898 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 52010614 ps |
| CPU time | 2.68 seconds |
| Started | Sep 01 09:47:51 AM UTC 24 |
| Finished | Sep 01 09:47:55 AM UTC 24 |
| Peak memory | 229584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613995898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3613995898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/48.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/48.edn_intr.305514163 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 24625106 ps |
| CPU time | 1.33 seconds |
| Started | Sep 01 09:47:52 AM UTC 24 |
| Finished | Sep 01 09:47:54 AM UTC 24 |
| Peak memory | 226436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305514163 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.305514163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/48.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/48.edn_smoke.190621642 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 17227842 ps |
| CPU time | 1.55 seconds |
| Started | Sep 01 09:47:50 AM UTC 24 |
| Finished | Sep 01 09:47:52 AM UTC 24 |
| Peak memory | 216016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190621642 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 48.edn_smoke.190621642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/48.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/48.edn_stress_all.4014879771 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 597518479 ps |
| CPU time | 6.68 seconds |
| Started | Sep 01 09:47:52 AM UTC 24 |
| Finished | Sep 01 09:48:00 AM UTC 24 |
| Peak memory | 227680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014879771 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.4014879771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/48.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/48.edn_stress_all_with_rand_reset.1141167047 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 23207501831 ps |
| CPU time | 73.66 seconds |
| Started | Sep 01 09:47:52 AM UTC 24 |
| Finished | Sep 01 09:49:07 AM UTC 24 |
| Peak memory | 233880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141167047 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all _with_rand_reset.1141167047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/48.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/49.edn_alert.1561249116 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 92864544 ps |
| CPU time | 1.84 seconds |
| Started | Sep 01 09:48:03 AM UTC 24 |
| Finished | Sep 01 09:48:06 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561249116 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 49.edn_alert.1561249116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/49.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/49.edn_alert_test.1105041093 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 21380149 ps |
| CPU time | 1.48 seconds |
| Started | Sep 01 09:48:08 AM UTC 24 |
| Finished | Sep 01 09:48:10 AM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105041093 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1105041093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/49.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/49.edn_disable.2400877163 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 11555026 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 09:48:08 AM UTC 24 |
| Finished | Sep 01 09:48:10 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400877163 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2400877163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/49.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/49.edn_disable_auto_req_mode.3592497150 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 27448936 ps |
| CPU time | 1.73 seconds |
| Started | Sep 01 09:48:08 AM UTC 24 |
| Finished | Sep 01 09:48:11 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592497150 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable_auto_req_mode.3592497150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/49.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/49.edn_err.414830078 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 163065274 ps |
| CPU time | 1.74 seconds |
| Started | Sep 01 09:48:04 AM UTC 24 |
| Finished | Sep 01 09:48:07 AM UTC 24 |
| Peak memory | 230548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414830078 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 49.edn_err.414830078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/49.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/49.edn_genbits.1984432646 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 55731927 ps |
| CPU time | 1.94 seconds |
| Started | Sep 01 09:48:00 AM UTC 24 |
| Finished | Sep 01 09:48:03 AM UTC 24 |
| Peak memory | 230416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984432646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1984432646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/49.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/49.edn_intr.2253922349 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 50412036 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 09:48:02 AM UTC 24 |
| Finished | Sep 01 09:48:04 AM UTC 24 |
| Peak memory | 226320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253922349 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2253922349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/49.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/49.edn_smoke.1386442522 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 23195704 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 09:47:58 AM UTC 24 |
| Finished | Sep 01 09:48:01 AM UTC 24 |
| Peak memory | 216016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386442522 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 49.edn_smoke.1386442522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/49.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/49.edn_stress_all.2147686430 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 403819188 ps |
| CPU time | 4.8 seconds |
| Started | Sep 01 09:48:01 AM UTC 24 |
| Finished | Sep 01 09:48:06 AM UTC 24 |
| Peak memory | 229716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147686430 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2147686430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/49.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/49.edn_stress_all_with_rand_reset.1265027086 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 3723479675 ps |
| CPU time | 61.58 seconds |
| Started | Sep 01 09:48:02 AM UTC 24 |
| Finished | Sep 01 09:49:05 AM UTC 24 |
| Peak memory | 229784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265027086 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all _with_rand_reset.1265027086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/49.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/5.edn_alert.2440146379 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 30812084 ps |
| CPU time | 1.95 seconds |
| Started | Sep 01 09:44:08 AM UTC 24 |
| Finished | Sep 01 09:44:11 AM UTC 24 |
| Peak memory | 230476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440146379 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 5.edn_alert.2440146379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/5.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/5.edn_alert_test.4025503026 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 14458095 ps |
| CPU time | 1.19 seconds |
| Started | Sep 01 09:44:11 AM UTC 24 |
| Finished | Sep 01 09:44:13 AM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025503026 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.4025503026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/5.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/5.edn_disable.1011759590 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 21808113 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 09:44:09 AM UTC 24 |
| Finished | Sep 01 09:44:11 AM UTC 24 |
| Peak memory | 226376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011759590 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1011759590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/5.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/5.edn_err.3114003131 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 23056143 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 09:44:08 AM UTC 24 |
| Finished | Sep 01 09:44:11 AM UTC 24 |
| Peak memory | 228480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114003131 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 5.edn_err.3114003131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/5.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/5.edn_intr.1848763920 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 25968199 ps |
| CPU time | 1.52 seconds |
| Started | Sep 01 09:44:08 AM UTC 24 |
| Finished | Sep 01 09:44:11 AM UTC 24 |
| Peak memory | 237216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848763920 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1848763920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/5.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/5.edn_regwen.197703001 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 57967010 ps |
| CPU time | 1.4 seconds |
| Started | Sep 01 09:44:08 AM UTC 24 |
| Finished | Sep 01 09:44:10 AM UTC 24 |
| Peak memory | 216016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197703001 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 5.edn_regwen.197703001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/5.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/5.edn_smoke.1827823521 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 38298885 ps |
| CPU time | 1.36 seconds |
| Started | Sep 01 09:44:08 AM UTC 24 |
| Finished | Sep 01 09:44:10 AM UTC 24 |
| Peak memory | 226260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827823521 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 5.edn_smoke.1827823521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/5.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/5.edn_stress_all.2047433718 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 166994422 ps |
| CPU time | 3.99 seconds |
| Started | Sep 01 09:44:08 AM UTC 24 |
| Finished | Sep 01 09:44:13 AM UTC 24 |
| Peak memory | 229724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047433718 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2047433718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/5.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/5.edn_stress_all_with_rand_reset.3325703560 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1771854988 ps |
| CPU time | 51.46 seconds |
| Started | Sep 01 09:44:08 AM UTC 24 |
| Finished | Sep 01 09:45:01 AM UTC 24 |
| Peak memory | 231704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325703560 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_ with_rand_reset.3325703560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/5.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/50.edn_alert.3729501338 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 49705659 ps |
| CPU time | 1.62 seconds |
| Started | Sep 01 09:48:08 AM UTC 24 |
| Finished | Sep 01 09:48:11 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729501338 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 50.edn_alert.3729501338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/50.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/50.edn_err.813776126 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 33197499 ps |
| CPU time | 1.47 seconds |
| Started | Sep 01 09:48:11 AM UTC 24 |
| Finished | Sep 01 09:48:13 AM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813776126 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 50.edn_err.813776126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/50.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/50.edn_genbits.438707169 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 28723823 ps |
| CPU time | 2.1 seconds |
| Started | Sep 01 09:48:08 AM UTC 24 |
| Finished | Sep 01 09:48:11 AM UTC 24 |
| Peak memory | 229452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438707169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 50.edn_genbits.438707169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/50.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/51.edn_alert.1845339921 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 30067556 ps |
| CPU time | 1.97 seconds |
| Started | Sep 01 09:48:11 AM UTC 24 |
| Finished | Sep 01 09:48:14 AM UTC 24 |
| Peak memory | 226376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845339921 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 51.edn_alert.1845339921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/51.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/51.edn_err.4191511532 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 48103518 ps |
| CPU time | 1.53 seconds |
| Started | Sep 01 09:48:11 AM UTC 24 |
| Finished | Sep 01 09:48:14 AM UTC 24 |
| Peak memory | 237176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191511532 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 51.edn_err.4191511532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/51.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/51.edn_genbits.2957030584 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 41278375 ps |
| CPU time | 1.97 seconds |
| Started | Sep 01 09:48:11 AM UTC 24 |
| Finished | Sep 01 09:48:14 AM UTC 24 |
| Peak memory | 230404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957030584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2957030584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/51.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/52.edn_alert.1365174917 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 71503577 ps |
| CPU time | 1.59 seconds |
| Started | Sep 01 09:48:12 AM UTC 24 |
| Finished | Sep 01 09:48:15 AM UTC 24 |
| Peak memory | 228428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365174917 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 52.edn_alert.1365174917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/52.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/52.edn_err.4218369471 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 72177845 ps |
| CPU time | 1.25 seconds |
| Started | Sep 01 09:48:14 AM UTC 24 |
| Finished | Sep 01 09:48:17 AM UTC 24 |
| Peak memory | 230408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218369471 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 52.edn_err.4218369471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/52.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/52.edn_genbits.3630093175 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 56382916 ps |
| CPU time | 1.86 seconds |
| Started | Sep 01 09:48:12 AM UTC 24 |
| Finished | Sep 01 09:48:15 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630093175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3630093175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/52.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/53.edn_alert.1922261731 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 174970887 ps |
| CPU time | 1.87 seconds |
| Started | Sep 01 09:48:15 AM UTC 24 |
| Finished | Sep 01 09:48:17 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922261731 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 53.edn_alert.1922261731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/53.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/53.edn_err.3870956591 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 29269688 ps |
| CPU time | 1.32 seconds |
| Started | Sep 01 09:48:15 AM UTC 24 |
| Finished | Sep 01 09:48:17 AM UTC 24 |
| Peak memory | 237140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870956591 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 53.edn_err.3870956591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/53.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/53.edn_genbits.4199545471 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 19491044 ps |
| CPU time | 1.54 seconds |
| Started | Sep 01 09:48:15 AM UTC 24 |
| Finished | Sep 01 09:48:17 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199545471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 53.edn_genbits.4199545471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/53.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/54.edn_alert.3238501339 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 51113621 ps |
| CPU time | 1.86 seconds |
| Started | Sep 01 09:48:16 AM UTC 24 |
| Finished | Sep 01 09:48:19 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238501339 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 54.edn_alert.3238501339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/54.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/54.edn_err.1104302304 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 26502590 ps |
| CPU time | 1.69 seconds |
| Started | Sep 01 09:48:18 AM UTC 24 |
| Finished | Sep 01 09:48:21 AM UTC 24 |
| Peak memory | 236944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104302304 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 54.edn_err.1104302304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/54.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/54.edn_genbits.1636276216 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 44499267 ps |
| CPU time | 1.57 seconds |
| Started | Sep 01 09:48:16 AM UTC 24 |
| Finished | Sep 01 09:48:18 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636276216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1636276216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/54.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/55.edn_alert.2120581510 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 108452539 ps |
| CPU time | 1.5 seconds |
| Started | Sep 01 09:48:18 AM UTC 24 |
| Finished | Sep 01 09:48:21 AM UTC 24 |
| Peak memory | 228404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120581510 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 55.edn_alert.2120581510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/55.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/55.edn_err.1807855245 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 24352468 ps |
| CPU time | 1.42 seconds |
| Started | Sep 01 09:48:18 AM UTC 24 |
| Finished | Sep 01 09:48:21 AM UTC 24 |
| Peak memory | 228360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807855245 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 55.edn_err.1807855245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/55.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/56.edn_alert.833184326 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 27796635 ps |
| CPU time | 1.68 seconds |
| Started | Sep 01 09:48:19 AM UTC 24 |
| Finished | Sep 01 09:48:22 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833184326 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 56.edn_alert.833184326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/56.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/56.edn_err.2780967230 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 19369829 ps |
| CPU time | 1.6 seconds |
| Started | Sep 01 09:48:21 AM UTC 24 |
| Finished | Sep 01 09:48:24 AM UTC 24 |
| Peak memory | 228360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780967230 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 56.edn_err.2780967230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/56.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/56.edn_genbits.1929180341 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 51509669 ps |
| CPU time | 2.79 seconds |
| Started | Sep 01 09:48:19 AM UTC 24 |
| Finished | Sep 01 09:48:23 AM UTC 24 |
| Peak memory | 229540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929180341 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 56.edn_genbits.1929180341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/56.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/57.edn_alert.2378190243 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 95738630 ps |
| CPU time | 1.73 seconds |
| Started | Sep 01 09:48:21 AM UTC 24 |
| Finished | Sep 01 09:48:24 AM UTC 24 |
| Peak memory | 226376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378190243 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 57.edn_alert.2378190243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/57.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/57.edn_err.733945659 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 29451146 ps |
| CPU time | 1.33 seconds |
| Started | Sep 01 09:48:22 AM UTC 24 |
| Finished | Sep 01 09:48:24 AM UTC 24 |
| Peak memory | 236964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733945659 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 57.edn_err.733945659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/57.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/57.edn_genbits.1311500049 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 54682649 ps |
| CPU time | 1.48 seconds |
| Started | Sep 01 09:48:21 AM UTC 24 |
| Finished | Sep 01 09:48:24 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311500049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 57.edn_genbits.1311500049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/57.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/58.edn_alert.786037688 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 92675582 ps |
| CPU time | 1.85 seconds |
| Started | Sep 01 09:48:24 AM UTC 24 |
| Finished | Sep 01 09:48:27 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786037688 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 58.edn_alert.786037688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/58.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/58.edn_err.1300934994 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 36669714 ps |
| CPU time | 1.34 seconds |
| Started | Sep 01 09:48:25 AM UTC 24 |
| Finished | Sep 01 09:48:27 AM UTC 24 |
| Peak memory | 230408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300934994 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 58.edn_err.1300934994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/58.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/58.edn_genbits.967683165 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 129956773 ps |
| CPU time | 1.75 seconds |
| Started | Sep 01 09:48:23 AM UTC 24 |
| Finished | Sep 01 09:48:25 AM UTC 24 |
| Peak memory | 230416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967683165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 58.edn_genbits.967683165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/58.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/59.edn_alert.3164929917 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 301153952 ps |
| CPU time | 2.06 seconds |
| Started | Sep 01 09:48:25 AM UTC 24 |
| Finished | Sep 01 09:48:28 AM UTC 24 |
| Peak memory | 232124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164929917 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 59.edn_alert.3164929917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/59.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/59.edn_err.2183534702 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 33888283 ps |
| CPU time | 1.34 seconds |
| Started | Sep 01 09:48:25 AM UTC 24 |
| Finished | Sep 01 09:48:28 AM UTC 24 |
| Peak memory | 228360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183534702 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 59.edn_err.2183534702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/59.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/59.edn_genbits.2153973384 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 88423630 ps |
| CPU time | 1.67 seconds |
| Started | Sep 01 09:48:25 AM UTC 24 |
| Finished | Sep 01 09:48:27 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153973384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2153973384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/59.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/6.edn_alert.1164996718 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 108489808 ps |
| CPU time | 1.56 seconds |
| Started | Sep 01 09:44:14 AM UTC 24 |
| Finished | Sep 01 09:44:17 AM UTC 24 |
| Peak memory | 230476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164996718 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 6.edn_alert.1164996718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/6.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/6.edn_alert_test.189661601 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 48855854 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 09:44:15 AM UTC 24 |
| Finished | Sep 01 09:44:17 AM UTC 24 |
| Peak memory | 226980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189661601 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.189661601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/6.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/6.edn_disable.741422720 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 27511794 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 09:44:15 AM UTC 24 |
| Finished | Sep 01 09:44:17 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741422720 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.741422720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/6.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/6.edn_disable_auto_req_mode.1743786984 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 37795845 ps |
| CPU time | 1.58 seconds |
| Started | Sep 01 09:44:15 AM UTC 24 |
| Finished | Sep 01 09:44:17 AM UTC 24 |
| Peak memory | 230352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743786984 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable_auto_req_mode.1743786984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/6.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/6.edn_err.2804847296 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 31278512 ps |
| CPU time | 1.64 seconds |
| Started | Sep 01 09:44:15 AM UTC 24 |
| Finished | Sep 01 09:44:17 AM UTC 24 |
| Peak memory | 243796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804847296 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 6.edn_err.2804847296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/6.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/6.edn_genbits.3300927657 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 99145943 ps |
| CPU time | 1.5 seconds |
| Started | Sep 01 09:44:11 AM UTC 24 |
| Finished | Sep 01 09:44:13 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300927657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3300927657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/6.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/6.edn_intr.367027607 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 20900277 ps |
| CPU time | 1.54 seconds |
| Started | Sep 01 09:44:14 AM UTC 24 |
| Finished | Sep 01 09:44:17 AM UTC 24 |
| Peak memory | 226316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367027607 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_i ntr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.367027607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/6.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/6.edn_regwen.4162011315 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 26733418 ps |
| CPU time | 1.47 seconds |
| Started | Sep 01 09:44:11 AM UTC 24 |
| Finished | Sep 01 09:44:13 AM UTC 24 |
| Peak memory | 216020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162011315 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 6.edn_regwen.4162011315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/6.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/6.edn_smoke.978824049 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 14947788 ps |
| CPU time | 1.2 seconds |
| Started | Sep 01 09:44:11 AM UTC 24 |
| Finished | Sep 01 09:44:13 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978824049 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 6.edn_smoke.978824049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/6.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/6.edn_stress_all.3737271585 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 118150485 ps |
| CPU time | 3.92 seconds |
| Started | Sep 01 09:44:14 AM UTC 24 |
| Finished | Sep 01 09:44:19 AM UTC 24 |
| Peak memory | 229628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737271585 -assert nopostproc +UVM_TESTNAME=edn _stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3737271585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/6.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/6.edn_stress_all_with_rand_reset.2252798237 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 7530977596 ps |
| CPU time | 130.03 seconds |
| Started | Sep 01 09:44:14 AM UTC 24 |
| Finished | Sep 01 09:46:27 AM UTC 24 |
| Peak memory | 234208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252798237 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_ with_rand_reset.2252798237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/6.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/60.edn_alert.3023953004 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 81237996 ps |
| CPU time | 1.84 seconds |
| Started | Sep 01 09:48:26 AM UTC 24 |
| Finished | Sep 01 09:48:29 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023953004 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 60.edn_alert.3023953004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/60.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/60.edn_err.3413658468 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 21015588 ps |
| CPU time | 1.3 seconds |
| Started | Sep 01 09:48:26 AM UTC 24 |
| Finished | Sep 01 09:48:29 AM UTC 24 |
| Peak memory | 228360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413658468 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 60.edn_err.3413658468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/60.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/60.edn_genbits.894845575 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 32989970 ps |
| CPU time | 1.53 seconds |
| Started | Sep 01 09:48:25 AM UTC 24 |
| Finished | Sep 01 09:48:28 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894845575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 60.edn_genbits.894845575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/60.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/61.edn_alert.2238871037 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 81313595 ps |
| CPU time | 1.64 seconds |
| Started | Sep 01 09:48:28 AM UTC 24 |
| Finished | Sep 01 09:48:31 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238871037 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 61.edn_alert.2238871037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/61.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/61.edn_err.3282986713 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 31000822 ps |
| CPU time | 1.83 seconds |
| Started | Sep 01 09:48:28 AM UTC 24 |
| Finished | Sep 01 09:48:31 AM UTC 24 |
| Peak memory | 230408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282986713 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 61.edn_err.3282986713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/61.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/61.edn_genbits.3106655293 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 58982017 ps |
| CPU time | 1.43 seconds |
| Started | Sep 01 09:48:27 AM UTC 24 |
| Finished | Sep 01 09:48:30 AM UTC 24 |
| Peak memory | 230612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106655293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 61.edn_genbits.3106655293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/61.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/62.edn_alert.1426809880 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 35260370 ps |
| CPU time | 1.45 seconds |
| Started | Sep 01 09:48:29 AM UTC 24 |
| Finished | Sep 01 09:48:31 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426809880 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 62.edn_alert.1426809880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/62.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/62.edn_err.2235560017 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 86118247 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 09:48:30 AM UTC 24 |
| Finished | Sep 01 09:48:32 AM UTC 24 |
| Peak memory | 228300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235560017 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 62.edn_err.2235560017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/62.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/62.edn_genbits.3212110735 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 116433777 ps |
| CPU time | 3.24 seconds |
| Started | Sep 01 09:48:28 AM UTC 24 |
| Finished | Sep 01 09:48:33 AM UTC 24 |
| Peak memory | 229516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212110735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 62.edn_genbits.3212110735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/62.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/63.edn_alert.4214813944 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 33171301 ps |
| CPU time | 1.69 seconds |
| Started | Sep 01 09:48:30 AM UTC 24 |
| Finished | Sep 01 09:48:33 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214813944 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 63.edn_alert.4214813944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/63.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/63.edn_err.3930461406 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 20086616 ps |
| CPU time | 1.34 seconds |
| Started | Sep 01 09:48:31 AM UTC 24 |
| Finished | Sep 01 09:48:34 AM UTC 24 |
| Peak memory | 228360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930461406 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 63.edn_err.3930461406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/63.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/63.edn_genbits.1622151790 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 34148808 ps |
| CPU time | 2.07 seconds |
| Started | Sep 01 09:48:30 AM UTC 24 |
| Finished | Sep 01 09:48:33 AM UTC 24 |
| Peak memory | 229448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622151790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 63.edn_genbits.1622151790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/63.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/64.edn_alert.1168317782 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 74630707 ps |
| CPU time | 1.81 seconds |
| Started | Sep 01 09:48:32 AM UTC 24 |
| Finished | Sep 01 09:48:35 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168317782 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 64.edn_alert.1168317782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/64.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/64.edn_err.2278918564 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 22383540 ps |
| CPU time | 1.52 seconds |
| Started | Sep 01 09:48:32 AM UTC 24 |
| Finished | Sep 01 09:48:35 AM UTC 24 |
| Peak memory | 230408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278918564 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 64.edn_err.2278918564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/64.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/64.edn_genbits.2956467813 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 42788749 ps |
| CPU time | 1.61 seconds |
| Started | Sep 01 09:48:32 AM UTC 24 |
| Finished | Sep 01 09:48:35 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956467813 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2956467813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/64.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/65.edn_alert.1201948928 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 290358193 ps |
| CPU time | 1.97 seconds |
| Started | Sep 01 09:48:34 AM UTC 24 |
| Finished | Sep 01 09:48:37 AM UTC 24 |
| Peak memory | 228392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201948928 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 65.edn_alert.1201948928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/65.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/65.edn_err.1302970866 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 27337315 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 09:48:34 AM UTC 24 |
| Finished | Sep 01 09:48:37 AM UTC 24 |
| Peak memory | 228340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302970866 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 65.edn_err.1302970866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/65.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/65.edn_genbits.753406131 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 57377874 ps |
| CPU time | 1.55 seconds |
| Started | Sep 01 09:48:33 AM UTC 24 |
| Finished | Sep 01 09:48:36 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753406131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 65.edn_genbits.753406131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/65.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/66.edn_alert.4146319357 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 285440912 ps |
| CPU time | 2.18 seconds |
| Started | Sep 01 09:48:34 AM UTC 24 |
| Finished | Sep 01 09:48:38 AM UTC 24 |
| Peak memory | 232324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146319357 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 66.edn_alert.4146319357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/66.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/66.edn_err.4235330480 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 35991296 ps |
| CPU time | 1.75 seconds |
| Started | Sep 01 09:48:35 AM UTC 24 |
| Finished | Sep 01 09:48:38 AM UTC 24 |
| Peak memory | 237156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235330480 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 66.edn_err.4235330480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/66.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/66.edn_genbits.549320402 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 23088423 ps |
| CPU time | 1.7 seconds |
| Started | Sep 01 09:48:34 AM UTC 24 |
| Finished | Sep 01 09:48:37 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549320402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 66.edn_genbits.549320402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/66.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/67.edn_alert.3111568645 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 45399631 ps |
| CPU time | 1.84 seconds |
| Started | Sep 01 09:48:37 AM UTC 24 |
| Finished | Sep 01 09:48:40 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111568645 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 67.edn_alert.3111568645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/67.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/67.edn_err.344738988 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 44126446 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 09:48:37 AM UTC 24 |
| Finished | Sep 01 09:48:39 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344738988 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 67.edn_err.344738988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/67.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/67.edn_genbits.3728770193 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 75370159 ps |
| CPU time | 1.55 seconds |
| Started | Sep 01 09:48:35 AM UTC 24 |
| Finished | Sep 01 09:48:38 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728770193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3728770193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/67.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/68.edn_alert.1965773060 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 36106724 ps |
| CPU time | 1.66 seconds |
| Started | Sep 01 09:48:38 AM UTC 24 |
| Finished | Sep 01 09:48:41 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965773060 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 68.edn_alert.1965773060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/68.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/68.edn_err.1613956195 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 20055792 ps |
| CPU time | 1.46 seconds |
| Started | Sep 01 09:48:39 AM UTC 24 |
| Finished | Sep 01 09:48:41 AM UTC 24 |
| Peak memory | 230408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613956195 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 68.edn_err.1613956195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/68.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/68.edn_genbits.1046311794 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 67197261 ps |
| CPU time | 2.19 seconds |
| Started | Sep 01 09:48:38 AM UTC 24 |
| Finished | Sep 01 09:48:41 AM UTC 24 |
| Peak memory | 229540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046311794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1046311794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/68.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/69.edn_alert.126399524 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 32707531 ps |
| CPU time | 2.01 seconds |
| Started | Sep 01 09:48:39 AM UTC 24 |
| Finished | Sep 01 09:48:42 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126399524 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 69.edn_alert.126399524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/69.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/69.edn_err.1218825253 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 63090581 ps |
| CPU time | 1.41 seconds |
| Started | Sep 01 09:48:39 AM UTC 24 |
| Finished | Sep 01 09:48:41 AM UTC 24 |
| Peak memory | 230408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218825253 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 69.edn_err.1218825253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/69.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/69.edn_genbits.4253791949 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 100941449 ps |
| CPU time | 1.69 seconds |
| Started | Sep 01 09:48:39 AM UTC 24 |
| Finished | Sep 01 09:48:42 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253791949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 69.edn_genbits.4253791949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/69.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/7.edn_alert.2732202229 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 68028548 ps |
| CPU time | 1.64 seconds |
| Started | Sep 01 09:44:16 AM UTC 24 |
| Finished | Sep 01 09:44:19 AM UTC 24 |
| Peak memory | 230476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732202229 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 7.edn_alert.2732202229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/7.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/7.edn_alert_test.782208647 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 21680709 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 09:44:18 AM UTC 24 |
| Finished | Sep 01 09:44:20 AM UTC 24 |
| Peak memory | 216372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782208647 -assert nopostproc +UVM_TESTNAME=edn_bas e_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.782208647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/7.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/7.edn_disable_auto_req_mode.1979362758 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 33759856 ps |
| CPU time | 1.69 seconds |
| Started | Sep 01 09:44:17 AM UTC 24 |
| Finished | Sep 01 09:44:20 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979362758 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable_auto_req_mode.1979362758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/7.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/7.edn_err.3738113730 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 26222577 ps |
| CPU time | 1.5 seconds |
| Started | Sep 01 09:44:16 AM UTC 24 |
| Finished | Sep 01 09:44:19 AM UTC 24 |
| Peak memory | 246084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738113730 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 7.edn_err.3738113730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/7.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/7.edn_genbits.3446985183 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 75504055 ps |
| CPU time | 1.54 seconds |
| Started | Sep 01 09:44:15 AM UTC 24 |
| Finished | Sep 01 09:44:17 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446985183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.edn_genbits.3446985183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/7.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/7.edn_intr.3691780661 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 76875022 ps |
| CPU time | 1.4 seconds |
| Started | Sep 01 09:44:15 AM UTC 24 |
| Finished | Sep 01 09:44:17 AM UTC 24 |
| Peak memory | 237624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691780661 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.3691780661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/7.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/7.edn_regwen.2062357633 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 21028005 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 09:44:15 AM UTC 24 |
| Finished | Sep 01 09:44:17 AM UTC 24 |
| Peak memory | 216020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062357633 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 7.edn_regwen.2062357633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/7.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/7.edn_smoke.769379802 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 196645695 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 09:44:15 AM UTC 24 |
| Finished | Sep 01 09:44:17 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769379802 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 7.edn_smoke.769379802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/7.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/7.edn_stress_all.656936770 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 109396165 ps |
| CPU time | 2.84 seconds |
| Started | Sep 01 09:44:15 AM UTC 24 |
| Finished | Sep 01 09:44:19 AM UTC 24 |
| Peak memory | 227376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656936770 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.656936770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/7.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/70.edn_alert.2420932497 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 114335777 ps |
| CPU time | 2.01 seconds |
| Started | Sep 01 09:48:40 AM UTC 24 |
| Finished | Sep 01 09:48:43 AM UTC 24 |
| Peak memory | 226356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420932497 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 70.edn_alert.2420932497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/70.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/70.edn_err.355764603 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 21213647 ps |
| CPU time | 1.55 seconds |
| Started | Sep 01 09:48:41 AM UTC 24 |
| Finished | Sep 01 09:48:44 AM UTC 24 |
| Peak memory | 236964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355764603 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 70.edn_err.355764603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/70.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/70.edn_genbits.2597282185 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 117122303 ps |
| CPU time | 2.06 seconds |
| Started | Sep 01 09:48:40 AM UTC 24 |
| Finished | Sep 01 09:48:43 AM UTC 24 |
| Peak memory | 231864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597282185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2597282185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/70.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/71.edn_alert.1822662183 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 41861266 ps |
| CPU time | 1.62 seconds |
| Started | Sep 01 09:48:42 AM UTC 24 |
| Finished | Sep 01 09:48:45 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822662183 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 71.edn_alert.1822662183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/71.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/71.edn_err.4002262674 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 26749110 ps |
| CPU time | 1.3 seconds |
| Started | Sep 01 09:48:42 AM UTC 24 |
| Finished | Sep 01 09:48:45 AM UTC 24 |
| Peak memory | 228360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002262674 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 71.edn_err.4002262674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/71.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/71.edn_genbits.610879643 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 320054348 ps |
| CPU time | 1.76 seconds |
| Started | Sep 01 09:48:42 AM UTC 24 |
| Finished | Sep 01 09:48:45 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610879643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 71.edn_genbits.610879643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/71.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/72.edn_alert.3577487069 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 71689546 ps |
| CPU time | 1.96 seconds |
| Started | Sep 01 09:48:43 AM UTC 24 |
| Finished | Sep 01 09:48:46 AM UTC 24 |
| Peak memory | 226344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577487069 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 72.edn_alert.3577487069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/72.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/72.edn_err.3040258284 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 32668465 ps |
| CPU time | 1.35 seconds |
| Started | Sep 01 09:48:44 AM UTC 24 |
| Finished | Sep 01 09:48:46 AM UTC 24 |
| Peak memory | 230408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040258284 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 72.edn_err.3040258284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/72.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/72.edn_genbits.1217143257 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 44193034 ps |
| CPU time | 2.46 seconds |
| Started | Sep 01 09:48:43 AM UTC 24 |
| Finished | Sep 01 09:48:46 AM UTC 24 |
| Peak memory | 229564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217143257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 72.edn_genbits.1217143257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/72.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/73.edn_alert.2771435008 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 77009852 ps |
| CPU time | 1.62 seconds |
| Started | Sep 01 09:48:45 AM UTC 24 |
| Finished | Sep 01 09:48:48 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771435008 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 73.edn_alert.2771435008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/73.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/73.edn_err.2722668100 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 24264762 ps |
| CPU time | 1.91 seconds |
| Started | Sep 01 09:48:46 AM UTC 24 |
| Finished | Sep 01 09:48:49 AM UTC 24 |
| Peak memory | 247180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722668100 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 73.edn_err.2722668100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/73.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/73.edn_genbits.1976636659 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 94541439 ps |
| CPU time | 2.25 seconds |
| Started | Sep 01 09:48:44 AM UTC 24 |
| Finished | Sep 01 09:48:47 AM UTC 24 |
| Peak memory | 229608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976636659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1976636659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/73.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/74.edn_alert.2141592689 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 206680819 ps |
| CPU time | 1.87 seconds |
| Started | Sep 01 09:48:46 AM UTC 24 |
| Finished | Sep 01 09:48:49 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141592689 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 74.edn_alert.2141592689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/74.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/74.edn_err.469268767 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 47982807 ps |
| CPU time | 1.72 seconds |
| Started | Sep 01 09:48:47 AM UTC 24 |
| Finished | Sep 01 09:48:50 AM UTC 24 |
| Peak memory | 243860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469268767 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 74.edn_err.469268767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/74.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/74.edn_genbits.1077677719 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 75276611 ps |
| CPU time | 1.77 seconds |
| Started | Sep 01 09:48:46 AM UTC 24 |
| Finished | Sep 01 09:48:49 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077677719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 74.edn_genbits.1077677719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/74.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/75.edn_alert.4177852096 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 136063272 ps |
| CPU time | 1.91 seconds |
| Started | Sep 01 09:48:47 AM UTC 24 |
| Finished | Sep 01 09:48:50 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177852096 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 75.edn_alert.4177852096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/75.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/75.edn_err.1462308193 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 54096467 ps |
| CPU time | 1.61 seconds |
| Started | Sep 01 09:48:48 AM UTC 24 |
| Finished | Sep 01 09:48:51 AM UTC 24 |
| Peak memory | 243736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462308193 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 75.edn_err.1462308193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/75.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/75.edn_genbits.2441331969 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 52665175 ps |
| CPU time | 1.72 seconds |
| Started | Sep 01 09:48:47 AM UTC 24 |
| Finished | Sep 01 09:48:50 AM UTC 24 |
| Peak memory | 226320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441331969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 75.edn_genbits.2441331969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/75.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/76.edn_alert.2413841400 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 66102118 ps |
| CPU time | 1.54 seconds |
| Started | Sep 01 09:48:49 AM UTC 24 |
| Finished | Sep 01 09:48:52 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413841400 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 76.edn_alert.2413841400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/76.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/76.edn_err.715469497 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 29405119 ps |
| CPU time | 1.29 seconds |
| Started | Sep 01 09:48:49 AM UTC 24 |
| Finished | Sep 01 09:48:52 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715469497 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 76.edn_err.715469497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/76.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/76.edn_genbits.3603177753 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 63045059 ps |
| CPU time | 1.72 seconds |
| Started | Sep 01 09:48:48 AM UTC 24 |
| Finished | Sep 01 09:48:51 AM UTC 24 |
| Peak memory | 230416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603177753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3603177753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/76.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/77.edn_alert.4171989484 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 27578498 ps |
| CPU time | 1.75 seconds |
| Started | Sep 01 09:48:51 AM UTC 24 |
| Finished | Sep 01 09:48:54 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171989484 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 77.edn_alert.4171989484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/77.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/77.edn_err.3231968837 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 35558812 ps |
| CPU time | 1.81 seconds |
| Started | Sep 01 09:48:51 AM UTC 24 |
| Finished | Sep 01 09:48:54 AM UTC 24 |
| Peak memory | 230348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231968837 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 77.edn_err.3231968837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/77.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/77.edn_genbits.242526212 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 65627861 ps |
| CPU time | 1.78 seconds |
| Started | Sep 01 09:48:51 AM UTC 24 |
| Finished | Sep 01 09:48:54 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242526212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 77.edn_genbits.242526212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/77.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/78.edn_alert.1182936254 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 53630863 ps |
| CPU time | 1.74 seconds |
| Started | Sep 01 09:48:52 AM UTC 24 |
| Finished | Sep 01 09:48:55 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182936254 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 78.edn_alert.1182936254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/78.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/78.edn_err.1391697852 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 18545254 ps |
| CPU time | 1.5 seconds |
| Started | Sep 01 09:48:52 AM UTC 24 |
| Finished | Sep 01 09:48:55 AM UTC 24 |
| Peak memory | 228360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391697852 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 78.edn_err.1391697852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/78.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/78.edn_genbits.3389613962 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 68662297 ps |
| CPU time | 2.03 seconds |
| Started | Sep 01 09:48:51 AM UTC 24 |
| Finished | Sep 01 09:48:54 AM UTC 24 |
| Peak memory | 231576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389613962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 78.edn_genbits.3389613962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/78.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/79.edn_alert.613983543 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 71736174 ps |
| CPU time | 1.64 seconds |
| Started | Sep 01 09:48:53 AM UTC 24 |
| Finished | Sep 01 09:48:56 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613983543 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 79.edn_alert.613983543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/79.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/79.edn_err.1200874268 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 45670468 ps |
| CPU time | 1.36 seconds |
| Started | Sep 01 09:48:54 AM UTC 24 |
| Finished | Sep 01 09:48:56 AM UTC 24 |
| Peak memory | 230392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200874268 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 79.edn_err.1200874268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/79.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/79.edn_genbits.2043648047 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 44207086 ps |
| CPU time | 1.6 seconds |
| Started | Sep 01 09:48:53 AM UTC 24 |
| Finished | Sep 01 09:48:56 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043648047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 79.edn_genbits.2043648047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/79.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/8.edn_alert.2983663373 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 62121657 ps |
| CPU time | 1.39 seconds |
| Started | Sep 01 09:44:19 AM UTC 24 |
| Finished | Sep 01 09:44:21 AM UTC 24 |
| Peak memory | 228416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983663373 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 8.edn_alert.2983663373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/8.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/8.edn_alert_test.4135885066 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 52765816 ps |
| CPU time | 1.96 seconds |
| Started | Sep 01 09:44:20 AM UTC 24 |
| Finished | Sep 01 09:44:23 AM UTC 24 |
| Peak memory | 216584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135885066 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.4135885066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/8.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/8.edn_disable.1467698530 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 33119660 ps |
| CPU time | 1.16 seconds |
| Started | Sep 01 09:44:20 AM UTC 24 |
| Finished | Sep 01 09:44:22 AM UTC 24 |
| Peak memory | 226376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467698530 -assert nopostproc +UVM_TESTNAME=edn_dis able_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/e dn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.1467698530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/8.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/8.edn_disable_auto_req_mode.1429883186 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 40141931 ps |
| CPU time | 1.49 seconds |
| Started | Sep 01 09:44:20 AM UTC 24 |
| Finished | Sep 01 09:44:23 AM UTC 24 |
| Peak memory | 226256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429883186 -assert nopostproc +UVM_TESTNAME=edn_dis able_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable_auto_req_mode.1429883186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/8.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/8.edn_err.4029583540 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 25398757 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 09:44:19 AM UTC 24 |
| Finished | Sep 01 09:44:21 AM UTC 24 |
| Peak memory | 230408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029583540 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 8.edn_err.4029583540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/8.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/8.edn_intr.2319986481 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 38767339 ps |
| CPU time | 1.21 seconds |
| Started | Sep 01 09:44:19 AM UTC 24 |
| Finished | Sep 01 09:44:21 AM UTC 24 |
| Peak memory | 226224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319986481 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_ intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2319986481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/8.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/8.edn_regwen.667074063 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 52322102 ps |
| CPU time | 1.1 seconds |
| Started | Sep 01 09:44:18 AM UTC 24 |
| Finished | Sep 01 09:44:20 AM UTC 24 |
| Peak memory | 216016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667074063 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 8.edn_regwen.667074063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/8.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/8.edn_smoke.677416215 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 38386296 ps |
| CPU time | 1.44 seconds |
| Started | Sep 01 09:44:18 AM UTC 24 |
| Finished | Sep 01 09:44:20 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677416215 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 8.edn_smoke.677416215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/8.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/8.edn_stress_all.843961337 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 3773459170 ps |
| CPU time | 7.66 seconds |
| Started | Sep 01 09:44:19 AM UTC 24 |
| Finished | Sep 01 09:44:28 AM UTC 24 |
| Peak memory | 229648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843961337 -assert nopostproc +UVM_TESTNAME=edn_ stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.843961337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/8.edn_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/8.edn_stress_all_with_rand_reset.2329961720 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 3829314080 ps |
| CPU time | 108.99 seconds |
| Started | Sep 01 09:44:19 AM UTC 24 |
| Finished | Sep 01 09:46:10 AM UTC 24 |
| Peak memory | 229800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ed n_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329961720 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_ with_rand_reset.2329961720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/8.edn_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/80.edn_alert.2853949962 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 37814332 ps |
| CPU time | 1.81 seconds |
| Started | Sep 01 09:48:54 AM UTC 24 |
| Finished | Sep 01 09:48:57 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853949962 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 80.edn_alert.2853949962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/80.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/80.edn_err.2156110954 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 277157586 ps |
| CPU time | 1.72 seconds |
| Started | Sep 01 09:48:55 AM UTC 24 |
| Finished | Sep 01 09:48:58 AM UTC 24 |
| Peak memory | 242240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156110954 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 80.edn_err.2156110954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/80.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/80.edn_genbits.1435712542 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 105789058 ps |
| CPU time | 2.91 seconds |
| Started | Sep 01 09:48:54 AM UTC 24 |
| Finished | Sep 01 09:48:58 AM UTC 24 |
| Peak memory | 231516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435712542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 80.edn_genbits.1435712542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/80.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/81.edn_alert.2423717965 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 29486172 ps |
| CPU time | 1.66 seconds |
| Started | Sep 01 09:48:55 AM UTC 24 |
| Finished | Sep 01 09:48:58 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423717965 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 81.edn_alert.2423717965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/81.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/81.edn_err.3880431289 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 19714566 ps |
| CPU time | 1.6 seconds |
| Started | Sep 01 09:48:55 AM UTC 24 |
| Finished | Sep 01 09:48:58 AM UTC 24 |
| Peak memory | 228300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880431289 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 81.edn_err.3880431289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/81.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/81.edn_genbits.2448658047 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 352672817 ps |
| CPU time | 2.31 seconds |
| Started | Sep 01 09:48:55 AM UTC 24 |
| Finished | Sep 01 09:48:59 AM UTC 24 |
| Peak memory | 229520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448658047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 81.edn_genbits.2448658047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/81.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/82.edn_alert.3694263472 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 25134889 ps |
| CPU time | 1.78 seconds |
| Started | Sep 01 09:48:57 AM UTC 24 |
| Finished | Sep 01 09:48:59 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694263472 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 82.edn_alert.3694263472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/82.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/82.edn_err.3692024383 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 48032398 ps |
| CPU time | 1.46 seconds |
| Started | Sep 01 09:48:58 AM UTC 24 |
| Finished | Sep 01 09:49:00 AM UTC 24 |
| Peak memory | 230408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692024383 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 82.edn_err.3692024383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/82.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/82.edn_genbits.920159811 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 399181046 ps |
| CPU time | 5.67 seconds |
| Started | Sep 01 09:48:57 AM UTC 24 |
| Finished | Sep 01 09:49:03 AM UTC 24 |
| Peak memory | 231508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920159811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 82.edn_genbits.920159811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/82.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/83.edn_alert.1302547999 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 33972135 ps |
| CPU time | 1.73 seconds |
| Started | Sep 01 09:48:59 AM UTC 24 |
| Finished | Sep 01 09:49:02 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302547999 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 83.edn_alert.1302547999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/83.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/83.edn_err.3857082667 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 18059609 ps |
| CPU time | 1.36 seconds |
| Started | Sep 01 09:48:59 AM UTC 24 |
| Finished | Sep 01 09:49:01 AM UTC 24 |
| Peak memory | 228300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857082667 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 83.edn_err.3857082667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/83.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/83.edn_genbits.1677033609 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 99182911 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 09:48:58 AM UTC 24 |
| Finished | Sep 01 09:49:00 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677033609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 83.edn_genbits.1677033609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/83.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/84.edn_alert.3821398014 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 24465954 ps |
| CPU time | 1.55 seconds |
| Started | Sep 01 09:48:59 AM UTC 24 |
| Finished | Sep 01 09:49:02 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821398014 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 84.edn_alert.3821398014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/84.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/84.edn_err.2296396358 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 45857859 ps |
| CPU time | 1.53 seconds |
| Started | Sep 01 09:49:00 AM UTC 24 |
| Finished | Sep 01 09:49:03 AM UTC 24 |
| Peak memory | 230388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296396358 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 84.edn_err.2296396358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/84.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/84.edn_genbits.3253965062 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 76718925 ps |
| CPU time | 2.7 seconds |
| Started | Sep 01 09:48:59 AM UTC 24 |
| Finished | Sep 01 09:49:03 AM UTC 24 |
| Peak memory | 231772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253965062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3253965062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/84.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/85.edn_alert.2766773609 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 93158908 ps |
| CPU time | 1.66 seconds |
| Started | Sep 01 09:49:01 AM UTC 24 |
| Finished | Sep 01 09:49:04 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766773609 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 85.edn_alert.2766773609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/85.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/85.edn_err.691300385 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 52124697 ps |
| CPU time | 1.34 seconds |
| Started | Sep 01 09:49:01 AM UTC 24 |
| Finished | Sep 01 09:49:04 AM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691300385 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 85.edn_err.691300385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/85.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/85.edn_genbits.840147801 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 151660136 ps |
| CPU time | 2.37 seconds |
| Started | Sep 01 09:49:00 AM UTC 24 |
| Finished | Sep 01 09:49:04 AM UTC 24 |
| Peak memory | 231988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840147801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 85.edn_genbits.840147801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/85.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/86.edn_alert.246843518 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 63712984 ps |
| CPU time | 1.46 seconds |
| Started | Sep 01 09:49:02 AM UTC 24 |
| Finished | Sep 01 09:49:05 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246843518 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 86.edn_alert.246843518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/86.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/86.edn_err.301661601 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 32941897 ps |
| CPU time | 1.15 seconds |
| Started | Sep 01 09:49:03 AM UTC 24 |
| Finished | Sep 01 09:49:05 AM UTC 24 |
| Peak memory | 228304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301661601 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 86.edn_err.301661601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/86.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/86.edn_genbits.2862408777 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 78227260 ps |
| CPU time | 1.77 seconds |
| Started | Sep 01 09:49:02 AM UTC 24 |
| Finished | Sep 01 09:49:05 AM UTC 24 |
| Peak memory | 230416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862408777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 86.edn_genbits.2862408777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/86.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/87.edn_alert.1547366599 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 28124616 ps |
| CPU time | 1.74 seconds |
| Started | Sep 01 09:49:04 AM UTC 24 |
| Finished | Sep 01 09:49:06 AM UTC 24 |
| Peak memory | 226376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547366599 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 87.edn_alert.1547366599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/87.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/87.edn_err.287666069 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 119596783 ps |
| CPU time | 1.31 seconds |
| Started | Sep 01 09:49:04 AM UTC 24 |
| Finished | Sep 01 09:49:06 AM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287666069 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 87.edn_err.287666069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/87.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/87.edn_genbits.2241728397 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 42247156 ps |
| CPU time | 2.01 seconds |
| Started | Sep 01 09:49:03 AM UTC 24 |
| Finished | Sep 01 09:49:06 AM UTC 24 |
| Peak memory | 230668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241728397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2241728397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/87.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/88.edn_alert.994171517 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 26458411 ps |
| CPU time | 1.96 seconds |
| Started | Sep 01 09:49:05 AM UTC 24 |
| Finished | Sep 01 09:49:08 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994171517 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 88.edn_alert.994171517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/88.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/88.edn_err.1490978121 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 51560330 ps |
| CPU time | 1.14 seconds |
| Started | Sep 01 09:49:05 AM UTC 24 |
| Finished | Sep 01 09:49:07 AM UTC 24 |
| Peak memory | 236960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490978121 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 88.edn_err.1490978121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/88.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/88.edn_genbits.1211985480 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 49879887 ps |
| CPU time | 1.7 seconds |
| Started | Sep 01 09:49:04 AM UTC 24 |
| Finished | Sep 01 09:49:06 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211985480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1211985480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/88.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/89.edn_alert.923239378 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 31438650 ps |
| CPU time | 1.8 seconds |
| Started | Sep 01 09:49:06 AM UTC 24 |
| Finished | Sep 01 09:49:09 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923239378 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 89.edn_alert.923239378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/89.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/89.edn_err.2052565969 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 34920470 ps |
| CPU time | 1.34 seconds |
| Started | Sep 01 09:49:06 AM UTC 24 |
| Finished | Sep 01 09:49:09 AM UTC 24 |
| Peak memory | 236960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052565969 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 89.edn_err.2052565969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/89.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/89.edn_genbits.1752021365 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 36539908 ps |
| CPU time | 1.8 seconds |
| Started | Sep 01 09:49:05 AM UTC 24 |
| Finished | Sep 01 09:49:08 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752021365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1752021365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/89.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/9.edn_alert.880852172 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 29015941 ps |
| CPU time | 1.77 seconds |
| Started | Sep 01 09:44:22 AM UTC 24 |
| Finished | Sep 01 09:44:25 AM UTC 24 |
| Peak memory | 230468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880852172 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 9.edn_alert.880852172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/9.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/9.edn_alert_test.2505849578 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 24461059 ps |
| CPU time | 1.18 seconds |
| Started | Sep 01 09:44:23 AM UTC 24 |
| Finished | Sep 01 09:44:25 AM UTC 24 |
| Peak memory | 226532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505849578 -assert nopostproc +UVM_TESTNAME=edn_ba se_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.2505849578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/9.edn_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/9.edn_disable.177636283 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 13463796 ps |
| CPU time | 1.3 seconds |
| Started | Sep 01 09:44:23 AM UTC 24 |
| Finished | Sep 01 09:44:25 AM UTC 24 |
| Peak memory | 226372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177636283 -assert nopostproc +UVM_TESTNAME=edn_disa ble_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ed n-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.177636283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/9.edn_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/9.edn_disable_auto_req_mode.597408876 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 78673768 ps |
| CPU time | 1.55 seconds |
| Started | Sep 01 09:44:23 AM UTC 24 |
| Finished | Sep 01 09:44:25 AM UTC 24 |
| Peak memory | 230348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597408876 -assert nopostproc +UVM_TESTNAME=edn_disa ble_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable_auto_req_mode.597408876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/9.edn_disable_auto_req_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/9.edn_err.2044134227 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 38661600 ps |
| CPU time | 1.17 seconds |
| Started | Sep 01 09:44:22 AM UTC 24 |
| Finished | Sep 01 09:44:24 AM UTC 24 |
| Peak memory | 230408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044134227 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 9.edn_err.2044134227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/9.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/9.edn_intr.69281555 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 34580891 ps |
| CPU time | 1.08 seconds |
| Started | Sep 01 09:44:22 AM UTC 24 |
| Finished | Sep 01 09:44:24 AM UTC 24 |
| Peak memory | 226316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69281555 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_in tr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 9.edn_intr.69281555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/9.edn_intr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/9.edn_regwen.1120396069 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 15985563 ps |
| CPU time | 1.4 seconds |
| Started | Sep 01 09:44:20 AM UTC 24 |
| Finished | Sep 01 09:44:23 AM UTC 24 |
| Peak memory | 216020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120396069 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=ed n_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 9.edn_regwen.1120396069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/9.edn_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/9.edn_smoke.551038654 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 28503340 ps |
| CPU time | 1.28 seconds |
| Started | Sep 01 09:44:20 AM UTC 24 |
| Finished | Sep 01 09:44:23 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551038654 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 9.edn_smoke.551038654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/9.edn_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/90.edn_alert.3048321947 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 27913426 ps |
| CPU time | 1.63 seconds |
| Started | Sep 01 09:49:06 AM UTC 24 |
| Finished | Sep 01 09:49:09 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048321947 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 90.edn_alert.3048321947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/90.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/90.edn_err.2024555194 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 75941128 ps |
| CPU time | 1.26 seconds |
| Started | Sep 01 09:49:06 AM UTC 24 |
| Finished | Sep 01 09:49:09 AM UTC 24 |
| Peak memory | 228360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024555194 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 90.edn_err.2024555194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/90.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/90.edn_genbits.3449264026 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 52077659 ps |
| CPU time | 1.68 seconds |
| Started | Sep 01 09:49:06 AM UTC 24 |
| Finished | Sep 01 09:49:09 AM UTC 24 |
| Peak memory | 228584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449264026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3449264026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/90.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/91.edn_alert.3276438066 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 200461395 ps |
| CPU time | 1.53 seconds |
| Started | Sep 01 09:49:07 AM UTC 24 |
| Finished | Sep 01 09:49:10 AM UTC 24 |
| Peak memory | 226376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276438066 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 91.edn_alert.3276438066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/91.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/91.edn_err.2360829089 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 51129620 ps |
| CPU time | 1.36 seconds |
| Started | Sep 01 09:49:08 AM UTC 24 |
| Finished | Sep 01 09:49:10 AM UTC 24 |
| Peak memory | 230392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360829089 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 91.edn_err.2360829089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/91.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/91.edn_genbits.3685886807 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 82623913 ps |
| CPU time | 2.67 seconds |
| Started | Sep 01 09:49:07 AM UTC 24 |
| Finished | Sep 01 09:49:11 AM UTC 24 |
| Peak memory | 231760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685886807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3685886807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/91.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/92.edn_alert.2970635869 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 71234072 ps |
| CPU time | 1.27 seconds |
| Started | Sep 01 09:49:09 AM UTC 24 |
| Finished | Sep 01 09:49:11 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970635869 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 92.edn_alert.2970635869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/92.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/92.edn_err.707211714 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 25753062 ps |
| CPU time | 1.37 seconds |
| Started | Sep 01 09:49:09 AM UTC 24 |
| Finished | Sep 01 09:49:11 AM UTC 24 |
| Peak memory | 230412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707211714 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 92.edn_err.707211714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/92.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/92.edn_genbits.1347353455 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 250921044 ps |
| CPU time | 2.37 seconds |
| Started | Sep 01 09:49:08 AM UTC 24 |
| Finished | Sep 01 09:49:11 AM UTC 24 |
| Peak memory | 231776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347353455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1347353455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/92.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/93.edn_alert.4211301955 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 47032974 ps |
| CPU time | 1.77 seconds |
| Started | Sep 01 09:49:10 AM UTC 24 |
| Finished | Sep 01 09:49:13 AM UTC 24 |
| Peak memory | 230476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211301955 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 93.edn_alert.4211301955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/93.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/93.edn_err.466994145 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 21103076 ps |
| CPU time | 1.61 seconds |
| Started | Sep 01 09:49:10 AM UTC 24 |
| Finished | Sep 01 09:49:13 AM UTC 24 |
| Peak memory | 228544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466994145 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 93.edn_err.466994145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/93.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/93.edn_genbits.1219287727 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 42136569 ps |
| CPU time | 1.74 seconds |
| Started | Sep 01 09:49:09 AM UTC 24 |
| Finished | Sep 01 09:49:12 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219287727 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 93.edn_genbits.1219287727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/93.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/94.edn_alert.3329231069 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 22794240 ps |
| CPU time | 1.81 seconds |
| Started | Sep 01 09:49:10 AM UTC 24 |
| Finished | Sep 01 09:49:13 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329231069 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 94.edn_alert.3329231069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/94.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/94.edn_err.459525496 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 21157189 ps |
| CPU time | 1.4 seconds |
| Started | Sep 01 09:49:10 AM UTC 24 |
| Finished | Sep 01 09:49:13 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459525496 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 94.edn_err.459525496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/94.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/94.edn_genbits.3018715249 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 67623843 ps |
| CPU time | 1.74 seconds |
| Started | Sep 01 09:49:10 AM UTC 24 |
| Finished | Sep 01 09:49:13 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018715249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3018715249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/94.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/95.edn_alert.736346282 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 32646206 ps |
| CPU time | 1.89 seconds |
| Started | Sep 01 09:49:11 AM UTC 24 |
| Finished | Sep 01 09:49:14 AM UTC 24 |
| Peak memory | 226376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736346282 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 95.edn_alert.736346282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/95.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/95.edn_err.3089517800 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 78806699 ps |
| CPU time | 1.52 seconds |
| Started | Sep 01 09:49:11 AM UTC 24 |
| Finished | Sep 01 09:49:14 AM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089517800 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 95.edn_err.3089517800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/95.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/95.edn_genbits.552773114 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 84047218 ps |
| CPU time | 3.59 seconds |
| Started | Sep 01 09:49:11 AM UTC 24 |
| Finished | Sep 01 09:49:16 AM UTC 24 |
| Peak memory | 227492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552773114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=ed n_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 95.edn_genbits.552773114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/95.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/96.edn_alert.20524435 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 244951057 ps |
| CPU time | 1.85 seconds |
| Started | Sep 01 09:49:12 AM UTC 24 |
| Finished | Sep 01 09:49:15 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20524435 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_a lert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.20524435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/96.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/96.edn_err.3363691567 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 43086301 ps |
| CPU time | 1.62 seconds |
| Started | Sep 01 09:49:13 AM UTC 24 |
| Finished | Sep 01 09:49:15 AM UTC 24 |
| Peak memory | 230408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363691567 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 96.edn_err.3363691567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/96.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/96.edn_genbits.1336110658 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 117445255 ps |
| CPU time | 2.51 seconds |
| Started | Sep 01 09:49:11 AM UTC 24 |
| Finished | Sep 01 09:49:15 AM UTC 24 |
| Peak memory | 229464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336110658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 96.edn_genbits.1336110658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/96.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/97.edn_alert.3138925270 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 44863372 ps |
| CPU time | 1.74 seconds |
| Started | Sep 01 09:49:13 AM UTC 24 |
| Finished | Sep 01 09:49:15 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138925270 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 97.edn_alert.3138925270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/97.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/97.edn_err.736583744 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 81875925 ps |
| CPU time | 1.38 seconds |
| Started | Sep 01 09:49:14 AM UTC 24 |
| Finished | Sep 01 09:49:16 AM UTC 24 |
| Peak memory | 237144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736583744 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_er r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 97.edn_err.736583744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/97.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/97.edn_genbits.1390526091 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 92980463 ps |
| CPU time | 2.04 seconds |
| Started | Sep 01 09:49:13 AM UTC 24 |
| Finished | Sep 01 09:49:16 AM UTC 24 |
| Peak memory | 231764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390526091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 97.edn_genbits.1390526091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/97.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/98.edn_alert.1071987618 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 33986810 ps |
| CPU time | 1.66 seconds |
| Started | Sep 01 09:49:14 AM UTC 24 |
| Finished | Sep 01 09:49:17 AM UTC 24 |
| Peak memory | 230472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071987618 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn _alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 98.edn_alert.1071987618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/98.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/98.edn_err.1668356139 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 23237404 ps |
| CPU time | 1.11 seconds |
| Started | Sep 01 09:49:14 AM UTC 24 |
| Finished | Sep 01 09:49:16 AM UTC 24 |
| Peak memory | 237156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668356139 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 98.edn_err.1668356139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/98.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/98.edn_genbits.4032472903 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 28963360 ps |
| CPU time | 1.7 seconds |
| Started | Sep 01 09:49:14 AM UTC 24 |
| Finished | Sep 01 09:49:17 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032472903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 98.edn_genbits.4032472903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/98.edn_genbits/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/99.edn_alert.864046478 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 41445484 ps |
| CPU time | 1.56 seconds |
| Started | Sep 01 09:49:15 AM UTC 24 |
| Finished | Sep 01 09:49:18 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864046478 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_ alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 99.edn_alert.864046478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/99.edn_alert/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/99.edn_err.1466021704 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 30699093 ps |
| CPU time | 1.9 seconds |
| Started | Sep 01 09:49:15 AM UTC 24 |
| Finished | Sep 01 09:49:18 AM UTC 24 |
| Peak memory | 242068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466021704 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_e rr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 99.edn_err.1466021704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/99.edn_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/default/99.edn_genbits.4095965191 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 48429387 ps |
| CPU time | 1.64 seconds |
| Started | Sep 01 09:49:14 AM UTC 24 |
| Finished | Sep 01 09:49:17 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095965191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=e dn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 99.edn_genbits.4095965191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/edn-sim-vcs/99.edn_genbits/latest |
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